pwm-img.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Imagination Technologies Pulse Width Modulator driver
  4. *
  5. * Copyright (c) 2014-2015, Imagination Technologies
  6. *
  7. * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/pwm.h>
  19. #include <linux/regmap.h>
  20. #include <linux/slab.h>
  21. /* PWM registers */
  22. #define PWM_CTRL_CFG 0x0000
  23. #define PWM_CTRL_CFG_NO_SUB_DIV 0
  24. #define PWM_CTRL_CFG_SUB_DIV0 1
  25. #define PWM_CTRL_CFG_SUB_DIV1 2
  26. #define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
  27. #define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
  28. #define PWM_CTRL_CFG_DIV_MASK 0x3
  29. #define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
  30. #define PWM_CH_CFG_TMBASE_SHIFT 0
  31. #define PWM_CH_CFG_DUTY_SHIFT 16
  32. #define PERIP_PWM_PDM_CONTROL 0x0140
  33. #define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
  34. #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
  35. #define IMG_PWM_PM_TIMEOUT 1000 /* ms */
  36. /*
  37. * PWM period is specified with a timebase register,
  38. * in number of step periods. The PWM duty cycle is also
  39. * specified in step periods, in the [0, $timebase] range.
  40. * In other words, the timebase imposes the duty cycle
  41. * resolution. Therefore, let's constraint the timebase to
  42. * a minimum value to allow a sane range of duty cycle values.
  43. * Imposing a minimum timebase, will impose a maximum PWM frequency.
  44. *
  45. * The value chosen is completely arbitrary.
  46. */
  47. #define MIN_TMBASE_STEPS 16
  48. #define IMG_PWM_NPWM 4
  49. struct img_pwm_soc_data {
  50. u32 max_timebase;
  51. };
  52. struct img_pwm_chip {
  53. struct device *dev;
  54. struct pwm_chip chip;
  55. struct clk *pwm_clk;
  56. struct clk *sys_clk;
  57. void __iomem *base;
  58. struct regmap *periph_regs;
  59. int max_period_ns;
  60. int min_period_ns;
  61. const struct img_pwm_soc_data *data;
  62. u32 suspend_ctrl_cfg;
  63. u32 suspend_ch_cfg[IMG_PWM_NPWM];
  64. };
  65. static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
  66. {
  67. return container_of(chip, struct img_pwm_chip, chip);
  68. }
  69. static inline void img_pwm_writel(struct img_pwm_chip *chip,
  70. u32 reg, u32 val)
  71. {
  72. writel(val, chip->base + reg);
  73. }
  74. static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
  75. u32 reg)
  76. {
  77. return readl(chip->base + reg);
  78. }
  79. static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  80. int duty_ns, int period_ns)
  81. {
  82. u32 val, div, duty, timebase;
  83. unsigned long mul, output_clk_hz, input_clk_hz;
  84. struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
  85. unsigned int max_timebase = pwm_chip->data->max_timebase;
  86. int ret;
  87. if (period_ns < pwm_chip->min_period_ns ||
  88. period_ns > pwm_chip->max_period_ns) {
  89. dev_err(chip->dev, "configured period not in range\n");
  90. return -ERANGE;
  91. }
  92. input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
  93. output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
  94. mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
  95. if (mul <= max_timebase) {
  96. div = PWM_CTRL_CFG_NO_SUB_DIV;
  97. timebase = DIV_ROUND_UP(mul, 1);
  98. } else if (mul <= max_timebase * 8) {
  99. div = PWM_CTRL_CFG_SUB_DIV0;
  100. timebase = DIV_ROUND_UP(mul, 8);
  101. } else if (mul <= max_timebase * 64) {
  102. div = PWM_CTRL_CFG_SUB_DIV1;
  103. timebase = DIV_ROUND_UP(mul, 64);
  104. } else if (mul <= max_timebase * 512) {
  105. div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
  106. timebase = DIV_ROUND_UP(mul, 512);
  107. } else {
  108. dev_err(chip->dev,
  109. "failed to configure timebase steps/divider value\n");
  110. return -EINVAL;
  111. }
  112. duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
  113. ret = pm_runtime_get_sync(chip->dev);
  114. if (ret < 0) {
  115. pm_runtime_put_autosuspend(chip->dev);
  116. return ret;
  117. }
  118. val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  119. val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
  120. val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
  121. PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
  122. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
  123. val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
  124. (timebase << PWM_CH_CFG_TMBASE_SHIFT);
  125. img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
  126. pm_runtime_mark_last_busy(chip->dev);
  127. pm_runtime_put_autosuspend(chip->dev);
  128. return 0;
  129. }
  130. static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  131. {
  132. u32 val;
  133. struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
  134. int ret;
  135. ret = pm_runtime_resume_and_get(chip->dev);
  136. if (ret < 0)
  137. return ret;
  138. val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  139. val |= BIT(pwm->hwpwm);
  140. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
  141. regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
  142. PERIP_PWM_PDM_CONTROL_CH_MASK <<
  143. PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
  144. return 0;
  145. }
  146. static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  147. {
  148. u32 val;
  149. struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
  150. val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  151. val &= ~BIT(pwm->hwpwm);
  152. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
  153. pm_runtime_mark_last_busy(chip->dev);
  154. pm_runtime_put_autosuspend(chip->dev);
  155. }
  156. static const struct pwm_ops img_pwm_ops = {
  157. .config = img_pwm_config,
  158. .enable = img_pwm_enable,
  159. .disable = img_pwm_disable,
  160. .owner = THIS_MODULE,
  161. };
  162. static const struct img_pwm_soc_data pistachio_pwm = {
  163. .max_timebase = 255,
  164. };
  165. static const struct of_device_id img_pwm_of_match[] = {
  166. {
  167. .compatible = "img,pistachio-pwm",
  168. .data = &pistachio_pwm,
  169. },
  170. { }
  171. };
  172. MODULE_DEVICE_TABLE(of, img_pwm_of_match);
  173. static int img_pwm_runtime_suspend(struct device *dev)
  174. {
  175. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  176. clk_disable_unprepare(pwm_chip->pwm_clk);
  177. clk_disable_unprepare(pwm_chip->sys_clk);
  178. return 0;
  179. }
  180. static int img_pwm_runtime_resume(struct device *dev)
  181. {
  182. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  183. int ret;
  184. ret = clk_prepare_enable(pwm_chip->sys_clk);
  185. if (ret < 0) {
  186. dev_err(dev, "could not prepare or enable sys clock\n");
  187. return ret;
  188. }
  189. ret = clk_prepare_enable(pwm_chip->pwm_clk);
  190. if (ret < 0) {
  191. dev_err(dev, "could not prepare or enable pwm clock\n");
  192. clk_disable_unprepare(pwm_chip->sys_clk);
  193. return ret;
  194. }
  195. return 0;
  196. }
  197. static int img_pwm_probe(struct platform_device *pdev)
  198. {
  199. int ret;
  200. u64 val;
  201. unsigned long clk_rate;
  202. struct resource *res;
  203. struct img_pwm_chip *pwm;
  204. const struct of_device_id *of_dev_id;
  205. pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
  206. if (!pwm)
  207. return -ENOMEM;
  208. pwm->dev = &pdev->dev;
  209. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  210. pwm->base = devm_ioremap_resource(&pdev->dev, res);
  211. if (IS_ERR(pwm->base))
  212. return PTR_ERR(pwm->base);
  213. of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
  214. if (!of_dev_id)
  215. return -ENODEV;
  216. pwm->data = of_dev_id->data;
  217. pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  218. "img,cr-periph");
  219. if (IS_ERR(pwm->periph_regs))
  220. return PTR_ERR(pwm->periph_regs);
  221. pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
  222. if (IS_ERR(pwm->sys_clk)) {
  223. dev_err(&pdev->dev, "failed to get system clock\n");
  224. return PTR_ERR(pwm->sys_clk);
  225. }
  226. pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
  227. if (IS_ERR(pwm->pwm_clk)) {
  228. dev_err(&pdev->dev, "failed to get pwm clock\n");
  229. return PTR_ERR(pwm->pwm_clk);
  230. }
  231. platform_set_drvdata(pdev, pwm);
  232. pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
  233. pm_runtime_use_autosuspend(&pdev->dev);
  234. pm_runtime_enable(&pdev->dev);
  235. if (!pm_runtime_enabled(&pdev->dev)) {
  236. ret = img_pwm_runtime_resume(&pdev->dev);
  237. if (ret)
  238. goto err_pm_disable;
  239. }
  240. clk_rate = clk_get_rate(pwm->pwm_clk);
  241. if (!clk_rate) {
  242. dev_err(&pdev->dev, "pwm clock has no frequency\n");
  243. ret = -EINVAL;
  244. goto err_suspend;
  245. }
  246. /* The maximum input clock divider is 512 */
  247. val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
  248. do_div(val, clk_rate);
  249. pwm->max_period_ns = val;
  250. val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
  251. do_div(val, clk_rate);
  252. pwm->min_period_ns = val;
  253. pwm->chip.dev = &pdev->dev;
  254. pwm->chip.ops = &img_pwm_ops;
  255. pwm->chip.base = -1;
  256. pwm->chip.npwm = IMG_PWM_NPWM;
  257. ret = pwmchip_add(&pwm->chip);
  258. if (ret < 0) {
  259. dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
  260. goto err_suspend;
  261. }
  262. return 0;
  263. err_suspend:
  264. if (!pm_runtime_enabled(&pdev->dev))
  265. img_pwm_runtime_suspend(&pdev->dev);
  266. err_pm_disable:
  267. pm_runtime_disable(&pdev->dev);
  268. pm_runtime_dont_use_autosuspend(&pdev->dev);
  269. return ret;
  270. }
  271. static int img_pwm_remove(struct platform_device *pdev)
  272. {
  273. struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
  274. pm_runtime_disable(&pdev->dev);
  275. if (!pm_runtime_status_suspended(&pdev->dev))
  276. img_pwm_runtime_suspend(&pdev->dev);
  277. return pwmchip_remove(&pwm_chip->chip);
  278. }
  279. #ifdef CONFIG_PM_SLEEP
  280. static int img_pwm_suspend(struct device *dev)
  281. {
  282. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  283. int i, ret;
  284. if (pm_runtime_status_suspended(dev)) {
  285. ret = img_pwm_runtime_resume(dev);
  286. if (ret)
  287. return ret;
  288. }
  289. for (i = 0; i < pwm_chip->chip.npwm; i++)
  290. pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,
  291. PWM_CH_CFG(i));
  292. pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
  293. img_pwm_runtime_suspend(dev);
  294. return 0;
  295. }
  296. static int img_pwm_resume(struct device *dev)
  297. {
  298. struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
  299. int ret;
  300. int i;
  301. ret = img_pwm_runtime_resume(dev);
  302. if (ret)
  303. return ret;
  304. for (i = 0; i < pwm_chip->chip.npwm; i++)
  305. img_pwm_writel(pwm_chip, PWM_CH_CFG(i),
  306. pwm_chip->suspend_ch_cfg[i]);
  307. img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);
  308. for (i = 0; i < pwm_chip->chip.npwm; i++)
  309. if (pwm_chip->suspend_ctrl_cfg & BIT(i))
  310. regmap_update_bits(pwm_chip->periph_regs,
  311. PERIP_PWM_PDM_CONTROL,
  312. PERIP_PWM_PDM_CONTROL_CH_MASK <<
  313. PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
  314. 0);
  315. if (pm_runtime_status_suspended(dev))
  316. img_pwm_runtime_suspend(dev);
  317. return 0;
  318. }
  319. #endif /* CONFIG_PM */
  320. static const struct dev_pm_ops img_pwm_pm_ops = {
  321. SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
  322. img_pwm_runtime_resume,
  323. NULL)
  324. SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
  325. };
  326. static struct platform_driver img_pwm_driver = {
  327. .driver = {
  328. .name = "img-pwm",
  329. .pm = &img_pwm_pm_ops,
  330. .of_match_table = img_pwm_of_match,
  331. },
  332. .probe = img_pwm_probe,
  333. .remove = img_pwm_remove,
  334. };
  335. module_platform_driver(img_pwm_driver);
  336. MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
  337. MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
  338. MODULE_LICENSE("GPL v2");