pwm-bcm-kona.c 9.4 KB

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  1. /*
  2. * Copyright (C) 2014 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/ioport.h>
  18. #include <linux/math64.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/pwm.h>
  23. #include <linux/slab.h>
  24. #include <linux/types.h>
  25. /*
  26. * The Kona PWM has some unusual characteristics. Here are the main points.
  27. *
  28. * 1) There is no disable bit and the hardware docs advise programming a zero
  29. * duty to achieve output equivalent to that of a normal disable operation.
  30. *
  31. * 2) Changes to prescale, duty, period, and polarity do not take effect until
  32. * a subsequent rising edge of the trigger bit.
  33. *
  34. * 3) If the smooth bit and trigger bit are both low, the output is a constant
  35. * high signal. Otherwise, the earlier waveform continues to be output.
  36. *
  37. * 4) If the smooth bit is set on the rising edge of the trigger bit, output
  38. * will transition to the new settings on a period boundary (which could be
  39. * seconds away). If the smooth bit is clear, new settings will be applied
  40. * as soon as possible (the hardware always has a 400ns delay).
  41. *
  42. * 5) When the external clock that feeds the PWM is disabled, output is pegged
  43. * high or low depending on its state at that exact instant.
  44. */
  45. #define PWM_CONTROL_OFFSET 0x00000000
  46. #define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
  47. #define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
  48. #define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
  49. #define PWM_CONTROL_TRIGGER_SHIFT(chan) (chan)
  50. #define PRESCALE_OFFSET 0x00000004
  51. #define PRESCALE_SHIFT(chan) ((chan) << 2)
  52. #define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
  53. #define PRESCALE_MIN 0x00000000
  54. #define PRESCALE_MAX 0x00000007
  55. #define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
  56. #define PERIOD_COUNT_MIN 0x00000002
  57. #define PERIOD_COUNT_MAX 0x00ffffff
  58. #define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
  59. #define DUTY_CYCLE_HIGH_MIN 0x00000000
  60. #define DUTY_CYCLE_HIGH_MAX 0x00ffffff
  61. struct kona_pwmc {
  62. struct pwm_chip chip;
  63. void __iomem *base;
  64. struct clk *clk;
  65. };
  66. static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
  67. {
  68. return container_of(_chip, struct kona_pwmc, chip);
  69. }
  70. /*
  71. * Clear trigger bit but set smooth bit to maintain old output.
  72. */
  73. static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
  74. unsigned int chan)
  75. {
  76. unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
  77. value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
  78. value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
  79. writel(value, kp->base + PWM_CONTROL_OFFSET);
  80. /*
  81. * There must be a min 400ns delay between clearing trigger and setting
  82. * it. Failing to do this may result in no PWM signal.
  83. */
  84. ndelay(400);
  85. }
  86. static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
  87. {
  88. unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
  89. /* Set trigger bit and clear smooth bit to apply new settings */
  90. value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
  91. value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
  92. writel(value, kp->base + PWM_CONTROL_OFFSET);
  93. /* Trigger bit must be held high for at least 400 ns. */
  94. ndelay(400);
  95. }
  96. static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
  97. int duty_ns, int period_ns)
  98. {
  99. struct kona_pwmc *kp = to_kona_pwmc(chip);
  100. u64 val, div, rate;
  101. unsigned long prescale = PRESCALE_MIN, pc, dc;
  102. unsigned int value, chan = pwm->hwpwm;
  103. /*
  104. * Find period count, duty count and prescale to suit duty_ns and
  105. * period_ns. This is done according to formulas described below:
  106. *
  107. * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
  108. * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
  109. *
  110. * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
  111. * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
  112. */
  113. rate = clk_get_rate(kp->clk);
  114. while (1) {
  115. div = 1000000000;
  116. div *= 1 + prescale;
  117. val = rate * period_ns;
  118. pc = div64_u64(val, div);
  119. val = rate * duty_ns;
  120. dc = div64_u64(val, div);
  121. /* If duty_ns or period_ns are not achievable then return */
  122. if (pc < PERIOD_COUNT_MIN)
  123. return -EINVAL;
  124. /* If pc and dc are in bounds, the calculation is done */
  125. if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
  126. break;
  127. /* Otherwise, increase prescale and recalculate pc and dc */
  128. if (++prescale > PRESCALE_MAX)
  129. return -EINVAL;
  130. }
  131. /*
  132. * Don't apply settings if disabled. The period and duty cycle are
  133. * always calculated above to ensure the new values are
  134. * validated immediately instead of on enable.
  135. */
  136. if (pwm_is_enabled(pwm)) {
  137. kona_pwmc_prepare_for_settings(kp, chan);
  138. value = readl(kp->base + PRESCALE_OFFSET);
  139. value &= ~PRESCALE_MASK(chan);
  140. value |= prescale << PRESCALE_SHIFT(chan);
  141. writel(value, kp->base + PRESCALE_OFFSET);
  142. writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
  143. writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
  144. kona_pwmc_apply_settings(kp, chan);
  145. }
  146. return 0;
  147. }
  148. static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
  149. enum pwm_polarity polarity)
  150. {
  151. struct kona_pwmc *kp = to_kona_pwmc(chip);
  152. unsigned int chan = pwm->hwpwm;
  153. unsigned int value;
  154. int ret;
  155. ret = clk_prepare_enable(kp->clk);
  156. if (ret < 0) {
  157. dev_err(chip->dev, "failed to enable clock: %d\n", ret);
  158. return ret;
  159. }
  160. kona_pwmc_prepare_for_settings(kp, chan);
  161. value = readl(kp->base + PWM_CONTROL_OFFSET);
  162. if (polarity == PWM_POLARITY_NORMAL)
  163. value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
  164. else
  165. value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));
  166. writel(value, kp->base + PWM_CONTROL_OFFSET);
  167. kona_pwmc_apply_settings(kp, chan);
  168. clk_disable_unprepare(kp->clk);
  169. return 0;
  170. }
  171. static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  172. {
  173. struct kona_pwmc *kp = to_kona_pwmc(chip);
  174. int ret;
  175. ret = clk_prepare_enable(kp->clk);
  176. if (ret < 0) {
  177. dev_err(chip->dev, "failed to enable clock: %d\n", ret);
  178. return ret;
  179. }
  180. ret = kona_pwmc_config(chip, pwm, pwm_get_duty_cycle(pwm),
  181. pwm_get_period(pwm));
  182. if (ret < 0) {
  183. clk_disable_unprepare(kp->clk);
  184. return ret;
  185. }
  186. return 0;
  187. }
  188. static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  189. {
  190. struct kona_pwmc *kp = to_kona_pwmc(chip);
  191. unsigned int chan = pwm->hwpwm;
  192. unsigned int value;
  193. kona_pwmc_prepare_for_settings(kp, chan);
  194. /* Simulate a disable by configuring for zero duty */
  195. writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
  196. writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
  197. /* Set prescale to 0 for this channel */
  198. value = readl(kp->base + PRESCALE_OFFSET);
  199. value &= ~PRESCALE_MASK(chan);
  200. writel(value, kp->base + PRESCALE_OFFSET);
  201. kona_pwmc_apply_settings(kp, chan);
  202. clk_disable_unprepare(kp->clk);
  203. }
  204. static const struct pwm_ops kona_pwm_ops = {
  205. .config = kona_pwmc_config,
  206. .set_polarity = kona_pwmc_set_polarity,
  207. .enable = kona_pwmc_enable,
  208. .disable = kona_pwmc_disable,
  209. .owner = THIS_MODULE,
  210. };
  211. static int kona_pwmc_probe(struct platform_device *pdev)
  212. {
  213. struct kona_pwmc *kp;
  214. struct resource *res;
  215. unsigned int chan;
  216. unsigned int value = 0;
  217. int ret = 0;
  218. kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
  219. if (kp == NULL)
  220. return -ENOMEM;
  221. platform_set_drvdata(pdev, kp);
  222. kp->chip.dev = &pdev->dev;
  223. kp->chip.ops = &kona_pwm_ops;
  224. kp->chip.base = -1;
  225. kp->chip.npwm = 6;
  226. kp->chip.of_xlate = of_pwm_xlate_with_flags;
  227. kp->chip.of_pwm_n_cells = 3;
  228. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  229. kp->base = devm_ioremap_resource(&pdev->dev, res);
  230. if (IS_ERR(kp->base))
  231. return PTR_ERR(kp->base);
  232. kp->clk = devm_clk_get(&pdev->dev, NULL);
  233. if (IS_ERR(kp->clk)) {
  234. dev_err(&pdev->dev, "failed to get clock: %ld\n",
  235. PTR_ERR(kp->clk));
  236. return PTR_ERR(kp->clk);
  237. }
  238. ret = clk_prepare_enable(kp->clk);
  239. if (ret < 0) {
  240. dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
  241. return ret;
  242. }
  243. /* Set push/pull for all channels */
  244. for (chan = 0; chan < kp->chip.npwm; chan++)
  245. value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
  246. writel(value, kp->base + PWM_CONTROL_OFFSET);
  247. clk_disable_unprepare(kp->clk);
  248. ret = pwmchip_add_with_polarity(&kp->chip, PWM_POLARITY_INVERSED);
  249. if (ret < 0)
  250. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  251. return ret;
  252. }
  253. static int kona_pwmc_remove(struct platform_device *pdev)
  254. {
  255. struct kona_pwmc *kp = platform_get_drvdata(pdev);
  256. unsigned int chan;
  257. for (chan = 0; chan < kp->chip.npwm; chan++)
  258. if (pwm_is_enabled(&kp->chip.pwms[chan]))
  259. clk_disable_unprepare(kp->clk);
  260. return pwmchip_remove(&kp->chip);
  261. }
  262. static const struct of_device_id bcm_kona_pwmc_dt[] = {
  263. { .compatible = "brcm,kona-pwm" },
  264. { },
  265. };
  266. MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
  267. static struct platform_driver kona_pwmc_driver = {
  268. .driver = {
  269. .name = "bcm-kona-pwm",
  270. .of_match_table = bcm_kona_pwmc_dt,
  271. },
  272. .probe = kona_pwmc_probe,
  273. .remove = kona_pwmc_remove,
  274. };
  275. module_platform_driver(kona_pwmc_driver);
  276. MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
  277. MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
  278. MODULE_DESCRIPTION("Broadcom Kona PWM driver");
  279. MODULE_LICENSE("GPL v2");