ptp_qoriq.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * PTP 1588 clock for Freescale QorIQ 1588 timer
  4. *
  5. * Copyright (C) 2010 OMICRON electronics GmbH
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/device.h>
  9. #include <linux/hrtimer.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/timex.h>
  15. #include <linux/slab.h>
  16. #include <linux/clk.h>
  17. #include <linux/fsl/ptp_qoriq.h>
  18. /*
  19. * Register access functions
  20. */
  21. /* Caller must hold ptp_qoriq->lock. */
  22. static u64 tmr_cnt_read(struct ptp_qoriq *ptp_qoriq)
  23. {
  24. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  25. u64 ns;
  26. u32 lo, hi;
  27. lo = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_l);
  28. hi = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_h);
  29. ns = ((u64) hi) << 32;
  30. ns |= lo;
  31. return ns;
  32. }
  33. /* Caller must hold ptp_qoriq->lock. */
  34. static void tmr_cnt_write(struct ptp_qoriq *ptp_qoriq, u64 ns)
  35. {
  36. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  37. u32 hi = ns >> 32;
  38. u32 lo = ns & 0xffffffff;
  39. ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_l, lo);
  40. ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_h, hi);
  41. }
  42. /* Caller must hold ptp_qoriq->lock. */
  43. static void set_alarm(struct ptp_qoriq *ptp_qoriq)
  44. {
  45. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  46. u64 ns;
  47. u32 lo, hi;
  48. ns = tmr_cnt_read(ptp_qoriq) + 1500000000ULL;
  49. ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
  50. ns -= ptp_qoriq->tclk_period;
  51. hi = ns >> 32;
  52. lo = ns & 0xffffffff;
  53. ptp_qoriq->write(&regs->alarm_regs->tmr_alarm1_l, lo);
  54. ptp_qoriq->write(&regs->alarm_regs->tmr_alarm1_h, hi);
  55. }
  56. /* Caller must hold ptp_qoriq->lock. */
  57. static void set_fipers(struct ptp_qoriq *ptp_qoriq)
  58. {
  59. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  60. set_alarm(ptp_qoriq);
  61. ptp_qoriq->write(&regs->fiper_regs->tmr_fiper1, ptp_qoriq->tmr_fiper1);
  62. ptp_qoriq->write(&regs->fiper_regs->tmr_fiper2, ptp_qoriq->tmr_fiper2);
  63. if (ptp_qoriq->fiper3_support)
  64. ptp_qoriq->write(&regs->fiper_regs->tmr_fiper3,
  65. ptp_qoriq->tmr_fiper3);
  66. }
  67. int extts_clean_up(struct ptp_qoriq *ptp_qoriq, int index, bool update_event)
  68. {
  69. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  70. struct ptp_clock_event event;
  71. void __iomem *reg_etts_l;
  72. void __iomem *reg_etts_h;
  73. u32 valid, lo, hi;
  74. switch (index) {
  75. case 0:
  76. valid = ETS1_VLD;
  77. reg_etts_l = &regs->etts_regs->tmr_etts1_l;
  78. reg_etts_h = &regs->etts_regs->tmr_etts1_h;
  79. break;
  80. case 1:
  81. valid = ETS2_VLD;
  82. reg_etts_l = &regs->etts_regs->tmr_etts2_l;
  83. reg_etts_h = &regs->etts_regs->tmr_etts2_h;
  84. break;
  85. default:
  86. return -EINVAL;
  87. }
  88. event.type = PTP_CLOCK_EXTTS;
  89. event.index = index;
  90. if (ptp_qoriq->extts_fifo_support)
  91. if (!(ptp_qoriq->read(&regs->ctrl_regs->tmr_stat) & valid))
  92. return 0;
  93. do {
  94. lo = ptp_qoriq->read(reg_etts_l);
  95. hi = ptp_qoriq->read(reg_etts_h);
  96. if (update_event) {
  97. event.timestamp = ((u64) hi) << 32;
  98. event.timestamp |= lo;
  99. ptp_clock_event(ptp_qoriq->clock, &event);
  100. }
  101. if (!ptp_qoriq->extts_fifo_support)
  102. break;
  103. } while (ptp_qoriq->read(&regs->ctrl_regs->tmr_stat) & valid);
  104. return 0;
  105. }
  106. EXPORT_SYMBOL_GPL(extts_clean_up);
  107. /*
  108. * Interrupt service routine
  109. */
  110. irqreturn_t ptp_qoriq_isr(int irq, void *priv)
  111. {
  112. struct ptp_qoriq *ptp_qoriq = priv;
  113. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  114. struct ptp_clock_event event;
  115. u32 ack = 0, mask, val, irqs;
  116. spin_lock(&ptp_qoriq->lock);
  117. val = ptp_qoriq->read(&regs->ctrl_regs->tmr_tevent);
  118. mask = ptp_qoriq->read(&regs->ctrl_regs->tmr_temask);
  119. spin_unlock(&ptp_qoriq->lock);
  120. irqs = val & mask;
  121. if (irqs & ETS1) {
  122. ack |= ETS1;
  123. extts_clean_up(ptp_qoriq, 0, true);
  124. }
  125. if (irqs & ETS2) {
  126. ack |= ETS2;
  127. extts_clean_up(ptp_qoriq, 1, true);
  128. }
  129. if (irqs & PP1) {
  130. ack |= PP1;
  131. event.type = PTP_CLOCK_PPS;
  132. ptp_clock_event(ptp_qoriq->clock, &event);
  133. }
  134. if (ack) {
  135. ptp_qoriq->write(&regs->ctrl_regs->tmr_tevent, ack);
  136. return IRQ_HANDLED;
  137. } else
  138. return IRQ_NONE;
  139. }
  140. EXPORT_SYMBOL_GPL(ptp_qoriq_isr);
  141. /*
  142. * PTP clock operations
  143. */
  144. int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
  145. {
  146. u64 adj, diff;
  147. u32 tmr_add;
  148. int neg_adj = 0;
  149. struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
  150. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  151. if (scaled_ppm < 0) {
  152. neg_adj = 1;
  153. scaled_ppm = -scaled_ppm;
  154. }
  155. tmr_add = ptp_qoriq->tmr_add;
  156. adj = tmr_add;
  157. /*
  158. * Calculate diff and round() to the nearest integer
  159. *
  160. * diff = adj * (ppb / 1000000000)
  161. * = adj * scaled_ppm / 65536000000
  162. */
  163. diff = mul_u64_u64_div_u64(adj, scaled_ppm, 32768000000);
  164. diff = DIV64_U64_ROUND_UP(diff, 2);
  165. tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
  166. ptp_qoriq->write(&regs->ctrl_regs->tmr_add, tmr_add);
  167. return 0;
  168. }
  169. EXPORT_SYMBOL_GPL(ptp_qoriq_adjfine);
  170. int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta)
  171. {
  172. s64 now;
  173. unsigned long flags;
  174. struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
  175. spin_lock_irqsave(&ptp_qoriq->lock, flags);
  176. now = tmr_cnt_read(ptp_qoriq);
  177. now += delta;
  178. tmr_cnt_write(ptp_qoriq, now);
  179. set_fipers(ptp_qoriq);
  180. spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
  181. return 0;
  182. }
  183. EXPORT_SYMBOL_GPL(ptp_qoriq_adjtime);
  184. int ptp_qoriq_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
  185. {
  186. u64 ns;
  187. unsigned long flags;
  188. struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
  189. spin_lock_irqsave(&ptp_qoriq->lock, flags);
  190. ns = tmr_cnt_read(ptp_qoriq);
  191. spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
  192. *ts = ns_to_timespec64(ns);
  193. return 0;
  194. }
  195. EXPORT_SYMBOL_GPL(ptp_qoriq_gettime);
  196. int ptp_qoriq_settime(struct ptp_clock_info *ptp,
  197. const struct timespec64 *ts)
  198. {
  199. u64 ns;
  200. unsigned long flags;
  201. struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
  202. ns = timespec64_to_ns(ts);
  203. spin_lock_irqsave(&ptp_qoriq->lock, flags);
  204. tmr_cnt_write(ptp_qoriq, ns);
  205. set_fipers(ptp_qoriq);
  206. spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
  207. return 0;
  208. }
  209. EXPORT_SYMBOL_GPL(ptp_qoriq_settime);
  210. int ptp_qoriq_enable(struct ptp_clock_info *ptp,
  211. struct ptp_clock_request *rq, int on)
  212. {
  213. struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
  214. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  215. unsigned long flags;
  216. u32 bit, mask = 0;
  217. switch (rq->type) {
  218. case PTP_CLK_REQ_EXTTS:
  219. switch (rq->extts.index) {
  220. case 0:
  221. bit = ETS1EN;
  222. break;
  223. case 1:
  224. bit = ETS2EN;
  225. break;
  226. default:
  227. return -EINVAL;
  228. }
  229. if (on)
  230. extts_clean_up(ptp_qoriq, rq->extts.index, false);
  231. break;
  232. case PTP_CLK_REQ_PPS:
  233. bit = PP1EN;
  234. break;
  235. default:
  236. return -EOPNOTSUPP;
  237. }
  238. spin_lock_irqsave(&ptp_qoriq->lock, flags);
  239. mask = ptp_qoriq->read(&regs->ctrl_regs->tmr_temask);
  240. if (on) {
  241. mask |= bit;
  242. ptp_qoriq->write(&regs->ctrl_regs->tmr_tevent, bit);
  243. } else {
  244. mask &= ~bit;
  245. }
  246. ptp_qoriq->write(&regs->ctrl_regs->tmr_temask, mask);
  247. spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
  248. return 0;
  249. }
  250. EXPORT_SYMBOL_GPL(ptp_qoriq_enable);
  251. static const struct ptp_clock_info ptp_qoriq_caps = {
  252. .owner = THIS_MODULE,
  253. .name = "qoriq ptp clock",
  254. .max_adj = 512000,
  255. .n_alarm = 0,
  256. .n_ext_ts = N_EXT_TS,
  257. .n_per_out = 0,
  258. .n_pins = 0,
  259. .pps = 1,
  260. .adjfine = ptp_qoriq_adjfine,
  261. .adjtime = ptp_qoriq_adjtime,
  262. .gettime64 = ptp_qoriq_gettime,
  263. .settime64 = ptp_qoriq_settime,
  264. .enable = ptp_qoriq_enable,
  265. };
  266. /**
  267. * ptp_qoriq_nominal_freq - calculate nominal frequency according to
  268. * reference clock frequency
  269. *
  270. * @clk_src: reference clock frequency
  271. *
  272. * The nominal frequency is the desired clock frequency.
  273. * It should be less than the reference clock frequency.
  274. * It should be a factor of 1000MHz.
  275. *
  276. * Return the nominal frequency
  277. */
  278. static u32 ptp_qoriq_nominal_freq(u32 clk_src)
  279. {
  280. u32 remainder = 0;
  281. clk_src /= 1000000;
  282. remainder = clk_src % 100;
  283. if (remainder) {
  284. clk_src -= remainder;
  285. clk_src += 100;
  286. }
  287. do {
  288. clk_src -= 100;
  289. } while (1000 % clk_src);
  290. return clk_src * 1000000;
  291. }
  292. /**
  293. * ptp_qoriq_auto_config - calculate a set of default configurations
  294. *
  295. * @ptp_qoriq: pointer to ptp_qoriq
  296. * @node: pointer to device_node
  297. *
  298. * If below dts properties are not provided, this function will be
  299. * called to calculate a set of default configurations for them.
  300. * "fsl,tclk-period"
  301. * "fsl,tmr-prsc"
  302. * "fsl,tmr-add"
  303. * "fsl,tmr-fiper1"
  304. * "fsl,tmr-fiper2"
  305. * "fsl,tmr-fiper3" (required only for DPAA2 and ENETC hardware)
  306. * "fsl,max-adj"
  307. *
  308. * Return 0 if success
  309. */
  310. static int ptp_qoriq_auto_config(struct ptp_qoriq *ptp_qoriq,
  311. struct device_node *node)
  312. {
  313. struct clk *clk;
  314. u64 freq_comp;
  315. u64 max_adj;
  316. u32 nominal_freq;
  317. u32 remainder = 0;
  318. u32 clk_src = 0;
  319. ptp_qoriq->cksel = DEFAULT_CKSEL;
  320. clk = of_clk_get(node, 0);
  321. if (!IS_ERR(clk)) {
  322. clk_src = clk_get_rate(clk);
  323. clk_put(clk);
  324. }
  325. if (clk_src <= 100000000UL) {
  326. pr_err("error reference clock value, or lower than 100MHz\n");
  327. return -EINVAL;
  328. }
  329. nominal_freq = ptp_qoriq_nominal_freq(clk_src);
  330. if (!nominal_freq)
  331. return -EINVAL;
  332. ptp_qoriq->tclk_period = 1000000000UL / nominal_freq;
  333. ptp_qoriq->tmr_prsc = DEFAULT_TMR_PRSC;
  334. /* Calculate initial frequency compensation value for TMR_ADD register.
  335. * freq_comp = ceil(2^32 / freq_ratio)
  336. * freq_ratio = reference_clock_freq / nominal_freq
  337. */
  338. freq_comp = ((u64)1 << 32) * nominal_freq;
  339. freq_comp = div_u64_rem(freq_comp, clk_src, &remainder);
  340. if (remainder)
  341. freq_comp++;
  342. ptp_qoriq->tmr_add = freq_comp;
  343. ptp_qoriq->tmr_fiper1 = DEFAULT_FIPER1_PERIOD - ptp_qoriq->tclk_period;
  344. ptp_qoriq->tmr_fiper2 = DEFAULT_FIPER2_PERIOD - ptp_qoriq->tclk_period;
  345. ptp_qoriq->tmr_fiper3 = DEFAULT_FIPER3_PERIOD - ptp_qoriq->tclk_period;
  346. /* max_adj = 1000000000 * (freq_ratio - 1.0) - 1
  347. * freq_ratio = reference_clock_freq / nominal_freq
  348. */
  349. max_adj = 1000000000ULL * (clk_src - nominal_freq);
  350. max_adj = div_u64(max_adj, nominal_freq) - 1;
  351. ptp_qoriq->caps.max_adj = max_adj;
  352. return 0;
  353. }
  354. int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base,
  355. const struct ptp_clock_info *caps)
  356. {
  357. struct device_node *node = ptp_qoriq->dev->of_node;
  358. struct ptp_qoriq_registers *regs;
  359. struct timespec64 now;
  360. unsigned long flags;
  361. u32 tmr_ctrl;
  362. if (!node)
  363. return -ENODEV;
  364. ptp_qoriq->base = base;
  365. ptp_qoriq->caps = *caps;
  366. if (of_property_read_u32(node, "fsl,cksel", &ptp_qoriq->cksel))
  367. ptp_qoriq->cksel = DEFAULT_CKSEL;
  368. if (of_property_read_bool(node, "fsl,extts-fifo"))
  369. ptp_qoriq->extts_fifo_support = true;
  370. else
  371. ptp_qoriq->extts_fifo_support = false;
  372. if (of_device_is_compatible(node, "fsl,dpaa2-ptp") ||
  373. of_device_is_compatible(node, "fsl,enetc-ptp"))
  374. ptp_qoriq->fiper3_support = true;
  375. if (of_property_read_u32(node,
  376. "fsl,tclk-period", &ptp_qoriq->tclk_period) ||
  377. of_property_read_u32(node,
  378. "fsl,tmr-prsc", &ptp_qoriq->tmr_prsc) ||
  379. of_property_read_u32(node,
  380. "fsl,tmr-add", &ptp_qoriq->tmr_add) ||
  381. of_property_read_u32(node,
  382. "fsl,tmr-fiper1", &ptp_qoriq->tmr_fiper1) ||
  383. of_property_read_u32(node,
  384. "fsl,tmr-fiper2", &ptp_qoriq->tmr_fiper2) ||
  385. of_property_read_u32(node,
  386. "fsl,max-adj", &ptp_qoriq->caps.max_adj) ||
  387. (ptp_qoriq->fiper3_support &&
  388. of_property_read_u32(node, "fsl,tmr-fiper3",
  389. &ptp_qoriq->tmr_fiper3))) {
  390. pr_warn("device tree node missing required elements, try automatic configuration\n");
  391. if (ptp_qoriq_auto_config(ptp_qoriq, node))
  392. return -ENODEV;
  393. }
  394. if (of_property_read_bool(node, "little-endian")) {
  395. ptp_qoriq->read = qoriq_read_le;
  396. ptp_qoriq->write = qoriq_write_le;
  397. } else {
  398. ptp_qoriq->read = qoriq_read_be;
  399. ptp_qoriq->write = qoriq_write_be;
  400. }
  401. /* The eTSEC uses differnt memory map with DPAA/ENETC */
  402. if (of_device_is_compatible(node, "fsl,etsec-ptp")) {
  403. ptp_qoriq->regs.ctrl_regs = base + ETSEC_CTRL_REGS_OFFSET;
  404. ptp_qoriq->regs.alarm_regs = base + ETSEC_ALARM_REGS_OFFSET;
  405. ptp_qoriq->regs.fiper_regs = base + ETSEC_FIPER_REGS_OFFSET;
  406. ptp_qoriq->regs.etts_regs = base + ETSEC_ETTS_REGS_OFFSET;
  407. } else {
  408. ptp_qoriq->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
  409. ptp_qoriq->regs.alarm_regs = base + ALARM_REGS_OFFSET;
  410. ptp_qoriq->regs.fiper_regs = base + FIPER_REGS_OFFSET;
  411. ptp_qoriq->regs.etts_regs = base + ETTS_REGS_OFFSET;
  412. }
  413. spin_lock_init(&ptp_qoriq->lock);
  414. ktime_get_real_ts64(&now);
  415. ptp_qoriq_settime(&ptp_qoriq->caps, &now);
  416. tmr_ctrl =
  417. (ptp_qoriq->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
  418. (ptp_qoriq->cksel & CKSEL_MASK) << CKSEL_SHIFT;
  419. spin_lock_irqsave(&ptp_qoriq->lock, flags);
  420. regs = &ptp_qoriq->regs;
  421. ptp_qoriq->write(&regs->ctrl_regs->tmr_ctrl, tmr_ctrl);
  422. ptp_qoriq->write(&regs->ctrl_regs->tmr_add, ptp_qoriq->tmr_add);
  423. ptp_qoriq->write(&regs->ctrl_regs->tmr_prsc, ptp_qoriq->tmr_prsc);
  424. ptp_qoriq->write(&regs->fiper_regs->tmr_fiper1, ptp_qoriq->tmr_fiper1);
  425. ptp_qoriq->write(&regs->fiper_regs->tmr_fiper2, ptp_qoriq->tmr_fiper2);
  426. if (ptp_qoriq->fiper3_support)
  427. ptp_qoriq->write(&regs->fiper_regs->tmr_fiper3,
  428. ptp_qoriq->tmr_fiper3);
  429. set_alarm(ptp_qoriq);
  430. ptp_qoriq->write(&regs->ctrl_regs->tmr_ctrl,
  431. tmr_ctrl|FIPERST|RTPE|TE|FRD);
  432. spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
  433. ptp_qoriq->clock = ptp_clock_register(&ptp_qoriq->caps, ptp_qoriq->dev);
  434. if (IS_ERR(ptp_qoriq->clock))
  435. return PTR_ERR(ptp_qoriq->clock);
  436. ptp_qoriq->phc_index = ptp_clock_index(ptp_qoriq->clock);
  437. ptp_qoriq_create_debugfs(ptp_qoriq);
  438. return 0;
  439. }
  440. EXPORT_SYMBOL_GPL(ptp_qoriq_init);
  441. void ptp_qoriq_free(struct ptp_qoriq *ptp_qoriq)
  442. {
  443. struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
  444. ptp_qoriq->write(&regs->ctrl_regs->tmr_temask, 0);
  445. ptp_qoriq->write(&regs->ctrl_regs->tmr_ctrl, 0);
  446. ptp_qoriq_remove_debugfs(ptp_qoriq);
  447. ptp_clock_unregister(ptp_qoriq->clock);
  448. iounmap(ptp_qoriq->base);
  449. free_irq(ptp_qoriq->irq, ptp_qoriq);
  450. }
  451. EXPORT_SYMBOL_GPL(ptp_qoriq_free);
  452. static int ptp_qoriq_probe(struct platform_device *dev)
  453. {
  454. struct ptp_qoriq *ptp_qoriq;
  455. int err = -ENOMEM;
  456. void __iomem *base;
  457. ptp_qoriq = kzalloc(sizeof(*ptp_qoriq), GFP_KERNEL);
  458. if (!ptp_qoriq)
  459. goto no_memory;
  460. ptp_qoriq->dev = &dev->dev;
  461. err = -ENODEV;
  462. ptp_qoriq->irq = platform_get_irq(dev, 0);
  463. if (ptp_qoriq->irq < 0) {
  464. pr_err("irq not in device tree\n");
  465. goto no_node;
  466. }
  467. if (request_irq(ptp_qoriq->irq, ptp_qoriq_isr, IRQF_SHARED,
  468. DRIVER, ptp_qoriq)) {
  469. pr_err("request_irq failed\n");
  470. goto no_node;
  471. }
  472. ptp_qoriq->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
  473. if (!ptp_qoriq->rsrc) {
  474. pr_err("no resource\n");
  475. goto no_resource;
  476. }
  477. if (request_resource(&iomem_resource, ptp_qoriq->rsrc)) {
  478. pr_err("resource busy\n");
  479. goto no_resource;
  480. }
  481. base = ioremap(ptp_qoriq->rsrc->start,
  482. resource_size(ptp_qoriq->rsrc));
  483. if (!base) {
  484. pr_err("ioremap ptp registers failed\n");
  485. goto no_ioremap;
  486. }
  487. err = ptp_qoriq_init(ptp_qoriq, base, &ptp_qoriq_caps);
  488. if (err)
  489. goto no_clock;
  490. platform_set_drvdata(dev, ptp_qoriq);
  491. return 0;
  492. no_clock:
  493. iounmap(ptp_qoriq->base);
  494. no_ioremap:
  495. release_resource(ptp_qoriq->rsrc);
  496. no_resource:
  497. free_irq(ptp_qoriq->irq, ptp_qoriq);
  498. no_node:
  499. kfree(ptp_qoriq);
  500. no_memory:
  501. return err;
  502. }
  503. static int ptp_qoriq_remove(struct platform_device *dev)
  504. {
  505. struct ptp_qoriq *ptp_qoriq = platform_get_drvdata(dev);
  506. ptp_qoriq_free(ptp_qoriq);
  507. release_resource(ptp_qoriq->rsrc);
  508. kfree(ptp_qoriq);
  509. return 0;
  510. }
  511. static const struct of_device_id match_table[] = {
  512. { .compatible = "fsl,etsec-ptp" },
  513. { .compatible = "fsl,fman-ptp-timer" },
  514. {},
  515. };
  516. MODULE_DEVICE_TABLE(of, match_table);
  517. static struct platform_driver ptp_qoriq_driver = {
  518. .driver = {
  519. .name = "ptp_qoriq",
  520. .of_match_table = match_table,
  521. },
  522. .probe = ptp_qoriq_probe,
  523. .remove = ptp_qoriq_remove,
  524. };
  525. module_platform_driver(ptp_qoriq_driver);
  526. MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
  527. MODULE_DESCRIPTION("PTP clock for Freescale QorIQ 1588 timer");
  528. MODULE_LICENSE("GPL");