ptp_idt82p33.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
  4. *
  5. * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
  6. */
  7. #ifndef PTP_IDT82P33_H
  8. #define PTP_IDT82P33_H
  9. #include <linux/ktime.h>
  10. #include <linux/workqueue.h>
  11. /* Register Map - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf */
  12. #define PAGE_NUM (8)
  13. #define _ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
  14. #define _PAGE(addr) (((addr) >> 0x7) & 0x7)
  15. #define _OFFSET(addr) ((addr) & 0x7f)
  16. #define DPLL1_TOD_CNFG 0x134
  17. #define DPLL2_TOD_CNFG 0x1B4
  18. #define DPLL1_TOD_STS 0x10B
  19. #define DPLL2_TOD_STS 0x18B
  20. #define DPLL1_TOD_TRIGGER 0x115
  21. #define DPLL2_TOD_TRIGGER 0x195
  22. #define DPLL1_OPERATING_MODE_CNFG 0x120
  23. #define DPLL2_OPERATING_MODE_CNFG 0x1A0
  24. #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
  25. #define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
  26. #define DPLL1_PHASE_OFFSET_CNFG 0x143
  27. #define DPLL2_PHASE_OFFSET_CNFG 0x1C3
  28. #define DPLL1_SYNC_EDGE_CNFG 0X140
  29. #define DPLL2_SYNC_EDGE_CNFG 0X1C0
  30. #define DPLL1_INPUT_MODE_CNFG 0X116
  31. #define DPLL2_INPUT_MODE_CNFG 0X196
  32. #define OUT_MUX_CNFG(outn) _ADDR(0x6, (0xC * (outn)))
  33. #define PAGE_ADDR 0x7F
  34. /* Register Map end */
  35. /* Register definitions - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf*/
  36. #define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
  37. #define SYNC_TOD BIT(1)
  38. #define PH_OFFSET_EN BIT(7)
  39. #define SQUELCH_ENABLE BIT(5)
  40. /* Bit definitions for the DPLL_MODE register */
  41. #define PLL_MODE_SHIFT (0)
  42. #define PLL_MODE_MASK (0x1F)
  43. enum pll_mode {
  44. PLL_MODE_MIN = 0,
  45. PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
  46. PLL_MODE_FORCE_FREERUN = 1,
  47. PLL_MODE_FORCE_HOLDOVER = 2,
  48. PLL_MODE_FORCE_LOCKED = 4,
  49. PLL_MODE_FORCE_PRE_LOCKED2 = 5,
  50. PLL_MODE_FORCE_PRE_LOCKED = 6,
  51. PLL_MODE_FORCE_LOST_PHASE = 7,
  52. PLL_MODE_DCO = 10,
  53. PLL_MODE_WPH = 18,
  54. PLL_MODE_MAX = PLL_MODE_WPH,
  55. };
  56. enum hw_tod_trig_sel {
  57. HW_TOD_TRIG_SEL_MIN = 0,
  58. HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
  59. HW_TOD_TRIG_SEL_SYNC_SEL = 1,
  60. HW_TOD_TRIG_SEL_IN12 = 2,
  61. HW_TOD_TRIG_SEL_IN13 = 3,
  62. HW_TOD_TRIG_SEL_IN14 = 4,
  63. HW_TOD_TRIG_SEL_TOD_PPS = 5,
  64. HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
  65. HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
  66. HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
  67. HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
  68. HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
  69. WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
  70. };
  71. /* Register bit definitions end */
  72. #define FW_FILENAME "idt82p33xxx.bin"
  73. #define MAX_PHC_PLL (2)
  74. #define TOD_BYTE_COUNT (10)
  75. #define MAX_MEASURMENT_COUNT (5)
  76. #define SNAP_THRESHOLD_NS (150000)
  77. #define SYNC_TOD_TIMEOUT_SEC (5)
  78. #define PLLMASK_ADDR_HI 0xFF
  79. #define PLLMASK_ADDR_LO 0xA5
  80. #define PLL0_OUTMASK_ADDR_HI 0xFF
  81. #define PLL0_OUTMASK_ADDR_LO 0xB0
  82. #define PLL1_OUTMASK_ADDR_HI 0xFF
  83. #define PLL1_OUTMASK_ADDR_LO 0xB2
  84. #define PLL2_OUTMASK_ADDR_HI 0xFF
  85. #define PLL2_OUTMASK_ADDR_LO 0xB4
  86. #define PLL3_OUTMASK_ADDR_HI 0xFF
  87. #define PLL3_OUTMASK_ADDR_LO 0xB6
  88. #define DEFAULT_PLL_MASK (0x01)
  89. #define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
  90. #define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
  91. /* PTP Hardware Clock interface */
  92. struct idt82p33_channel {
  93. struct ptp_clock_info caps;
  94. struct ptp_clock *ptp_clock;
  95. struct idt82p33 *idt82p33;
  96. enum pll_mode pll_mode;
  97. /* task to turn off SYNC_TOD bit after pps sync */
  98. struct delayed_work sync_tod_work;
  99. bool sync_tod_on;
  100. s32 current_freq_ppb;
  101. u8 output_mask;
  102. u16 dpll_tod_cnfg;
  103. u16 dpll_tod_trigger;
  104. u16 dpll_tod_sts;
  105. u16 dpll_mode_cnfg;
  106. u16 dpll_freq_cnfg;
  107. u16 dpll_phase_cnfg;
  108. u16 dpll_sync_cnfg;
  109. u16 dpll_input_mode_cnfg;
  110. };
  111. struct idt82p33 {
  112. struct idt82p33_channel channel[MAX_PHC_PLL];
  113. struct i2c_client *client;
  114. u8 page_offset;
  115. u8 pll_mask;
  116. ktime_t start_time;
  117. int calculate_overhead_flag;
  118. s64 tod_write_overhead_ns;
  119. /* Protects I2C read/modify/write registers from concurrent access */
  120. struct mutex reg_lock;
  121. };
  122. /* firmware interface */
  123. struct idt82p33_fwrc {
  124. u8 hiaddr;
  125. u8 loaddr;
  126. u8 value;
  127. u8 reserved;
  128. } __packed;
  129. /**
  130. * @brief Maximum absolute value for write phase offset in femtoseconds
  131. */
  132. #define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
  133. /** @brief Phase offset resolution
  134. *
  135. * DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
  136. * = 10^15 fs / ( 1638400000 * 2^23)
  137. * = 74.5058059692382 fs
  138. */
  139. #define IDT_T0DPLL_PHASE_RESOL 74506
  140. #endif /* PTP_IDT82P33_H */