idt8a340_reg.h 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* idt8a340_reg.h
  3. *
  4. * Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019
  5. * https://github.com/richardcochran/regen
  6. *
  7. * Hand modified to include some HW registers.
  8. * Based on 4.8.0, SCSR rev C commit a03c7ae5
  9. */
  10. #ifndef HAVE_IDT8A340_REG
  11. #define HAVE_IDT8A340_REG
  12. #define PAGE_ADDR_BASE 0x0000
  13. #define PAGE_ADDR 0x00fc
  14. #define HW_REVISION 0x8180
  15. #define REV_ID 0x007a
  16. #define HW_DPLL_0 (0x8a00)
  17. #define HW_DPLL_1 (0x8b00)
  18. #define HW_DPLL_2 (0x8c00)
  19. #define HW_DPLL_3 (0x8d00)
  20. #define HW_DPLL_4 (0x8e00)
  21. #define HW_DPLL_5 (0x8f00)
  22. #define HW_DPLL_6 (0x9000)
  23. #define HW_DPLL_7 (0x9100)
  24. #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
  25. #define HW_DPLL_TOD_CTRL_1 (0x089)
  26. #define HW_DPLL_TOD_CTRL_2 (0x08A)
  27. #define HW_DPLL_TOD_OVR__0 (0x098)
  28. #define HW_DPLL_TOD_OUT_0__0 (0x0B0)
  29. #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740)
  30. #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741)
  31. #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742)
  32. #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743)
  33. #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744)
  34. #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745)
  35. #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746)
  36. #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747)
  37. #define HW_Q8_CH_SYNC_CTRL_0 (0xa748)
  38. #define HW_Q8_CH_SYNC_CTRL_1 (0xa749)
  39. #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a)
  40. #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b)
  41. #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c)
  42. #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d)
  43. #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e)
  44. #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f)
  45. #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14
  46. #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15
  47. #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16
  48. #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17
  49. #define SYNCTRL1_MASTER_SYNC_RST BIT(7)
  50. #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5)
  51. #define SYNCTRL1_TOD_SYNC_TRIG BIT(4)
  52. #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3)
  53. #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2)
  54. #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
  55. #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
  56. #define HW_Q8_CTRL_SPARE (0xa7d4)
  57. #define HW_Q11_CTRL_SPARE (0xa7ec)
  58. /**
  59. * Select FOD5 as sync_trigger for Q8 divider.
  60. * Transition from logic zero to one
  61. * sets trigger to sync Q8 divider.
  62. *
  63. * Unused when FOD4 is driving Q8 divider (normal operation).
  64. */
  65. #define Q9_TO_Q8_SYNC_TRIG BIT(1)
  66. /**
  67. * Enable FOD5 as driver for clock and sync for Q8 divider.
  68. * Enable fanout buffer for FOD5.
  69. *
  70. * Unused when FOD4 is driving Q8 divider (normal operation).
  71. */
  72. #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
  73. /**
  74. * Select FOD6 as sync_trigger for Q11 divider.
  75. * Transition from logic zero to one
  76. * sets trigger to sync Q11 divider.
  77. *
  78. * Unused when FOD7 is driving Q11 divider (normal operation).
  79. */
  80. #define Q10_TO_Q11_SYNC_TRIG BIT(1)
  81. /**
  82. * Enable FOD6 as driver for clock and sync for Q11 divider.
  83. * Enable fanout buffer for FOD6.
  84. *
  85. * Unused when FOD7 is driving Q11 divider (normal operation).
  86. */
  87. #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
  88. #define RESET_CTRL 0xc000
  89. #define SM_RESET 0x0012
  90. #define SM_RESET_CMD 0x5A
  91. #define GENERAL_STATUS 0xc014
  92. #define HW_REV_ID 0x000A
  93. #define BOND_ID 0x000B
  94. #define HW_CSR_ID 0x000C
  95. #define HW_IRQ_ID 0x000E
  96. #define MAJ_REL 0x0010
  97. #define MIN_REL 0x0011
  98. #define HOTFIX_REL 0x0012
  99. #define PIPELINE_ID 0x0014
  100. #define BUILD_ID 0x0018
  101. #define JTAG_DEVICE_ID 0x001c
  102. #define PRODUCT_ID 0x001e
  103. #define OTP_SCSR_CONFIG_SELECT 0x0022
  104. #define STATUS 0xc03c
  105. #define USER_GPIO0_TO_7_STATUS 0x008a
  106. #define USER_GPIO8_TO_15_STATUS 0x008b
  107. #define GPIO_USER_CONTROL 0xc160
  108. #define GPIO0_TO_7_OUT 0x0000
  109. #define GPIO8_TO_15_OUT 0x0001
  110. #define STICKY_STATUS_CLEAR 0xc164
  111. #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c
  112. #define ALERT_CFG 0xc188
  113. #define SYS_DPLL_XO 0xc194
  114. #define SYS_APLL 0xc19c
  115. #define INPUT_0 0xc1b0
  116. #define INPUT_1 0xc1c0
  117. #define INPUT_2 0xc1d0
  118. #define INPUT_3 0xc200
  119. #define INPUT_4 0xc210
  120. #define INPUT_5 0xc220
  121. #define INPUT_6 0xc230
  122. #define INPUT_7 0xc240
  123. #define INPUT_8 0xc250
  124. #define INPUT_9 0xc260
  125. #define INPUT_10 0xc280
  126. #define INPUT_11 0xc290
  127. #define INPUT_12 0xc2a0
  128. #define INPUT_13 0xc2b0
  129. #define INPUT_14 0xc2c0
  130. #define INPUT_15 0xc2d0
  131. #define REF_MON_0 0xc2e0
  132. #define REF_MON_1 0xc2ec
  133. #define REF_MON_2 0xc300
  134. #define REF_MON_3 0xc30c
  135. #define REF_MON_4 0xc318
  136. #define REF_MON_5 0xc324
  137. #define REF_MON_6 0xc330
  138. #define REF_MON_7 0xc33c
  139. #define REF_MON_8 0xc348
  140. #define REF_MON_9 0xc354
  141. #define REF_MON_10 0xc360
  142. #define REF_MON_11 0xc36c
  143. #define REF_MON_12 0xc380
  144. #define REF_MON_13 0xc38c
  145. #define REF_MON_14 0xc398
  146. #define REF_MON_15 0xc3a4
  147. #define DPLL_0 0xc3b0
  148. #define DPLL_CTRL_REG_0 0x0002
  149. #define DPLL_CTRL_REG_1 0x0003
  150. #define DPLL_CTRL_REG_2 0x0004
  151. #define DPLL_TOD_SYNC_CFG 0x0031
  152. #define DPLL_COMBO_SLAVE_CFG_0 0x0032
  153. #define DPLL_COMBO_SLAVE_CFG_1 0x0033
  154. #define DPLL_SLAVE_REF_CFG 0x0034
  155. #define DPLL_REF_MODE 0x0035
  156. #define DPLL_PHASE_MEASUREMENT_CFG 0x0036
  157. #define DPLL_MODE 0x0037
  158. #define DPLL_1 0xc400
  159. #define DPLL_2 0xc438
  160. #define DPLL_3 0xc480
  161. #define DPLL_4 0xc4b8
  162. #define DPLL_5 0xc500
  163. #define DPLL_6 0xc538
  164. #define DPLL_7 0xc580
  165. #define SYS_DPLL 0xc5b8
  166. #define DPLL_CTRL_0 0xc600
  167. #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
  168. #define DPLL_CTRL_COMBO_MASTER_CFG 0x003a
  169. #define DPLL_CTRL_1 0xc63c
  170. #define DPLL_CTRL_2 0xc680
  171. #define DPLL_CTRL_3 0xc6bc
  172. #define DPLL_CTRL_4 0xc700
  173. #define DPLL_CTRL_5 0xc73c
  174. #define DPLL_CTRL_6 0xc780
  175. #define DPLL_CTRL_7 0xc7bc
  176. #define SYS_DPLL_CTRL 0xc800
  177. #define DPLL_PHASE_0 0xc818
  178. /* Signed 42-bit FFO in units of 2^(-53) */
  179. #define DPLL_WR_PHASE 0x0000
  180. #define DPLL_PHASE_1 0xc81c
  181. #define DPLL_PHASE_2 0xc820
  182. #define DPLL_PHASE_3 0xc824
  183. #define DPLL_PHASE_4 0xc828
  184. #define DPLL_PHASE_5 0xc82c
  185. #define DPLL_PHASE_6 0xc830
  186. #define DPLL_PHASE_7 0xc834
  187. #define DPLL_FREQ_0 0xc838
  188. /* Signed 42-bit FFO in units of 2^(-53) */
  189. #define DPLL_WR_FREQ 0x0000
  190. #define DPLL_FREQ_1 0xc840
  191. #define DPLL_FREQ_2 0xc848
  192. #define DPLL_FREQ_3 0xc850
  193. #define DPLL_FREQ_4 0xc858
  194. #define DPLL_FREQ_5 0xc860
  195. #define DPLL_FREQ_6 0xc868
  196. #define DPLL_FREQ_7 0xc870
  197. #define DPLL_PHASE_PULL_IN_0 0xc880
  198. #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */
  199. #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */
  200. #define PULL_IN_CTRL 0x0007
  201. #define DPLL_PHASE_PULL_IN_1 0xc888
  202. #define DPLL_PHASE_PULL_IN_2 0xc890
  203. #define DPLL_PHASE_PULL_IN_3 0xc898
  204. #define DPLL_PHASE_PULL_IN_4 0xc8a0
  205. #define DPLL_PHASE_PULL_IN_5 0xc8a8
  206. #define DPLL_PHASE_PULL_IN_6 0xc8b0
  207. #define DPLL_PHASE_PULL_IN_7 0xc8b8
  208. #define GPIO_CFG 0xc8c0
  209. #define GPIO_CFG_GBL 0x0000
  210. #define GPIO_0 0xc8c2
  211. #define GPIO_DCO_INC_DEC 0x0000
  212. #define GPIO_OUT_CTRL_0 0x0001
  213. #define GPIO_OUT_CTRL_1 0x0002
  214. #define GPIO_TOD_TRIG 0x0003
  215. #define GPIO_DPLL_INDICATOR 0x0004
  216. #define GPIO_LOS_INDICATOR 0x0005
  217. #define GPIO_REF_INPUT_DSQ_0 0x0006
  218. #define GPIO_REF_INPUT_DSQ_1 0x0007
  219. #define GPIO_REF_INPUT_DSQ_2 0x0008
  220. #define GPIO_REF_INPUT_DSQ_3 0x0009
  221. #define GPIO_MAN_CLK_SEL_0 0x000a
  222. #define GPIO_MAN_CLK_SEL_1 0x000b
  223. #define GPIO_MAN_CLK_SEL_2 0x000c
  224. #define GPIO_SLAVE 0x000d
  225. #define GPIO_ALERT_OUT_CFG 0x000e
  226. #define GPIO_TOD_NOTIFICATION_CFG 0x000f
  227. #define GPIO_CTRL 0x0010
  228. #define GPIO_1 0xc8d4
  229. #define GPIO_2 0xc8e6
  230. #define GPIO_3 0xc900
  231. #define GPIO_4 0xc912
  232. #define GPIO_5 0xc924
  233. #define GPIO_6 0xc936
  234. #define GPIO_7 0xc948
  235. #define GPIO_8 0xc95a
  236. #define GPIO_9 0xc980
  237. #define GPIO_10 0xc992
  238. #define GPIO_11 0xc9a4
  239. #define GPIO_12 0xc9b6
  240. #define GPIO_13 0xc9c8
  241. #define GPIO_14 0xc9da
  242. #define GPIO_15 0xca00
  243. #define OUT_DIV_MUX 0xca12
  244. #define OUTPUT_0 0xca14
  245. /* FOD frequency output divider value */
  246. #define OUT_DIV 0x0000
  247. #define OUT_DUTY_CYCLE_HIGH 0x0004
  248. #define OUT_CTRL_0 0x0008
  249. #define OUT_CTRL_1 0x0009
  250. /* Phase adjustment in FOD cycles */
  251. #define OUT_PHASE_ADJ 0x000c
  252. #define OUTPUT_1 0xca24
  253. #define OUTPUT_2 0xca34
  254. #define OUTPUT_3 0xca44
  255. #define OUTPUT_4 0xca54
  256. #define OUTPUT_5 0xca64
  257. #define OUTPUT_6 0xca80
  258. #define OUTPUT_7 0xca90
  259. #define OUTPUT_8 0xcaa0
  260. #define OUTPUT_9 0xcab0
  261. #define OUTPUT_10 0xcac0
  262. #define OUTPUT_11 0xcad0
  263. #define SERIAL 0xcae0
  264. #define PWM_ENCODER_0 0xcb00
  265. #define PWM_ENCODER_1 0xcb08
  266. #define PWM_ENCODER_2 0xcb10
  267. #define PWM_ENCODER_3 0xcb18
  268. #define PWM_ENCODER_4 0xcb20
  269. #define PWM_ENCODER_5 0xcb28
  270. #define PWM_ENCODER_6 0xcb30
  271. #define PWM_ENCODER_7 0xcb38
  272. #define PWM_DECODER_0 0xcb40
  273. #define PWM_DECODER_1 0xcb48
  274. #define PWM_DECODER_2 0xcb50
  275. #define PWM_DECODER_3 0xcb58
  276. #define PWM_DECODER_4 0xcb60
  277. #define PWM_DECODER_5 0xcb68
  278. #define PWM_DECODER_6 0xcb70
  279. #define PWM_DECODER_7 0xcb80
  280. #define PWM_DECODER_8 0xcb88
  281. #define PWM_DECODER_9 0xcb90
  282. #define PWM_DECODER_10 0xcb98
  283. #define PWM_DECODER_11 0xcba0
  284. #define PWM_DECODER_12 0xcba8
  285. #define PWM_DECODER_13 0xcbb0
  286. #define PWM_DECODER_14 0xcbb8
  287. #define PWM_DECODER_15 0xcbc0
  288. #define PWM_USER_DATA 0xcbc8
  289. #define TOD_0 0xcbcc
  290. /* Enable TOD counter, output channel sync and even-PPS mode */
  291. #define TOD_CFG 0x0000
  292. #define TOD_1 0xcbce
  293. #define TOD_2 0xcbd0
  294. #define TOD_3 0xcbd2
  295. #define TOD_WRITE_0 0xcc00
  296. /* 8-bit subns, 32-bit ns, 48-bit seconds */
  297. #define TOD_WRITE 0x0000
  298. /* Counter increments after TOD write is completed */
  299. #define TOD_WRITE_COUNTER 0x000c
  300. /* TOD write trigger configuration */
  301. #define TOD_WRITE_SELECT_CFG_0 0x000d
  302. /* TOD write trigger selection */
  303. #define TOD_WRITE_CMD 0x000f
  304. #define TOD_WRITE_1 0xcc10
  305. #define TOD_WRITE_2 0xcc20
  306. #define TOD_WRITE_3 0xcc30
  307. #define TOD_READ_PRIMARY_0 0xcc40
  308. /* 8-bit subns, 32-bit ns, 48-bit seconds */
  309. #define TOD_READ_PRIMARY 0x0000
  310. /* Counter increments after TOD write is completed */
  311. #define TOD_READ_PRIMARY_COUNTER 0x000b
  312. /* Read trigger configuration */
  313. #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c
  314. /* Read trigger selection */
  315. #define TOD_READ_PRIMARY_CMD 0x000e
  316. #define TOD_READ_PRIMARY_1 0xcc50
  317. #define TOD_READ_PRIMARY_2 0xcc60
  318. #define TOD_READ_PRIMARY_3 0xcc80
  319. #define TOD_READ_SECONDARY_0 0xcc90
  320. #define TOD_READ_SECONDARY_1 0xcca0
  321. #define TOD_READ_SECONDARY_2 0xccb0
  322. #define TOD_READ_SECONDARY_3 0xccc0
  323. #define OUTPUT_TDC_CFG 0xccd0
  324. #define OUTPUT_TDC_0 0xcd00
  325. #define OUTPUT_TDC_1 0xcd08
  326. #define OUTPUT_TDC_2 0xcd10
  327. #define OUTPUT_TDC_3 0xcd18
  328. #define INPUT_TDC 0xcd20
  329. #define SCRATCH 0xcf50
  330. #define EEPROM 0xcf68
  331. #define OTP 0xcf70
  332. #define BYTE 0xcf80
  333. /* Bit definitions for the MAJ_REL register */
  334. #define MAJOR_SHIFT (1)
  335. #define MAJOR_MASK (0x7f)
  336. #define PR_BUILD BIT(0)
  337. /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
  338. #define GPIO0_LEVEL BIT(0)
  339. #define GPIO1_LEVEL BIT(1)
  340. #define GPIO2_LEVEL BIT(2)
  341. #define GPIO3_LEVEL BIT(3)
  342. #define GPIO4_LEVEL BIT(4)
  343. #define GPIO5_LEVEL BIT(5)
  344. #define GPIO6_LEVEL BIT(6)
  345. #define GPIO7_LEVEL BIT(7)
  346. /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
  347. #define GPIO8_LEVEL BIT(0)
  348. #define GPIO9_LEVEL BIT(1)
  349. #define GPIO10_LEVEL BIT(2)
  350. #define GPIO11_LEVEL BIT(3)
  351. #define GPIO12_LEVEL BIT(4)
  352. #define GPIO13_LEVEL BIT(5)
  353. #define GPIO14_LEVEL BIT(6)
  354. #define GPIO15_LEVEL BIT(7)
  355. /* Bit definitions for the GPIO0_TO_7_OUT register */
  356. #define GPIO0_DRIVE_LEVEL BIT(0)
  357. #define GPIO1_DRIVE_LEVEL BIT(1)
  358. #define GPIO2_DRIVE_LEVEL BIT(2)
  359. #define GPIO3_DRIVE_LEVEL BIT(3)
  360. #define GPIO4_DRIVE_LEVEL BIT(4)
  361. #define GPIO5_DRIVE_LEVEL BIT(5)
  362. #define GPIO6_DRIVE_LEVEL BIT(6)
  363. #define GPIO7_DRIVE_LEVEL BIT(7)
  364. /* Bit definitions for the GPIO8_TO_15_OUT register */
  365. #define GPIO8_DRIVE_LEVEL BIT(0)
  366. #define GPIO9_DRIVE_LEVEL BIT(1)
  367. #define GPIO10_DRIVE_LEVEL BIT(2)
  368. #define GPIO11_DRIVE_LEVEL BIT(3)
  369. #define GPIO12_DRIVE_LEVEL BIT(4)
  370. #define GPIO13_DRIVE_LEVEL BIT(5)
  371. #define GPIO14_DRIVE_LEVEL BIT(6)
  372. #define GPIO15_DRIVE_LEVEL BIT(7)
  373. /* Bit definitions for the DPLL_TOD_SYNC_CFG register */
  374. #define TOD_SYNC_SOURCE_SHIFT (1)
  375. #define TOD_SYNC_SOURCE_MASK (0x3)
  376. #define TOD_SYNC_EN BIT(0)
  377. /* Bit definitions for the DPLL_MODE register */
  378. #define WRITE_TIMER_MODE BIT(6)
  379. #define PLL_MODE_SHIFT (3)
  380. #define PLL_MODE_MASK (0x7)
  381. #define STATE_MODE_SHIFT (0)
  382. #define STATE_MODE_MASK (0x7)
  383. /* Bit definitions for the GPIO_CFG_GBL register */
  384. #define SUPPLY_MODE_SHIFT (0)
  385. #define SUPPLY_MODE_MASK (0x3)
  386. /* Bit definitions for the GPIO_DCO_INC_DEC register */
  387. #define INCDEC_DPLL_INDEX_SHIFT (0)
  388. #define INCDEC_DPLL_INDEX_MASK (0x7)
  389. /* Bit definitions for the GPIO_OUT_CTRL_0 register */
  390. #define CTRL_OUT_0 BIT(0)
  391. #define CTRL_OUT_1 BIT(1)
  392. #define CTRL_OUT_2 BIT(2)
  393. #define CTRL_OUT_3 BIT(3)
  394. #define CTRL_OUT_4 BIT(4)
  395. #define CTRL_OUT_5 BIT(5)
  396. #define CTRL_OUT_6 BIT(6)
  397. #define CTRL_OUT_7 BIT(7)
  398. /* Bit definitions for the GPIO_OUT_CTRL_1 register */
  399. #define CTRL_OUT_8 BIT(0)
  400. #define CTRL_OUT_9 BIT(1)
  401. #define CTRL_OUT_10 BIT(2)
  402. #define CTRL_OUT_11 BIT(3)
  403. #define CTRL_OUT_12 BIT(4)
  404. #define CTRL_OUT_13 BIT(5)
  405. #define CTRL_OUT_14 BIT(6)
  406. #define CTRL_OUT_15 BIT(7)
  407. /* Bit definitions for the GPIO_TOD_TRIG register */
  408. #define TOD_TRIG_0 BIT(0)
  409. #define TOD_TRIG_1 BIT(1)
  410. #define TOD_TRIG_2 BIT(2)
  411. #define TOD_TRIG_3 BIT(3)
  412. /* Bit definitions for the GPIO_DPLL_INDICATOR register */
  413. #define IND_DPLL_INDEX_SHIFT (0)
  414. #define IND_DPLL_INDEX_MASK (0x7)
  415. /* Bit definitions for the GPIO_LOS_INDICATOR register */
  416. #define REFMON_INDEX_SHIFT (0)
  417. #define REFMON_INDEX_MASK (0xf)
  418. /* Active level of LOS indicator, 0=low 1=high */
  419. #define ACTIVE_LEVEL BIT(4)
  420. /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
  421. #define DSQ_INP_0 BIT(0)
  422. #define DSQ_INP_1 BIT(1)
  423. #define DSQ_INP_2 BIT(2)
  424. #define DSQ_INP_3 BIT(3)
  425. #define DSQ_INP_4 BIT(4)
  426. #define DSQ_INP_5 BIT(5)
  427. #define DSQ_INP_6 BIT(6)
  428. #define DSQ_INP_7 BIT(7)
  429. /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
  430. #define DSQ_INP_8 BIT(0)
  431. #define DSQ_INP_9 BIT(1)
  432. #define DSQ_INP_10 BIT(2)
  433. #define DSQ_INP_11 BIT(3)
  434. #define DSQ_INP_12 BIT(4)
  435. #define DSQ_INP_13 BIT(5)
  436. #define DSQ_INP_14 BIT(6)
  437. #define DSQ_INP_15 BIT(7)
  438. /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
  439. #define DSQ_DPLL_0 BIT(0)
  440. #define DSQ_DPLL_1 BIT(1)
  441. #define DSQ_DPLL_2 BIT(2)
  442. #define DSQ_DPLL_3 BIT(3)
  443. #define DSQ_DPLL_4 BIT(4)
  444. #define DSQ_DPLL_5 BIT(5)
  445. #define DSQ_DPLL_6 BIT(6)
  446. #define DSQ_DPLL_7 BIT(7)
  447. /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
  448. #define DSQ_DPLL_SYS BIT(0)
  449. #define GPIO_DSQ_LEVEL BIT(1)
  450. /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
  451. #define DPLL_TOD_SHIFT (0)
  452. #define DPLL_TOD_MASK (0x3)
  453. #define TOD_READ_SECONDARY BIT(2)
  454. #define GPIO_ASSERT_LEVEL BIT(3)
  455. /* Bit definitions for the GPIO_CTRL register */
  456. #define GPIO_FUNCTION_EN BIT(0)
  457. #define GPIO_CMOS_OD_MODE BIT(1)
  458. #define GPIO_CONTROL_DIR BIT(2)
  459. #define GPIO_PU_PD_MODE BIT(3)
  460. #define GPIO_FUNCTION_SHIFT (4)
  461. #define GPIO_FUNCTION_MASK (0xf)
  462. /* Bit definitions for the OUT_CTRL_1 register */
  463. #define OUT_SYNC_DISABLE BIT(7)
  464. #define SQUELCH_VALUE BIT(6)
  465. #define SQUELCH_DISABLE BIT(5)
  466. #define PAD_VDDO_SHIFT (2)
  467. #define PAD_VDDO_MASK (0x7)
  468. #define PAD_CMOSDRV_SHIFT (0)
  469. #define PAD_CMOSDRV_MASK (0x3)
  470. /* Bit definitions for the TOD_CFG register */
  471. #define TOD_EVEN_PPS_MODE BIT(2)
  472. #define TOD_OUT_SYNC_ENABLE BIT(1)
  473. #define TOD_ENABLE BIT(0)
  474. /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
  475. #define WR_PWM_DECODER_INDEX_SHIFT (4)
  476. #define WR_PWM_DECODER_INDEX_MASK (0xf)
  477. #define WR_REF_INDEX_SHIFT (0)
  478. #define WR_REF_INDEX_MASK (0xf)
  479. /* Bit definitions for the TOD_WRITE_CMD register */
  480. #define TOD_WRITE_SELECTION_SHIFT (0)
  481. #define TOD_WRITE_SELECTION_MASK (0xf)
  482. /* 4.8.7 */
  483. #define TOD_WRITE_TYPE_SHIFT (4)
  484. #define TOD_WRITE_TYPE_MASK (0x3)
  485. /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
  486. #define RD_PWM_DECODER_INDEX_SHIFT (4)
  487. #define RD_PWM_DECODER_INDEX_MASK (0xf)
  488. #define RD_REF_INDEX_SHIFT (0)
  489. #define RD_REF_INDEX_MASK (0xf)
  490. /* Bit definitions for the TOD_READ_PRIMARY_CMD register */
  491. #define TOD_READ_TRIGGER_MODE BIT(4)
  492. #define TOD_READ_TRIGGER_SHIFT (0)
  493. #define TOD_READ_TRIGGER_MASK (0xf)
  494. /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
  495. #define COMBO_MASTER_HOLD BIT(0)
  496. #endif