pinctrl-common.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020 TOSHIBA CORPORATION
  4. * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation
  5. * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
  6. */
  7. #include <linux/init.h>
  8. #include <linux/of.h>
  9. #include <linux/io.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include <linux/pinctrl/pinmux.h>
  13. #include <linux/pinctrl/pinconf.h>
  14. #include <linux/pinctrl/pinconf-generic.h>
  15. #include "pinctrl-common.h"
  16. #include "../core.h"
  17. #include "../pinconf.h"
  18. #include "../pinctrl-utils.h"
  19. #define DSEL_MASK GENMASK(3, 0)
  20. /* private data */
  21. struct visconti_pinctrl {
  22. void __iomem *base;
  23. struct device *dev;
  24. struct pinctrl_dev *pctl;
  25. struct pinctrl_desc pctl_desc;
  26. const struct visconti_pinctrl_devdata *devdata;
  27. spinlock_t lock; /* protect pinctrl register */
  28. };
  29. /* pinconf */
  30. static int visconti_pin_config_set(struct pinctrl_dev *pctldev,
  31. unsigned int _pin,
  32. unsigned long *configs,
  33. unsigned int num_configs)
  34. {
  35. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  36. const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin];
  37. enum pin_config_param param;
  38. unsigned int arg;
  39. int i, ret = 0;
  40. unsigned int val, set_val, pude_val;
  41. unsigned long flags;
  42. dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name);
  43. spin_lock_irqsave(&priv->lock, flags);
  44. for (i = 0; i < num_configs; i++) {
  45. set_val = 0;
  46. pude_val = 0;
  47. param = pinconf_to_config_param(configs[i]);
  48. switch (param) {
  49. case PIN_CONFIG_BIAS_PULL_UP:
  50. set_val = 1;
  51. fallthrough;
  52. case PIN_CONFIG_BIAS_PULL_DOWN:
  53. /* update pudsel setting */
  54. val = readl(priv->base + pin->pudsel_offset);
  55. val &= ~BIT(pin->pud_shift);
  56. val |= set_val << pin->pud_shift;
  57. writel(val, priv->base + pin->pudsel_offset);
  58. pude_val = 1;
  59. fallthrough;
  60. case PIN_CONFIG_BIAS_DISABLE:
  61. /* update pude setting */
  62. val = readl(priv->base + pin->pude_offset);
  63. val &= ~BIT(pin->pud_shift);
  64. val |= pude_val << pin->pud_shift;
  65. writel(val, priv->base + pin->pude_offset);
  66. dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n",
  67. param, pin->pude_offset, val);
  68. break;
  69. case PIN_CONFIG_DRIVE_STRENGTH:
  70. arg = pinconf_to_config_argument(configs[i]);
  71. dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg);
  72. switch (arg) {
  73. case 2:
  74. case 4:
  75. case 8:
  76. case 16:
  77. case 24:
  78. case 32:
  79. /*
  80. * I/O drive capacity setting:
  81. * 2mA: 0
  82. * 4mA: 1
  83. * 8mA: 3
  84. * 16mA: 7
  85. * 24mA: 11
  86. * 32mA: 15
  87. */
  88. set_val = DIV_ROUND_CLOSEST(arg, 2) - 1;
  89. break;
  90. default:
  91. ret = -EINVAL;
  92. goto err;
  93. }
  94. /* update drive setting */
  95. val = readl(priv->base + pin->dsel_offset);
  96. val &= ~(DSEL_MASK << pin->dsel_shift);
  97. val |= set_val << pin->dsel_shift;
  98. writel(val, priv->base + pin->dsel_offset);
  99. break;
  100. default:
  101. ret = -EOPNOTSUPP;
  102. goto err;
  103. }
  104. }
  105. err:
  106. spin_unlock_irqrestore(&priv->lock, flags);
  107. return ret;
  108. }
  109. static int visconti_pin_config_group_set(struct pinctrl_dev *pctldev,
  110. unsigned int selector,
  111. unsigned long *configs,
  112. unsigned int num_configs)
  113. {
  114. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  115. const unsigned int *pins;
  116. unsigned int num_pins;
  117. int i, ret;
  118. pins = priv->devdata->groups[selector].pins;
  119. num_pins = priv->devdata->groups[selector].nr_pins;
  120. dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n",
  121. __func__, selector, num_pins, num_configs);
  122. for (i = 0; i < num_pins; i++) {
  123. ret = visconti_pin_config_set(pctldev, pins[i],
  124. configs, num_configs);
  125. if (ret)
  126. return ret;
  127. }
  128. return 0;
  129. }
  130. static const struct pinconf_ops visconti_pinconf_ops = {
  131. .is_generic = true,
  132. .pin_config_set = visconti_pin_config_set,
  133. .pin_config_group_set = visconti_pin_config_group_set,
  134. .pin_config_config_dbg_show = pinconf_generic_dump_config,
  135. };
  136. /* pinctrl */
  137. static int visconti_get_groups_count(struct pinctrl_dev *pctldev)
  138. {
  139. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  140. return priv->devdata->nr_groups;
  141. }
  142. static const char *visconti_get_group_name(struct pinctrl_dev *pctldev,
  143. unsigned int selector)
  144. {
  145. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  146. return priv->devdata->groups[selector].name;
  147. }
  148. static int visconti_get_group_pins(struct pinctrl_dev *pctldev,
  149. unsigned int selector,
  150. const unsigned int **pins,
  151. unsigned int *num_pins)
  152. {
  153. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  154. *pins = priv->devdata->groups[selector].pins;
  155. *num_pins = priv->devdata->groups[selector].nr_pins;
  156. return 0;
  157. }
  158. static const struct pinctrl_ops visconti_pinctrl_ops = {
  159. .get_groups_count = visconti_get_groups_count,
  160. .get_group_name = visconti_get_group_name,
  161. .get_group_pins = visconti_get_group_pins,
  162. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  163. .dt_free_map = pinctrl_utils_free_map,
  164. };
  165. /* pinmux */
  166. static int visconti_get_functions_count(struct pinctrl_dev *pctldev)
  167. {
  168. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  169. return priv->devdata->nr_functions;
  170. }
  171. static const char *visconti_get_function_name(struct pinctrl_dev *pctldev,
  172. unsigned int selector)
  173. {
  174. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  175. return priv->devdata->functions[selector].name;
  176. }
  177. static int visconti_get_function_groups(struct pinctrl_dev *pctldev,
  178. unsigned int selector,
  179. const char * const **groups,
  180. unsigned * const num_groups)
  181. {
  182. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  183. *groups = priv->devdata->functions[selector].groups;
  184. *num_groups = priv->devdata->functions[selector].nr_groups;
  185. return 0;
  186. }
  187. static int visconti_set_mux(struct pinctrl_dev *pctldev,
  188. unsigned int function, unsigned int group)
  189. {
  190. struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
  191. const struct visconti_pin_function *func = &priv->devdata->functions[function];
  192. const struct visconti_pin_group *grp = &priv->devdata->groups[group];
  193. const struct visconti_mux *mux = &grp->mux;
  194. unsigned int val;
  195. unsigned long flags;
  196. dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__,
  197. function, func->name, group, grp->name);
  198. spin_lock_irqsave(&priv->lock, flags);
  199. /* update mux */
  200. val = readl(priv->base + mux->offset);
  201. val &= ~mux->mask;
  202. val |= mux->val;
  203. writel(val, priv->base + mux->offset);
  204. spin_unlock_irqrestore(&priv->lock, flags);
  205. dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val);
  206. return 0;
  207. }
  208. static const struct pinmux_ops visconti_pinmux_ops = {
  209. .get_functions_count = visconti_get_functions_count,
  210. .get_function_name = visconti_get_function_name,
  211. .get_function_groups = visconti_get_function_groups,
  212. .set_mux = visconti_set_mux,
  213. .strict = true,
  214. };
  215. int visconti_pinctrl_probe(struct platform_device *pdev,
  216. const struct visconti_pinctrl_devdata *devdata)
  217. {
  218. struct device *dev = &pdev->dev;
  219. struct visconti_pinctrl *priv;
  220. struct pinctrl_pin_desc *pins;
  221. int i, ret;
  222. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  223. if (!priv)
  224. return -ENOMEM;
  225. priv->dev = dev;
  226. priv->devdata = devdata;
  227. spin_lock_init(&priv->lock);
  228. priv->base = devm_platform_ioremap_resource(pdev, 0);
  229. if (IS_ERR(priv->base)) {
  230. dev_err(dev, "unable to map I/O space\n");
  231. return PTR_ERR(priv->base);
  232. }
  233. pins = devm_kcalloc(dev, devdata->nr_pins,
  234. sizeof(*pins), GFP_KERNEL);
  235. if (!pins)
  236. return -ENOMEM;
  237. for (i = 0; i < devdata->nr_pins; i++)
  238. pins[i] = devdata->pins[i].pin;
  239. priv->pctl_desc.name = dev_name(dev);
  240. priv->pctl_desc.owner = THIS_MODULE;
  241. priv->pctl_desc.pins = pins;
  242. priv->pctl_desc.npins = devdata->nr_pins;
  243. priv->pctl_desc.confops = &visconti_pinconf_ops;
  244. priv->pctl_desc.pctlops = &visconti_pinctrl_ops;
  245. priv->pctl_desc.pmxops = &visconti_pinmux_ops;
  246. ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc,
  247. priv, &priv->pctl);
  248. if (ret) {
  249. dev_err(dev, "couldn't register pinctrl: %d\n", ret);
  250. return ret;
  251. }
  252. if (devdata->unlock)
  253. devdata->unlock(priv->base);
  254. return pinctrl_enable(priv->pctl);
  255. }