pinctrl-tegra210.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Pinctrl data for the NVIDIA Tegra210 pinmux
  4. *
  5. * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/init.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/pinctrl/pinctrl.h>
  11. #include <linux/pinctrl/pinmux.h>
  12. #include "pinctrl-tegra.h"
  13. /*
  14. * Most pins affected by the pinmux can also be GPIOs. Define these first.
  15. * These must match how the GPIO driver names/numbers its pins.
  16. */
  17. #define _GPIO(offset) (offset)
  18. #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
  19. #define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
  20. #define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2)
  21. #define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3)
  22. #define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4)
  23. #define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5)
  24. #define TEGRA_PIN_PA6 _GPIO(6)
  25. #define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8)
  26. #define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9)
  27. #define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10)
  28. #define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11)
  29. #define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12)
  30. #define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13)
  31. #define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14)
  32. #define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15)
  33. #define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16)
  34. #define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17)
  35. #define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18)
  36. #define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19)
  37. #define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20)
  38. #define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21)
  39. #define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22)
  40. #define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23)
  41. #define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24)
  42. #define TEGRA_PIN_UART3_TX_PD1 _GPIO(25)
  43. #define TEGRA_PIN_UART3_RX_PD2 _GPIO(26)
  44. #define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27)
  45. #define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28)
  46. #define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32)
  47. #define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33)
  48. #define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34)
  49. #define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35)
  50. #define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36)
  51. #define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37)
  52. #define TEGRA_PIN_PE6 _GPIO(38)
  53. #define TEGRA_PIN_PE7 _GPIO(39)
  54. #define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40)
  55. #define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41)
  56. #define TEGRA_PIN_UART2_TX_PG0 _GPIO(48)
  57. #define TEGRA_PIN_UART2_RX_PG1 _GPIO(49)
  58. #define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50)
  59. #define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51)
  60. #define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56)
  61. #define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57)
  62. #define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58)
  63. #define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59)
  64. #define TEGRA_PIN_BT_RST_PH4 _GPIO(60)
  65. #define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61)
  66. #define TEGRA_PIN_PH6 _GPIO(62)
  67. #define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63)
  68. #define TEGRA_PIN_NFC_EN_PI0 _GPIO(64)
  69. #define TEGRA_PIN_NFC_INT_PI1 _GPIO(65)
  70. #define TEGRA_PIN_GPS_EN_PI2 _GPIO(66)
  71. #define TEGRA_PIN_GPS_RST_PI3 _GPIO(67)
  72. #define TEGRA_PIN_UART4_TX_PI4 _GPIO(68)
  73. #define TEGRA_PIN_UART4_RX_PI5 _GPIO(69)
  74. #define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70)
  75. #define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71)
  76. #define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72)
  77. #define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73)
  78. #define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74)
  79. #define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75)
  80. #define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76)
  81. #define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77)
  82. #define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78)
  83. #define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79)
  84. #define TEGRA_PIN_PK0 _GPIO(80)
  85. #define TEGRA_PIN_PK1 _GPIO(81)
  86. #define TEGRA_PIN_PK2 _GPIO(82)
  87. #define TEGRA_PIN_PK3 _GPIO(83)
  88. #define TEGRA_PIN_PK4 _GPIO(84)
  89. #define TEGRA_PIN_PK5 _GPIO(85)
  90. #define TEGRA_PIN_PK6 _GPIO(86)
  91. #define TEGRA_PIN_PK7 _GPIO(87)
  92. #define TEGRA_PIN_PL0 _GPIO(88)
  93. #define TEGRA_PIN_PL1 _GPIO(89)
  94. #define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96)
  95. #define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97)
  96. #define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98)
  97. #define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99)
  98. #define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100)
  99. #define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101)
  100. #define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120)
  101. #define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121)
  102. #define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122)
  103. #define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123)
  104. #define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124)
  105. #define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125)
  106. #define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144)
  107. #define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145)
  108. #define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146)
  109. #define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147)
  110. #define TEGRA_PIN_CAM_RST_PS4 _GPIO(148)
  111. #define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149)
  112. #define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150)
  113. #define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151)
  114. #define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152)
  115. #define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153)
  116. #define TEGRA_PIN_UART1_TX_PU0 _GPIO(160)
  117. #define TEGRA_PIN_UART1_RX_PU1 _GPIO(161)
  118. #define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162)
  119. #define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163)
  120. #define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168)
  121. #define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169)
  122. #define TEGRA_PIN_LCD_RST_PV2 _GPIO(170)
  123. #define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171)
  124. #define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172)
  125. #define TEGRA_PIN_AP_READY_PV5 _GPIO(173)
  126. #define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174)
  127. #define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175)
  128. #define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184)
  129. #define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185)
  130. #define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186)
  131. #define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187)
  132. #define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188)
  133. #define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189)
  134. #define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190)
  135. #define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191)
  136. #define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192)
  137. #define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193)
  138. #define TEGRA_PIN_LCD_TE_PY2 _GPIO(194)
  139. #define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195)
  140. #define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196)
  141. #define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197)
  142. #define TEGRA_PIN_PZ0 _GPIO(200)
  143. #define TEGRA_PIN_PZ1 _GPIO(201)
  144. #define TEGRA_PIN_PZ2 _GPIO(202)
  145. #define TEGRA_PIN_PZ3 _GPIO(203)
  146. #define TEGRA_PIN_PZ4 _GPIO(204)
  147. #define TEGRA_PIN_PZ5 _GPIO(205)
  148. #define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208)
  149. #define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209)
  150. #define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210)
  151. #define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211)
  152. #define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216)
  153. #define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217)
  154. #define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218)
  155. #define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219)
  156. #define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220)
  157. #define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224)
  158. #define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225)
  159. #define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226)
  160. #define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227)
  161. #define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228)
  162. #define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229)
  163. #define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230)
  164. #define TEGRA_PIN_PCC7 _GPIO(231)
  165. #define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232)
  166. #define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240)
  167. #define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241)
  168. #define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242)
  169. #define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243)
  170. #define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244)
  171. #define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245)
  172. /* All non-GPIO pins follow */
  173. #define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
  174. #define _PIN(offset) (NUM_GPIOS + (offset))
  175. /* Non-GPIO pins */
  176. #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
  177. #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
  178. #define TEGRA_PIN_PWR_INT_N _PIN(2)
  179. #define TEGRA_PIN_CLK_32K_IN _PIN(3)
  180. #define TEGRA_PIN_JTAG_RTCK _PIN(4)
  181. #define TEGRA_PIN_BATT_BCL _PIN(5)
  182. #define TEGRA_PIN_CLK_REQ _PIN(6)
  183. #define TEGRA_PIN_SHUTDOWN _PIN(7)
  184. static const struct pinctrl_pin_desc tegra210_pins[] = {
  185. PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0"),
  186. PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1"),
  187. PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2"),
  188. PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3"),
  189. PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4"),
  190. PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5"),
  191. PINCTRL_PIN(TEGRA_PIN_PA6, "PA6"),
  192. PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0"),
  193. PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1"),
  194. PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2"),
  195. PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3"),
  196. PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4"),
  197. PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5"),
  198. PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6"),
  199. PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7"),
  200. PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0"),
  201. PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1"),
  202. PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2"),
  203. PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3"),
  204. PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4"),
  205. PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5"),
  206. PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6"),
  207. PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7"),
  208. PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0"),
  209. PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1"),
  210. PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2"),
  211. PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3"),
  212. PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4"),
  213. PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0"),
  214. PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1"),
  215. PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2"),
  216. PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3"),
  217. PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4"),
  218. PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5"),
  219. PINCTRL_PIN(TEGRA_PIN_PE6, "PE6"),
  220. PINCTRL_PIN(TEGRA_PIN_PE7, "PE7"),
  221. PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0"),
  222. PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1"),
  223. PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0"),
  224. PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1"),
  225. PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2"),
  226. PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3"),
  227. PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0"),
  228. PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1"),
  229. PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2"),
  230. PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3"),
  231. PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4"),
  232. PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5"),
  233. PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
  234. PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7"),
  235. PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0"),
  236. PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1"),
  237. PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2"),
  238. PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3"),
  239. PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4"),
  240. PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5"),
  241. PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6"),
  242. PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7"),
  243. PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0"),
  244. PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1"),
  245. PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2"),
  246. PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3"),
  247. PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4"),
  248. PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5"),
  249. PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6"),
  250. PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7"),
  251. PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
  252. PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
  253. PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
  254. PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
  255. PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
  256. PINCTRL_PIN(TEGRA_PIN_PK5, "PK5"),
  257. PINCTRL_PIN(TEGRA_PIN_PK6, "PK6"),
  258. PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
  259. PINCTRL_PIN(TEGRA_PIN_PL0, "PL0"),
  260. PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"),
  261. PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0"),
  262. PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1"),
  263. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2"),
  264. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3"),
  265. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4"),
  266. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5"),
  267. PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0"),
  268. PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1"),
  269. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2"),
  270. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3"),
  271. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4"),
  272. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5"),
  273. PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0"),
  274. PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1"),
  275. PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2"),
  276. PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3"),
  277. PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4"),
  278. PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5"),
  279. PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6"),
  280. PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7"),
  281. PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0"),
  282. PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1"),
  283. PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0"),
  284. PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1"),
  285. PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2"),
  286. PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3"),
  287. PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0"),
  288. PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1"),
  289. PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2"),
  290. PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3"),
  291. PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4"),
  292. PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5"),
  293. PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6"),
  294. PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7"),
  295. PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0"),
  296. PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1"),
  297. PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2"),
  298. PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3"),
  299. PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4"),
  300. PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5"),
  301. PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6"),
  302. PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7"),
  303. PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0"),
  304. PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1"),
  305. PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2"),
  306. PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3"),
  307. PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4"),
  308. PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5"),
  309. PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0"),
  310. PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1"),
  311. PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2"),
  312. PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3"),
  313. PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4"),
  314. PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5"),
  315. PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0"),
  316. PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1"),
  317. PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2"),
  318. PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3"),
  319. PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0"),
  320. PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1"),
  321. PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2"),
  322. PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3"),
  323. PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4"),
  324. PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0"),
  325. PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1"),
  326. PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2"),
  327. PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"),
  328. PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4"),
  329. PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5"),
  330. PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6"),
  331. PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7"),
  332. PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0"),
  333. PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0"),
  334. PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1"),
  335. PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2"),
  336. PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3"),
  337. PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4"),
  338. PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5"),
  339. PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
  340. PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
  341. PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
  342. PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
  343. PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
  344. PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL"),
  345. PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ"),
  346. PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
  347. };
  348. static const unsigned pex_l0_rst_n_pa0_pins[] = {
  349. TEGRA_PIN_PEX_L0_RST_N_PA0,
  350. };
  351. static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
  352. TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
  353. };
  354. static const unsigned pex_wake_n_pa2_pins[] = {
  355. TEGRA_PIN_PEX_WAKE_N_PA2,
  356. };
  357. static const unsigned pex_l1_rst_n_pa3_pins[] = {
  358. TEGRA_PIN_PEX_L1_RST_N_PA3,
  359. };
  360. static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
  361. TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
  362. };
  363. static const unsigned sata_led_active_pa5_pins[] = {
  364. TEGRA_PIN_SATA_LED_ACTIVE_PA5,
  365. };
  366. static const unsigned pa6_pins[] = {
  367. TEGRA_PIN_PA6,
  368. };
  369. static const unsigned dap1_fs_pb0_pins[] = {
  370. TEGRA_PIN_DAP1_FS_PB0,
  371. };
  372. static const unsigned dap1_din_pb1_pins[] = {
  373. TEGRA_PIN_DAP1_DIN_PB1,
  374. };
  375. static const unsigned dap1_dout_pb2_pins[] = {
  376. TEGRA_PIN_DAP1_DOUT_PB2,
  377. };
  378. static const unsigned dap1_sclk_pb3_pins[] = {
  379. TEGRA_PIN_DAP1_SCLK_PB3,
  380. };
  381. static const unsigned spi2_mosi_pb4_pins[] = {
  382. TEGRA_PIN_SPI2_MOSI_PB4,
  383. };
  384. static const unsigned spi2_miso_pb5_pins[] = {
  385. TEGRA_PIN_SPI2_MISO_PB5,
  386. };
  387. static const unsigned spi2_sck_pb6_pins[] = {
  388. TEGRA_PIN_SPI2_SCK_PB6,
  389. };
  390. static const unsigned spi2_cs0_pb7_pins[] = {
  391. TEGRA_PIN_SPI2_CS0_PB7,
  392. };
  393. static const unsigned spi1_mosi_pc0_pins[] = {
  394. TEGRA_PIN_SPI1_MOSI_PC0,
  395. };
  396. static const unsigned spi1_miso_pc1_pins[] = {
  397. TEGRA_PIN_SPI1_MISO_PC1,
  398. };
  399. static const unsigned spi1_sck_pc2_pins[] = {
  400. TEGRA_PIN_SPI1_SCK_PC2,
  401. };
  402. static const unsigned spi1_cs0_pc3_pins[] = {
  403. TEGRA_PIN_SPI1_CS0_PC3,
  404. };
  405. static const unsigned spi1_cs1_pc4_pins[] = {
  406. TEGRA_PIN_SPI1_CS1_PC4,
  407. };
  408. static const unsigned spi4_sck_pc5_pins[] = {
  409. TEGRA_PIN_SPI4_SCK_PC5,
  410. };
  411. static const unsigned spi4_cs0_pc6_pins[] = {
  412. TEGRA_PIN_SPI4_CS0_PC6,
  413. };
  414. static const unsigned spi4_mosi_pc7_pins[] = {
  415. TEGRA_PIN_SPI4_MOSI_PC7,
  416. };
  417. static const unsigned spi4_miso_pd0_pins[] = {
  418. TEGRA_PIN_SPI4_MISO_PD0,
  419. };
  420. static const unsigned uart3_tx_pd1_pins[] = {
  421. TEGRA_PIN_UART3_TX_PD1,
  422. };
  423. static const unsigned uart3_rx_pd2_pins[] = {
  424. TEGRA_PIN_UART3_RX_PD2,
  425. };
  426. static const unsigned uart3_rts_pd3_pins[] = {
  427. TEGRA_PIN_UART3_RTS_PD3,
  428. };
  429. static const unsigned uart3_cts_pd4_pins[] = {
  430. TEGRA_PIN_UART3_CTS_PD4,
  431. };
  432. static const unsigned dmic1_clk_pe0_pins[] = {
  433. TEGRA_PIN_DMIC1_CLK_PE0,
  434. };
  435. static const unsigned dmic1_dat_pe1_pins[] = {
  436. TEGRA_PIN_DMIC1_DAT_PE1,
  437. };
  438. static const unsigned dmic2_clk_pe2_pins[] = {
  439. TEGRA_PIN_DMIC2_CLK_PE2,
  440. };
  441. static const unsigned dmic2_dat_pe3_pins[] = {
  442. TEGRA_PIN_DMIC2_DAT_PE3,
  443. };
  444. static const unsigned dmic3_clk_pe4_pins[] = {
  445. TEGRA_PIN_DMIC3_CLK_PE4,
  446. };
  447. static const unsigned dmic3_dat_pe5_pins[] = {
  448. TEGRA_PIN_DMIC3_DAT_PE5,
  449. };
  450. static const unsigned pe6_pins[] = {
  451. TEGRA_PIN_PE6,
  452. };
  453. static const unsigned pe7_pins[] = {
  454. TEGRA_PIN_PE7,
  455. };
  456. static const unsigned gen3_i2c_scl_pf0_pins[] = {
  457. TEGRA_PIN_GEN3_I2C_SCL_PF0,
  458. };
  459. static const unsigned gen3_i2c_sda_pf1_pins[] = {
  460. TEGRA_PIN_GEN3_I2C_SDA_PF1,
  461. };
  462. static const unsigned uart2_tx_pg0_pins[] = {
  463. TEGRA_PIN_UART2_TX_PG0,
  464. };
  465. static const unsigned uart2_rx_pg1_pins[] = {
  466. TEGRA_PIN_UART2_RX_PG1,
  467. };
  468. static const unsigned uart2_rts_pg2_pins[] = {
  469. TEGRA_PIN_UART2_RTS_PG2,
  470. };
  471. static const unsigned uart2_cts_pg3_pins[] = {
  472. TEGRA_PIN_UART2_CTS_PG3,
  473. };
  474. static const unsigned wifi_en_ph0_pins[] = {
  475. TEGRA_PIN_WIFI_EN_PH0,
  476. };
  477. static const unsigned wifi_rst_ph1_pins[] = {
  478. TEGRA_PIN_WIFI_RST_PH1,
  479. };
  480. static const unsigned wifi_wake_ap_ph2_pins[] = {
  481. TEGRA_PIN_WIFI_WAKE_AP_PH2,
  482. };
  483. static const unsigned ap_wake_bt_ph3_pins[] = {
  484. TEGRA_PIN_AP_WAKE_BT_PH3,
  485. };
  486. static const unsigned bt_rst_ph4_pins[] = {
  487. TEGRA_PIN_BT_RST_PH4,
  488. };
  489. static const unsigned bt_wake_ap_ph5_pins[] = {
  490. TEGRA_PIN_BT_WAKE_AP_PH5,
  491. };
  492. static const unsigned ph6_pins[] = {
  493. TEGRA_PIN_PH6,
  494. };
  495. static const unsigned ap_wake_nfc_ph7_pins[] = {
  496. TEGRA_PIN_AP_WAKE_NFC_PH7,
  497. };
  498. static const unsigned nfc_en_pi0_pins[] = {
  499. TEGRA_PIN_NFC_EN_PI0,
  500. };
  501. static const unsigned nfc_int_pi1_pins[] = {
  502. TEGRA_PIN_NFC_INT_PI1,
  503. };
  504. static const unsigned gps_en_pi2_pins[] = {
  505. TEGRA_PIN_GPS_EN_PI2,
  506. };
  507. static const unsigned gps_rst_pi3_pins[] = {
  508. TEGRA_PIN_GPS_RST_PI3,
  509. };
  510. static const unsigned uart4_tx_pi4_pins[] = {
  511. TEGRA_PIN_UART4_TX_PI4,
  512. };
  513. static const unsigned uart4_rx_pi5_pins[] = {
  514. TEGRA_PIN_UART4_RX_PI5,
  515. };
  516. static const unsigned uart4_rts_pi6_pins[] = {
  517. TEGRA_PIN_UART4_RTS_PI6,
  518. };
  519. static const unsigned uart4_cts_pi7_pins[] = {
  520. TEGRA_PIN_UART4_CTS_PI7,
  521. };
  522. static const unsigned gen1_i2c_sda_pj0_pins[] = {
  523. TEGRA_PIN_GEN1_I2C_SDA_PJ0,
  524. };
  525. static const unsigned gen1_i2c_scl_pj1_pins[] = {
  526. TEGRA_PIN_GEN1_I2C_SCL_PJ1,
  527. };
  528. static const unsigned gen2_i2c_scl_pj2_pins[] = {
  529. TEGRA_PIN_GEN2_I2C_SCL_PJ2,
  530. };
  531. static const unsigned gen2_i2c_sda_pj3_pins[] = {
  532. TEGRA_PIN_GEN2_I2C_SDA_PJ3,
  533. };
  534. static const unsigned dap4_fs_pj4_pins[] = {
  535. TEGRA_PIN_DAP4_FS_PJ4,
  536. };
  537. static const unsigned dap4_din_pj5_pins[] = {
  538. TEGRA_PIN_DAP4_DIN_PJ5,
  539. };
  540. static const unsigned dap4_dout_pj6_pins[] = {
  541. TEGRA_PIN_DAP4_DOUT_PJ6,
  542. };
  543. static const unsigned dap4_sclk_pj7_pins[] = {
  544. TEGRA_PIN_DAP4_SCLK_PJ7,
  545. };
  546. static const unsigned pk0_pins[] = {
  547. TEGRA_PIN_PK0,
  548. };
  549. static const unsigned pk1_pins[] = {
  550. TEGRA_PIN_PK1,
  551. };
  552. static const unsigned pk2_pins[] = {
  553. TEGRA_PIN_PK2,
  554. };
  555. static const unsigned pk3_pins[] = {
  556. TEGRA_PIN_PK3,
  557. };
  558. static const unsigned pk4_pins[] = {
  559. TEGRA_PIN_PK4,
  560. };
  561. static const unsigned pk5_pins[] = {
  562. TEGRA_PIN_PK5,
  563. };
  564. static const unsigned pk6_pins[] = {
  565. TEGRA_PIN_PK6,
  566. };
  567. static const unsigned pk7_pins[] = {
  568. TEGRA_PIN_PK7,
  569. };
  570. static const unsigned pl0_pins[] = {
  571. TEGRA_PIN_PL0,
  572. };
  573. static const unsigned pl1_pins[] = {
  574. TEGRA_PIN_PL1,
  575. };
  576. static const unsigned sdmmc1_clk_pm0_pins[] = {
  577. TEGRA_PIN_SDMMC1_CLK_PM0,
  578. };
  579. static const unsigned sdmmc1_cmd_pm1_pins[] = {
  580. TEGRA_PIN_SDMMC1_CMD_PM1,
  581. };
  582. static const unsigned sdmmc1_dat3_pm2_pins[] = {
  583. TEGRA_PIN_SDMMC1_DAT3_PM2,
  584. };
  585. static const unsigned sdmmc1_dat2_pm3_pins[] = {
  586. TEGRA_PIN_SDMMC1_DAT2_PM3,
  587. };
  588. static const unsigned sdmmc1_dat1_pm4_pins[] = {
  589. TEGRA_PIN_SDMMC1_DAT1_PM4,
  590. };
  591. static const unsigned sdmmc1_dat0_pm5_pins[] = {
  592. TEGRA_PIN_SDMMC1_DAT0_PM5,
  593. };
  594. static const unsigned sdmmc3_clk_pp0_pins[] = {
  595. TEGRA_PIN_SDMMC3_CLK_PP0,
  596. };
  597. static const unsigned sdmmc3_cmd_pp1_pins[] = {
  598. TEGRA_PIN_SDMMC3_CMD_PP1,
  599. };
  600. static const unsigned sdmmc3_dat3_pp2_pins[] = {
  601. TEGRA_PIN_SDMMC3_DAT3_PP2,
  602. };
  603. static const unsigned sdmmc3_dat2_pp3_pins[] = {
  604. TEGRA_PIN_SDMMC3_DAT2_PP3,
  605. };
  606. static const unsigned sdmmc3_dat1_pp4_pins[] = {
  607. TEGRA_PIN_SDMMC3_DAT1_PP4,
  608. };
  609. static const unsigned sdmmc3_dat0_pp5_pins[] = {
  610. TEGRA_PIN_SDMMC3_DAT0_PP5,
  611. };
  612. static const unsigned cam1_mclk_ps0_pins[] = {
  613. TEGRA_PIN_CAM1_MCLK_PS0,
  614. };
  615. static const unsigned cam2_mclk_ps1_pins[] = {
  616. TEGRA_PIN_CAM2_MCLK_PS1,
  617. };
  618. static const unsigned cam_i2c_scl_ps2_pins[] = {
  619. TEGRA_PIN_CAM_I2C_SCL_PS2,
  620. };
  621. static const unsigned cam_i2c_sda_ps3_pins[] = {
  622. TEGRA_PIN_CAM_I2C_SDA_PS3,
  623. };
  624. static const unsigned cam_rst_ps4_pins[] = {
  625. TEGRA_PIN_CAM_RST_PS4,
  626. };
  627. static const unsigned cam_af_en_ps5_pins[] = {
  628. TEGRA_PIN_CAM_AF_EN_PS5,
  629. };
  630. static const unsigned cam_flash_en_ps6_pins[] = {
  631. TEGRA_PIN_CAM_FLASH_EN_PS6,
  632. };
  633. static const unsigned cam1_pwdn_ps7_pins[] = {
  634. TEGRA_PIN_CAM1_PWDN_PS7,
  635. };
  636. static const unsigned cam2_pwdn_pt0_pins[] = {
  637. TEGRA_PIN_CAM2_PWDN_PT0,
  638. };
  639. static const unsigned cam1_strobe_pt1_pins[] = {
  640. TEGRA_PIN_CAM1_STROBE_PT1,
  641. };
  642. static const unsigned uart1_tx_pu0_pins[] = {
  643. TEGRA_PIN_UART1_TX_PU0,
  644. };
  645. static const unsigned uart1_rx_pu1_pins[] = {
  646. TEGRA_PIN_UART1_RX_PU1,
  647. };
  648. static const unsigned uart1_rts_pu2_pins[] = {
  649. TEGRA_PIN_UART1_RTS_PU2,
  650. };
  651. static const unsigned uart1_cts_pu3_pins[] = {
  652. TEGRA_PIN_UART1_CTS_PU3,
  653. };
  654. static const unsigned lcd_bl_pwm_pv0_pins[] = {
  655. TEGRA_PIN_LCD_BL_PWM_PV0,
  656. };
  657. static const unsigned lcd_bl_en_pv1_pins[] = {
  658. TEGRA_PIN_LCD_BL_EN_PV1,
  659. };
  660. static const unsigned lcd_rst_pv2_pins[] = {
  661. TEGRA_PIN_LCD_RST_PV2,
  662. };
  663. static const unsigned lcd_gpio1_pv3_pins[] = {
  664. TEGRA_PIN_LCD_GPIO1_PV3,
  665. };
  666. static const unsigned lcd_gpio2_pv4_pins[] = {
  667. TEGRA_PIN_LCD_GPIO2_PV4,
  668. };
  669. static const unsigned ap_ready_pv5_pins[] = {
  670. TEGRA_PIN_AP_READY_PV5,
  671. };
  672. static const unsigned touch_rst_pv6_pins[] = {
  673. TEGRA_PIN_TOUCH_RST_PV6,
  674. };
  675. static const unsigned touch_clk_pv7_pins[] = {
  676. TEGRA_PIN_TOUCH_CLK_PV7,
  677. };
  678. static const unsigned modem_wake_ap_px0_pins[] = {
  679. TEGRA_PIN_MODEM_WAKE_AP_PX0,
  680. };
  681. static const unsigned touch_int_px1_pins[] = {
  682. TEGRA_PIN_TOUCH_INT_PX1,
  683. };
  684. static const unsigned motion_int_px2_pins[] = {
  685. TEGRA_PIN_MOTION_INT_PX2,
  686. };
  687. static const unsigned als_prox_int_px3_pins[] = {
  688. TEGRA_PIN_ALS_PROX_INT_PX3,
  689. };
  690. static const unsigned temp_alert_px4_pins[] = {
  691. TEGRA_PIN_TEMP_ALERT_PX4,
  692. };
  693. static const unsigned button_power_on_px5_pins[] = {
  694. TEGRA_PIN_BUTTON_POWER_ON_PX5,
  695. };
  696. static const unsigned button_vol_up_px6_pins[] = {
  697. TEGRA_PIN_BUTTON_VOL_UP_PX6,
  698. };
  699. static const unsigned button_vol_down_px7_pins[] = {
  700. TEGRA_PIN_BUTTON_VOL_DOWN_PX7,
  701. };
  702. static const unsigned button_slide_sw_py0_pins[] = {
  703. TEGRA_PIN_BUTTON_SLIDE_SW_PY0,
  704. };
  705. static const unsigned button_home_py1_pins[] = {
  706. TEGRA_PIN_BUTTON_HOME_PY1,
  707. };
  708. static const unsigned lcd_te_py2_pins[] = {
  709. TEGRA_PIN_LCD_TE_PY2,
  710. };
  711. static const unsigned pwr_i2c_scl_py3_pins[] = {
  712. TEGRA_PIN_PWR_I2C_SCL_PY3,
  713. };
  714. static const unsigned pwr_i2c_sda_py4_pins[] = {
  715. TEGRA_PIN_PWR_I2C_SDA_PY4,
  716. };
  717. static const unsigned clk_32k_out_py5_pins[] = {
  718. TEGRA_PIN_CLK_32K_OUT_PY5,
  719. };
  720. static const unsigned pz0_pins[] = {
  721. TEGRA_PIN_PZ0,
  722. };
  723. static const unsigned pz1_pins[] = {
  724. TEGRA_PIN_PZ1,
  725. };
  726. static const unsigned pz2_pins[] = {
  727. TEGRA_PIN_PZ2,
  728. };
  729. static const unsigned pz3_pins[] = {
  730. TEGRA_PIN_PZ3,
  731. };
  732. static const unsigned pz4_pins[] = {
  733. TEGRA_PIN_PZ4,
  734. };
  735. static const unsigned pz5_pins[] = {
  736. TEGRA_PIN_PZ5,
  737. };
  738. static const unsigned dap2_fs_paa0_pins[] = {
  739. TEGRA_PIN_DAP2_FS_PAA0,
  740. };
  741. static const unsigned dap2_sclk_paa1_pins[] = {
  742. TEGRA_PIN_DAP2_SCLK_PAA1,
  743. };
  744. static const unsigned dap2_din_paa2_pins[] = {
  745. TEGRA_PIN_DAP2_DIN_PAA2,
  746. };
  747. static const unsigned dap2_dout_paa3_pins[] = {
  748. TEGRA_PIN_DAP2_DOUT_PAA3,
  749. };
  750. static const unsigned aud_mclk_pbb0_pins[] = {
  751. TEGRA_PIN_AUD_MCLK_PBB0,
  752. };
  753. static const unsigned dvfs_pwm_pbb1_pins[] = {
  754. TEGRA_PIN_DVFS_PWM_PBB1,
  755. };
  756. static const unsigned dvfs_clk_pbb2_pins[] = {
  757. TEGRA_PIN_DVFS_CLK_PBB2,
  758. };
  759. static const unsigned gpio_x1_aud_pbb3_pins[] = {
  760. TEGRA_PIN_GPIO_X1_AUD_PBB3,
  761. };
  762. static const unsigned gpio_x3_aud_pbb4_pins[] = {
  763. TEGRA_PIN_GPIO_X3_AUD_PBB4,
  764. };
  765. static const unsigned hdmi_cec_pcc0_pins[] = {
  766. TEGRA_PIN_HDMI_CEC_PCC0,
  767. };
  768. static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = {
  769. TEGRA_PIN_HDMI_INT_DP_HPD_PCC1,
  770. };
  771. static const unsigned spdif_out_pcc2_pins[] = {
  772. TEGRA_PIN_SPDIF_OUT_PCC2,
  773. };
  774. static const unsigned spdif_in_pcc3_pins[] = {
  775. TEGRA_PIN_SPDIF_IN_PCC3,
  776. };
  777. static const unsigned usb_vbus_en0_pcc4_pins[] = {
  778. TEGRA_PIN_USB_VBUS_EN0_PCC4,
  779. };
  780. static const unsigned usb_vbus_en1_pcc5_pins[] = {
  781. TEGRA_PIN_USB_VBUS_EN1_PCC5,
  782. };
  783. static const unsigned dp_hpd0_pcc6_pins[] = {
  784. TEGRA_PIN_DP_HPD0_PCC6,
  785. };
  786. static const unsigned pcc7_pins[] = {
  787. TEGRA_PIN_PCC7,
  788. };
  789. static const unsigned spi2_cs1_pdd0_pins[] = {
  790. TEGRA_PIN_SPI2_CS1_PDD0,
  791. };
  792. static const unsigned qspi_sck_pee0_pins[] = {
  793. TEGRA_PIN_QSPI_SCK_PEE0,
  794. };
  795. static const unsigned qspi_cs_n_pee1_pins[] = {
  796. TEGRA_PIN_QSPI_CS_N_PEE1,
  797. };
  798. static const unsigned qspi_io0_pee2_pins[] = {
  799. TEGRA_PIN_QSPI_IO0_PEE2,
  800. };
  801. static const unsigned qspi_io1_pee3_pins[] = {
  802. TEGRA_PIN_QSPI_IO1_PEE3,
  803. };
  804. static const unsigned qspi_io2_pee4_pins[] = {
  805. TEGRA_PIN_QSPI_IO2_PEE4,
  806. };
  807. static const unsigned qspi_io3_pee5_pins[] = {
  808. TEGRA_PIN_QSPI_IO3_PEE5,
  809. };
  810. static const unsigned core_pwr_req_pins[] = {
  811. TEGRA_PIN_CORE_PWR_REQ,
  812. };
  813. static const unsigned cpu_pwr_req_pins[] = {
  814. TEGRA_PIN_CPU_PWR_REQ,
  815. };
  816. static const unsigned pwr_int_n_pins[] = {
  817. TEGRA_PIN_PWR_INT_N,
  818. };
  819. static const unsigned clk_32k_in_pins[] = {
  820. TEGRA_PIN_CLK_32K_IN,
  821. };
  822. static const unsigned jtag_rtck_pins[] = {
  823. TEGRA_PIN_JTAG_RTCK,
  824. };
  825. static const unsigned batt_bcl_pins[] = {
  826. TEGRA_PIN_BATT_BCL,
  827. };
  828. static const unsigned clk_req_pins[] = {
  829. TEGRA_PIN_CLK_REQ,
  830. };
  831. static const unsigned shutdown_pins[] = {
  832. TEGRA_PIN_SHUTDOWN,
  833. };
  834. static const unsigned drive_pa6_pins[] = {
  835. TEGRA_PIN_PA6,
  836. };
  837. static const unsigned drive_pcc7_pins[] = {
  838. TEGRA_PIN_PCC7,
  839. };
  840. static const unsigned drive_pe6_pins[] = {
  841. TEGRA_PIN_PE6,
  842. };
  843. static const unsigned drive_pe7_pins[] = {
  844. TEGRA_PIN_PE7,
  845. };
  846. static const unsigned drive_ph6_pins[] = {
  847. TEGRA_PIN_PH6,
  848. };
  849. static const unsigned drive_pk0_pins[] = {
  850. TEGRA_PIN_PK0,
  851. };
  852. static const unsigned drive_pk1_pins[] = {
  853. TEGRA_PIN_PK1,
  854. };
  855. static const unsigned drive_pk2_pins[] = {
  856. TEGRA_PIN_PK2,
  857. };
  858. static const unsigned drive_pk3_pins[] = {
  859. TEGRA_PIN_PK3,
  860. };
  861. static const unsigned drive_pk4_pins[] = {
  862. TEGRA_PIN_PK4,
  863. };
  864. static const unsigned drive_pk5_pins[] = {
  865. TEGRA_PIN_PK5,
  866. };
  867. static const unsigned drive_pk6_pins[] = {
  868. TEGRA_PIN_PK6,
  869. };
  870. static const unsigned drive_pk7_pins[] = {
  871. TEGRA_PIN_PK7,
  872. };
  873. static const unsigned drive_pl0_pins[] = {
  874. TEGRA_PIN_PL0,
  875. };
  876. static const unsigned drive_pl1_pins[] = {
  877. TEGRA_PIN_PL1,
  878. };
  879. static const unsigned drive_pz0_pins[] = {
  880. TEGRA_PIN_PZ0,
  881. };
  882. static const unsigned drive_pz1_pins[] = {
  883. TEGRA_PIN_PZ1,
  884. };
  885. static const unsigned drive_pz2_pins[] = {
  886. TEGRA_PIN_PZ2,
  887. };
  888. static const unsigned drive_pz3_pins[] = {
  889. TEGRA_PIN_PZ3,
  890. };
  891. static const unsigned drive_pz4_pins[] = {
  892. TEGRA_PIN_PZ4,
  893. };
  894. static const unsigned drive_pz5_pins[] = {
  895. TEGRA_PIN_PZ5,
  896. };
  897. static const unsigned drive_sdmmc1_pins[] = {
  898. TEGRA_PIN_SDMMC1_CLK_PM0,
  899. TEGRA_PIN_SDMMC1_CMD_PM1,
  900. TEGRA_PIN_SDMMC1_DAT3_PM2,
  901. TEGRA_PIN_SDMMC1_DAT2_PM3,
  902. TEGRA_PIN_SDMMC1_DAT1_PM4,
  903. TEGRA_PIN_SDMMC1_DAT0_PM5,
  904. };
  905. static const unsigned drive_sdmmc2_pins[] = {
  906. };
  907. static const unsigned drive_sdmmc3_pins[] = {
  908. TEGRA_PIN_SDMMC3_CLK_PP0,
  909. TEGRA_PIN_SDMMC3_CMD_PP1,
  910. TEGRA_PIN_SDMMC3_DAT3_PP2,
  911. TEGRA_PIN_SDMMC3_DAT2_PP3,
  912. TEGRA_PIN_SDMMC3_DAT1_PP4,
  913. TEGRA_PIN_SDMMC3_DAT0_PP5,
  914. };
  915. static const unsigned drive_sdmmc4_pins[] = {
  916. };
  917. enum tegra_mux {
  918. TEGRA_MUX_AUD,
  919. TEGRA_MUX_BCL,
  920. TEGRA_MUX_BLINK,
  921. TEGRA_MUX_CCLA,
  922. TEGRA_MUX_CEC,
  923. TEGRA_MUX_CLDVFS,
  924. TEGRA_MUX_CLK,
  925. TEGRA_MUX_CORE,
  926. TEGRA_MUX_CPU,
  927. TEGRA_MUX_DISPLAYA,
  928. TEGRA_MUX_DISPLAYB,
  929. TEGRA_MUX_DMIC1,
  930. TEGRA_MUX_DMIC2,
  931. TEGRA_MUX_DMIC3,
  932. TEGRA_MUX_DP,
  933. TEGRA_MUX_DTV,
  934. TEGRA_MUX_EXTPERIPH3,
  935. TEGRA_MUX_I2C1,
  936. TEGRA_MUX_I2C2,
  937. TEGRA_MUX_I2C3,
  938. TEGRA_MUX_I2CPMU,
  939. TEGRA_MUX_I2CVI,
  940. TEGRA_MUX_I2S1,
  941. TEGRA_MUX_I2S2,
  942. TEGRA_MUX_I2S3,
  943. TEGRA_MUX_I2S4A,
  944. TEGRA_MUX_I2S4B,
  945. TEGRA_MUX_I2S5A,
  946. TEGRA_MUX_I2S5B,
  947. TEGRA_MUX_IQC0,
  948. TEGRA_MUX_IQC1,
  949. TEGRA_MUX_JTAG,
  950. TEGRA_MUX_PE,
  951. TEGRA_MUX_PE0,
  952. TEGRA_MUX_PE1,
  953. TEGRA_MUX_PMI,
  954. TEGRA_MUX_PWM0,
  955. TEGRA_MUX_PWM1,
  956. TEGRA_MUX_PWM2,
  957. TEGRA_MUX_PWM3,
  958. TEGRA_MUX_QSPI,
  959. TEGRA_MUX_RSVD0,
  960. TEGRA_MUX_RSVD1,
  961. TEGRA_MUX_RSVD2,
  962. TEGRA_MUX_RSVD3,
  963. TEGRA_MUX_SATA,
  964. TEGRA_MUX_SDMMC1,
  965. TEGRA_MUX_SDMMC3,
  966. TEGRA_MUX_SHUTDOWN,
  967. TEGRA_MUX_SOC,
  968. TEGRA_MUX_SOR0,
  969. TEGRA_MUX_SOR1,
  970. TEGRA_MUX_SPDIF,
  971. TEGRA_MUX_SPI1,
  972. TEGRA_MUX_SPI2,
  973. TEGRA_MUX_SPI3,
  974. TEGRA_MUX_SPI4,
  975. TEGRA_MUX_SYS,
  976. TEGRA_MUX_TOUCH,
  977. TEGRA_MUX_UART,
  978. TEGRA_MUX_UARTA,
  979. TEGRA_MUX_UARTB,
  980. TEGRA_MUX_UARTC,
  981. TEGRA_MUX_UARTD,
  982. TEGRA_MUX_USB,
  983. TEGRA_MUX_VGP1,
  984. TEGRA_MUX_VGP2,
  985. TEGRA_MUX_VGP3,
  986. TEGRA_MUX_VGP4,
  987. TEGRA_MUX_VGP5,
  988. TEGRA_MUX_VGP6,
  989. TEGRA_MUX_VIMCLK,
  990. TEGRA_MUX_VIMCLK2,
  991. };
  992. #define FUNCTION(fname) \
  993. { \
  994. .name = #fname, \
  995. }
  996. static struct tegra_function tegra210_functions[] = {
  997. FUNCTION(aud),
  998. FUNCTION(bcl),
  999. FUNCTION(blink),
  1000. FUNCTION(ccla),
  1001. FUNCTION(cec),
  1002. FUNCTION(cldvfs),
  1003. FUNCTION(clk),
  1004. FUNCTION(core),
  1005. FUNCTION(cpu),
  1006. FUNCTION(displaya),
  1007. FUNCTION(displayb),
  1008. FUNCTION(dmic1),
  1009. FUNCTION(dmic2),
  1010. FUNCTION(dmic3),
  1011. FUNCTION(dp),
  1012. FUNCTION(dtv),
  1013. FUNCTION(extperiph3),
  1014. FUNCTION(i2c1),
  1015. FUNCTION(i2c2),
  1016. FUNCTION(i2c3),
  1017. FUNCTION(i2cpmu),
  1018. FUNCTION(i2cvi),
  1019. FUNCTION(i2s1),
  1020. FUNCTION(i2s2),
  1021. FUNCTION(i2s3),
  1022. FUNCTION(i2s4a),
  1023. FUNCTION(i2s4b),
  1024. FUNCTION(i2s5a),
  1025. FUNCTION(i2s5b),
  1026. FUNCTION(iqc0),
  1027. FUNCTION(iqc1),
  1028. FUNCTION(jtag),
  1029. FUNCTION(pe),
  1030. FUNCTION(pe0),
  1031. FUNCTION(pe1),
  1032. FUNCTION(pmi),
  1033. FUNCTION(pwm0),
  1034. FUNCTION(pwm1),
  1035. FUNCTION(pwm2),
  1036. FUNCTION(pwm3),
  1037. FUNCTION(qspi),
  1038. FUNCTION(rsvd0),
  1039. FUNCTION(rsvd1),
  1040. FUNCTION(rsvd2),
  1041. FUNCTION(rsvd3),
  1042. FUNCTION(sata),
  1043. FUNCTION(sdmmc1),
  1044. FUNCTION(sdmmc3),
  1045. FUNCTION(shutdown),
  1046. FUNCTION(soc),
  1047. FUNCTION(sor0),
  1048. FUNCTION(sor1),
  1049. FUNCTION(spdif),
  1050. FUNCTION(spi1),
  1051. FUNCTION(spi2),
  1052. FUNCTION(spi3),
  1053. FUNCTION(spi4),
  1054. FUNCTION(sys),
  1055. FUNCTION(touch),
  1056. FUNCTION(uart),
  1057. FUNCTION(uarta),
  1058. FUNCTION(uartb),
  1059. FUNCTION(uartc),
  1060. FUNCTION(uartd),
  1061. FUNCTION(usb),
  1062. FUNCTION(vgp1),
  1063. FUNCTION(vgp2),
  1064. FUNCTION(vgp3),
  1065. FUNCTION(vgp4),
  1066. FUNCTION(vgp5),
  1067. FUNCTION(vgp6),
  1068. FUNCTION(vimclk),
  1069. FUNCTION(vimclk2),
  1070. };
  1071. #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
  1072. #define PINGROUP_REG_A 0x3000 /* bank 1 */
  1073. #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
  1074. #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
  1075. #define PINGROUP_BIT_Y(b) (b)
  1076. #define PINGROUP_BIT_N(b) (-1)
  1077. #define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \
  1078. rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, \
  1079. slwr_w, slwf_b, slwf_w) \
  1080. { \
  1081. .name = #pg_name, \
  1082. .pins = pg_name##_pins, \
  1083. .npins = ARRAY_SIZE(pg_name##_pins), \
  1084. .funcs = { \
  1085. TEGRA_MUX_##f0, \
  1086. TEGRA_MUX_##f1, \
  1087. TEGRA_MUX_##f2, \
  1088. TEGRA_MUX_##f3, \
  1089. }, \
  1090. .mux_reg = PINGROUP_REG(r), \
  1091. .mux_bank = 1, \
  1092. .mux_bit = 0, \
  1093. .pupd_reg = PINGROUP_REG(r), \
  1094. .pupd_bank = 1, \
  1095. .pupd_bit = 2, \
  1096. .tri_reg = PINGROUP_REG(r), \
  1097. .tri_bank = 1, \
  1098. .tri_bit = 4, \
  1099. .einput_bit = 6, \
  1100. .odrain_bit = 11, \
  1101. .lock_bit = 7, \
  1102. .ioreset_bit = -1, \
  1103. .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
  1104. .hsm_bit = PINGROUP_BIT_##hsm(9), \
  1105. .schmitt_bit = 12, \
  1106. .drvtype_bit = PINGROUP_BIT_##drvtype(13), \
  1107. .drv_reg = DRV_PINGROUP_REG(rdrv), \
  1108. .drv_bank = 0, \
  1109. .lpmd_bit = -1, \
  1110. .drvdn_bit = drvdn_b, \
  1111. .drvdn_width = drvdn_w, \
  1112. .drvup_bit = drvup_b, \
  1113. .drvup_width = drvup_w, \
  1114. .slwr_bit = slwr_b, \
  1115. .slwr_width = slwr_w, \
  1116. .slwf_bit = slwf_b, \
  1117. .slwf_width = slwf_w, \
  1118. .parked_bitmask = BIT(5), \
  1119. }
  1120. #define DRV_PINGROUP(pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, \
  1121. drvup_w, slwr_b, slwr_w, slwf_b, slwf_w) \
  1122. { \
  1123. .name = "drive_" #pg_name, \
  1124. .pins = drive_##pg_name##_pins, \
  1125. .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
  1126. .mux_reg = -1, \
  1127. .pupd_reg = -1, \
  1128. .tri_reg = -1, \
  1129. .einput_bit = -1, \
  1130. .odrain_bit = -1, \
  1131. .lock_bit = -1, \
  1132. .ioreset_bit = -1, \
  1133. .rcv_sel_bit = -1, \
  1134. .drv_reg = DRV_PINGROUP_REG(r), \
  1135. .drv_bank = 0, \
  1136. .hsm_bit = -1, \
  1137. .schmitt_bit = -1, \
  1138. .lpmd_bit = -1, \
  1139. .drvdn_bit = drvdn_b, \
  1140. .drvdn_width = drvdn_w, \
  1141. .drvup_bit = drvup_b, \
  1142. .drvup_width = drvup_w, \
  1143. .slwr_bit = slwr_b, \
  1144. .slwr_width = slwr_w, \
  1145. .slwf_bit = slwf_b, \
  1146. .slwf_width = slwf_w, \
  1147. .drvtype_bit = -1, \
  1148. .parked_bitmask = prk_mask, \
  1149. }
  1150. static const struct tegra_pingroup tegra210_groups[] = {
  1151. /* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
  1152. PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1153. PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1154. PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1155. PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1156. PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1157. PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1158. PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1159. PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1160. PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1161. PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1162. PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1163. PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1164. PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1),
  1165. PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1),
  1166. PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1),
  1167. PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1),
  1168. PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1),
  1169. PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1),
  1170. PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2),
  1171. PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2),
  1172. PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2),
  1173. PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2),
  1174. PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2),
  1175. PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2),
  1176. PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2),
  1177. PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2),
  1178. PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2),
  1179. PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2),
  1180. PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2),
  1181. PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2),
  1182. PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2),
  1183. PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2),
  1184. PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2),
  1185. PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1186. PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1187. PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1188. PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1189. PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1190. PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, 0x984, 12, 5, 20, 5, -1, -1, -1, -1),
  1191. PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, 0x988, 12, 5, 20, 5, -1, -1, -1, -1),
  1192. PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1),
  1193. PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, 0x990, 12, 5, 20, 5, -1, -1, -1, -1),
  1194. PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, 0x994, 12, 5, 20, 5, -1, -1, -1, -1),
  1195. PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, 0x998, 12, 5, 20, 5, -1, -1, -1, -1),
  1196. PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1),
  1197. PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1),
  1198. PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1),
  1199. PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1),
  1200. PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1),
  1201. PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1),
  1202. PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1),
  1203. PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1),
  1204. PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1),
  1205. PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1),
  1206. PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1),
  1207. PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1),
  1208. PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1),
  1209. PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1),
  1210. PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1),
  1211. PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1),
  1212. PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1),
  1213. PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1),
  1214. PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1),
  1215. PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1),
  1216. PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1),
  1217. PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1),
  1218. PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1),
  1219. PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1),
  1220. PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1),
  1221. PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1),
  1222. PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2),
  1223. PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2),
  1224. PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2),
  1225. PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2),
  1226. PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2),
  1227. PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2),
  1228. PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2),
  1229. PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2),
  1230. PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1),
  1231. PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, 0x974, 12, 5, 20, 5, -1, -1, -1, -1),
  1232. PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, 0x978, 12, 5, 20, 5, -1, -1, -1, -1),
  1233. PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, 0x980, 12, 5, 20, 5, -1, -1, -1, -1),
  1234. PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, 0x918, 12, 5, 20, 5, -1, -1, -1, -1),
  1235. PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, 0x924, 12, 5, 20, 5, -1, -1, -1, -1),
  1236. PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1),
  1237. PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, 0x940, 12, 5, 20, 5, -1, -1, -1, -1),
  1238. PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, 0x944, 12, 5, 20, 5, -1, -1, -1, -1),
  1239. PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1),
  1240. PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, 0x948, 12, 5, 20, 5, -1, -1, -1, -1),
  1241. PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, 0x950, 12, 5, 20, 5, -1, -1, -1, -1),
  1242. PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1),
  1243. PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1),
  1244. PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1),
  1245. PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1),
  1246. PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1),
  1247. PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1),
  1248. PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1),
  1249. PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1),
  1250. PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1251. PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1),
  1252. PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1),
  1253. PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1),
  1254. PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1),
  1255. PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1),
  1256. PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1),
  1257. PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1),
  1258. PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1),
  1259. PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1),
  1260. PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1),
  1261. PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1),
  1262. PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1),
  1263. PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, 0x900, 12, 5, 20, 5, -1, -1, -1, -1),
  1264. PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1),
  1265. PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1),
  1266. PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1),
  1267. PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1),
  1268. PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1),
  1269. PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1),
  1270. PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1),
  1271. PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, 0x930, 12, 5, 20, 5, -1, -1, -1, -1),
  1272. PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1),
  1273. PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, 0x928, 12, 5, 20, 5, -1, -1, -1, -1),
  1274. PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, 0x920, 12, 5, 20, 5, -1, -1, -1, -1),
  1275. PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1),
  1276. PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1),
  1277. PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1),
  1278. PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1),
  1279. PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1),
  1280. PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1),
  1281. PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1),
  1282. PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1),
  1283. PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1),
  1284. PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1),
  1285. PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1),
  1286. PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1),
  1287. PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1),
  1288. PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1),
  1289. PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, 0x908, 12, 5, 20, 5, -1, -1, -1, -1),
  1290. PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, 0x914, 12, 5, 20, 5, -1, -1, -1, -1),
  1291. PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, 0x910, 12, 5, 20, 5, -1, -1, -1, -1),
  1292. PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1),
  1293. PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, 0x904, 12, 5, 20, 5, -1, -1, -1, -1),
  1294. PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1295. PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1296. PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1297. PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1298. PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1299. PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1300. PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1301. PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1302. PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1303. PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1304. PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1305. PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1306. PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1307. PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1308. PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1309. PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1310. PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1311. PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1312. PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1313. PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
  1314. /* pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
  1315. DRV_PINGROUP(pa6, 0x9c0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
  1316. DRV_PINGROUP(pcc7, 0x9c4, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
  1317. DRV_PINGROUP(pe6, 0x9c8, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
  1318. DRV_PINGROUP(pe7, 0x9cc, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
  1319. DRV_PINGROUP(ph6, 0x9d0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
  1320. DRV_PINGROUP(pk0, 0x9d4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1321. DRV_PINGROUP(pk1, 0x9d8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1322. DRV_PINGROUP(pk2, 0x9dc, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1323. DRV_PINGROUP(pk3, 0x9e0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1324. DRV_PINGROUP(pk4, 0x9e4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1325. DRV_PINGROUP(pk5, 0x9e8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1326. DRV_PINGROUP(pk6, 0x9ec, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1327. DRV_PINGROUP(pk7, 0x9f0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1328. DRV_PINGROUP(pl0, 0x9f4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1329. DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
  1330. DRV_PINGROUP(pz0, 0x9fc, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
  1331. DRV_PINGROUP(pz1, 0xa00, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
  1332. DRV_PINGROUP(pz2, 0xa04, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
  1333. DRV_PINGROUP(pz3, 0xa08, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
  1334. DRV_PINGROUP(pz4, 0xa0c, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
  1335. DRV_PINGROUP(pz5, 0xa10, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
  1336. DRV_PINGROUP(sdmmc1, 0xa98, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
  1337. DRV_PINGROUP(sdmmc2, 0xa9c, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
  1338. DRV_PINGROUP(sdmmc3, 0xab0, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
  1339. DRV_PINGROUP(sdmmc4, 0xab4, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
  1340. };
  1341. static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
  1342. .ngpios = NUM_GPIOS,
  1343. .gpio_compatible = "nvidia,tegra210-gpio",
  1344. .pins = tegra210_pins,
  1345. .npins = ARRAY_SIZE(tegra210_pins),
  1346. .functions = tegra210_functions,
  1347. .nfunctions = ARRAY_SIZE(tegra210_functions),
  1348. .groups = tegra210_groups,
  1349. .ngroups = ARRAY_SIZE(tegra210_groups),
  1350. .hsm_in_mux = true,
  1351. .schmitt_in_mux = true,
  1352. .drvtype_in_mux = true,
  1353. };
  1354. static int tegra210_pinctrl_probe(struct platform_device *pdev)
  1355. {
  1356. return tegra_pinctrl_probe(pdev, &tegra210_pinctrl);
  1357. }
  1358. static const struct of_device_id tegra210_pinctrl_of_match[] = {
  1359. { .compatible = "nvidia,tegra210-pinmux", },
  1360. { },
  1361. };
  1362. static struct platform_driver tegra210_pinctrl_driver = {
  1363. .driver = {
  1364. .name = "tegra210-pinctrl",
  1365. .of_match_table = tegra210_pinctrl_of_match,
  1366. .pm = &tegra_pinctrl_pm,
  1367. },
  1368. .probe = tegra210_pinctrl_probe,
  1369. };
  1370. static int __init tegra210_pinctrl_init(void)
  1371. {
  1372. return platform_driver_register(&tegra210_pinctrl_driver);
  1373. }
  1374. arch_initcall(tegra210_pinctrl_init);