pinctrl-tegra20.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Pinctrl data for the NVIDIA Tegra20 pinmux
  4. *
  5. * Author: Stephen Warren <swarren@nvidia.com>
  6. *
  7. * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
  8. *
  9. * Derived from code:
  10. * Copyright (C) 2010 Google, Inc.
  11. * Copyright (C) 2010 NVIDIA Corporation
  12. */
  13. #include <linux/clk-provider.h>
  14. #include <linux/init.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pinctrl/pinctrl.h>
  18. #include <linux/pinctrl/pinmux.h>
  19. #include "pinctrl-tegra.h"
  20. /*
  21. * Most pins affected by the pinmux can also be GPIOs. Define these first.
  22. * These must match how the GPIO driver names/numbers its pins.
  23. */
  24. #define _GPIO(offset) (offset)
  25. #define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
  26. #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
  27. #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
  28. #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
  29. #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
  30. #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
  31. #define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
  32. #define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
  33. #define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
  34. #define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
  35. #define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
  36. #define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
  37. #define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
  38. #define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
  39. #define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
  40. #define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
  41. #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
  42. #define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
  43. #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
  44. #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
  45. #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
  46. #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
  47. #define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
  48. #define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
  49. #define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
  50. #define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
  51. #define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
  52. #define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
  53. #define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
  54. #define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
  55. #define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
  56. #define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
  57. #define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
  58. #define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
  59. #define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
  60. #define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
  61. #define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
  62. #define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
  63. #define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
  64. #define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
  65. #define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
  66. #define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
  67. #define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
  68. #define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
  69. #define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
  70. #define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
  71. #define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
  72. #define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
  73. #define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
  74. #define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
  75. #define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
  76. #define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
  77. #define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
  78. #define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
  79. #define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
  80. #define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
  81. #define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
  82. #define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
  83. #define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
  84. #define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
  85. #define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
  86. #define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
  87. #define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
  88. #define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
  89. #define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
  90. #define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
  91. #define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
  92. #define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
  93. #define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
  94. #define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
  95. #define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
  96. #define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
  97. #define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
  98. #define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
  99. #define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
  100. #define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
  101. #define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
  102. #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
  103. #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
  104. #define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
  105. #define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
  106. #define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
  107. #define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
  108. #define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
  109. #define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
  110. #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
  111. #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
  112. #define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
  113. #define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
  114. #define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
  115. #define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
  116. #define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
  117. #define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
  118. #define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
  119. #define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
  120. #define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
  121. #define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
  122. #define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
  123. #define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
  124. #define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
  125. #define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
  126. #define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
  127. #define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
  128. #define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
  129. #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
  130. #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
  131. #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
  132. #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
  133. #define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
  134. #define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
  135. #define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
  136. #define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
  137. #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
  138. #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
  139. #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
  140. #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
  141. #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
  142. #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
  143. #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
  144. #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
  145. #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
  146. #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
  147. #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
  148. #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
  149. #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
  150. #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
  151. #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
  152. #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
  153. #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
  154. #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
  155. #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
  156. #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
  157. #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
  158. #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
  159. #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
  160. #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
  161. #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
  162. #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
  163. #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
  164. #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
  165. #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
  166. #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
  167. #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
  168. #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
  169. #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
  170. #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
  171. #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
  172. #define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
  173. #define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
  174. #define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
  175. #define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
  176. #define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
  177. #define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
  178. #define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
  179. #define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
  180. #define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
  181. #define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
  182. #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
  183. #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
  184. #define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
  185. #define TEGRA_PIN_PU0 _GPIO(160)
  186. #define TEGRA_PIN_PU1 _GPIO(161)
  187. #define TEGRA_PIN_PU2 _GPIO(162)
  188. #define TEGRA_PIN_PU3 _GPIO(163)
  189. #define TEGRA_PIN_PU4 _GPIO(164)
  190. #define TEGRA_PIN_PU5 _GPIO(165)
  191. #define TEGRA_PIN_PU6 _GPIO(166)
  192. #define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
  193. #define TEGRA_PIN_PV0 _GPIO(168)
  194. #define TEGRA_PIN_PV1 _GPIO(169)
  195. #define TEGRA_PIN_PV2 _GPIO(170)
  196. #define TEGRA_PIN_PV3 _GPIO(171)
  197. #define TEGRA_PIN_PV4 _GPIO(172)
  198. #define TEGRA_PIN_PV5 _GPIO(173)
  199. #define TEGRA_PIN_PV6 _GPIO(174)
  200. #define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
  201. #define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
  202. #define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
  203. #define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
  204. #define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
  205. #define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
  206. #define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
  207. #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
  208. #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
  209. #define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
  210. #define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
  211. #define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
  212. #define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
  213. #define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
  214. #define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
  215. #define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
  216. #define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
  217. #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
  218. #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
  219. #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
  220. #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
  221. #define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
  222. #define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
  223. #define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
  224. #define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
  225. #define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
  226. #define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
  227. #define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
  228. #define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
  229. #define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
  230. #define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
  231. #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
  232. #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
  233. #define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
  234. #define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
  235. #define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
  236. #define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
  237. #define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
  238. #define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
  239. #define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
  240. #define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
  241. #define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
  242. #define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
  243. #define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
  244. #define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
  245. #define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
  246. #define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
  247. #define TEGRA_PIN_PBB6 _GPIO(222)
  248. #define TEGRA_PIN_PBB7 _GPIO(223)
  249. /* All non-GPIO pins follow */
  250. #define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
  251. #define _PIN(offset) (NUM_GPIOS + (offset))
  252. #define TEGRA_PIN_CRT_HSYNC _PIN(30)
  253. #define TEGRA_PIN_CRT_VSYNC _PIN(31)
  254. #define TEGRA_PIN_DDC_SCL _PIN(32)
  255. #define TEGRA_PIN_DDC_SDA _PIN(33)
  256. #define TEGRA_PIN_OWC _PIN(34)
  257. #define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
  258. #define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
  259. #define TEGRA_PIN_PWR_INT_N _PIN(37)
  260. #define TEGRA_PIN_CLK_32_K_IN _PIN(38)
  261. #define TEGRA_PIN_DDR_COMP_PD _PIN(39)
  262. #define TEGRA_PIN_DDR_COMP_PU _PIN(40)
  263. #define TEGRA_PIN_DDR_A0 _PIN(41)
  264. #define TEGRA_PIN_DDR_A1 _PIN(42)
  265. #define TEGRA_PIN_DDR_A2 _PIN(43)
  266. #define TEGRA_PIN_DDR_A3 _PIN(44)
  267. #define TEGRA_PIN_DDR_A4 _PIN(45)
  268. #define TEGRA_PIN_DDR_A5 _PIN(46)
  269. #define TEGRA_PIN_DDR_A6 _PIN(47)
  270. #define TEGRA_PIN_DDR_A7 _PIN(48)
  271. #define TEGRA_PIN_DDR_A8 _PIN(49)
  272. #define TEGRA_PIN_DDR_A9 _PIN(50)
  273. #define TEGRA_PIN_DDR_A10 _PIN(51)
  274. #define TEGRA_PIN_DDR_A11 _PIN(52)
  275. #define TEGRA_PIN_DDR_A12 _PIN(53)
  276. #define TEGRA_PIN_DDR_A13 _PIN(54)
  277. #define TEGRA_PIN_DDR_A14 _PIN(55)
  278. #define TEGRA_PIN_DDR_CAS_N _PIN(56)
  279. #define TEGRA_PIN_DDR_BA0 _PIN(57)
  280. #define TEGRA_PIN_DDR_BA1 _PIN(58)
  281. #define TEGRA_PIN_DDR_BA2 _PIN(59)
  282. #define TEGRA_PIN_DDR_DQS0P _PIN(60)
  283. #define TEGRA_PIN_DDR_DQS0N _PIN(61)
  284. #define TEGRA_PIN_DDR_DQS1P _PIN(62)
  285. #define TEGRA_PIN_DDR_DQS1N _PIN(63)
  286. #define TEGRA_PIN_DDR_DQS2P _PIN(64)
  287. #define TEGRA_PIN_DDR_DQS2N _PIN(65)
  288. #define TEGRA_PIN_DDR_DQS3P _PIN(66)
  289. #define TEGRA_PIN_DDR_DQS3N _PIN(67)
  290. #define TEGRA_PIN_DDR_CKE0 _PIN(68)
  291. #define TEGRA_PIN_DDR_CKE1 _PIN(69)
  292. #define TEGRA_PIN_DDR_CLK _PIN(70)
  293. #define TEGRA_PIN_DDR_CLK_N _PIN(71)
  294. #define TEGRA_PIN_DDR_DM0 _PIN(72)
  295. #define TEGRA_PIN_DDR_DM1 _PIN(73)
  296. #define TEGRA_PIN_DDR_DM2 _PIN(74)
  297. #define TEGRA_PIN_DDR_DM3 _PIN(75)
  298. #define TEGRA_PIN_DDR_ODT _PIN(76)
  299. #define TEGRA_PIN_DDR_QUSE0 _PIN(77)
  300. #define TEGRA_PIN_DDR_QUSE1 _PIN(78)
  301. #define TEGRA_PIN_DDR_QUSE2 _PIN(79)
  302. #define TEGRA_PIN_DDR_QUSE3 _PIN(80)
  303. #define TEGRA_PIN_DDR_RAS_N _PIN(81)
  304. #define TEGRA_PIN_DDR_WE_N _PIN(82)
  305. #define TEGRA_PIN_DDR_DQ0 _PIN(83)
  306. #define TEGRA_PIN_DDR_DQ1 _PIN(84)
  307. #define TEGRA_PIN_DDR_DQ2 _PIN(85)
  308. #define TEGRA_PIN_DDR_DQ3 _PIN(86)
  309. #define TEGRA_PIN_DDR_DQ4 _PIN(87)
  310. #define TEGRA_PIN_DDR_DQ5 _PIN(88)
  311. #define TEGRA_PIN_DDR_DQ6 _PIN(89)
  312. #define TEGRA_PIN_DDR_DQ7 _PIN(90)
  313. #define TEGRA_PIN_DDR_DQ8 _PIN(91)
  314. #define TEGRA_PIN_DDR_DQ9 _PIN(92)
  315. #define TEGRA_PIN_DDR_DQ10 _PIN(93)
  316. #define TEGRA_PIN_DDR_DQ11 _PIN(94)
  317. #define TEGRA_PIN_DDR_DQ12 _PIN(95)
  318. #define TEGRA_PIN_DDR_DQ13 _PIN(96)
  319. #define TEGRA_PIN_DDR_DQ14 _PIN(97)
  320. #define TEGRA_PIN_DDR_DQ15 _PIN(98)
  321. #define TEGRA_PIN_DDR_DQ16 _PIN(99)
  322. #define TEGRA_PIN_DDR_DQ17 _PIN(100)
  323. #define TEGRA_PIN_DDR_DQ18 _PIN(101)
  324. #define TEGRA_PIN_DDR_DQ19 _PIN(102)
  325. #define TEGRA_PIN_DDR_DQ20 _PIN(103)
  326. #define TEGRA_PIN_DDR_DQ21 _PIN(104)
  327. #define TEGRA_PIN_DDR_DQ22 _PIN(105)
  328. #define TEGRA_PIN_DDR_DQ23 _PIN(106)
  329. #define TEGRA_PIN_DDR_DQ24 _PIN(107)
  330. #define TEGRA_PIN_DDR_DQ25 _PIN(108)
  331. #define TEGRA_PIN_DDR_DQ26 _PIN(109)
  332. #define TEGRA_PIN_DDR_DQ27 _PIN(110)
  333. #define TEGRA_PIN_DDR_DQ28 _PIN(111)
  334. #define TEGRA_PIN_DDR_DQ29 _PIN(112)
  335. #define TEGRA_PIN_DDR_DQ30 _PIN(113)
  336. #define TEGRA_PIN_DDR_DQ31 _PIN(114)
  337. #define TEGRA_PIN_DDR_CS0_N _PIN(115)
  338. #define TEGRA_PIN_DDR_CS1_N _PIN(116)
  339. #define TEGRA_PIN_SYS_RESET _PIN(117)
  340. #define TEGRA_PIN_JTAG_TRST_N _PIN(118)
  341. #define TEGRA_PIN_JTAG_TDO _PIN(119)
  342. #define TEGRA_PIN_JTAG_TMS _PIN(120)
  343. #define TEGRA_PIN_JTAG_TCK _PIN(121)
  344. #define TEGRA_PIN_JTAG_TDI _PIN(122)
  345. #define TEGRA_PIN_TEST_MODE_EN _PIN(123)
  346. static const struct pinctrl_pin_desc tegra20_pins[] = {
  347. PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
  348. PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
  349. PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
  350. PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
  351. PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
  352. PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
  353. PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
  354. PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
  355. PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
  356. PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
  357. PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
  358. PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
  359. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
  360. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
  361. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
  362. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
  363. PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
  364. PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
  365. PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
  366. PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
  367. PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
  368. PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
  369. PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
  370. PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
  371. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
  372. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
  373. PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
  374. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
  375. PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
  376. PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
  377. PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
  378. PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
  379. PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
  380. PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
  381. PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
  382. PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
  383. PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
  384. PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
  385. PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
  386. PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
  387. PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
  388. PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
  389. PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
  390. PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
  391. PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
  392. PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
  393. PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
  394. PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
  395. PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
  396. PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
  397. PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
  398. PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
  399. PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
  400. PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
  401. PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
  402. PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
  403. PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
  404. PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
  405. PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
  406. PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
  407. PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
  408. PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
  409. PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
  410. PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
  411. PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
  412. PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
  413. PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
  414. PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
  415. PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
  416. PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
  417. PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
  418. PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
  419. PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
  420. PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
  421. PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
  422. PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
  423. PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
  424. PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
  425. PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
  426. PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
  427. PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
  428. PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
  429. PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
  430. PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
  431. PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
  432. PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
  433. PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
  434. PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
  435. PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
  436. PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
  437. PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
  438. PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
  439. PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
  440. PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
  441. PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
  442. PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
  443. PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
  444. PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
  445. PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
  446. PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
  447. PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
  448. PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
  449. PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
  450. PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
  451. PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
  452. PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
  453. PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
  454. PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
  455. PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
  456. PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
  457. PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
  458. PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
  459. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
  460. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
  461. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
  462. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
  463. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
  464. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
  465. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
  466. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
  467. PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
  468. PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
  469. PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
  470. PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
  471. PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
  472. PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
  473. PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
  474. PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
  475. PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
  476. PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
  477. PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
  478. PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
  479. PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
  480. PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
  481. PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
  482. PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
  483. PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
  484. PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
  485. PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
  486. PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
  487. PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
  488. PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
  489. PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
  490. PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
  491. PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
  492. PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
  493. PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
  494. PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
  495. PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
  496. PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
  497. PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
  498. PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
  499. PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
  500. PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
  501. PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
  502. PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
  503. PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
  504. PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
  505. PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
  506. PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
  507. /* PU0..6: GPIO only */
  508. PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
  509. PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
  510. PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
  511. PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
  512. PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
  513. PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
  514. PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
  515. PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
  516. /* PV0..1: GPIO only */
  517. PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
  518. PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
  519. /* PV2..3: Balls are named after GPIO not function */
  520. PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
  521. PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
  522. /* PV4..6: GPIO only */
  523. PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
  524. PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
  525. PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
  526. PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
  527. PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
  528. PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
  529. PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
  530. PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
  531. PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
  532. PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
  533. PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
  534. PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
  535. PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
  536. PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
  537. PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
  538. PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
  539. PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
  540. PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
  541. PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
  542. PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
  543. PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
  544. PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
  545. PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
  546. PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
  547. PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
  548. PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
  549. PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
  550. PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
  551. PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
  552. PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
  553. PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
  554. PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
  555. PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
  556. PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
  557. PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
  558. PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
  559. PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
  560. PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
  561. PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
  562. PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
  563. PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
  564. PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
  565. PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
  566. PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
  567. PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
  568. PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
  569. PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
  570. PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
  571. PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
  572. PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
  573. PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
  574. PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
  575. PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
  576. PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
  577. PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
  578. PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
  579. PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
  580. PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
  581. PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
  582. PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
  583. PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
  584. PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
  585. PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
  586. PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
  587. PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
  588. PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
  589. PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
  590. PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
  591. PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
  592. PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
  593. PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
  594. PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
  595. PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
  596. PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
  597. PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
  598. PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
  599. PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
  600. PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
  601. PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
  602. PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
  603. PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
  604. PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
  605. PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
  606. PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
  607. PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
  608. PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
  609. PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
  610. PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
  611. PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
  612. PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
  613. PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
  614. PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
  615. PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
  616. PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
  617. PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
  618. PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
  619. PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
  620. PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
  621. PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
  622. PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
  623. PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
  624. PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
  625. PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
  626. PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
  627. PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
  628. PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
  629. PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
  630. PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
  631. PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
  632. PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
  633. PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
  634. PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
  635. PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
  636. PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
  637. PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
  638. PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
  639. PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
  640. PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
  641. PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
  642. PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
  643. PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
  644. PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
  645. PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
  646. PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
  647. PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
  648. PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
  649. PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
  650. PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
  651. PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
  652. PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
  653. PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
  654. PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
  655. PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
  656. PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
  657. PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
  658. PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
  659. PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
  660. PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
  661. PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
  662. PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
  663. PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
  664. PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
  665. PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
  666. PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
  667. PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
  668. PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
  669. };
  670. static const unsigned ata_pins[] = {
  671. TEGRA_PIN_GMI_CS6_N_PI3,
  672. TEGRA_PIN_GMI_CS7_N_PI6,
  673. TEGRA_PIN_GMI_RST_N_PI4,
  674. };
  675. static const unsigned atb_pins[] = {
  676. TEGRA_PIN_GMI_CS5_N_PI2,
  677. TEGRA_PIN_GMI_DPD_PT7,
  678. };
  679. static const unsigned atc_pins[] = {
  680. TEGRA_PIN_GMI_IORDY_PI5,
  681. TEGRA_PIN_GMI_WAIT_PI7,
  682. TEGRA_PIN_GMI_ADV_N_PK0,
  683. TEGRA_PIN_GMI_CLK_PK1,
  684. TEGRA_PIN_GMI_CS2_N_PK3,
  685. TEGRA_PIN_GMI_CS3_N_PK4,
  686. TEGRA_PIN_GMI_CS4_N_PK2,
  687. TEGRA_PIN_GMI_AD0_PG0,
  688. TEGRA_PIN_GMI_AD1_PG1,
  689. TEGRA_PIN_GMI_AD2_PG2,
  690. TEGRA_PIN_GMI_AD3_PG3,
  691. TEGRA_PIN_GMI_AD4_PG4,
  692. TEGRA_PIN_GMI_AD5_PG5,
  693. TEGRA_PIN_GMI_AD6_PG6,
  694. TEGRA_PIN_GMI_AD7_PG7,
  695. TEGRA_PIN_GMI_HIOW_N_PI0,
  696. TEGRA_PIN_GMI_HIOR_N_PI1,
  697. };
  698. static const unsigned atd_pins[] = {
  699. TEGRA_PIN_GMI_AD8_PH0,
  700. TEGRA_PIN_GMI_AD9_PH1,
  701. TEGRA_PIN_GMI_AD10_PH2,
  702. TEGRA_PIN_GMI_AD11_PH3,
  703. };
  704. static const unsigned ate_pins[] = {
  705. TEGRA_PIN_GMI_AD12_PH4,
  706. TEGRA_PIN_GMI_AD13_PH5,
  707. TEGRA_PIN_GMI_AD14_PH6,
  708. TEGRA_PIN_GMI_AD15_PH7,
  709. };
  710. static const unsigned cdev1_pins[] = {
  711. TEGRA_PIN_DAP_MCLK1_PW4,
  712. };
  713. static const unsigned cdev2_pins[] = {
  714. TEGRA_PIN_DAP_MCLK2_PW5,
  715. };
  716. static const unsigned crtp_pins[] = {
  717. TEGRA_PIN_CRT_HSYNC,
  718. TEGRA_PIN_CRT_VSYNC,
  719. };
  720. static const unsigned csus_pins[] = {
  721. TEGRA_PIN_VI_MCLK_PT1,
  722. };
  723. static const unsigned dap1_pins[] = {
  724. TEGRA_PIN_DAP1_FS_PN0,
  725. TEGRA_PIN_DAP1_DIN_PN1,
  726. TEGRA_PIN_DAP1_DOUT_PN2,
  727. TEGRA_PIN_DAP1_SCLK_PN3,
  728. };
  729. static const unsigned dap2_pins[] = {
  730. TEGRA_PIN_DAP2_FS_PA2,
  731. TEGRA_PIN_DAP2_SCLK_PA3,
  732. TEGRA_PIN_DAP2_DIN_PA4,
  733. TEGRA_PIN_DAP2_DOUT_PA5,
  734. };
  735. static const unsigned dap3_pins[] = {
  736. TEGRA_PIN_DAP3_FS_PP0,
  737. TEGRA_PIN_DAP3_DIN_PP1,
  738. TEGRA_PIN_DAP3_DOUT_PP2,
  739. TEGRA_PIN_DAP3_SCLK_PP3,
  740. };
  741. static const unsigned dap4_pins[] = {
  742. TEGRA_PIN_DAP4_FS_PP4,
  743. TEGRA_PIN_DAP4_DIN_PP5,
  744. TEGRA_PIN_DAP4_DOUT_PP6,
  745. TEGRA_PIN_DAP4_SCLK_PP7,
  746. };
  747. static const unsigned ddc_pins[] = {
  748. TEGRA_PIN_DDC_SCL,
  749. TEGRA_PIN_DDC_SDA,
  750. };
  751. static const unsigned dta_pins[] = {
  752. TEGRA_PIN_VI_D0_PT4,
  753. TEGRA_PIN_VI_D1_PD5,
  754. };
  755. static const unsigned dtb_pins[] = {
  756. TEGRA_PIN_VI_D10_PT2,
  757. TEGRA_PIN_VI_D11_PT3,
  758. };
  759. static const unsigned dtc_pins[] = {
  760. TEGRA_PIN_VI_HSYNC_PD7,
  761. TEGRA_PIN_VI_VSYNC_PD6,
  762. };
  763. static const unsigned dtd_pins[] = {
  764. TEGRA_PIN_VI_PCLK_PT0,
  765. TEGRA_PIN_VI_D2_PL0,
  766. TEGRA_PIN_VI_D3_PL1,
  767. TEGRA_PIN_VI_D4_PL2,
  768. TEGRA_PIN_VI_D5_PL3,
  769. TEGRA_PIN_VI_D6_PL4,
  770. TEGRA_PIN_VI_D7_PL5,
  771. TEGRA_PIN_VI_D8_PL6,
  772. TEGRA_PIN_VI_D9_PL7,
  773. };
  774. static const unsigned dte_pins[] = {
  775. TEGRA_PIN_VI_GP0_PBB1,
  776. TEGRA_PIN_VI_GP3_PBB4,
  777. TEGRA_PIN_VI_GP4_PBB5,
  778. TEGRA_PIN_VI_GP5_PD2,
  779. TEGRA_PIN_VI_GP6_PA0,
  780. };
  781. static const unsigned dtf_pins[] = {
  782. TEGRA_PIN_CAM_I2C_SCL_PBB2,
  783. TEGRA_PIN_CAM_I2C_SDA_PBB3,
  784. };
  785. static const unsigned gma_pins[] = {
  786. TEGRA_PIN_GMI_AD20_PAA0,
  787. TEGRA_PIN_GMI_AD21_PAA1,
  788. TEGRA_PIN_GMI_AD22_PAA2,
  789. TEGRA_PIN_GMI_AD23_PAA3,
  790. };
  791. static const unsigned gmb_pins[] = {
  792. TEGRA_PIN_GMI_WP_N_PC7,
  793. };
  794. static const unsigned gmc_pins[] = {
  795. TEGRA_PIN_GMI_AD16_PJ7,
  796. TEGRA_PIN_GMI_AD17_PB0,
  797. TEGRA_PIN_GMI_AD18_PB1,
  798. TEGRA_PIN_GMI_AD19_PK7,
  799. };
  800. static const unsigned gmd_pins[] = {
  801. TEGRA_PIN_GMI_CS0_N_PJ0,
  802. TEGRA_PIN_GMI_CS1_N_PJ2,
  803. };
  804. static const unsigned gme_pins[] = {
  805. TEGRA_PIN_GMI_AD24_PAA4,
  806. TEGRA_PIN_GMI_AD25_PAA5,
  807. TEGRA_PIN_GMI_AD26_PAA6,
  808. TEGRA_PIN_GMI_AD27_PAA7,
  809. };
  810. static const unsigned gpu_pins[] = {
  811. TEGRA_PIN_PU0,
  812. TEGRA_PIN_PU1,
  813. TEGRA_PIN_PU2,
  814. TEGRA_PIN_PU3,
  815. TEGRA_PIN_PU4,
  816. TEGRA_PIN_PU5,
  817. TEGRA_PIN_PU6,
  818. };
  819. static const unsigned gpu7_pins[] = {
  820. TEGRA_PIN_JTAG_RTCK_PU7,
  821. };
  822. static const unsigned gpv_pins[] = {
  823. TEGRA_PIN_PV4,
  824. TEGRA_PIN_PV5,
  825. TEGRA_PIN_PV6,
  826. };
  827. static const unsigned hdint_pins[] = {
  828. TEGRA_PIN_HDMI_INT_N_PN7,
  829. };
  830. static const unsigned i2cp_pins[] = {
  831. TEGRA_PIN_PWR_I2C_SCL_PZ6,
  832. TEGRA_PIN_PWR_I2C_SDA_PZ7,
  833. };
  834. static const unsigned irrx_pins[] = {
  835. TEGRA_PIN_UART2_RTS_N_PJ6,
  836. };
  837. static const unsigned irtx_pins[] = {
  838. TEGRA_PIN_UART2_CTS_N_PJ5,
  839. };
  840. static const unsigned kbca_pins[] = {
  841. TEGRA_PIN_KB_ROW0_PR0,
  842. TEGRA_PIN_KB_ROW1_PR1,
  843. TEGRA_PIN_KB_ROW2_PR2,
  844. };
  845. static const unsigned kbcb_pins[] = {
  846. TEGRA_PIN_KB_ROW7_PR7,
  847. TEGRA_PIN_KB_ROW8_PS0,
  848. TEGRA_PIN_KB_ROW9_PS1,
  849. TEGRA_PIN_KB_ROW10_PS2,
  850. TEGRA_PIN_KB_ROW11_PS3,
  851. TEGRA_PIN_KB_ROW12_PS4,
  852. TEGRA_PIN_KB_ROW13_PS5,
  853. TEGRA_PIN_KB_ROW14_PS6,
  854. TEGRA_PIN_KB_ROW15_PS7,
  855. };
  856. static const unsigned kbcc_pins[] = {
  857. TEGRA_PIN_KB_COL0_PQ0,
  858. TEGRA_PIN_KB_COL1_PQ1,
  859. };
  860. static const unsigned kbcd_pins[] = {
  861. TEGRA_PIN_KB_ROW3_PR3,
  862. TEGRA_PIN_KB_ROW4_PR4,
  863. TEGRA_PIN_KB_ROW5_PR5,
  864. TEGRA_PIN_KB_ROW6_PR6,
  865. };
  866. static const unsigned kbce_pins[] = {
  867. TEGRA_PIN_KB_COL7_PQ7,
  868. };
  869. static const unsigned kbcf_pins[] = {
  870. TEGRA_PIN_KB_COL2_PQ2,
  871. TEGRA_PIN_KB_COL3_PQ3,
  872. TEGRA_PIN_KB_COL4_PQ4,
  873. TEGRA_PIN_KB_COL5_PQ5,
  874. TEGRA_PIN_KB_COL6_PQ6,
  875. };
  876. static const unsigned lcsn_pins[] = {
  877. TEGRA_PIN_LCD_CS0_N_PN4,
  878. };
  879. static const unsigned ld0_pins[] = {
  880. TEGRA_PIN_LCD_D0_PE0,
  881. };
  882. static const unsigned ld1_pins[] = {
  883. TEGRA_PIN_LCD_D1_PE1,
  884. };
  885. static const unsigned ld2_pins[] = {
  886. TEGRA_PIN_LCD_D2_PE2,
  887. };
  888. static const unsigned ld3_pins[] = {
  889. TEGRA_PIN_LCD_D3_PE3,
  890. };
  891. static const unsigned ld4_pins[] = {
  892. TEGRA_PIN_LCD_D4_PE4,
  893. };
  894. static const unsigned ld5_pins[] = {
  895. TEGRA_PIN_LCD_D5_PE5,
  896. };
  897. static const unsigned ld6_pins[] = {
  898. TEGRA_PIN_LCD_D6_PE6,
  899. };
  900. static const unsigned ld7_pins[] = {
  901. TEGRA_PIN_LCD_D7_PE7,
  902. };
  903. static const unsigned ld8_pins[] = {
  904. TEGRA_PIN_LCD_D8_PF0,
  905. };
  906. static const unsigned ld9_pins[] = {
  907. TEGRA_PIN_LCD_D9_PF1,
  908. };
  909. static const unsigned ld10_pins[] = {
  910. TEGRA_PIN_LCD_D10_PF2,
  911. };
  912. static const unsigned ld11_pins[] = {
  913. TEGRA_PIN_LCD_D11_PF3,
  914. };
  915. static const unsigned ld12_pins[] = {
  916. TEGRA_PIN_LCD_D12_PF4,
  917. };
  918. static const unsigned ld13_pins[] = {
  919. TEGRA_PIN_LCD_D13_PF5,
  920. };
  921. static const unsigned ld14_pins[] = {
  922. TEGRA_PIN_LCD_D14_PF6,
  923. };
  924. static const unsigned ld15_pins[] = {
  925. TEGRA_PIN_LCD_D15_PF7,
  926. };
  927. static const unsigned ld16_pins[] = {
  928. TEGRA_PIN_LCD_D16_PM0,
  929. };
  930. static const unsigned ld17_pins[] = {
  931. TEGRA_PIN_LCD_D17_PM1,
  932. };
  933. static const unsigned ldc_pins[] = {
  934. TEGRA_PIN_LCD_DC0_PN6,
  935. };
  936. static const unsigned ldi_pins[] = {
  937. TEGRA_PIN_LCD_D22_PM6,
  938. };
  939. static const unsigned lhp0_pins[] = {
  940. TEGRA_PIN_LCD_D21_PM5,
  941. };
  942. static const unsigned lhp1_pins[] = {
  943. TEGRA_PIN_LCD_D18_PM2,
  944. };
  945. static const unsigned lhp2_pins[] = {
  946. TEGRA_PIN_LCD_D19_PM3,
  947. };
  948. static const unsigned lhs_pins[] = {
  949. TEGRA_PIN_LCD_HSYNC_PJ3,
  950. };
  951. static const unsigned lm0_pins[] = {
  952. TEGRA_PIN_LCD_CS1_N_PW0,
  953. };
  954. static const unsigned lm1_pins[] = {
  955. TEGRA_PIN_LCD_M1_PW1,
  956. };
  957. static const unsigned lpp_pins[] = {
  958. TEGRA_PIN_LCD_D23_PM7,
  959. };
  960. static const unsigned lpw0_pins[] = {
  961. TEGRA_PIN_LCD_PWR0_PB2,
  962. };
  963. static const unsigned lpw1_pins[] = {
  964. TEGRA_PIN_LCD_PWR1_PC1,
  965. };
  966. static const unsigned lpw2_pins[] = {
  967. TEGRA_PIN_LCD_PWR2_PC6,
  968. };
  969. static const unsigned lsc0_pins[] = {
  970. TEGRA_PIN_LCD_PCLK_PB3,
  971. };
  972. static const unsigned lsc1_pins[] = {
  973. TEGRA_PIN_LCD_WR_N_PZ3,
  974. };
  975. static const unsigned lsck_pins[] = {
  976. TEGRA_PIN_LCD_SCK_PZ4,
  977. };
  978. static const unsigned lsda_pins[] = {
  979. TEGRA_PIN_LCD_SDOUT_PN5,
  980. };
  981. static const unsigned lsdi_pins[] = {
  982. TEGRA_PIN_LCD_SDIN_PZ2,
  983. };
  984. static const unsigned lspi_pins[] = {
  985. TEGRA_PIN_LCD_DE_PJ1,
  986. };
  987. static const unsigned lvp0_pins[] = {
  988. TEGRA_PIN_LCD_DC1_PV7,
  989. };
  990. static const unsigned lvp1_pins[] = {
  991. TEGRA_PIN_LCD_D20_PM4,
  992. };
  993. static const unsigned lvs_pins[] = {
  994. TEGRA_PIN_LCD_VSYNC_PJ4,
  995. };
  996. static const unsigned ls_pins[] = {
  997. TEGRA_PIN_LCD_PWR0_PB2,
  998. TEGRA_PIN_LCD_PWR1_PC1,
  999. TEGRA_PIN_LCD_PWR2_PC6,
  1000. TEGRA_PIN_LCD_SDIN_PZ2,
  1001. TEGRA_PIN_LCD_SDOUT_PN5,
  1002. TEGRA_PIN_LCD_WR_N_PZ3,
  1003. TEGRA_PIN_LCD_CS0_N_PN4,
  1004. TEGRA_PIN_LCD_DC0_PN6,
  1005. TEGRA_PIN_LCD_SCK_PZ4,
  1006. };
  1007. static const unsigned lc_pins[] = {
  1008. TEGRA_PIN_LCD_PCLK_PB3,
  1009. TEGRA_PIN_LCD_DE_PJ1,
  1010. TEGRA_PIN_LCD_HSYNC_PJ3,
  1011. TEGRA_PIN_LCD_VSYNC_PJ4,
  1012. TEGRA_PIN_LCD_CS1_N_PW0,
  1013. TEGRA_PIN_LCD_M1_PW1,
  1014. TEGRA_PIN_LCD_DC1_PV7,
  1015. TEGRA_PIN_HDMI_INT_N_PN7,
  1016. };
  1017. static const unsigned ld17_0_pins[] = {
  1018. TEGRA_PIN_LCD_D0_PE0,
  1019. TEGRA_PIN_LCD_D1_PE1,
  1020. TEGRA_PIN_LCD_D2_PE2,
  1021. TEGRA_PIN_LCD_D3_PE3,
  1022. TEGRA_PIN_LCD_D4_PE4,
  1023. TEGRA_PIN_LCD_D5_PE5,
  1024. TEGRA_PIN_LCD_D6_PE6,
  1025. TEGRA_PIN_LCD_D7_PE7,
  1026. TEGRA_PIN_LCD_D8_PF0,
  1027. TEGRA_PIN_LCD_D9_PF1,
  1028. TEGRA_PIN_LCD_D10_PF2,
  1029. TEGRA_PIN_LCD_D11_PF3,
  1030. TEGRA_PIN_LCD_D12_PF4,
  1031. TEGRA_PIN_LCD_D13_PF5,
  1032. TEGRA_PIN_LCD_D14_PF6,
  1033. TEGRA_PIN_LCD_D15_PF7,
  1034. TEGRA_PIN_LCD_D16_PM0,
  1035. TEGRA_PIN_LCD_D17_PM1,
  1036. };
  1037. static const unsigned ld19_18_pins[] = {
  1038. TEGRA_PIN_LCD_D18_PM2,
  1039. TEGRA_PIN_LCD_D19_PM3,
  1040. };
  1041. static const unsigned ld21_20_pins[] = {
  1042. TEGRA_PIN_LCD_D20_PM4,
  1043. TEGRA_PIN_LCD_D21_PM5,
  1044. };
  1045. static const unsigned ld23_22_pins[] = {
  1046. TEGRA_PIN_LCD_D22_PM6,
  1047. TEGRA_PIN_LCD_D23_PM7,
  1048. };
  1049. static const unsigned owc_pins[] = {
  1050. TEGRA_PIN_OWC,
  1051. };
  1052. static const unsigned pmc_pins[] = {
  1053. TEGRA_PIN_LED_BLINK_PBB0,
  1054. TEGRA_PIN_SYS_CLK_REQ_PZ5,
  1055. TEGRA_PIN_CORE_PWR_REQ,
  1056. TEGRA_PIN_CPU_PWR_REQ,
  1057. TEGRA_PIN_PWR_INT_N,
  1058. };
  1059. static const unsigned pta_pins[] = {
  1060. TEGRA_PIN_GEN2_I2C_SCL_PT5,
  1061. TEGRA_PIN_GEN2_I2C_SDA_PT6,
  1062. };
  1063. static const unsigned rm_pins[] = {
  1064. TEGRA_PIN_GEN1_I2C_SCL_PC4,
  1065. TEGRA_PIN_GEN1_I2C_SDA_PC5,
  1066. };
  1067. static const unsigned sdb_pins[] = {
  1068. TEGRA_PIN_SDIO3_CMD_PA7,
  1069. };
  1070. static const unsigned sdc_pins[] = {
  1071. TEGRA_PIN_SDIO3_DAT0_PB7,
  1072. TEGRA_PIN_SDIO3_DAT1_PB6,
  1073. TEGRA_PIN_SDIO3_DAT2_PB5,
  1074. TEGRA_PIN_SDIO3_DAT3_PB4,
  1075. };
  1076. static const unsigned sdd_pins[] = {
  1077. TEGRA_PIN_SDIO3_CLK_PA6,
  1078. };
  1079. static const unsigned sdio1_pins[] = {
  1080. TEGRA_PIN_SDIO1_CLK_PZ0,
  1081. TEGRA_PIN_SDIO1_CMD_PZ1,
  1082. TEGRA_PIN_SDIO1_DAT0_PY7,
  1083. TEGRA_PIN_SDIO1_DAT1_PY6,
  1084. TEGRA_PIN_SDIO1_DAT2_PY5,
  1085. TEGRA_PIN_SDIO1_DAT3_PY4,
  1086. };
  1087. static const unsigned slxa_pins[] = {
  1088. TEGRA_PIN_SDIO3_DAT4_PD1,
  1089. };
  1090. static const unsigned slxc_pins[] = {
  1091. TEGRA_PIN_SDIO3_DAT6_PD3,
  1092. };
  1093. static const unsigned slxd_pins[] = {
  1094. TEGRA_PIN_SDIO3_DAT7_PD4,
  1095. };
  1096. static const unsigned slxk_pins[] = {
  1097. TEGRA_PIN_SDIO3_DAT5_PD0,
  1098. };
  1099. static const unsigned spdi_pins[] = {
  1100. TEGRA_PIN_SPDIF_IN_PK6,
  1101. };
  1102. static const unsigned spdo_pins[] = {
  1103. TEGRA_PIN_SPDIF_OUT_PK5,
  1104. };
  1105. static const unsigned spia_pins[] = {
  1106. TEGRA_PIN_SPI2_MOSI_PX0,
  1107. };
  1108. static const unsigned spib_pins[] = {
  1109. TEGRA_PIN_SPI2_MISO_PX1,
  1110. };
  1111. static const unsigned spic_pins[] = {
  1112. TEGRA_PIN_SPI2_CS0_N_PX3,
  1113. TEGRA_PIN_SPI2_SCK_PX2,
  1114. };
  1115. static const unsigned spid_pins[] = {
  1116. TEGRA_PIN_SPI1_MOSI_PX4,
  1117. };
  1118. static const unsigned spie_pins[] = {
  1119. TEGRA_PIN_SPI1_CS0_N_PX6,
  1120. TEGRA_PIN_SPI1_SCK_PX5,
  1121. };
  1122. static const unsigned spif_pins[] = {
  1123. TEGRA_PIN_SPI1_MISO_PX7,
  1124. };
  1125. static const unsigned spig_pins[] = {
  1126. TEGRA_PIN_SPI2_CS1_N_PW2,
  1127. };
  1128. static const unsigned spih_pins[] = {
  1129. TEGRA_PIN_SPI2_CS2_N_PW3,
  1130. };
  1131. static const unsigned uaa_pins[] = {
  1132. TEGRA_PIN_ULPI_DATA0_PO1,
  1133. TEGRA_PIN_ULPI_DATA1_PO2,
  1134. TEGRA_PIN_ULPI_DATA2_PO3,
  1135. TEGRA_PIN_ULPI_DATA3_PO4,
  1136. };
  1137. static const unsigned uab_pins[] = {
  1138. TEGRA_PIN_ULPI_DATA4_PO5,
  1139. TEGRA_PIN_ULPI_DATA5_PO6,
  1140. TEGRA_PIN_ULPI_DATA6_PO7,
  1141. TEGRA_PIN_ULPI_DATA7_PO0,
  1142. };
  1143. static const unsigned uac_pins[] = {
  1144. TEGRA_PIN_PV0,
  1145. TEGRA_PIN_PV1,
  1146. TEGRA_PIN_PV2,
  1147. TEGRA_PIN_PV3,
  1148. };
  1149. static const unsigned ck32_pins[] = {
  1150. TEGRA_PIN_CLK_32_K_IN,
  1151. };
  1152. static const unsigned uad_pins[] = {
  1153. TEGRA_PIN_UART2_RXD_PC3,
  1154. TEGRA_PIN_UART2_TXD_PC2,
  1155. };
  1156. static const unsigned uca_pins[] = {
  1157. TEGRA_PIN_UART3_RXD_PW7,
  1158. TEGRA_PIN_UART3_TXD_PW6,
  1159. };
  1160. static const unsigned ucb_pins[] = {
  1161. TEGRA_PIN_UART3_CTS_N_PA1,
  1162. TEGRA_PIN_UART3_RTS_N_PC0,
  1163. };
  1164. static const unsigned uda_pins[] = {
  1165. TEGRA_PIN_ULPI_CLK_PY0,
  1166. TEGRA_PIN_ULPI_DIR_PY1,
  1167. TEGRA_PIN_ULPI_NXT_PY2,
  1168. TEGRA_PIN_ULPI_STP_PY3,
  1169. };
  1170. static const unsigned ddrc_pins[] = {
  1171. TEGRA_PIN_DDR_COMP_PD,
  1172. TEGRA_PIN_DDR_COMP_PU,
  1173. };
  1174. static const unsigned pmca_pins[] = {
  1175. TEGRA_PIN_LED_BLINK_PBB0,
  1176. };
  1177. static const unsigned pmcb_pins[] = {
  1178. TEGRA_PIN_SYS_CLK_REQ_PZ5,
  1179. };
  1180. static const unsigned pmcc_pins[] = {
  1181. TEGRA_PIN_CORE_PWR_REQ,
  1182. };
  1183. static const unsigned pmcd_pins[] = {
  1184. TEGRA_PIN_CPU_PWR_REQ,
  1185. };
  1186. static const unsigned pmce_pins[] = {
  1187. TEGRA_PIN_PWR_INT_N,
  1188. };
  1189. static const unsigned xm2c_pins[] = {
  1190. TEGRA_PIN_DDR_A0,
  1191. TEGRA_PIN_DDR_A1,
  1192. TEGRA_PIN_DDR_A2,
  1193. TEGRA_PIN_DDR_A3,
  1194. TEGRA_PIN_DDR_A4,
  1195. TEGRA_PIN_DDR_A5,
  1196. TEGRA_PIN_DDR_A6,
  1197. TEGRA_PIN_DDR_A7,
  1198. TEGRA_PIN_DDR_A8,
  1199. TEGRA_PIN_DDR_A9,
  1200. TEGRA_PIN_DDR_A10,
  1201. TEGRA_PIN_DDR_A11,
  1202. TEGRA_PIN_DDR_A12,
  1203. TEGRA_PIN_DDR_A13,
  1204. TEGRA_PIN_DDR_A14,
  1205. TEGRA_PIN_DDR_CAS_N,
  1206. TEGRA_PIN_DDR_BA0,
  1207. TEGRA_PIN_DDR_BA1,
  1208. TEGRA_PIN_DDR_BA2,
  1209. TEGRA_PIN_DDR_DQS0P,
  1210. TEGRA_PIN_DDR_DQS0N,
  1211. TEGRA_PIN_DDR_DQS1P,
  1212. TEGRA_PIN_DDR_DQS1N,
  1213. TEGRA_PIN_DDR_DQS2P,
  1214. TEGRA_PIN_DDR_DQS2N,
  1215. TEGRA_PIN_DDR_DQS3P,
  1216. TEGRA_PIN_DDR_DQS3N,
  1217. TEGRA_PIN_DDR_CS0_N,
  1218. TEGRA_PIN_DDR_CS1_N,
  1219. TEGRA_PIN_DDR_CKE0,
  1220. TEGRA_PIN_DDR_CKE1,
  1221. TEGRA_PIN_DDR_CLK,
  1222. TEGRA_PIN_DDR_CLK_N,
  1223. TEGRA_PIN_DDR_DM0,
  1224. TEGRA_PIN_DDR_DM1,
  1225. TEGRA_PIN_DDR_DM2,
  1226. TEGRA_PIN_DDR_DM3,
  1227. TEGRA_PIN_DDR_ODT,
  1228. TEGRA_PIN_DDR_RAS_N,
  1229. TEGRA_PIN_DDR_WE_N,
  1230. TEGRA_PIN_DDR_QUSE0,
  1231. TEGRA_PIN_DDR_QUSE1,
  1232. TEGRA_PIN_DDR_QUSE2,
  1233. TEGRA_PIN_DDR_QUSE3,
  1234. };
  1235. static const unsigned xm2d_pins[] = {
  1236. TEGRA_PIN_DDR_DQ0,
  1237. TEGRA_PIN_DDR_DQ1,
  1238. TEGRA_PIN_DDR_DQ2,
  1239. TEGRA_PIN_DDR_DQ3,
  1240. TEGRA_PIN_DDR_DQ4,
  1241. TEGRA_PIN_DDR_DQ5,
  1242. TEGRA_PIN_DDR_DQ6,
  1243. TEGRA_PIN_DDR_DQ7,
  1244. TEGRA_PIN_DDR_DQ8,
  1245. TEGRA_PIN_DDR_DQ9,
  1246. TEGRA_PIN_DDR_DQ10,
  1247. TEGRA_PIN_DDR_DQ11,
  1248. TEGRA_PIN_DDR_DQ12,
  1249. TEGRA_PIN_DDR_DQ13,
  1250. TEGRA_PIN_DDR_DQ14,
  1251. TEGRA_PIN_DDR_DQ15,
  1252. TEGRA_PIN_DDR_DQ16,
  1253. TEGRA_PIN_DDR_DQ17,
  1254. TEGRA_PIN_DDR_DQ18,
  1255. TEGRA_PIN_DDR_DQ19,
  1256. TEGRA_PIN_DDR_DQ20,
  1257. TEGRA_PIN_DDR_DQ21,
  1258. TEGRA_PIN_DDR_DQ22,
  1259. TEGRA_PIN_DDR_DQ23,
  1260. TEGRA_PIN_DDR_DQ24,
  1261. TEGRA_PIN_DDR_DQ25,
  1262. TEGRA_PIN_DDR_DQ26,
  1263. TEGRA_PIN_DDR_DQ27,
  1264. TEGRA_PIN_DDR_DQ28,
  1265. TEGRA_PIN_DDR_DQ29,
  1266. TEGRA_PIN_DDR_DQ30,
  1267. TEGRA_PIN_DDR_DQ31,
  1268. };
  1269. static const unsigned drive_ao1_pins[] = {
  1270. TEGRA_PIN_SYS_RESET,
  1271. TEGRA_PIN_PWR_I2C_SCL_PZ6,
  1272. TEGRA_PIN_PWR_I2C_SDA_PZ7,
  1273. TEGRA_PIN_KB_ROW0_PR0,
  1274. TEGRA_PIN_KB_ROW1_PR1,
  1275. TEGRA_PIN_KB_ROW2_PR2,
  1276. TEGRA_PIN_KB_ROW3_PR3,
  1277. TEGRA_PIN_KB_ROW4_PR4,
  1278. TEGRA_PIN_KB_ROW5_PR5,
  1279. TEGRA_PIN_KB_ROW6_PR6,
  1280. TEGRA_PIN_KB_ROW7_PR7,
  1281. };
  1282. static const unsigned drive_ao2_pins[] = {
  1283. TEGRA_PIN_KB_ROW8_PS0,
  1284. TEGRA_PIN_KB_ROW9_PS1,
  1285. TEGRA_PIN_KB_ROW10_PS2,
  1286. TEGRA_PIN_KB_ROW11_PS3,
  1287. TEGRA_PIN_KB_ROW12_PS4,
  1288. TEGRA_PIN_KB_ROW13_PS5,
  1289. TEGRA_PIN_KB_ROW14_PS6,
  1290. TEGRA_PIN_KB_ROW15_PS7,
  1291. TEGRA_PIN_KB_COL0_PQ0,
  1292. TEGRA_PIN_KB_COL1_PQ1,
  1293. TEGRA_PIN_KB_COL2_PQ2,
  1294. TEGRA_PIN_KB_COL3_PQ3,
  1295. TEGRA_PIN_KB_COL4_PQ4,
  1296. TEGRA_PIN_KB_COL5_PQ5,
  1297. TEGRA_PIN_KB_COL6_PQ6,
  1298. TEGRA_PIN_KB_COL7_PQ7,
  1299. TEGRA_PIN_LED_BLINK_PBB0,
  1300. TEGRA_PIN_SYS_CLK_REQ_PZ5,
  1301. TEGRA_PIN_CORE_PWR_REQ,
  1302. TEGRA_PIN_CPU_PWR_REQ,
  1303. TEGRA_PIN_PWR_INT_N,
  1304. TEGRA_PIN_CLK_32_K_IN,
  1305. };
  1306. static const unsigned drive_at1_pins[] = {
  1307. TEGRA_PIN_GMI_IORDY_PI5,
  1308. TEGRA_PIN_GMI_AD8_PH0,
  1309. TEGRA_PIN_GMI_AD9_PH1,
  1310. TEGRA_PIN_GMI_AD10_PH2,
  1311. TEGRA_PIN_GMI_AD11_PH3,
  1312. TEGRA_PIN_GMI_AD12_PH4,
  1313. TEGRA_PIN_GMI_AD13_PH5,
  1314. TEGRA_PIN_GMI_AD14_PH6,
  1315. TEGRA_PIN_GMI_AD15_PH7,
  1316. TEGRA_PIN_GMI_CS7_N_PI6,
  1317. TEGRA_PIN_GMI_DPD_PT7,
  1318. TEGRA_PIN_GEN2_I2C_SCL_PT5,
  1319. TEGRA_PIN_GEN2_I2C_SDA_PT6,
  1320. };
  1321. static const unsigned drive_at2_pins[] = {
  1322. TEGRA_PIN_GMI_WAIT_PI7,
  1323. TEGRA_PIN_GMI_ADV_N_PK0,
  1324. TEGRA_PIN_GMI_CLK_PK1,
  1325. TEGRA_PIN_GMI_CS6_N_PI3,
  1326. TEGRA_PIN_GMI_CS5_N_PI2,
  1327. TEGRA_PIN_GMI_CS4_N_PK2,
  1328. TEGRA_PIN_GMI_CS3_N_PK4,
  1329. TEGRA_PIN_GMI_CS2_N_PK3,
  1330. TEGRA_PIN_GMI_AD0_PG0,
  1331. TEGRA_PIN_GMI_AD1_PG1,
  1332. TEGRA_PIN_GMI_AD2_PG2,
  1333. TEGRA_PIN_GMI_AD3_PG3,
  1334. TEGRA_PIN_GMI_AD4_PG4,
  1335. TEGRA_PIN_GMI_AD5_PG5,
  1336. TEGRA_PIN_GMI_AD6_PG6,
  1337. TEGRA_PIN_GMI_AD7_PG7,
  1338. TEGRA_PIN_GMI_HIOW_N_PI0,
  1339. TEGRA_PIN_GMI_HIOR_N_PI1,
  1340. TEGRA_PIN_GMI_RST_N_PI4,
  1341. };
  1342. static const unsigned drive_cdev1_pins[] = {
  1343. TEGRA_PIN_DAP_MCLK1_PW4,
  1344. };
  1345. static const unsigned drive_cdev2_pins[] = {
  1346. TEGRA_PIN_DAP_MCLK2_PW5,
  1347. };
  1348. static const unsigned drive_csus_pins[] = {
  1349. TEGRA_PIN_VI_MCLK_PT1,
  1350. };
  1351. static const unsigned drive_dap1_pins[] = {
  1352. TEGRA_PIN_DAP1_FS_PN0,
  1353. TEGRA_PIN_DAP1_DIN_PN1,
  1354. TEGRA_PIN_DAP1_DOUT_PN2,
  1355. TEGRA_PIN_DAP1_SCLK_PN3,
  1356. TEGRA_PIN_SPDIF_OUT_PK5,
  1357. TEGRA_PIN_SPDIF_IN_PK6,
  1358. };
  1359. static const unsigned drive_dap2_pins[] = {
  1360. TEGRA_PIN_DAP2_FS_PA2,
  1361. TEGRA_PIN_DAP2_SCLK_PA3,
  1362. TEGRA_PIN_DAP2_DIN_PA4,
  1363. TEGRA_PIN_DAP2_DOUT_PA5,
  1364. };
  1365. static const unsigned drive_dap3_pins[] = {
  1366. TEGRA_PIN_DAP3_FS_PP0,
  1367. TEGRA_PIN_DAP3_DIN_PP1,
  1368. TEGRA_PIN_DAP3_DOUT_PP2,
  1369. TEGRA_PIN_DAP3_SCLK_PP3,
  1370. };
  1371. static const unsigned drive_dap4_pins[] = {
  1372. TEGRA_PIN_DAP4_FS_PP4,
  1373. TEGRA_PIN_DAP4_DIN_PP5,
  1374. TEGRA_PIN_DAP4_DOUT_PP6,
  1375. TEGRA_PIN_DAP4_SCLK_PP7,
  1376. };
  1377. static const unsigned drive_dbg_pins[] = {
  1378. TEGRA_PIN_PU0,
  1379. TEGRA_PIN_PU1,
  1380. TEGRA_PIN_PU2,
  1381. TEGRA_PIN_PU3,
  1382. TEGRA_PIN_PU4,
  1383. TEGRA_PIN_PU5,
  1384. TEGRA_PIN_PU6,
  1385. TEGRA_PIN_JTAG_RTCK_PU7,
  1386. TEGRA_PIN_GEN1_I2C_SDA_PC5,
  1387. TEGRA_PIN_GEN1_I2C_SCL_PC4,
  1388. TEGRA_PIN_JTAG_TRST_N,
  1389. TEGRA_PIN_JTAG_TDO,
  1390. TEGRA_PIN_JTAG_TMS,
  1391. TEGRA_PIN_JTAG_TCK,
  1392. TEGRA_PIN_JTAG_TDI,
  1393. TEGRA_PIN_TEST_MODE_EN,
  1394. };
  1395. static const unsigned drive_lcd1_pins[] = {
  1396. TEGRA_PIN_LCD_PWR1_PC1,
  1397. TEGRA_PIN_LCD_PWR2_PC6,
  1398. TEGRA_PIN_LCD_SDIN_PZ2,
  1399. TEGRA_PIN_LCD_SDOUT_PN5,
  1400. TEGRA_PIN_LCD_WR_N_PZ3,
  1401. TEGRA_PIN_LCD_CS0_N_PN4,
  1402. TEGRA_PIN_LCD_DC0_PN6,
  1403. TEGRA_PIN_LCD_SCK_PZ4,
  1404. };
  1405. static const unsigned drive_lcd2_pins[] = {
  1406. TEGRA_PIN_LCD_PWR0_PB2,
  1407. TEGRA_PIN_LCD_PCLK_PB3,
  1408. TEGRA_PIN_LCD_DE_PJ1,
  1409. TEGRA_PIN_LCD_HSYNC_PJ3,
  1410. TEGRA_PIN_LCD_VSYNC_PJ4,
  1411. TEGRA_PIN_LCD_D0_PE0,
  1412. TEGRA_PIN_LCD_D1_PE1,
  1413. TEGRA_PIN_LCD_D2_PE2,
  1414. TEGRA_PIN_LCD_D3_PE3,
  1415. TEGRA_PIN_LCD_D4_PE4,
  1416. TEGRA_PIN_LCD_D5_PE5,
  1417. TEGRA_PIN_LCD_D6_PE6,
  1418. TEGRA_PIN_LCD_D7_PE7,
  1419. TEGRA_PIN_LCD_D8_PF0,
  1420. TEGRA_PIN_LCD_D9_PF1,
  1421. TEGRA_PIN_LCD_D10_PF2,
  1422. TEGRA_PIN_LCD_D11_PF3,
  1423. TEGRA_PIN_LCD_D12_PF4,
  1424. TEGRA_PIN_LCD_D13_PF5,
  1425. TEGRA_PIN_LCD_D14_PF6,
  1426. TEGRA_PIN_LCD_D15_PF7,
  1427. TEGRA_PIN_LCD_D16_PM0,
  1428. TEGRA_PIN_LCD_D17_PM1,
  1429. TEGRA_PIN_LCD_D18_PM2,
  1430. TEGRA_PIN_LCD_D19_PM3,
  1431. TEGRA_PIN_LCD_D20_PM4,
  1432. TEGRA_PIN_LCD_D21_PM5,
  1433. TEGRA_PIN_LCD_D22_PM6,
  1434. TEGRA_PIN_LCD_D23_PM7,
  1435. TEGRA_PIN_LCD_CS1_N_PW0,
  1436. TEGRA_PIN_LCD_M1_PW1,
  1437. TEGRA_PIN_LCD_DC1_PV7,
  1438. TEGRA_PIN_HDMI_INT_N_PN7,
  1439. };
  1440. static const unsigned drive_sdmmc2_pins[] = {
  1441. TEGRA_PIN_SDIO3_DAT4_PD1,
  1442. TEGRA_PIN_SDIO3_DAT5_PD0,
  1443. TEGRA_PIN_SDIO3_DAT6_PD3,
  1444. TEGRA_PIN_SDIO3_DAT7_PD4,
  1445. };
  1446. static const unsigned drive_sdmmc3_pins[] = {
  1447. TEGRA_PIN_SDIO3_CLK_PA6,
  1448. TEGRA_PIN_SDIO3_CMD_PA7,
  1449. TEGRA_PIN_SDIO3_DAT0_PB7,
  1450. TEGRA_PIN_SDIO3_DAT1_PB6,
  1451. TEGRA_PIN_SDIO3_DAT2_PB5,
  1452. TEGRA_PIN_SDIO3_DAT3_PB4,
  1453. TEGRA_PIN_PV4,
  1454. TEGRA_PIN_PV5,
  1455. TEGRA_PIN_PV6,
  1456. };
  1457. static const unsigned drive_spi_pins[] = {
  1458. TEGRA_PIN_SPI2_MOSI_PX0,
  1459. TEGRA_PIN_SPI2_MISO_PX1,
  1460. TEGRA_PIN_SPI2_SCK_PX2,
  1461. TEGRA_PIN_SPI2_CS0_N_PX3,
  1462. TEGRA_PIN_SPI1_MOSI_PX4,
  1463. TEGRA_PIN_SPI1_SCK_PX5,
  1464. TEGRA_PIN_SPI1_CS0_N_PX6,
  1465. TEGRA_PIN_SPI1_MISO_PX7,
  1466. TEGRA_PIN_SPI2_CS1_N_PW2,
  1467. TEGRA_PIN_SPI2_CS2_N_PW3,
  1468. };
  1469. static const unsigned drive_uaa_pins[] = {
  1470. TEGRA_PIN_ULPI_DATA0_PO1,
  1471. TEGRA_PIN_ULPI_DATA1_PO2,
  1472. TEGRA_PIN_ULPI_DATA2_PO3,
  1473. TEGRA_PIN_ULPI_DATA3_PO4,
  1474. };
  1475. static const unsigned drive_uab_pins[] = {
  1476. TEGRA_PIN_ULPI_DATA4_PO5,
  1477. TEGRA_PIN_ULPI_DATA5_PO6,
  1478. TEGRA_PIN_ULPI_DATA6_PO7,
  1479. TEGRA_PIN_ULPI_DATA7_PO0,
  1480. TEGRA_PIN_PV0,
  1481. TEGRA_PIN_PV1,
  1482. TEGRA_PIN_PV2,
  1483. TEGRA_PIN_PV3,
  1484. };
  1485. static const unsigned drive_uart2_pins[] = {
  1486. TEGRA_PIN_UART2_TXD_PC2,
  1487. TEGRA_PIN_UART2_RXD_PC3,
  1488. TEGRA_PIN_UART2_RTS_N_PJ6,
  1489. TEGRA_PIN_UART2_CTS_N_PJ5,
  1490. };
  1491. static const unsigned drive_uart3_pins[] = {
  1492. TEGRA_PIN_UART3_TXD_PW6,
  1493. TEGRA_PIN_UART3_RXD_PW7,
  1494. TEGRA_PIN_UART3_RTS_N_PC0,
  1495. TEGRA_PIN_UART3_CTS_N_PA1,
  1496. };
  1497. static const unsigned drive_vi1_pins[] = {
  1498. TEGRA_PIN_VI_D0_PT4,
  1499. TEGRA_PIN_VI_D1_PD5,
  1500. TEGRA_PIN_VI_D2_PL0,
  1501. TEGRA_PIN_VI_D3_PL1,
  1502. TEGRA_PIN_VI_D4_PL2,
  1503. TEGRA_PIN_VI_D5_PL3,
  1504. TEGRA_PIN_VI_D6_PL4,
  1505. TEGRA_PIN_VI_D7_PL5,
  1506. TEGRA_PIN_VI_D8_PL6,
  1507. TEGRA_PIN_VI_D9_PL7,
  1508. TEGRA_PIN_VI_D10_PT2,
  1509. TEGRA_PIN_VI_D11_PT3,
  1510. TEGRA_PIN_VI_PCLK_PT0,
  1511. TEGRA_PIN_VI_VSYNC_PD6,
  1512. TEGRA_PIN_VI_HSYNC_PD7,
  1513. };
  1514. static const unsigned drive_vi2_pins[] = {
  1515. TEGRA_PIN_VI_GP0_PBB1,
  1516. TEGRA_PIN_CAM_I2C_SCL_PBB2,
  1517. TEGRA_PIN_CAM_I2C_SDA_PBB3,
  1518. TEGRA_PIN_VI_GP3_PBB4,
  1519. TEGRA_PIN_VI_GP4_PBB5,
  1520. TEGRA_PIN_VI_GP5_PD2,
  1521. TEGRA_PIN_VI_GP6_PA0,
  1522. };
  1523. static const unsigned drive_xm2a_pins[] = {
  1524. TEGRA_PIN_DDR_A0,
  1525. TEGRA_PIN_DDR_A1,
  1526. TEGRA_PIN_DDR_A2,
  1527. TEGRA_PIN_DDR_A3,
  1528. TEGRA_PIN_DDR_A4,
  1529. TEGRA_PIN_DDR_A5,
  1530. TEGRA_PIN_DDR_A6,
  1531. TEGRA_PIN_DDR_A7,
  1532. TEGRA_PIN_DDR_A8,
  1533. TEGRA_PIN_DDR_A9,
  1534. TEGRA_PIN_DDR_A10,
  1535. TEGRA_PIN_DDR_A11,
  1536. TEGRA_PIN_DDR_A12,
  1537. TEGRA_PIN_DDR_A13,
  1538. TEGRA_PIN_DDR_A14,
  1539. TEGRA_PIN_DDR_BA0,
  1540. TEGRA_PIN_DDR_BA1,
  1541. TEGRA_PIN_DDR_BA2,
  1542. TEGRA_PIN_DDR_CS0_N,
  1543. TEGRA_PIN_DDR_CS1_N,
  1544. TEGRA_PIN_DDR_ODT,
  1545. TEGRA_PIN_DDR_RAS_N,
  1546. TEGRA_PIN_DDR_CAS_N,
  1547. TEGRA_PIN_DDR_WE_N,
  1548. TEGRA_PIN_DDR_CKE0,
  1549. TEGRA_PIN_DDR_CKE1,
  1550. };
  1551. static const unsigned drive_xm2c_pins[] = {
  1552. TEGRA_PIN_DDR_DQS0P,
  1553. TEGRA_PIN_DDR_DQS0N,
  1554. TEGRA_PIN_DDR_DQS1P,
  1555. TEGRA_PIN_DDR_DQS1N,
  1556. TEGRA_PIN_DDR_DQS2P,
  1557. TEGRA_PIN_DDR_DQS2N,
  1558. TEGRA_PIN_DDR_DQS3P,
  1559. TEGRA_PIN_DDR_DQS3N,
  1560. TEGRA_PIN_DDR_QUSE0,
  1561. TEGRA_PIN_DDR_QUSE1,
  1562. TEGRA_PIN_DDR_QUSE2,
  1563. TEGRA_PIN_DDR_QUSE3,
  1564. };
  1565. static const unsigned drive_xm2d_pins[] = {
  1566. TEGRA_PIN_DDR_DQ0,
  1567. TEGRA_PIN_DDR_DQ1,
  1568. TEGRA_PIN_DDR_DQ2,
  1569. TEGRA_PIN_DDR_DQ3,
  1570. TEGRA_PIN_DDR_DQ4,
  1571. TEGRA_PIN_DDR_DQ5,
  1572. TEGRA_PIN_DDR_DQ6,
  1573. TEGRA_PIN_DDR_DQ7,
  1574. TEGRA_PIN_DDR_DQ8,
  1575. TEGRA_PIN_DDR_DQ9,
  1576. TEGRA_PIN_DDR_DQ10,
  1577. TEGRA_PIN_DDR_DQ11,
  1578. TEGRA_PIN_DDR_DQ12,
  1579. TEGRA_PIN_DDR_DQ13,
  1580. TEGRA_PIN_DDR_DQ14,
  1581. TEGRA_PIN_DDR_DQ15,
  1582. TEGRA_PIN_DDR_DQ16,
  1583. TEGRA_PIN_DDR_DQ17,
  1584. TEGRA_PIN_DDR_DQ18,
  1585. TEGRA_PIN_DDR_DQ19,
  1586. TEGRA_PIN_DDR_DQ20,
  1587. TEGRA_PIN_DDR_DQ21,
  1588. TEGRA_PIN_DDR_DQ22,
  1589. TEGRA_PIN_DDR_DQ23,
  1590. TEGRA_PIN_DDR_DQ24,
  1591. TEGRA_PIN_DDR_DQ25,
  1592. TEGRA_PIN_DDR_DQ26,
  1593. TEGRA_PIN_DDR_DQ27,
  1594. TEGRA_PIN_DDR_DQ28,
  1595. TEGRA_PIN_DDR_DQ29,
  1596. TEGRA_PIN_DDR_DQ30,
  1597. TEGRA_PIN_DDR_DQ31,
  1598. TEGRA_PIN_DDR_DM0,
  1599. TEGRA_PIN_DDR_DM1,
  1600. TEGRA_PIN_DDR_DM2,
  1601. TEGRA_PIN_DDR_DM3,
  1602. };
  1603. static const unsigned drive_xm2clk_pins[] = {
  1604. TEGRA_PIN_DDR_CLK,
  1605. TEGRA_PIN_DDR_CLK_N,
  1606. };
  1607. static const unsigned drive_sdio1_pins[] = {
  1608. TEGRA_PIN_SDIO1_CLK_PZ0,
  1609. TEGRA_PIN_SDIO1_CMD_PZ1,
  1610. TEGRA_PIN_SDIO1_DAT0_PY7,
  1611. TEGRA_PIN_SDIO1_DAT1_PY6,
  1612. TEGRA_PIN_SDIO1_DAT2_PY5,
  1613. TEGRA_PIN_SDIO1_DAT3_PY4,
  1614. };
  1615. static const unsigned drive_crt_pins[] = {
  1616. TEGRA_PIN_CRT_HSYNC,
  1617. TEGRA_PIN_CRT_VSYNC,
  1618. };
  1619. static const unsigned drive_ddc_pins[] = {
  1620. TEGRA_PIN_DDC_SCL,
  1621. TEGRA_PIN_DDC_SDA,
  1622. };
  1623. static const unsigned drive_gma_pins[] = {
  1624. TEGRA_PIN_GMI_AD20_PAA0,
  1625. TEGRA_PIN_GMI_AD21_PAA1,
  1626. TEGRA_PIN_GMI_AD22_PAA2,
  1627. TEGRA_PIN_GMI_AD23_PAA3,
  1628. };
  1629. static const unsigned drive_gmb_pins[] = {
  1630. TEGRA_PIN_GMI_WP_N_PC7,
  1631. };
  1632. static const unsigned drive_gmc_pins[] = {
  1633. TEGRA_PIN_GMI_AD16_PJ7,
  1634. TEGRA_PIN_GMI_AD17_PB0,
  1635. TEGRA_PIN_GMI_AD18_PB1,
  1636. TEGRA_PIN_GMI_AD19_PK7,
  1637. };
  1638. static const unsigned drive_gmd_pins[] = {
  1639. TEGRA_PIN_GMI_CS0_N_PJ0,
  1640. TEGRA_PIN_GMI_CS1_N_PJ2,
  1641. };
  1642. static const unsigned drive_gme_pins[] = {
  1643. TEGRA_PIN_GMI_AD24_PAA4,
  1644. TEGRA_PIN_GMI_AD25_PAA5,
  1645. TEGRA_PIN_GMI_AD26_PAA6,
  1646. TEGRA_PIN_GMI_AD27_PAA7,
  1647. };
  1648. static const unsigned drive_owr_pins[] = {
  1649. TEGRA_PIN_OWC,
  1650. };
  1651. static const unsigned drive_uda_pins[] = {
  1652. TEGRA_PIN_ULPI_CLK_PY0,
  1653. TEGRA_PIN_ULPI_DIR_PY1,
  1654. TEGRA_PIN_ULPI_NXT_PY2,
  1655. TEGRA_PIN_ULPI_STP_PY3,
  1656. };
  1657. enum tegra_mux {
  1658. TEGRA_MUX_AHB_CLK,
  1659. TEGRA_MUX_APB_CLK,
  1660. TEGRA_MUX_AUDIO_SYNC,
  1661. TEGRA_MUX_CRT,
  1662. TEGRA_MUX_DAP1,
  1663. TEGRA_MUX_DAP2,
  1664. TEGRA_MUX_DAP3,
  1665. TEGRA_MUX_DAP4,
  1666. TEGRA_MUX_DAP5,
  1667. TEGRA_MUX_DISPLAYA,
  1668. TEGRA_MUX_DISPLAYB,
  1669. TEGRA_MUX_EMC_TEST0_DLL,
  1670. TEGRA_MUX_EMC_TEST1_DLL,
  1671. TEGRA_MUX_GMI,
  1672. TEGRA_MUX_GMI_INT,
  1673. TEGRA_MUX_HDMI,
  1674. TEGRA_MUX_I2CP,
  1675. TEGRA_MUX_I2C1,
  1676. TEGRA_MUX_I2C2,
  1677. TEGRA_MUX_I2C3,
  1678. TEGRA_MUX_IDE,
  1679. TEGRA_MUX_IRDA,
  1680. TEGRA_MUX_KBC,
  1681. TEGRA_MUX_MIO,
  1682. TEGRA_MUX_MIPI_HS,
  1683. TEGRA_MUX_NAND,
  1684. TEGRA_MUX_OSC,
  1685. TEGRA_MUX_OWR,
  1686. TEGRA_MUX_PCIE,
  1687. TEGRA_MUX_PLLA_OUT,
  1688. TEGRA_MUX_PLLC_OUT1,
  1689. TEGRA_MUX_PLLM_OUT1,
  1690. TEGRA_MUX_PLLP_OUT2,
  1691. TEGRA_MUX_PLLP_OUT3,
  1692. TEGRA_MUX_PLLP_OUT4,
  1693. TEGRA_MUX_PWM,
  1694. TEGRA_MUX_PWR_INTR,
  1695. TEGRA_MUX_PWR_ON,
  1696. TEGRA_MUX_RSVD1,
  1697. TEGRA_MUX_RSVD2,
  1698. TEGRA_MUX_RSVD3,
  1699. TEGRA_MUX_RSVD4,
  1700. TEGRA_MUX_RTCK,
  1701. TEGRA_MUX_SDIO1,
  1702. TEGRA_MUX_SDIO2,
  1703. TEGRA_MUX_SDIO3,
  1704. TEGRA_MUX_SDIO4,
  1705. TEGRA_MUX_SFLASH,
  1706. TEGRA_MUX_SPDIF,
  1707. TEGRA_MUX_SPI1,
  1708. TEGRA_MUX_SPI2,
  1709. TEGRA_MUX_SPI2_ALT,
  1710. TEGRA_MUX_SPI3,
  1711. TEGRA_MUX_SPI4,
  1712. TEGRA_MUX_TRACE,
  1713. TEGRA_MUX_TWC,
  1714. TEGRA_MUX_UARTA,
  1715. TEGRA_MUX_UARTB,
  1716. TEGRA_MUX_UARTC,
  1717. TEGRA_MUX_UARTD,
  1718. TEGRA_MUX_UARTE,
  1719. TEGRA_MUX_ULPI,
  1720. TEGRA_MUX_VI,
  1721. TEGRA_MUX_VI_SENSOR_CLK,
  1722. TEGRA_MUX_XIO,
  1723. };
  1724. #define FUNCTION(fname) \
  1725. { \
  1726. .name = #fname, \
  1727. }
  1728. static struct tegra_function tegra20_functions[] = {
  1729. FUNCTION(ahb_clk),
  1730. FUNCTION(apb_clk),
  1731. FUNCTION(audio_sync),
  1732. FUNCTION(crt),
  1733. FUNCTION(dap1),
  1734. FUNCTION(dap2),
  1735. FUNCTION(dap3),
  1736. FUNCTION(dap4),
  1737. FUNCTION(dap5),
  1738. FUNCTION(displaya),
  1739. FUNCTION(displayb),
  1740. FUNCTION(emc_test0_dll),
  1741. FUNCTION(emc_test1_dll),
  1742. FUNCTION(gmi),
  1743. FUNCTION(gmi_int),
  1744. FUNCTION(hdmi),
  1745. FUNCTION(i2cp),
  1746. FUNCTION(i2c1),
  1747. FUNCTION(i2c2),
  1748. FUNCTION(i2c3),
  1749. FUNCTION(ide),
  1750. FUNCTION(irda),
  1751. FUNCTION(kbc),
  1752. FUNCTION(mio),
  1753. FUNCTION(mipi_hs),
  1754. FUNCTION(nand),
  1755. FUNCTION(osc),
  1756. FUNCTION(owr),
  1757. FUNCTION(pcie),
  1758. FUNCTION(plla_out),
  1759. FUNCTION(pllc_out1),
  1760. FUNCTION(pllm_out1),
  1761. FUNCTION(pllp_out2),
  1762. FUNCTION(pllp_out3),
  1763. FUNCTION(pllp_out4),
  1764. FUNCTION(pwm),
  1765. FUNCTION(pwr_intr),
  1766. FUNCTION(pwr_on),
  1767. FUNCTION(rsvd1),
  1768. FUNCTION(rsvd2),
  1769. FUNCTION(rsvd3),
  1770. FUNCTION(rsvd4),
  1771. FUNCTION(rtck),
  1772. FUNCTION(sdio1),
  1773. FUNCTION(sdio2),
  1774. FUNCTION(sdio3),
  1775. FUNCTION(sdio4),
  1776. FUNCTION(sflash),
  1777. FUNCTION(spdif),
  1778. FUNCTION(spi1),
  1779. FUNCTION(spi2),
  1780. FUNCTION(spi2_alt),
  1781. FUNCTION(spi3),
  1782. FUNCTION(spi4),
  1783. FUNCTION(trace),
  1784. FUNCTION(twc),
  1785. FUNCTION(uarta),
  1786. FUNCTION(uartb),
  1787. FUNCTION(uartc),
  1788. FUNCTION(uartd),
  1789. FUNCTION(uarte),
  1790. FUNCTION(ulpi),
  1791. FUNCTION(vi),
  1792. FUNCTION(vi_sensor_clk),
  1793. FUNCTION(xio),
  1794. };
  1795. #define TRISTATE_REG_A 0x14
  1796. #define PIN_MUX_CTL_REG_A 0x80
  1797. #define PULLUPDOWN_REG_A 0xa0
  1798. #define PINGROUP_REG_A 0x868
  1799. /* Pin group with mux control, and typically tri-state and pull-up/down too */
  1800. #define MUX_PG(pg_name, f0, f1, f2, f3, \
  1801. tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
  1802. { \
  1803. .name = #pg_name, \
  1804. .pins = pg_name##_pins, \
  1805. .npins = ARRAY_SIZE(pg_name##_pins), \
  1806. .funcs = { \
  1807. TEGRA_MUX_ ## f0, \
  1808. TEGRA_MUX_ ## f1, \
  1809. TEGRA_MUX_ ## f2, \
  1810. TEGRA_MUX_ ## f3, \
  1811. }, \
  1812. .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
  1813. .mux_bank = 1, \
  1814. .mux_bit = mux_b, \
  1815. .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
  1816. .pupd_bank = 2, \
  1817. .pupd_bit = pupd_b, \
  1818. .tri_reg = ((tri_r) - TRISTATE_REG_A), \
  1819. .tri_bank = 0, \
  1820. .tri_bit = tri_b, \
  1821. .einput_bit = -1, \
  1822. .odrain_bit = -1, \
  1823. .lock_bit = -1, \
  1824. .ioreset_bit = -1, \
  1825. .rcv_sel_bit = -1, \
  1826. .drv_reg = -1, \
  1827. .parked_bitmask = 0, \
  1828. }
  1829. /* Pin groups with only pull up and pull down control */
  1830. #define PULL_PG(pg_name, pupd_r, pupd_b) \
  1831. { \
  1832. .name = #pg_name, \
  1833. .pins = pg_name##_pins, \
  1834. .npins = ARRAY_SIZE(pg_name##_pins), \
  1835. .mux_reg = -1, \
  1836. .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
  1837. .pupd_bank = 2, \
  1838. .pupd_bit = pupd_b, \
  1839. .drv_reg = -1, \
  1840. .parked_bitmask = 0, \
  1841. }
  1842. /* Pin groups for drive strength registers (configurable version) */
  1843. #define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
  1844. drvdn_b, drvup_b, \
  1845. slwr_b, slwr_w, slwf_b, slwf_w) \
  1846. { \
  1847. .name = "drive_" #pg_name, \
  1848. .pins = drive_##pg_name##_pins, \
  1849. .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
  1850. .mux_reg = -1, \
  1851. .pupd_reg = -1, \
  1852. .tri_reg = -1, \
  1853. .drv_reg = ((r) - PINGROUP_REG_A), \
  1854. .drv_bank = 3, \
  1855. .parked_bitmask = 0, \
  1856. .hsm_bit = hsm_b, \
  1857. .schmitt_bit = schmitt_b, \
  1858. .lpmd_bit = lpmd_b, \
  1859. .drvdn_bit = drvdn_b, \
  1860. .drvdn_width = 5, \
  1861. .drvup_bit = drvup_b, \
  1862. .drvup_width = 5, \
  1863. .slwr_bit = slwr_b, \
  1864. .slwr_width = slwr_w, \
  1865. .slwf_bit = slwf_b, \
  1866. .slwf_width = slwf_w, \
  1867. .drvtype_bit = -1, \
  1868. }
  1869. /* Pin groups for drive strength registers (simple version) */
  1870. #define DRV_PG(pg_name, r) \
  1871. DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
  1872. static const struct tegra_pingroup tegra20_groups[] = {
  1873. /* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */
  1874. MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0),
  1875. MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2),
  1876. MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4),
  1877. MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6),
  1878. MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8),
  1879. MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
  1880. MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
  1881. MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24),
  1882. MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
  1883. MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10),
  1884. MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
  1885. MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14),
  1886. MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16),
  1887. MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
  1888. MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
  1889. MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20),
  1890. MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22),
  1891. MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
  1892. MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26),
  1893. MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
  1894. MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20),
  1895. MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22),
  1896. MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24),
  1897. MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26),
  1898. MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24),
  1899. MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
  1900. MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6),
  1901. MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
  1902. MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1),
  1903. MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
  1904. MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22),
  1905. MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20),
  1906. MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
  1907. MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10),
  1908. MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
  1909. MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14),
  1910. MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2),
  1911. MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0),
  1912. MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
  1913. MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
  1914. MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
  1915. MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
  1916. MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
  1917. MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
  1918. MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
  1919. MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
  1920. MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
  1921. MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
  1922. MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
  1923. MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
  1924. MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
  1925. MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
  1926. MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
  1927. MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
  1928. MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
  1929. MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
  1930. MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
  1931. MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
  1932. MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
  1933. MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
  1934. MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
  1935. MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
  1936. MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
  1937. MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
  1938. MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1),
  1939. MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
  1940. MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1),
  1941. MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
  1942. MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1),
  1943. MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
  1944. MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1),
  1945. MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1),
  1946. MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1),
  1947. MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1),
  1948. MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1),
  1949. MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
  1950. MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
  1951. MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
  1952. MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30),
  1953. MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1),
  1954. MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
  1955. MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
  1956. MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
  1957. MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
  1958. MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
  1959. MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18),
  1960. MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
  1961. MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26),
  1962. MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28),
  1963. MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
  1964. MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16),
  1965. MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18),
  1966. MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
  1967. MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
  1968. MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
  1969. MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
  1970. MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
  1971. MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
  1972. MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16),
  1973. MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18),
  1974. MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0),
  1975. MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2),
  1976. MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
  1977. MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6),
  1978. MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
  1979. MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
  1980. MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16),
  1981. /* pg_name, pupd_r/b */
  1982. PULL_PG(ck32, 0xb0, 14),
  1983. PULL_PG(ddrc, 0xac, 26),
  1984. PULL_PG(pmca, 0xb0, 4),
  1985. PULL_PG(pmcb, 0xb0, 6),
  1986. PULL_PG(pmcc, 0xb0, 8),
  1987. PULL_PG(pmcd, 0xb0, 10),
  1988. PULL_PG(pmce, 0xb0, 12),
  1989. PULL_PG(xm2c, 0xa8, 30),
  1990. PULL_PG(xm2d, 0xa8, 28),
  1991. PULL_PG(ls, 0xac, 20),
  1992. PULL_PG(lc, 0xac, 22),
  1993. PULL_PG(ld17_0, 0xac, 12),
  1994. PULL_PG(ld19_18, 0xac, 14),
  1995. PULL_PG(ld21_20, 0xac, 16),
  1996. PULL_PG(ld23_22, 0xac, 18),
  1997. /* pg_name, r */
  1998. DRV_PG(ao1, 0x868),
  1999. DRV_PG(ao2, 0x86c),
  2000. DRV_PG(at1, 0x870),
  2001. DRV_PG(at2, 0x874),
  2002. DRV_PG(cdev1, 0x878),
  2003. DRV_PG(cdev2, 0x87c),
  2004. DRV_PG(csus, 0x880),
  2005. DRV_PG(dap1, 0x884),
  2006. DRV_PG(dap2, 0x888),
  2007. DRV_PG(dap3, 0x88c),
  2008. DRV_PG(dap4, 0x890),
  2009. DRV_PG(dbg, 0x894),
  2010. DRV_PG(lcd1, 0x898),
  2011. DRV_PG(lcd2, 0x89c),
  2012. DRV_PG(sdmmc2, 0x8a0),
  2013. DRV_PG(sdmmc3, 0x8a4),
  2014. DRV_PG(spi, 0x8a8),
  2015. DRV_PG(uaa, 0x8ac),
  2016. DRV_PG(uab, 0x8b0),
  2017. DRV_PG(uart2, 0x8b4),
  2018. DRV_PG(uart3, 0x8b8),
  2019. DRV_PG(vi1, 0x8bc),
  2020. DRV_PG(vi2, 0x8c0),
  2021. /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
  2022. DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
  2023. DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
  2024. DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
  2025. DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
  2026. /* pg_name, r */
  2027. DRV_PG(sdio1, 0x8e0),
  2028. DRV_PG(crt, 0x8ec),
  2029. DRV_PG(ddc, 0x8f0),
  2030. DRV_PG(gma, 0x8f4),
  2031. DRV_PG(gmb, 0x8f8),
  2032. DRV_PG(gmc, 0x8fc),
  2033. DRV_PG(gmd, 0x900),
  2034. DRV_PG(gme, 0x904),
  2035. DRV_PG(owr, 0x908),
  2036. DRV_PG(uda, 0x90c),
  2037. };
  2038. static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
  2039. .ngpios = NUM_GPIOS,
  2040. .gpio_compatible = "nvidia,tegra20-gpio",
  2041. .pins = tegra20_pins,
  2042. .npins = ARRAY_SIZE(tegra20_pins),
  2043. .functions = tegra20_functions,
  2044. .nfunctions = ARRAY_SIZE(tegra20_functions),
  2045. .groups = tegra20_groups,
  2046. .ngroups = ARRAY_SIZE(tegra20_groups),
  2047. .hsm_in_mux = false,
  2048. .schmitt_in_mux = false,
  2049. .drvtype_in_mux = false,
  2050. };
  2051. static const char *cdev1_parents[] = {
  2052. "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
  2053. };
  2054. static const char *cdev2_parents[] = {
  2055. "dev2_osc_div", "hclk", "pclk", "pll_p_out4",
  2056. };
  2057. static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
  2058. {
  2059. struct tegra_pmx *pmx = platform_get_drvdata(pdev);
  2060. clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
  2061. pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
  2062. clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
  2063. pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
  2064. }
  2065. static int tegra20_pinctrl_probe(struct platform_device *pdev)
  2066. {
  2067. int err;
  2068. err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
  2069. if (err)
  2070. return err;
  2071. tegra20_pinctrl_register_clock_muxes(pdev);
  2072. return 0;
  2073. }
  2074. static const struct of_device_id tegra20_pinctrl_of_match[] = {
  2075. { .compatible = "nvidia,tegra20-pinmux", },
  2076. { },
  2077. };
  2078. static struct platform_driver tegra20_pinctrl_driver = {
  2079. .driver = {
  2080. .name = "tegra20-pinctrl",
  2081. .of_match_table = tegra20_pinctrl_of_match,
  2082. },
  2083. .probe = tegra20_pinctrl_probe,
  2084. };
  2085. static int __init tegra20_pinctrl_init(void)
  2086. {
  2087. return platform_driver_register(&tegra20_pinctrl_driver);
  2088. }
  2089. arch_initcall(tegra20_pinctrl_init);