pinctrl-tegra194.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Pinctrl data for the NVIDIA Tegra194 pinmux
  4. *
  5. * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/of.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pinctrl/pinctrl.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include "pinctrl-tegra.h"
  22. /* Define unique ID for each pins */
  23. enum pin_id {
  24. TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
  25. TEGRA_PIN_PEX_L5_RST_N_PGG1,
  26. };
  27. /* Table for pin descriptor */
  28. static const struct pinctrl_pin_desc tegra194_pins[] = {
  29. PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
  30. PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
  31. };
  32. static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
  33. TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
  34. };
  35. static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
  36. TEGRA_PIN_PEX_L5_RST_N_PGG1,
  37. };
  38. /* Define unique ID for each function */
  39. enum tegra_mux_dt {
  40. TEGRA_MUX_RSVD0,
  41. TEGRA_MUX_RSVD1,
  42. TEGRA_MUX_RSVD2,
  43. TEGRA_MUX_RSVD3,
  44. TEGRA_MUX_PE5,
  45. };
  46. /* Make list of each function name */
  47. #define TEGRA_PIN_FUNCTION(lid) \
  48. { \
  49. .name = #lid, \
  50. }
  51. static struct tegra_function tegra194_functions[] = {
  52. TEGRA_PIN_FUNCTION(rsvd0),
  53. TEGRA_PIN_FUNCTION(rsvd1),
  54. TEGRA_PIN_FUNCTION(rsvd2),
  55. TEGRA_PIN_FUNCTION(rsvd3),
  56. TEGRA_PIN_FUNCTION(pe5),
  57. };
  58. #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
  59. drvup_w, slwr_b, slwr_w, slwf_b, \
  60. slwf_w, bank) \
  61. .drv_reg = ((r)), \
  62. .drv_bank = bank, \
  63. .drvdn_bit = drvdn_b, \
  64. .drvdn_width = drvdn_w, \
  65. .drvup_bit = drvup_b, \
  66. .drvup_width = drvup_w, \
  67. .slwr_bit = slwr_b, \
  68. .slwr_width = slwr_w, \
  69. .slwf_bit = slwf_b, \
  70. .slwf_width = slwf_w
  71. #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \
  72. e_od, schmitt_b, drvtype) \
  73. .mux_reg = ((r)), \
  74. .lpmd_bit = -1, \
  75. .lock_bit = -1, \
  76. .hsm_bit = -1, \
  77. .mux_bank = bank, \
  78. .mux_bit = 0, \
  79. .pupd_reg = ((r)), \
  80. .pupd_bank = bank, \
  81. .pupd_bit = 2, \
  82. .tri_reg = ((r)), \
  83. .tri_bank = bank, \
  84. .tri_bit = 4, \
  85. .einput_bit = e_input, \
  86. .odrain_bit = e_od, \
  87. .sfsel_bit = 10, \
  88. .schmitt_bit = schmitt_b, \
  89. .drvtype_bit = 13, \
  90. .parked_bitmask = 0
  91. #define drive_pex_l5_clkreq_n_pgg0 \
  92. DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
  93. #define drive_pex_l5_rst_n_pgg1 \
  94. DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
  95. #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \
  96. e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \
  97. { \
  98. .name = #pg_name, \
  99. .pins = pg_name##_pins, \
  100. .npins = ARRAY_SIZE(pg_name##_pins), \
  101. .funcs = { \
  102. TEGRA_MUX_##f0, \
  103. TEGRA_MUX_##f1, \
  104. TEGRA_MUX_##f2, \
  105. TEGRA_MUX_##f3, \
  106. }, \
  107. PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \
  108. e_input, e_od, \
  109. schmitt_b, drvtype), \
  110. drive_##pg_name, \
  111. }
  112. static const struct tegra_pingroup tegra194_groups[] = {
  113. PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0,
  114. Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
  115. PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0,
  116. Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
  117. };
  118. static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
  119. .pins = tegra194_pins,
  120. .npins = ARRAY_SIZE(tegra194_pins),
  121. .functions = tegra194_functions,
  122. .nfunctions = ARRAY_SIZE(tegra194_functions),
  123. .groups = tegra194_groups,
  124. .ngroups = ARRAY_SIZE(tegra194_groups),
  125. .hsm_in_mux = true,
  126. .schmitt_in_mux = true,
  127. .drvtype_in_mux = true,
  128. .sfsel_in_mux = true,
  129. };
  130. static int tegra194_pinctrl_probe(struct platform_device *pdev)
  131. {
  132. return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
  133. }
  134. static const struct of_device_id tegra194_pinctrl_of_match[] = {
  135. { .compatible = "nvidia,tegra194-pinmux", },
  136. { },
  137. };
  138. static struct platform_driver tegra194_pinctrl_driver = {
  139. .driver = {
  140. .name = "tegra194-pinctrl",
  141. .of_match_table = tegra194_pinctrl_of_match,
  142. },
  143. .probe = tegra194_pinctrl_probe,
  144. };
  145. static int __init tegra194_pinctrl_init(void)
  146. {
  147. return platform_driver_register(&tegra194_pinctrl_driver);
  148. }
  149. arch_initcall(tegra194_pinctrl_init);