pinctrl-tegra114.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Pinctrl data for the NVIDIA Tegra114 pinmux
  4. *
  5. * Author: Pritesh Raithatha <praithatha@nvidia.com>
  6. *
  7. * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
  8. */
  9. #include <linux/init.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pinctrl/pinctrl.h>
  13. #include <linux/pinctrl/pinmux.h>
  14. #include "pinctrl-tegra.h"
  15. /*
  16. * Most pins affected by the pinmux can also be GPIOs. Define these first.
  17. * These must match how the GPIO driver names/numbers its pins.
  18. */
  19. #define _GPIO(offset) (offset)
  20. #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
  21. #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
  22. #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
  23. #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
  24. #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
  25. #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
  26. #define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
  27. #define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
  28. #define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
  29. #define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
  30. #define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
  31. #define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
  32. #define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
  33. #define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
  34. #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
  35. #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
  36. #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
  37. #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
  38. #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
  39. #define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
  40. #define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
  41. #define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
  42. #define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
  43. #define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
  44. #define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
  45. #define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
  46. #define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
  47. #define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
  48. #define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
  49. #define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
  50. #define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
  51. #define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
  52. #define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
  53. #define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
  54. #define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
  55. #define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
  56. #define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
  57. #define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
  58. #define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
  59. #define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
  60. #define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
  61. #define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
  62. #define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
  63. #define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
  64. #define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
  65. #define TEGRA_PIN_GMI_DQS_P_PJ3 _GPIO(75)
  66. #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
  67. #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
  68. #define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
  69. #define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
  70. #define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
  71. #define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
  72. #define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
  73. #define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
  74. #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
  75. #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
  76. #define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
  77. #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
  78. #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
  79. #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
  80. #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
  81. #define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
  82. #define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
  83. #define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
  84. #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
  85. #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
  86. #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
  87. #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
  88. #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
  89. #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
  90. #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
  91. #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
  92. #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
  93. #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
  94. #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
  95. #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
  96. #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
  97. #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
  98. #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
  99. #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
  100. #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
  101. #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
  102. #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
  103. #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
  104. #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
  105. #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
  106. #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
  107. #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
  108. #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
  109. #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
  110. #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
  111. #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
  112. #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
  113. #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
  114. #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
  115. #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
  116. #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
  117. #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
  118. #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
  119. #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
  120. #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
  121. #define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
  122. #define TEGRA_PIN_PU0 _GPIO(160)
  123. #define TEGRA_PIN_PU1 _GPIO(161)
  124. #define TEGRA_PIN_PU2 _GPIO(162)
  125. #define TEGRA_PIN_PU3 _GPIO(163)
  126. #define TEGRA_PIN_PU4 _GPIO(164)
  127. #define TEGRA_PIN_PU5 _GPIO(165)
  128. #define TEGRA_PIN_PU6 _GPIO(166)
  129. #define TEGRA_PIN_PV0 _GPIO(168)
  130. #define TEGRA_PIN_PV1 _GPIO(169)
  131. #define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
  132. #define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
  133. #define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
  134. #define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
  135. #define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
  136. #define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
  137. #define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
  138. #define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
  139. #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
  140. #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
  141. #define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
  142. #define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
  143. #define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
  144. #define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
  145. #define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
  146. #define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
  147. #define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
  148. #define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
  149. #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
  150. #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
  151. #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
  152. #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
  153. #define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
  154. #define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
  155. #define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
  156. #define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
  157. #define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
  158. #define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
  159. #define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
  160. #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
  161. #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
  162. #define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
  163. #define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
  164. #define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
  165. #define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
  166. #define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
  167. #define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
  168. #define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
  169. #define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
  170. #define TEGRA_PIN_PBB0 _GPIO(216)
  171. #define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
  172. #define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
  173. #define TEGRA_PIN_PBB3 _GPIO(219)
  174. #define TEGRA_PIN_PBB4 _GPIO(220)
  175. #define TEGRA_PIN_PBB5 _GPIO(221)
  176. #define TEGRA_PIN_PBB6 _GPIO(222)
  177. #define TEGRA_PIN_PBB7 _GPIO(223)
  178. #define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
  179. #define TEGRA_PIN_PCC1 _GPIO(225)
  180. #define TEGRA_PIN_PCC2 _GPIO(226)
  181. #define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
  182. #define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
  183. #define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
  184. #define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
  185. #define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
  186. #define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
  187. #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
  188. #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
  189. /* All non-GPIO pins follow */
  190. #define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
  191. #define _PIN(offset) (NUM_GPIOS + (offset))
  192. /* Non-GPIO pins */
  193. #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
  194. #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
  195. #define TEGRA_PIN_PWR_INT_N _PIN(2)
  196. #define TEGRA_PIN_RESET_OUT_N _PIN(3)
  197. #define TEGRA_PIN_OWR _PIN(4)
  198. #define TEGRA_PIN_JTAG_RTCK _PIN(5)
  199. #define TEGRA_PIN_CLK_32K_IN _PIN(6)
  200. #define TEGRA_PIN_GMI_CLK_LB _PIN(7)
  201. static const struct pinctrl_pin_desc tegra114_pins[] = {
  202. PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
  203. PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
  204. PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
  205. PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
  206. PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
  207. PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
  208. PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
  209. PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
  210. PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
  211. PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
  212. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
  213. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
  214. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
  215. PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
  216. PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
  217. PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
  218. PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
  219. PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
  220. PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
  221. PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
  222. PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
  223. PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
  224. PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
  225. PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
  226. PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
  227. PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
  228. PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
  229. PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
  230. PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
  231. PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
  232. PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
  233. PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
  234. PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
  235. PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
  236. PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
  237. PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
  238. PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
  239. PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
  240. PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
  241. PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
  242. PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
  243. PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
  244. PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
  245. PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
  246. PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
  247. PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
  248. PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
  249. PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
  250. PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
  251. PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
  252. PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
  253. PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
  254. PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
  255. PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
  256. PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
  257. PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
  258. PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
  259. PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
  260. PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
  261. PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
  262. PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
  263. PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
  264. PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
  265. PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
  266. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
  267. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
  268. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
  269. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
  270. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
  271. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
  272. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
  273. PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
  274. PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
  275. PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
  276. PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
  277. PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
  278. PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
  279. PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
  280. PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
  281. PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
  282. PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
  283. PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
  284. PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
  285. PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
  286. PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
  287. PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
  288. PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
  289. PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
  290. PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
  291. PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
  292. PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
  293. PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
  294. PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
  295. PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
  296. PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
  297. PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
  298. PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
  299. PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
  300. PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
  301. PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
  302. PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
  303. PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
  304. PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
  305. PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
  306. PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
  307. PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
  308. PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
  309. PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
  310. PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
  311. PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
  312. PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
  313. PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
  314. PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
  315. PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
  316. PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
  317. PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
  318. PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
  319. PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
  320. PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
  321. PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
  322. PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
  323. PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
  324. PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
  325. PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
  326. PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
  327. PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
  328. PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
  329. PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
  330. PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
  331. PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
  332. PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
  333. PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
  334. PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
  335. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
  336. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
  337. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
  338. PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
  339. PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
  340. PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
  341. PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
  342. PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
  343. PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
  344. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
  345. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
  346. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
  347. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
  348. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
  349. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
  350. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
  351. PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
  352. PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
  353. PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
  354. PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
  355. PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
  356. PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
  357. PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
  358. PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
  359. PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
  360. PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
  361. PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
  362. PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
  363. PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
  364. PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
  365. PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
  366. PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
  367. PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
  368. PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
  369. PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
  370. PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
  371. PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
  372. PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
  373. PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
  374. PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
  375. PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
  376. PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
  377. PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
  378. PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
  379. };
  380. static const unsigned clk_32k_out_pa0_pins[] = {
  381. TEGRA_PIN_CLK_32K_OUT_PA0,
  382. };
  383. static const unsigned uart3_cts_n_pa1_pins[] = {
  384. TEGRA_PIN_UART3_CTS_N_PA1,
  385. };
  386. static const unsigned dap2_fs_pa2_pins[] = {
  387. TEGRA_PIN_DAP2_FS_PA2,
  388. };
  389. static const unsigned dap2_sclk_pa3_pins[] = {
  390. TEGRA_PIN_DAP2_SCLK_PA3,
  391. };
  392. static const unsigned dap2_din_pa4_pins[] = {
  393. TEGRA_PIN_DAP2_DIN_PA4,
  394. };
  395. static const unsigned dap2_dout_pa5_pins[] = {
  396. TEGRA_PIN_DAP2_DOUT_PA5,
  397. };
  398. static const unsigned sdmmc3_clk_pa6_pins[] = {
  399. TEGRA_PIN_SDMMC3_CLK_PA6,
  400. };
  401. static const unsigned sdmmc3_cmd_pa7_pins[] = {
  402. TEGRA_PIN_SDMMC3_CMD_PA7,
  403. };
  404. static const unsigned gmi_a17_pb0_pins[] = {
  405. TEGRA_PIN_GMI_A17_PB0,
  406. };
  407. static const unsigned gmi_a18_pb1_pins[] = {
  408. TEGRA_PIN_GMI_A18_PB1,
  409. };
  410. static const unsigned sdmmc3_dat3_pb4_pins[] = {
  411. TEGRA_PIN_SDMMC3_DAT3_PB4,
  412. };
  413. static const unsigned sdmmc3_dat2_pb5_pins[] = {
  414. TEGRA_PIN_SDMMC3_DAT2_PB5,
  415. };
  416. static const unsigned sdmmc3_dat1_pb6_pins[] = {
  417. TEGRA_PIN_SDMMC3_DAT1_PB6,
  418. };
  419. static const unsigned sdmmc3_dat0_pb7_pins[] = {
  420. TEGRA_PIN_SDMMC3_DAT0_PB7,
  421. };
  422. static const unsigned uart3_rts_n_pc0_pins[] = {
  423. TEGRA_PIN_UART3_RTS_N_PC0,
  424. };
  425. static const unsigned uart2_txd_pc2_pins[] = {
  426. TEGRA_PIN_UART2_TXD_PC2,
  427. };
  428. static const unsigned uart2_rxd_pc3_pins[] = {
  429. TEGRA_PIN_UART2_RXD_PC3,
  430. };
  431. static const unsigned gen1_i2c_scl_pc4_pins[] = {
  432. TEGRA_PIN_GEN1_I2C_SCL_PC4,
  433. };
  434. static const unsigned gen1_i2c_sda_pc5_pins[] = {
  435. TEGRA_PIN_GEN1_I2C_SDA_PC5,
  436. };
  437. static const unsigned gmi_wp_n_pc7_pins[] = {
  438. TEGRA_PIN_GMI_WP_N_PC7,
  439. };
  440. static const unsigned gmi_ad0_pg0_pins[] = {
  441. TEGRA_PIN_GMI_AD0_PG0,
  442. };
  443. static const unsigned gmi_ad1_pg1_pins[] = {
  444. TEGRA_PIN_GMI_AD1_PG1,
  445. };
  446. static const unsigned gmi_ad2_pg2_pins[] = {
  447. TEGRA_PIN_GMI_AD2_PG2,
  448. };
  449. static const unsigned gmi_ad3_pg3_pins[] = {
  450. TEGRA_PIN_GMI_AD3_PG3,
  451. };
  452. static const unsigned gmi_ad4_pg4_pins[] = {
  453. TEGRA_PIN_GMI_AD4_PG4,
  454. };
  455. static const unsigned gmi_ad5_pg5_pins[] = {
  456. TEGRA_PIN_GMI_AD5_PG5,
  457. };
  458. static const unsigned gmi_ad6_pg6_pins[] = {
  459. TEGRA_PIN_GMI_AD6_PG6,
  460. };
  461. static const unsigned gmi_ad7_pg7_pins[] = {
  462. TEGRA_PIN_GMI_AD7_PG7,
  463. };
  464. static const unsigned gmi_ad8_ph0_pins[] = {
  465. TEGRA_PIN_GMI_AD8_PH0,
  466. };
  467. static const unsigned gmi_ad9_ph1_pins[] = {
  468. TEGRA_PIN_GMI_AD9_PH1,
  469. };
  470. static const unsigned gmi_ad10_ph2_pins[] = {
  471. TEGRA_PIN_GMI_AD10_PH2,
  472. };
  473. static const unsigned gmi_ad11_ph3_pins[] = {
  474. TEGRA_PIN_GMI_AD11_PH3,
  475. };
  476. static const unsigned gmi_ad12_ph4_pins[] = {
  477. TEGRA_PIN_GMI_AD12_PH4,
  478. };
  479. static const unsigned gmi_ad13_ph5_pins[] = {
  480. TEGRA_PIN_GMI_AD13_PH5,
  481. };
  482. static const unsigned gmi_ad14_ph6_pins[] = {
  483. TEGRA_PIN_GMI_AD14_PH6,
  484. };
  485. static const unsigned gmi_ad15_ph7_pins[] = {
  486. TEGRA_PIN_GMI_AD15_PH7,
  487. };
  488. static const unsigned gmi_wr_n_pi0_pins[] = {
  489. TEGRA_PIN_GMI_WR_N_PI0,
  490. };
  491. static const unsigned gmi_oe_n_pi1_pins[] = {
  492. TEGRA_PIN_GMI_OE_N_PI1,
  493. };
  494. static const unsigned gmi_cs6_n_pi3_pins[] = {
  495. TEGRA_PIN_GMI_CS6_N_PI3,
  496. };
  497. static const unsigned gmi_rst_n_pi4_pins[] = {
  498. TEGRA_PIN_GMI_RST_N_PI4,
  499. };
  500. static const unsigned gmi_iordy_pi5_pins[] = {
  501. TEGRA_PIN_GMI_IORDY_PI5,
  502. };
  503. static const unsigned gmi_cs7_n_pi6_pins[] = {
  504. TEGRA_PIN_GMI_CS7_N_PI6,
  505. };
  506. static const unsigned gmi_wait_pi7_pins[] = {
  507. TEGRA_PIN_GMI_WAIT_PI7,
  508. };
  509. static const unsigned gmi_cs0_n_pj0_pins[] = {
  510. TEGRA_PIN_GMI_CS0_N_PJ0,
  511. };
  512. static const unsigned gmi_cs1_n_pj2_pins[] = {
  513. TEGRA_PIN_GMI_CS1_N_PJ2,
  514. };
  515. static const unsigned gmi_dqs_p_pj3_pins[] = {
  516. TEGRA_PIN_GMI_DQS_P_PJ3,
  517. };
  518. static const unsigned uart2_cts_n_pj5_pins[] = {
  519. TEGRA_PIN_UART2_CTS_N_PJ5,
  520. };
  521. static const unsigned uart2_rts_n_pj6_pins[] = {
  522. TEGRA_PIN_UART2_RTS_N_PJ6,
  523. };
  524. static const unsigned gmi_a16_pj7_pins[] = {
  525. TEGRA_PIN_GMI_A16_PJ7,
  526. };
  527. static const unsigned gmi_adv_n_pk0_pins[] = {
  528. TEGRA_PIN_GMI_ADV_N_PK0,
  529. };
  530. static const unsigned gmi_clk_pk1_pins[] = {
  531. TEGRA_PIN_GMI_CLK_PK1,
  532. };
  533. static const unsigned gmi_cs4_n_pk2_pins[] = {
  534. TEGRA_PIN_GMI_CS4_N_PK2,
  535. };
  536. static const unsigned gmi_cs2_n_pk3_pins[] = {
  537. TEGRA_PIN_GMI_CS2_N_PK3,
  538. };
  539. static const unsigned gmi_cs3_n_pk4_pins[] = {
  540. TEGRA_PIN_GMI_CS3_N_PK4,
  541. };
  542. static const unsigned spdif_out_pk5_pins[] = {
  543. TEGRA_PIN_SPDIF_OUT_PK5,
  544. };
  545. static const unsigned spdif_in_pk6_pins[] = {
  546. TEGRA_PIN_SPDIF_IN_PK6,
  547. };
  548. static const unsigned gmi_a19_pk7_pins[] = {
  549. TEGRA_PIN_GMI_A19_PK7,
  550. };
  551. static const unsigned dap1_fs_pn0_pins[] = {
  552. TEGRA_PIN_DAP1_FS_PN0,
  553. };
  554. static const unsigned dap1_din_pn1_pins[] = {
  555. TEGRA_PIN_DAP1_DIN_PN1,
  556. };
  557. static const unsigned dap1_dout_pn2_pins[] = {
  558. TEGRA_PIN_DAP1_DOUT_PN2,
  559. };
  560. static const unsigned dap1_sclk_pn3_pins[] = {
  561. TEGRA_PIN_DAP1_SCLK_PN3,
  562. };
  563. static const unsigned usb_vbus_en0_pn4_pins[] = {
  564. TEGRA_PIN_USB_VBUS_EN0_PN4,
  565. };
  566. static const unsigned usb_vbus_en1_pn5_pins[] = {
  567. TEGRA_PIN_USB_VBUS_EN1_PN5,
  568. };
  569. static const unsigned hdmi_int_pn7_pins[] = {
  570. TEGRA_PIN_HDMI_INT_PN7,
  571. };
  572. static const unsigned ulpi_data7_po0_pins[] = {
  573. TEGRA_PIN_ULPI_DATA7_PO0,
  574. };
  575. static const unsigned ulpi_data0_po1_pins[] = {
  576. TEGRA_PIN_ULPI_DATA0_PO1,
  577. };
  578. static const unsigned ulpi_data1_po2_pins[] = {
  579. TEGRA_PIN_ULPI_DATA1_PO2,
  580. };
  581. static const unsigned ulpi_data2_po3_pins[] = {
  582. TEGRA_PIN_ULPI_DATA2_PO3,
  583. };
  584. static const unsigned ulpi_data3_po4_pins[] = {
  585. TEGRA_PIN_ULPI_DATA3_PO4,
  586. };
  587. static const unsigned ulpi_data4_po5_pins[] = {
  588. TEGRA_PIN_ULPI_DATA4_PO5,
  589. };
  590. static const unsigned ulpi_data5_po6_pins[] = {
  591. TEGRA_PIN_ULPI_DATA5_PO6,
  592. };
  593. static const unsigned ulpi_data6_po7_pins[] = {
  594. TEGRA_PIN_ULPI_DATA6_PO7,
  595. };
  596. static const unsigned dap3_fs_pp0_pins[] = {
  597. TEGRA_PIN_DAP3_FS_PP0,
  598. };
  599. static const unsigned dap3_din_pp1_pins[] = {
  600. TEGRA_PIN_DAP3_DIN_PP1,
  601. };
  602. static const unsigned dap3_dout_pp2_pins[] = {
  603. TEGRA_PIN_DAP3_DOUT_PP2,
  604. };
  605. static const unsigned dap3_sclk_pp3_pins[] = {
  606. TEGRA_PIN_DAP3_SCLK_PP3,
  607. };
  608. static const unsigned dap4_fs_pp4_pins[] = {
  609. TEGRA_PIN_DAP4_FS_PP4,
  610. };
  611. static const unsigned dap4_din_pp5_pins[] = {
  612. TEGRA_PIN_DAP4_DIN_PP5,
  613. };
  614. static const unsigned dap4_dout_pp6_pins[] = {
  615. TEGRA_PIN_DAP4_DOUT_PP6,
  616. };
  617. static const unsigned dap4_sclk_pp7_pins[] = {
  618. TEGRA_PIN_DAP4_SCLK_PP7,
  619. };
  620. static const unsigned kb_col0_pq0_pins[] = {
  621. TEGRA_PIN_KB_COL0_PQ0,
  622. };
  623. static const unsigned kb_col1_pq1_pins[] = {
  624. TEGRA_PIN_KB_COL1_PQ1,
  625. };
  626. static const unsigned kb_col2_pq2_pins[] = {
  627. TEGRA_PIN_KB_COL2_PQ2,
  628. };
  629. static const unsigned kb_col3_pq3_pins[] = {
  630. TEGRA_PIN_KB_COL3_PQ3,
  631. };
  632. static const unsigned kb_col4_pq4_pins[] = {
  633. TEGRA_PIN_KB_COL4_PQ4,
  634. };
  635. static const unsigned kb_col5_pq5_pins[] = {
  636. TEGRA_PIN_KB_COL5_PQ5,
  637. };
  638. static const unsigned kb_col6_pq6_pins[] = {
  639. TEGRA_PIN_KB_COL6_PQ6,
  640. };
  641. static const unsigned kb_col7_pq7_pins[] = {
  642. TEGRA_PIN_KB_COL7_PQ7,
  643. };
  644. static const unsigned kb_row0_pr0_pins[] = {
  645. TEGRA_PIN_KB_ROW0_PR0,
  646. };
  647. static const unsigned kb_row1_pr1_pins[] = {
  648. TEGRA_PIN_KB_ROW1_PR1,
  649. };
  650. static const unsigned kb_row2_pr2_pins[] = {
  651. TEGRA_PIN_KB_ROW2_PR2,
  652. };
  653. static const unsigned kb_row3_pr3_pins[] = {
  654. TEGRA_PIN_KB_ROW3_PR3,
  655. };
  656. static const unsigned kb_row4_pr4_pins[] = {
  657. TEGRA_PIN_KB_ROW4_PR4,
  658. };
  659. static const unsigned kb_row5_pr5_pins[] = {
  660. TEGRA_PIN_KB_ROW5_PR5,
  661. };
  662. static const unsigned kb_row6_pr6_pins[] = {
  663. TEGRA_PIN_KB_ROW6_PR6,
  664. };
  665. static const unsigned kb_row7_pr7_pins[] = {
  666. TEGRA_PIN_KB_ROW7_PR7,
  667. };
  668. static const unsigned kb_row8_ps0_pins[] = {
  669. TEGRA_PIN_KB_ROW8_PS0,
  670. };
  671. static const unsigned kb_row9_ps1_pins[] = {
  672. TEGRA_PIN_KB_ROW9_PS1,
  673. };
  674. static const unsigned kb_row10_ps2_pins[] = {
  675. TEGRA_PIN_KB_ROW10_PS2,
  676. };
  677. static const unsigned gen2_i2c_scl_pt5_pins[] = {
  678. TEGRA_PIN_GEN2_I2C_SCL_PT5,
  679. };
  680. static const unsigned gen2_i2c_sda_pt6_pins[] = {
  681. TEGRA_PIN_GEN2_I2C_SDA_PT6,
  682. };
  683. static const unsigned sdmmc4_cmd_pt7_pins[] = {
  684. TEGRA_PIN_SDMMC4_CMD_PT7,
  685. };
  686. static const unsigned pu0_pins[] = {
  687. TEGRA_PIN_PU0,
  688. };
  689. static const unsigned pu1_pins[] = {
  690. TEGRA_PIN_PU1,
  691. };
  692. static const unsigned pu2_pins[] = {
  693. TEGRA_PIN_PU2,
  694. };
  695. static const unsigned pu3_pins[] = {
  696. TEGRA_PIN_PU3,
  697. };
  698. static const unsigned pu4_pins[] = {
  699. TEGRA_PIN_PU4,
  700. };
  701. static const unsigned pu5_pins[] = {
  702. TEGRA_PIN_PU5,
  703. };
  704. static const unsigned pu6_pins[] = {
  705. TEGRA_PIN_PU6,
  706. };
  707. static const unsigned pv0_pins[] = {
  708. TEGRA_PIN_PV0,
  709. };
  710. static const unsigned pv1_pins[] = {
  711. TEGRA_PIN_PV1,
  712. };
  713. static const unsigned sdmmc3_cd_n_pv2_pins[] = {
  714. TEGRA_PIN_SDMMC3_CD_N_PV2,
  715. };
  716. static const unsigned sdmmc1_wp_n_pv3_pins[] = {
  717. TEGRA_PIN_SDMMC1_WP_N_PV3,
  718. };
  719. static const unsigned ddc_scl_pv4_pins[] = {
  720. TEGRA_PIN_DDC_SCL_PV4,
  721. };
  722. static const unsigned ddc_sda_pv5_pins[] = {
  723. TEGRA_PIN_DDC_SDA_PV5,
  724. };
  725. static const unsigned gpio_w2_aud_pw2_pins[] = {
  726. TEGRA_PIN_GPIO_W2_AUD_PW2,
  727. };
  728. static const unsigned gpio_w3_aud_pw3_pins[] = {
  729. TEGRA_PIN_GPIO_W3_AUD_PW3,
  730. };
  731. static const unsigned clk1_out_pw4_pins[] = {
  732. TEGRA_PIN_CLK1_OUT_PW4,
  733. };
  734. static const unsigned clk2_out_pw5_pins[] = {
  735. TEGRA_PIN_CLK2_OUT_PW5,
  736. };
  737. static const unsigned uart3_txd_pw6_pins[] = {
  738. TEGRA_PIN_UART3_TXD_PW6,
  739. };
  740. static const unsigned uart3_rxd_pw7_pins[] = {
  741. TEGRA_PIN_UART3_RXD_PW7,
  742. };
  743. static const unsigned dvfs_pwm_px0_pins[] = {
  744. TEGRA_PIN_DVFS_PWM_PX0,
  745. };
  746. static const unsigned gpio_x1_aud_px1_pins[] = {
  747. TEGRA_PIN_GPIO_X1_AUD_PX1,
  748. };
  749. static const unsigned dvfs_clk_px2_pins[] = {
  750. TEGRA_PIN_DVFS_CLK_PX2,
  751. };
  752. static const unsigned gpio_x3_aud_px3_pins[] = {
  753. TEGRA_PIN_GPIO_X3_AUD_PX3,
  754. };
  755. static const unsigned gpio_x4_aud_px4_pins[] = {
  756. TEGRA_PIN_GPIO_X4_AUD_PX4,
  757. };
  758. static const unsigned gpio_x5_aud_px5_pins[] = {
  759. TEGRA_PIN_GPIO_X5_AUD_PX5,
  760. };
  761. static const unsigned gpio_x6_aud_px6_pins[] = {
  762. TEGRA_PIN_GPIO_X6_AUD_PX6,
  763. };
  764. static const unsigned gpio_x7_aud_px7_pins[] = {
  765. TEGRA_PIN_GPIO_X7_AUD_PX7,
  766. };
  767. static const unsigned ulpi_clk_py0_pins[] = {
  768. TEGRA_PIN_ULPI_CLK_PY0,
  769. };
  770. static const unsigned ulpi_dir_py1_pins[] = {
  771. TEGRA_PIN_ULPI_DIR_PY1,
  772. };
  773. static const unsigned ulpi_nxt_py2_pins[] = {
  774. TEGRA_PIN_ULPI_NXT_PY2,
  775. };
  776. static const unsigned ulpi_stp_py3_pins[] = {
  777. TEGRA_PIN_ULPI_STP_PY3,
  778. };
  779. static const unsigned sdmmc1_dat3_py4_pins[] = {
  780. TEGRA_PIN_SDMMC1_DAT3_PY4,
  781. };
  782. static const unsigned sdmmc1_dat2_py5_pins[] = {
  783. TEGRA_PIN_SDMMC1_DAT2_PY5,
  784. };
  785. static const unsigned sdmmc1_dat1_py6_pins[] = {
  786. TEGRA_PIN_SDMMC1_DAT1_PY6,
  787. };
  788. static const unsigned sdmmc1_dat0_py7_pins[] = {
  789. TEGRA_PIN_SDMMC1_DAT0_PY7,
  790. };
  791. static const unsigned sdmmc1_clk_pz0_pins[] = {
  792. TEGRA_PIN_SDMMC1_CLK_PZ0,
  793. };
  794. static const unsigned sdmmc1_cmd_pz1_pins[] = {
  795. TEGRA_PIN_SDMMC1_CMD_PZ1,
  796. };
  797. static const unsigned sys_clk_req_pz5_pins[] = {
  798. TEGRA_PIN_SYS_CLK_REQ_PZ5,
  799. };
  800. static const unsigned pwr_i2c_scl_pz6_pins[] = {
  801. TEGRA_PIN_PWR_I2C_SCL_PZ6,
  802. };
  803. static const unsigned pwr_i2c_sda_pz7_pins[] = {
  804. TEGRA_PIN_PWR_I2C_SDA_PZ7,
  805. };
  806. static const unsigned sdmmc4_dat0_paa0_pins[] = {
  807. TEGRA_PIN_SDMMC4_DAT0_PAA0,
  808. };
  809. static const unsigned sdmmc4_dat1_paa1_pins[] = {
  810. TEGRA_PIN_SDMMC4_DAT1_PAA1,
  811. };
  812. static const unsigned sdmmc4_dat2_paa2_pins[] = {
  813. TEGRA_PIN_SDMMC4_DAT2_PAA2,
  814. };
  815. static const unsigned sdmmc4_dat3_paa3_pins[] = {
  816. TEGRA_PIN_SDMMC4_DAT3_PAA3,
  817. };
  818. static const unsigned sdmmc4_dat4_paa4_pins[] = {
  819. TEGRA_PIN_SDMMC4_DAT4_PAA4,
  820. };
  821. static const unsigned sdmmc4_dat5_paa5_pins[] = {
  822. TEGRA_PIN_SDMMC4_DAT5_PAA5,
  823. };
  824. static const unsigned sdmmc4_dat6_paa6_pins[] = {
  825. TEGRA_PIN_SDMMC4_DAT6_PAA6,
  826. };
  827. static const unsigned sdmmc4_dat7_paa7_pins[] = {
  828. TEGRA_PIN_SDMMC4_DAT7_PAA7,
  829. };
  830. static const unsigned pbb0_pins[] = {
  831. TEGRA_PIN_PBB0,
  832. };
  833. static const unsigned cam_i2c_scl_pbb1_pins[] = {
  834. TEGRA_PIN_CAM_I2C_SCL_PBB1,
  835. };
  836. static const unsigned cam_i2c_sda_pbb2_pins[] = {
  837. TEGRA_PIN_CAM_I2C_SDA_PBB2,
  838. };
  839. static const unsigned pbb3_pins[] = {
  840. TEGRA_PIN_PBB3,
  841. };
  842. static const unsigned pbb4_pins[] = {
  843. TEGRA_PIN_PBB4,
  844. };
  845. static const unsigned pbb5_pins[] = {
  846. TEGRA_PIN_PBB5,
  847. };
  848. static const unsigned pbb6_pins[] = {
  849. TEGRA_PIN_PBB6,
  850. };
  851. static const unsigned pbb7_pins[] = {
  852. TEGRA_PIN_PBB7,
  853. };
  854. static const unsigned cam_mclk_pcc0_pins[] = {
  855. TEGRA_PIN_CAM_MCLK_PCC0,
  856. };
  857. static const unsigned pcc1_pins[] = {
  858. TEGRA_PIN_PCC1,
  859. };
  860. static const unsigned pcc2_pins[] = {
  861. TEGRA_PIN_PCC2,
  862. };
  863. static const unsigned sdmmc4_clk_pcc4_pins[] = {
  864. TEGRA_PIN_SDMMC4_CLK_PCC4,
  865. };
  866. static const unsigned clk2_req_pcc5_pins[] = {
  867. TEGRA_PIN_CLK2_REQ_PCC5,
  868. };
  869. static const unsigned clk3_out_pee0_pins[] = {
  870. TEGRA_PIN_CLK3_OUT_PEE0,
  871. };
  872. static const unsigned clk3_req_pee1_pins[] = {
  873. TEGRA_PIN_CLK3_REQ_PEE1,
  874. };
  875. static const unsigned clk1_req_pee2_pins[] = {
  876. TEGRA_PIN_CLK1_REQ_PEE2,
  877. };
  878. static const unsigned hdmi_cec_pee3_pins[] = {
  879. TEGRA_PIN_HDMI_CEC_PEE3,
  880. };
  881. static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
  882. TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
  883. };
  884. static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
  885. TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
  886. };
  887. static const unsigned core_pwr_req_pins[] = {
  888. TEGRA_PIN_CORE_PWR_REQ,
  889. };
  890. static const unsigned cpu_pwr_req_pins[] = {
  891. TEGRA_PIN_CPU_PWR_REQ,
  892. };
  893. static const unsigned pwr_int_n_pins[] = {
  894. TEGRA_PIN_PWR_INT_N,
  895. };
  896. static const unsigned reset_out_n_pins[] = {
  897. TEGRA_PIN_RESET_OUT_N,
  898. };
  899. static const unsigned owr_pins[] = {
  900. TEGRA_PIN_OWR,
  901. };
  902. static const unsigned jtag_rtck_pins[] = {
  903. TEGRA_PIN_JTAG_RTCK,
  904. };
  905. static const unsigned clk_32k_in_pins[] = {
  906. TEGRA_PIN_CLK_32K_IN,
  907. };
  908. static const unsigned gmi_clk_lb_pins[] = {
  909. TEGRA_PIN_GMI_CLK_LB,
  910. };
  911. static const unsigned drive_ao1_pins[] = {
  912. TEGRA_PIN_KB_ROW0_PR0,
  913. TEGRA_PIN_KB_ROW1_PR1,
  914. TEGRA_PIN_KB_ROW2_PR2,
  915. TEGRA_PIN_KB_ROW3_PR3,
  916. TEGRA_PIN_KB_ROW4_PR4,
  917. TEGRA_PIN_KB_ROW5_PR5,
  918. TEGRA_PIN_KB_ROW6_PR6,
  919. TEGRA_PIN_KB_ROW7_PR7,
  920. TEGRA_PIN_PWR_I2C_SCL_PZ6,
  921. TEGRA_PIN_PWR_I2C_SDA_PZ7,
  922. };
  923. static const unsigned drive_ao2_pins[] = {
  924. TEGRA_PIN_CLK_32K_OUT_PA0,
  925. TEGRA_PIN_KB_COL0_PQ0,
  926. TEGRA_PIN_KB_COL1_PQ1,
  927. TEGRA_PIN_KB_COL2_PQ2,
  928. TEGRA_PIN_KB_COL3_PQ3,
  929. TEGRA_PIN_KB_COL4_PQ4,
  930. TEGRA_PIN_KB_COL5_PQ5,
  931. TEGRA_PIN_KB_COL6_PQ6,
  932. TEGRA_PIN_KB_COL7_PQ7,
  933. TEGRA_PIN_KB_ROW8_PS0,
  934. TEGRA_PIN_KB_ROW9_PS1,
  935. TEGRA_PIN_KB_ROW10_PS2,
  936. TEGRA_PIN_SYS_CLK_REQ_PZ5,
  937. TEGRA_PIN_CORE_PWR_REQ,
  938. TEGRA_PIN_CPU_PWR_REQ,
  939. TEGRA_PIN_RESET_OUT_N,
  940. };
  941. static const unsigned drive_at1_pins[] = {
  942. TEGRA_PIN_GMI_AD8_PH0,
  943. TEGRA_PIN_GMI_AD9_PH1,
  944. TEGRA_PIN_GMI_AD10_PH2,
  945. TEGRA_PIN_GMI_AD11_PH3,
  946. TEGRA_PIN_GMI_AD12_PH4,
  947. TEGRA_PIN_GMI_AD13_PH5,
  948. TEGRA_PIN_GMI_AD14_PH6,
  949. TEGRA_PIN_GMI_AD15_PH7,
  950. TEGRA_PIN_GMI_IORDY_PI5,
  951. TEGRA_PIN_GMI_CS7_N_PI6,
  952. };
  953. static const unsigned drive_at2_pins[] = {
  954. TEGRA_PIN_GMI_AD0_PG0,
  955. TEGRA_PIN_GMI_AD1_PG1,
  956. TEGRA_PIN_GMI_AD2_PG2,
  957. TEGRA_PIN_GMI_AD3_PG3,
  958. TEGRA_PIN_GMI_AD4_PG4,
  959. TEGRA_PIN_GMI_AD5_PG5,
  960. TEGRA_PIN_GMI_AD6_PG6,
  961. TEGRA_PIN_GMI_AD7_PG7,
  962. TEGRA_PIN_GMI_WR_N_PI0,
  963. TEGRA_PIN_GMI_OE_N_PI1,
  964. TEGRA_PIN_GMI_CS6_N_PI3,
  965. TEGRA_PIN_GMI_RST_N_PI4,
  966. TEGRA_PIN_GMI_WAIT_PI7,
  967. TEGRA_PIN_GMI_DQS_P_PJ3,
  968. TEGRA_PIN_GMI_ADV_N_PK0,
  969. TEGRA_PIN_GMI_CLK_PK1,
  970. TEGRA_PIN_GMI_CS4_N_PK2,
  971. TEGRA_PIN_GMI_CS2_N_PK3,
  972. TEGRA_PIN_GMI_CS3_N_PK4,
  973. };
  974. static const unsigned drive_at3_pins[] = {
  975. TEGRA_PIN_GMI_WP_N_PC7,
  976. TEGRA_PIN_GMI_CS0_N_PJ0,
  977. };
  978. static const unsigned drive_at4_pins[] = {
  979. TEGRA_PIN_GMI_A17_PB0,
  980. TEGRA_PIN_GMI_A18_PB1,
  981. TEGRA_PIN_GMI_CS1_N_PJ2,
  982. TEGRA_PIN_GMI_A16_PJ7,
  983. TEGRA_PIN_GMI_A19_PK7,
  984. };
  985. static const unsigned drive_at5_pins[] = {
  986. TEGRA_PIN_GEN2_I2C_SCL_PT5,
  987. TEGRA_PIN_GEN2_I2C_SDA_PT6,
  988. };
  989. static const unsigned drive_cdev1_pins[] = {
  990. TEGRA_PIN_CLK1_OUT_PW4,
  991. TEGRA_PIN_CLK1_REQ_PEE2,
  992. };
  993. static const unsigned drive_cdev2_pins[] = {
  994. TEGRA_PIN_CLK2_OUT_PW5,
  995. TEGRA_PIN_CLK2_REQ_PCC5,
  996. TEGRA_PIN_SDMMC1_WP_N_PV3,
  997. };
  998. static const unsigned drive_dap1_pins[] = {
  999. TEGRA_PIN_DAP1_FS_PN0,
  1000. TEGRA_PIN_DAP1_DIN_PN1,
  1001. TEGRA_PIN_DAP1_DOUT_PN2,
  1002. TEGRA_PIN_DAP1_SCLK_PN3,
  1003. };
  1004. static const unsigned drive_dap2_pins[] = {
  1005. TEGRA_PIN_DAP2_FS_PA2,
  1006. TEGRA_PIN_DAP2_SCLK_PA3,
  1007. TEGRA_PIN_DAP2_DIN_PA4,
  1008. TEGRA_PIN_DAP2_DOUT_PA5,
  1009. };
  1010. static const unsigned drive_dap3_pins[] = {
  1011. TEGRA_PIN_DAP3_FS_PP0,
  1012. TEGRA_PIN_DAP3_DIN_PP1,
  1013. TEGRA_PIN_DAP3_DOUT_PP2,
  1014. TEGRA_PIN_DAP3_SCLK_PP3,
  1015. };
  1016. static const unsigned drive_dap4_pins[] = {
  1017. TEGRA_PIN_DAP4_FS_PP4,
  1018. TEGRA_PIN_DAP4_DIN_PP5,
  1019. TEGRA_PIN_DAP4_DOUT_PP6,
  1020. TEGRA_PIN_DAP4_SCLK_PP7,
  1021. };
  1022. static const unsigned drive_dbg_pins[] = {
  1023. TEGRA_PIN_GEN1_I2C_SCL_PC4,
  1024. TEGRA_PIN_GEN1_I2C_SDA_PC5,
  1025. TEGRA_PIN_PU0,
  1026. TEGRA_PIN_PU1,
  1027. TEGRA_PIN_PU2,
  1028. TEGRA_PIN_PU3,
  1029. TEGRA_PIN_PU4,
  1030. TEGRA_PIN_PU5,
  1031. TEGRA_PIN_PU6,
  1032. };
  1033. static const unsigned drive_sdio3_pins[] = {
  1034. TEGRA_PIN_SDMMC3_CLK_PA6,
  1035. TEGRA_PIN_SDMMC3_CMD_PA7,
  1036. TEGRA_PIN_SDMMC3_DAT3_PB4,
  1037. TEGRA_PIN_SDMMC3_DAT2_PB5,
  1038. TEGRA_PIN_SDMMC3_DAT1_PB6,
  1039. TEGRA_PIN_SDMMC3_DAT0_PB7,
  1040. TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
  1041. TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
  1042. };
  1043. static const unsigned drive_spi_pins[] = {
  1044. TEGRA_PIN_DVFS_PWM_PX0,
  1045. TEGRA_PIN_GPIO_X1_AUD_PX1,
  1046. TEGRA_PIN_DVFS_CLK_PX2,
  1047. TEGRA_PIN_GPIO_X3_AUD_PX3,
  1048. TEGRA_PIN_GPIO_X4_AUD_PX4,
  1049. TEGRA_PIN_GPIO_X5_AUD_PX5,
  1050. TEGRA_PIN_GPIO_X6_AUD_PX6,
  1051. TEGRA_PIN_GPIO_X7_AUD_PX7,
  1052. TEGRA_PIN_GPIO_W2_AUD_PW2,
  1053. TEGRA_PIN_GPIO_W3_AUD_PW3,
  1054. };
  1055. static const unsigned drive_uaa_pins[] = {
  1056. TEGRA_PIN_ULPI_DATA0_PO1,
  1057. TEGRA_PIN_ULPI_DATA1_PO2,
  1058. TEGRA_PIN_ULPI_DATA2_PO3,
  1059. TEGRA_PIN_ULPI_DATA3_PO4,
  1060. };
  1061. static const unsigned drive_uab_pins[] = {
  1062. TEGRA_PIN_ULPI_DATA7_PO0,
  1063. TEGRA_PIN_ULPI_DATA4_PO5,
  1064. TEGRA_PIN_ULPI_DATA5_PO6,
  1065. TEGRA_PIN_ULPI_DATA6_PO7,
  1066. TEGRA_PIN_PV0,
  1067. TEGRA_PIN_PV1,
  1068. };
  1069. static const unsigned drive_uart2_pins[] = {
  1070. TEGRA_PIN_UART2_TXD_PC2,
  1071. TEGRA_PIN_UART2_RXD_PC3,
  1072. TEGRA_PIN_UART2_CTS_N_PJ5,
  1073. TEGRA_PIN_UART2_RTS_N_PJ6,
  1074. };
  1075. static const unsigned drive_uart3_pins[] = {
  1076. TEGRA_PIN_UART3_CTS_N_PA1,
  1077. TEGRA_PIN_UART3_RTS_N_PC0,
  1078. TEGRA_PIN_UART3_TXD_PW6,
  1079. TEGRA_PIN_UART3_RXD_PW7,
  1080. };
  1081. static const unsigned drive_sdio1_pins[] = {
  1082. TEGRA_PIN_SDMMC1_DAT3_PY4,
  1083. TEGRA_PIN_SDMMC1_DAT2_PY5,
  1084. TEGRA_PIN_SDMMC1_DAT1_PY6,
  1085. TEGRA_PIN_SDMMC1_DAT0_PY7,
  1086. TEGRA_PIN_SDMMC1_CLK_PZ0,
  1087. TEGRA_PIN_SDMMC1_CMD_PZ1,
  1088. };
  1089. static const unsigned drive_ddc_pins[] = {
  1090. TEGRA_PIN_DDC_SCL_PV4,
  1091. TEGRA_PIN_DDC_SDA_PV5,
  1092. };
  1093. static const unsigned drive_gma_pins[] = {
  1094. TEGRA_PIN_SDMMC4_CLK_PCC4,
  1095. TEGRA_PIN_SDMMC4_CMD_PT7,
  1096. TEGRA_PIN_SDMMC4_DAT0_PAA0,
  1097. TEGRA_PIN_SDMMC4_DAT1_PAA1,
  1098. TEGRA_PIN_SDMMC4_DAT2_PAA2,
  1099. TEGRA_PIN_SDMMC4_DAT3_PAA3,
  1100. TEGRA_PIN_SDMMC4_DAT4_PAA4,
  1101. TEGRA_PIN_SDMMC4_DAT5_PAA5,
  1102. TEGRA_PIN_SDMMC4_DAT6_PAA6,
  1103. TEGRA_PIN_SDMMC4_DAT7_PAA7,
  1104. };
  1105. static const unsigned drive_gme_pins[] = {
  1106. TEGRA_PIN_PBB0,
  1107. TEGRA_PIN_CAM_I2C_SCL_PBB1,
  1108. TEGRA_PIN_CAM_I2C_SDA_PBB2,
  1109. TEGRA_PIN_PBB3,
  1110. TEGRA_PIN_PCC2,
  1111. };
  1112. static const unsigned drive_gmf_pins[] = {
  1113. TEGRA_PIN_PBB4,
  1114. TEGRA_PIN_PBB5,
  1115. TEGRA_PIN_PBB6,
  1116. TEGRA_PIN_PBB7,
  1117. };
  1118. static const unsigned drive_gmg_pins[] = {
  1119. TEGRA_PIN_CAM_MCLK_PCC0,
  1120. };
  1121. static const unsigned drive_gmh_pins[] = {
  1122. TEGRA_PIN_PCC1,
  1123. };
  1124. static const unsigned drive_owr_pins[] = {
  1125. TEGRA_PIN_SDMMC3_CD_N_PV2,
  1126. };
  1127. static const unsigned drive_uda_pins[] = {
  1128. TEGRA_PIN_ULPI_CLK_PY0,
  1129. TEGRA_PIN_ULPI_DIR_PY1,
  1130. TEGRA_PIN_ULPI_NXT_PY2,
  1131. TEGRA_PIN_ULPI_STP_PY3,
  1132. };
  1133. static const unsigned drive_dev3_pins[] = {
  1134. };
  1135. static const unsigned drive_cec_pins[] = {
  1136. };
  1137. static const unsigned drive_at6_pins[] = {
  1138. };
  1139. static const unsigned drive_dap5_pins[] = {
  1140. };
  1141. static const unsigned drive_usb_vbus_en_pins[] = {
  1142. };
  1143. static const unsigned drive_ao3_pins[] = {
  1144. };
  1145. static const unsigned drive_hv0_pins[] = {
  1146. };
  1147. static const unsigned drive_sdio4_pins[] = {
  1148. };
  1149. static const unsigned drive_ao0_pins[] = {
  1150. };
  1151. enum tegra_mux {
  1152. TEGRA_MUX_BLINK,
  1153. TEGRA_MUX_CEC,
  1154. TEGRA_MUX_CLDVFS,
  1155. TEGRA_MUX_CLK,
  1156. TEGRA_MUX_CLK12,
  1157. TEGRA_MUX_CPU,
  1158. TEGRA_MUX_DAP,
  1159. TEGRA_MUX_DAP1,
  1160. TEGRA_MUX_DAP2,
  1161. TEGRA_MUX_DEV3,
  1162. TEGRA_MUX_DISPLAYA,
  1163. TEGRA_MUX_DISPLAYA_ALT,
  1164. TEGRA_MUX_DISPLAYB,
  1165. TEGRA_MUX_DTV,
  1166. TEGRA_MUX_EMC_DLL,
  1167. TEGRA_MUX_EXTPERIPH1,
  1168. TEGRA_MUX_EXTPERIPH2,
  1169. TEGRA_MUX_EXTPERIPH3,
  1170. TEGRA_MUX_GMI,
  1171. TEGRA_MUX_GMI_ALT,
  1172. TEGRA_MUX_HDA,
  1173. TEGRA_MUX_HSI,
  1174. TEGRA_MUX_I2C1,
  1175. TEGRA_MUX_I2C2,
  1176. TEGRA_MUX_I2C3,
  1177. TEGRA_MUX_I2C4,
  1178. TEGRA_MUX_I2CPWR,
  1179. TEGRA_MUX_I2S0,
  1180. TEGRA_MUX_I2S1,
  1181. TEGRA_MUX_I2S2,
  1182. TEGRA_MUX_I2S3,
  1183. TEGRA_MUX_I2S4,
  1184. TEGRA_MUX_IRDA,
  1185. TEGRA_MUX_KBC,
  1186. TEGRA_MUX_NAND,
  1187. TEGRA_MUX_NAND_ALT,
  1188. TEGRA_MUX_OWR,
  1189. TEGRA_MUX_PMI,
  1190. TEGRA_MUX_PWM0,
  1191. TEGRA_MUX_PWM1,
  1192. TEGRA_MUX_PWM2,
  1193. TEGRA_MUX_PWM3,
  1194. TEGRA_MUX_PWRON,
  1195. TEGRA_MUX_RESET_OUT_N,
  1196. TEGRA_MUX_RSVD1,
  1197. TEGRA_MUX_RSVD2,
  1198. TEGRA_MUX_RSVD3,
  1199. TEGRA_MUX_RSVD4,
  1200. TEGRA_MUX_RTCK,
  1201. TEGRA_MUX_SDMMC1,
  1202. TEGRA_MUX_SDMMC2,
  1203. TEGRA_MUX_SDMMC3,
  1204. TEGRA_MUX_SDMMC4,
  1205. TEGRA_MUX_SOC,
  1206. TEGRA_MUX_SPDIF,
  1207. TEGRA_MUX_SPI1,
  1208. TEGRA_MUX_SPI2,
  1209. TEGRA_MUX_SPI3,
  1210. TEGRA_MUX_SPI4,
  1211. TEGRA_MUX_SPI5,
  1212. TEGRA_MUX_SPI6,
  1213. TEGRA_MUX_SYSCLK,
  1214. TEGRA_MUX_TRACE,
  1215. TEGRA_MUX_UARTA,
  1216. TEGRA_MUX_UARTB,
  1217. TEGRA_MUX_UARTC,
  1218. TEGRA_MUX_UARTD,
  1219. TEGRA_MUX_ULPI,
  1220. TEGRA_MUX_USB,
  1221. TEGRA_MUX_VGP1,
  1222. TEGRA_MUX_VGP2,
  1223. TEGRA_MUX_VGP3,
  1224. TEGRA_MUX_VGP4,
  1225. TEGRA_MUX_VGP5,
  1226. TEGRA_MUX_VGP6,
  1227. TEGRA_MUX_VI,
  1228. TEGRA_MUX_VI_ALT1,
  1229. TEGRA_MUX_VI_ALT3,
  1230. };
  1231. #define FUNCTION(fname) \
  1232. { \
  1233. .name = #fname, \
  1234. }
  1235. static struct tegra_function tegra114_functions[] = {
  1236. FUNCTION(blink),
  1237. FUNCTION(cec),
  1238. FUNCTION(cldvfs),
  1239. FUNCTION(clk),
  1240. FUNCTION(clk12),
  1241. FUNCTION(cpu),
  1242. FUNCTION(dap),
  1243. FUNCTION(dap1),
  1244. FUNCTION(dap2),
  1245. FUNCTION(dev3),
  1246. FUNCTION(displaya),
  1247. FUNCTION(displaya_alt),
  1248. FUNCTION(displayb),
  1249. FUNCTION(dtv),
  1250. FUNCTION(emc_dll),
  1251. FUNCTION(extperiph1),
  1252. FUNCTION(extperiph2),
  1253. FUNCTION(extperiph3),
  1254. FUNCTION(gmi),
  1255. FUNCTION(gmi_alt),
  1256. FUNCTION(hda),
  1257. FUNCTION(hsi),
  1258. FUNCTION(i2c1),
  1259. FUNCTION(i2c2),
  1260. FUNCTION(i2c3),
  1261. FUNCTION(i2c4),
  1262. FUNCTION(i2cpwr),
  1263. FUNCTION(i2s0),
  1264. FUNCTION(i2s1),
  1265. FUNCTION(i2s2),
  1266. FUNCTION(i2s3),
  1267. FUNCTION(i2s4),
  1268. FUNCTION(irda),
  1269. FUNCTION(kbc),
  1270. FUNCTION(nand),
  1271. FUNCTION(nand_alt),
  1272. FUNCTION(owr),
  1273. FUNCTION(pmi),
  1274. FUNCTION(pwm0),
  1275. FUNCTION(pwm1),
  1276. FUNCTION(pwm2),
  1277. FUNCTION(pwm3),
  1278. FUNCTION(pwron),
  1279. FUNCTION(reset_out_n),
  1280. FUNCTION(rsvd1),
  1281. FUNCTION(rsvd2),
  1282. FUNCTION(rsvd3),
  1283. FUNCTION(rsvd4),
  1284. FUNCTION(rtck),
  1285. FUNCTION(sdmmc1),
  1286. FUNCTION(sdmmc2),
  1287. FUNCTION(sdmmc3),
  1288. FUNCTION(sdmmc4),
  1289. FUNCTION(soc),
  1290. FUNCTION(spdif),
  1291. FUNCTION(spi1),
  1292. FUNCTION(spi2),
  1293. FUNCTION(spi3),
  1294. FUNCTION(spi4),
  1295. FUNCTION(spi5),
  1296. FUNCTION(spi6),
  1297. FUNCTION(sysclk),
  1298. FUNCTION(trace),
  1299. FUNCTION(uarta),
  1300. FUNCTION(uartb),
  1301. FUNCTION(uartc),
  1302. FUNCTION(uartd),
  1303. FUNCTION(ulpi),
  1304. FUNCTION(usb),
  1305. FUNCTION(vgp1),
  1306. FUNCTION(vgp2),
  1307. FUNCTION(vgp3),
  1308. FUNCTION(vgp4),
  1309. FUNCTION(vgp5),
  1310. FUNCTION(vgp6),
  1311. FUNCTION(vi),
  1312. FUNCTION(vi_alt1),
  1313. FUNCTION(vi_alt3),
  1314. };
  1315. #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
  1316. #define PINGROUP_REG_A 0x3000 /* bank 1 */
  1317. #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
  1318. #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
  1319. #define PINGROUP_BIT_Y(b) (b)
  1320. #define PINGROUP_BIT_N(b) (-1)
  1321. #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
  1322. { \
  1323. .name = #pg_name, \
  1324. .pins = pg_name##_pins, \
  1325. .npins = ARRAY_SIZE(pg_name##_pins), \
  1326. .funcs = { \
  1327. TEGRA_MUX_##f0, \
  1328. TEGRA_MUX_##f1, \
  1329. TEGRA_MUX_##f2, \
  1330. TEGRA_MUX_##f3, \
  1331. }, \
  1332. .mux_reg = PINGROUP_REG(r), \
  1333. .mux_bank = 1, \
  1334. .mux_bit = 0, \
  1335. .pupd_reg = PINGROUP_REG(r), \
  1336. .pupd_bank = 1, \
  1337. .pupd_bit = 2, \
  1338. .tri_reg = PINGROUP_REG(r), \
  1339. .tri_bank = 1, \
  1340. .tri_bit = 4, \
  1341. .einput_bit = 5, \
  1342. .odrain_bit = PINGROUP_BIT_##od(6), \
  1343. .lock_bit = 7, \
  1344. .ioreset_bit = PINGROUP_BIT_##ior(8), \
  1345. .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
  1346. .drv_reg = -1, \
  1347. .parked_bitmask = 0, \
  1348. }
  1349. #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
  1350. drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
  1351. slwf_b, slwf_w, drvtype) \
  1352. { \
  1353. .name = "drive_" #pg_name, \
  1354. .pins = drive_##pg_name##_pins, \
  1355. .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
  1356. .mux_reg = -1, \
  1357. .pupd_reg = -1, \
  1358. .tri_reg = -1, \
  1359. .einput_bit = -1, \
  1360. .odrain_bit = -1, \
  1361. .lock_bit = -1, \
  1362. .ioreset_bit = -1, \
  1363. .rcv_sel_bit = -1, \
  1364. .drv_reg = DRV_PINGROUP_REG(r), \
  1365. .drv_bank = 0, \
  1366. .hsm_bit = hsm_b, \
  1367. .schmitt_bit = schmitt_b, \
  1368. .lpmd_bit = lpmd_b, \
  1369. .drvdn_bit = drvdn_b, \
  1370. .drvdn_width = drvdn_w, \
  1371. .drvup_bit = drvup_b, \
  1372. .drvup_width = drvup_w, \
  1373. .slwr_bit = slwr_b, \
  1374. .slwr_width = slwr_w, \
  1375. .slwf_bit = slwf_b, \
  1376. .slwf_width = slwf_w, \
  1377. .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
  1378. .parked_bitmask = 0, \
  1379. }
  1380. static const struct tegra_pingroup tegra114_groups[] = {
  1381. /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
  1382. PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
  1383. PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
  1384. PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
  1385. PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
  1386. PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
  1387. PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
  1388. PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
  1389. PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
  1390. PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
  1391. PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
  1392. PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
  1393. PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
  1394. PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
  1395. PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
  1396. PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3038, N, N, N),
  1397. PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x303c, N, N, N),
  1398. PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
  1399. PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
  1400. PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
  1401. PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
  1402. PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
  1403. PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
  1404. PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
  1405. PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
  1406. PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
  1407. PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
  1408. PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
  1409. PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
  1410. PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
  1411. PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
  1412. PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
  1413. PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, 0x316c, N, N, N),
  1414. PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, 0x3170, N, N, N),
  1415. PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, 0x3174, N, N, N),
  1416. PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, 0x3178, N, N, N),
  1417. PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, 0x317c, N, N, N),
  1418. PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N),
  1419. PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, 0x3184, N, N, N),
  1420. PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, 0x3188, N, N, N),
  1421. PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, 0x318c, N, N, N),
  1422. PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N),
  1423. PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, 0x3194, N, N, N),
  1424. PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, 0x3198, N, N, N),
  1425. PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, 0x319c, N, N, N),
  1426. PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
  1427. PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
  1428. PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, 0x31a8, N, N, N),
  1429. PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, 0x31ac, N, N, N),
  1430. PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, 0x31b0, N, N, N),
  1431. PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, 0x31b4, N, N, N),
  1432. PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
  1433. PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
  1434. PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N, N),
  1435. PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, 0x31c4, N, N, N),
  1436. PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N, N),
  1437. PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N, N),
  1438. PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N, N),
  1439. PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N, N),
  1440. PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N, N),
  1441. PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N, N),
  1442. PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N, N),
  1443. PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N, N),
  1444. PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N, N),
  1445. PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, 0x31ec, N, N, N),
  1446. PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N, N),
  1447. PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N, N),
  1448. PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N, N),
  1449. PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N, N),
  1450. PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N, N),
  1451. PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, 0x3204, N, N, N),
  1452. PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, 0x3208, N, N, N),
  1453. PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, 0x320c, N, N, N),
  1454. PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N),
  1455. PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, 0x3214, N, N, N),
  1456. PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, 0x3218, N, N, N),
  1457. PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, 0x321c, N, N, N),
  1458. PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, 0x3220, N, N, N),
  1459. PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, 0x3224, N, N, N),
  1460. PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, 0x3228, N, N, N),
  1461. PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, 0x322c, N, N, N),
  1462. PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, 0x3230, N, N, N),
  1463. PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, 0x3234, N, N, N),
  1464. PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, 0x3238, N, N, N),
  1465. PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, 0x323c, N, N, N),
  1466. PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, 0x3240, N, N, N),
  1467. PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, 0x3244, N, N, N),
  1468. PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, 0x3248, N, N, N),
  1469. PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N, N),
  1470. PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
  1471. PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
  1472. PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
  1473. PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
  1474. PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
  1475. PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
  1476. PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
  1477. PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
  1478. PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
  1479. PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, 0x3274, N, Y, N),
  1480. PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
  1481. PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
  1482. PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, 0x3284, N, N, N),
  1483. PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, 0x3288, N, N, N),
  1484. PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, 0x328c, N, N, N),
  1485. PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, 0x3290, Y, N, N),
  1486. PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, 0x3294, Y, N, N),
  1487. PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, 0x3298, N, N, N),
  1488. PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, 0x329c, N, N, N),
  1489. PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, 0x32a0, N, N, N),
  1490. PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, 0x32a4, N, N, N),
  1491. PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, 0x32a8, N, N, N),
  1492. PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N, N),
  1493. PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
  1494. PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
  1495. PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
  1496. PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
  1497. PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
  1498. PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
  1499. PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32c8, N, N, N),
  1500. PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32cc, N, N, N),
  1501. PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32d0, N, N, N),
  1502. PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
  1503. PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
  1504. PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
  1505. PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
  1506. PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
  1507. PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, 0x32fc, N, N, N),
  1508. PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, 0x3300, N, N, N),
  1509. PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
  1510. PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
  1511. PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
  1512. PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, 0x3310, N, N, N),
  1513. PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, 0x3314, N, N, N),
  1514. PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, 0x3318, N, N, N),
  1515. PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
  1516. PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N, N),
  1517. PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
  1518. PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
  1519. PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
  1520. PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
  1521. PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
  1522. PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
  1523. PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
  1524. PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, 0x3340, N, N, N),
  1525. PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
  1526. PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, 0x3348, N, N, N),
  1527. PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
  1528. PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, 0x3350, N, N, N),
  1529. PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, 0x3354, N, N, N),
  1530. PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, 0x3358, N, N, N),
  1531. PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, 0x335c, N, N, N),
  1532. PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, 0x3360, N, N, N),
  1533. PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, 0x3364, N, N, N),
  1534. PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, 0x3368, N, N, N),
  1535. PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, 0x336c, N, N, N),
  1536. PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, 0x3370, N, N, N),
  1537. PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, 0x3374, N, N, N),
  1538. PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, 0x3378, N, N, N),
  1539. PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
  1540. PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, 0x3380, N, N, N),
  1541. PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
  1542. PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
  1543. PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
  1544. PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
  1545. PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
  1546. PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
  1547. PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
  1548. PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, 0x33e0, Y, N, N),
  1549. PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
  1550. PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
  1551. PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
  1552. PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
  1553. PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
  1554. PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
  1555. PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
  1556. PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
  1557. PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, 0x3404, N, N, N),
  1558. PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
  1559. /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
  1560. DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1561. DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1562. DRV_PINGROUP(at1, 0x870, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
  1563. DRV_PINGROUP(at2, 0x874, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
  1564. DRV_PINGROUP(at3, 0x878, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
  1565. DRV_PINGROUP(at4, 0x87c, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
  1566. DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
  1567. DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1568. DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1569. DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1570. DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1571. DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1572. DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1573. DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1574. DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
  1575. DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1576. DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1577. DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1578. DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1579. DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1580. DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
  1581. DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1582. DRV_PINGROUP(gma, 0x900, 2, 3, -1, 14, 5, 20, 5, 28, 2, 30, 2, N),
  1583. DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
  1584. DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
  1585. DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
  1586. DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
  1587. DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1588. DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1589. DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1590. DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1591. DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, Y),
  1592. DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1593. DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1594. DRV_PINGROUP(ao3, 0x9a0, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
  1595. DRV_PINGROUP(hv0, 0x9a4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
  1596. DRV_PINGROUP(sdio4, 0x9a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1597. DRV_PINGROUP(ao0, 0x9ac, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
  1598. };
  1599. static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
  1600. .ngpios = NUM_GPIOS,
  1601. .gpio_compatible = "nvidia,tegra114-gpio",
  1602. .pins = tegra114_pins,
  1603. .npins = ARRAY_SIZE(tegra114_pins),
  1604. .functions = tegra114_functions,
  1605. .nfunctions = ARRAY_SIZE(tegra114_functions),
  1606. .groups = tegra114_groups,
  1607. .ngroups = ARRAY_SIZE(tegra114_groups),
  1608. .hsm_in_mux = false,
  1609. .schmitt_in_mux = false,
  1610. .drvtype_in_mux = false,
  1611. };
  1612. static int tegra114_pinctrl_probe(struct platform_device *pdev)
  1613. {
  1614. return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
  1615. }
  1616. static const struct of_device_id tegra114_pinctrl_of_match[] = {
  1617. { .compatible = "nvidia,tegra114-pinmux", },
  1618. { },
  1619. };
  1620. static struct platform_driver tegra114_pinctrl_driver = {
  1621. .driver = {
  1622. .name = "tegra114-pinctrl",
  1623. .of_match_table = tegra114_pinctrl_of_match,
  1624. },
  1625. .probe = tegra114_pinctrl_probe,
  1626. };
  1627. static int __init tegra114_pinctrl_init(void)
  1628. {
  1629. return platform_driver_register(&tegra114_pinctrl_driver);
  1630. }
  1631. arch_initcall(tegra114_pinctrl_init);