pinctrl-tegra-xusb.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/io.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/phy/phy.h>
  10. #include <linux/pinctrl/pinctrl.h>
  11. #include <linux/pinctrl/pinmux.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/reset.h>
  14. #include <linux/slab.h>
  15. #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  16. #include "../core.h"
  17. #include "../pinctrl-utils.h"
  18. #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
  19. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
  20. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
  21. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
  22. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
  23. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
  24. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
  25. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
  26. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
  27. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
  28. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
  29. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
  30. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
  31. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
  32. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
  33. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
  34. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
  35. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
  36. #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
  37. #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
  38. #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
  39. struct tegra_xusb_padctl_function {
  40. const char *name;
  41. const char * const *groups;
  42. unsigned int num_groups;
  43. };
  44. struct tegra_xusb_padctl_soc {
  45. const struct pinctrl_pin_desc *pins;
  46. unsigned int num_pins;
  47. const struct tegra_xusb_padctl_function *functions;
  48. unsigned int num_functions;
  49. const struct tegra_xusb_padctl_lane *lanes;
  50. unsigned int num_lanes;
  51. };
  52. struct tegra_xusb_padctl_lane {
  53. const char *name;
  54. unsigned int offset;
  55. unsigned int shift;
  56. unsigned int mask;
  57. unsigned int iddq;
  58. const unsigned int *funcs;
  59. unsigned int num_funcs;
  60. };
  61. struct tegra_xusb_padctl {
  62. struct device *dev;
  63. void __iomem *regs;
  64. struct mutex lock;
  65. struct reset_control *rst;
  66. const struct tegra_xusb_padctl_soc *soc;
  67. struct pinctrl_dev *pinctrl;
  68. struct pinctrl_desc desc;
  69. struct phy_provider *provider;
  70. struct phy *phys[2];
  71. unsigned int enable;
  72. };
  73. static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
  74. unsigned long offset)
  75. {
  76. writel(value, padctl->regs + offset);
  77. }
  78. static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
  79. unsigned long offset)
  80. {
  81. return readl(padctl->regs + offset);
  82. }
  83. static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
  84. {
  85. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  86. return padctl->soc->num_pins;
  87. }
  88. static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
  89. unsigned int group)
  90. {
  91. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  92. return padctl->soc->pins[group].name;
  93. }
  94. static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
  95. unsigned group,
  96. const unsigned **pins,
  97. unsigned *num_pins)
  98. {
  99. /*
  100. * For the tegra-xusb pad controller groups are synonymous
  101. * with lanes/pins and there is always one lane/pin per group.
  102. */
  103. *pins = &pinctrl->desc->pins[group].number;
  104. *num_pins = 1;
  105. return 0;
  106. }
  107. enum tegra_xusb_padctl_param {
  108. TEGRA_XUSB_PADCTL_IDDQ,
  109. };
  110. static const struct tegra_xusb_padctl_property {
  111. const char *name;
  112. enum tegra_xusb_padctl_param param;
  113. } properties[] = {
  114. { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
  115. };
  116. #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
  117. #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
  118. #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
  119. static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
  120. struct device_node *np,
  121. struct pinctrl_map **maps,
  122. unsigned int *reserved_maps,
  123. unsigned int *num_maps)
  124. {
  125. unsigned int i, reserve = 0, num_configs = 0;
  126. unsigned long config, *configs = NULL;
  127. const char *function, *group;
  128. struct property *prop;
  129. int err = 0;
  130. u32 value;
  131. err = of_property_read_string(np, "nvidia,function", &function);
  132. if (err < 0) {
  133. if (err != -EINVAL)
  134. return err;
  135. function = NULL;
  136. }
  137. for (i = 0; i < ARRAY_SIZE(properties); i++) {
  138. err = of_property_read_u32(np, properties[i].name, &value);
  139. if (err < 0) {
  140. if (err == -EINVAL)
  141. continue;
  142. goto out;
  143. }
  144. config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
  145. err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
  146. &num_configs, config);
  147. if (err < 0)
  148. goto out;
  149. }
  150. if (function)
  151. reserve++;
  152. if (num_configs)
  153. reserve++;
  154. err = of_property_count_strings(np, "nvidia,lanes");
  155. if (err < 0)
  156. goto out;
  157. reserve *= err;
  158. err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
  159. num_maps, reserve);
  160. if (err < 0)
  161. goto out;
  162. of_property_for_each_string(np, "nvidia,lanes", prop, group) {
  163. if (function) {
  164. err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
  165. reserved_maps, num_maps, group,
  166. function);
  167. if (err < 0)
  168. goto out;
  169. }
  170. if (num_configs) {
  171. err = pinctrl_utils_add_map_configs(padctl->pinctrl,
  172. maps, reserved_maps, num_maps, group,
  173. configs, num_configs,
  174. PIN_MAP_TYPE_CONFIGS_GROUP);
  175. if (err < 0)
  176. goto out;
  177. }
  178. }
  179. err = 0;
  180. out:
  181. kfree(configs);
  182. return err;
  183. }
  184. static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
  185. struct device_node *parent,
  186. struct pinctrl_map **maps,
  187. unsigned int *num_maps)
  188. {
  189. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  190. unsigned int reserved_maps = 0;
  191. struct device_node *np;
  192. int err;
  193. *num_maps = 0;
  194. *maps = NULL;
  195. for_each_child_of_node(parent, np) {
  196. err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
  197. &reserved_maps,
  198. num_maps);
  199. if (err < 0) {
  200. of_node_put(np);
  201. return err;
  202. }
  203. }
  204. return 0;
  205. }
  206. static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
  207. .get_groups_count = tegra_xusb_padctl_get_groups_count,
  208. .get_group_name = tegra_xusb_padctl_get_group_name,
  209. .get_group_pins = tegra_xusb_padctl_get_group_pins,
  210. .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
  211. .dt_free_map = pinctrl_utils_free_map,
  212. };
  213. static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
  214. {
  215. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  216. return padctl->soc->num_functions;
  217. }
  218. static const char *
  219. tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
  220. unsigned int function)
  221. {
  222. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  223. return padctl->soc->functions[function].name;
  224. }
  225. static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
  226. unsigned int function,
  227. const char * const **groups,
  228. unsigned * const num_groups)
  229. {
  230. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  231. *num_groups = padctl->soc->functions[function].num_groups;
  232. *groups = padctl->soc->functions[function].groups;
  233. return 0;
  234. }
  235. static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
  236. unsigned int function,
  237. unsigned int group)
  238. {
  239. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  240. const struct tegra_xusb_padctl_lane *lane;
  241. unsigned int i;
  242. u32 value;
  243. lane = &padctl->soc->lanes[group];
  244. for (i = 0; i < lane->num_funcs; i++)
  245. if (lane->funcs[i] == function)
  246. break;
  247. if (i >= lane->num_funcs)
  248. return -EINVAL;
  249. value = padctl_readl(padctl, lane->offset);
  250. value &= ~(lane->mask << lane->shift);
  251. value |= i << lane->shift;
  252. padctl_writel(padctl, value, lane->offset);
  253. return 0;
  254. }
  255. static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
  256. .get_functions_count = tegra_xusb_padctl_get_functions_count,
  257. .get_function_name = tegra_xusb_padctl_get_function_name,
  258. .get_function_groups = tegra_xusb_padctl_get_function_groups,
  259. .set_mux = tegra_xusb_padctl_pinmux_set,
  260. };
  261. static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
  262. unsigned int group,
  263. unsigned long *config)
  264. {
  265. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  266. const struct tegra_xusb_padctl_lane *lane;
  267. enum tegra_xusb_padctl_param param;
  268. u32 value;
  269. param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
  270. lane = &padctl->soc->lanes[group];
  271. switch (param) {
  272. case TEGRA_XUSB_PADCTL_IDDQ:
  273. /* lanes with iddq == 0 don't support this parameter */
  274. if (lane->iddq == 0)
  275. return -EINVAL;
  276. value = padctl_readl(padctl, lane->offset);
  277. if (value & BIT(lane->iddq))
  278. value = 0;
  279. else
  280. value = 1;
  281. *config = TEGRA_XUSB_PADCTL_PACK(param, value);
  282. break;
  283. default:
  284. dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
  285. param);
  286. return -ENOTSUPP;
  287. }
  288. return 0;
  289. }
  290. static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
  291. unsigned int group,
  292. unsigned long *configs,
  293. unsigned int num_configs)
  294. {
  295. struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
  296. const struct tegra_xusb_padctl_lane *lane;
  297. enum tegra_xusb_padctl_param param;
  298. unsigned long value;
  299. unsigned int i;
  300. u32 regval;
  301. lane = &padctl->soc->lanes[group];
  302. for (i = 0; i < num_configs; i++) {
  303. param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
  304. value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
  305. switch (param) {
  306. case TEGRA_XUSB_PADCTL_IDDQ:
  307. /* lanes with iddq == 0 don't support this parameter */
  308. if (lane->iddq == 0)
  309. return -EINVAL;
  310. regval = padctl_readl(padctl, lane->offset);
  311. if (value)
  312. regval &= ~BIT(lane->iddq);
  313. else
  314. regval |= BIT(lane->iddq);
  315. padctl_writel(padctl, regval, lane->offset);
  316. break;
  317. default:
  318. dev_err(padctl->dev,
  319. "invalid configuration parameter: %04x\n",
  320. param);
  321. return -ENOTSUPP;
  322. }
  323. }
  324. return 0;
  325. }
  326. #ifdef CONFIG_DEBUG_FS
  327. static const char *strip_prefix(const char *s)
  328. {
  329. const char *comma = strchr(s, ',');
  330. if (!comma)
  331. return s;
  332. return comma + 1;
  333. }
  334. static void
  335. tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
  336. struct seq_file *s,
  337. unsigned int group)
  338. {
  339. unsigned int i;
  340. for (i = 0; i < ARRAY_SIZE(properties); i++) {
  341. unsigned long config, value;
  342. int err;
  343. config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
  344. err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
  345. &config);
  346. if (err < 0)
  347. continue;
  348. value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
  349. seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
  350. value);
  351. }
  352. }
  353. static void
  354. tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
  355. struct seq_file *s,
  356. unsigned long config)
  357. {
  358. enum tegra_xusb_padctl_param param;
  359. const char *name = "unknown";
  360. unsigned long value;
  361. unsigned int i;
  362. param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
  363. value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
  364. for (i = 0; i < ARRAY_SIZE(properties); i++) {
  365. if (properties[i].param == param) {
  366. name = properties[i].name;
  367. break;
  368. }
  369. }
  370. seq_printf(s, "%s=%lu", strip_prefix(name), value);
  371. }
  372. #endif
  373. static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
  374. .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
  375. .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
  376. #ifdef CONFIG_DEBUG_FS
  377. .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
  378. .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
  379. #endif
  380. };
  381. static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
  382. {
  383. u32 value;
  384. mutex_lock(&padctl->lock);
  385. if (padctl->enable++ > 0)
  386. goto out;
  387. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  388. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
  389. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  390. usleep_range(100, 200);
  391. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  392. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
  393. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  394. usleep_range(100, 200);
  395. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  396. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
  397. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  398. out:
  399. mutex_unlock(&padctl->lock);
  400. return 0;
  401. }
  402. static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
  403. {
  404. u32 value;
  405. mutex_lock(&padctl->lock);
  406. if (WARN_ON(padctl->enable == 0))
  407. goto out;
  408. if (--padctl->enable > 0)
  409. goto out;
  410. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  411. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
  412. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  413. usleep_range(100, 200);
  414. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  415. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
  416. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  417. usleep_range(100, 200);
  418. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  419. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
  420. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  421. out:
  422. mutex_unlock(&padctl->lock);
  423. return 0;
  424. }
  425. static int tegra_xusb_phy_init(struct phy *phy)
  426. {
  427. struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
  428. return tegra_xusb_padctl_enable(padctl);
  429. }
  430. static int tegra_xusb_phy_exit(struct phy *phy)
  431. {
  432. struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
  433. return tegra_xusb_padctl_disable(padctl);
  434. }
  435. static int pcie_phy_power_on(struct phy *phy)
  436. {
  437. struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
  438. unsigned long timeout;
  439. int err = -ETIMEDOUT;
  440. u32 value;
  441. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  442. value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
  443. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  444. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
  445. value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
  446. XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
  447. XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
  448. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
  449. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  450. value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
  451. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  452. timeout = jiffies + msecs_to_jiffies(50);
  453. while (time_before(jiffies, timeout)) {
  454. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  455. if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
  456. err = 0;
  457. break;
  458. }
  459. usleep_range(100, 200);
  460. }
  461. return err;
  462. }
  463. static int pcie_phy_power_off(struct phy *phy)
  464. {
  465. struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
  466. u32 value;
  467. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  468. value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
  469. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  470. return 0;
  471. }
  472. static const struct phy_ops pcie_phy_ops = {
  473. .init = tegra_xusb_phy_init,
  474. .exit = tegra_xusb_phy_exit,
  475. .power_on = pcie_phy_power_on,
  476. .power_off = pcie_phy_power_off,
  477. .owner = THIS_MODULE,
  478. };
  479. static int sata_phy_power_on(struct phy *phy)
  480. {
  481. struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
  482. unsigned long timeout;
  483. int err = -ETIMEDOUT;
  484. u32 value;
  485. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  486. value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
  487. value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
  488. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  489. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  490. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
  491. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
  492. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  493. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  494. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
  495. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  496. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  497. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
  498. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  499. timeout = jiffies + msecs_to_jiffies(50);
  500. while (time_before(jiffies, timeout)) {
  501. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  502. if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
  503. err = 0;
  504. break;
  505. }
  506. usleep_range(100, 200);
  507. }
  508. return err;
  509. }
  510. static int sata_phy_power_off(struct phy *phy)
  511. {
  512. struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
  513. u32 value;
  514. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  515. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
  516. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  517. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  518. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
  519. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  520. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  521. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
  522. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
  523. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  524. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  525. value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
  526. value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
  527. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  528. return 0;
  529. }
  530. static const struct phy_ops sata_phy_ops = {
  531. .init = tegra_xusb_phy_init,
  532. .exit = tegra_xusb_phy_exit,
  533. .power_on = sata_phy_power_on,
  534. .power_off = sata_phy_power_off,
  535. .owner = THIS_MODULE,
  536. };
  537. static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
  538. struct of_phandle_args *args)
  539. {
  540. struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
  541. unsigned int index = args->args[0];
  542. if (args->args_count <= 0)
  543. return ERR_PTR(-EINVAL);
  544. if (index >= ARRAY_SIZE(padctl->phys))
  545. return ERR_PTR(-EINVAL);
  546. return padctl->phys[index];
  547. }
  548. #define PIN_OTG_0 0
  549. #define PIN_OTG_1 1
  550. #define PIN_OTG_2 2
  551. #define PIN_ULPI_0 3
  552. #define PIN_HSIC_0 4
  553. #define PIN_HSIC_1 5
  554. #define PIN_PCIE_0 6
  555. #define PIN_PCIE_1 7
  556. #define PIN_PCIE_2 8
  557. #define PIN_PCIE_3 9
  558. #define PIN_PCIE_4 10
  559. #define PIN_SATA_0 11
  560. static const struct pinctrl_pin_desc tegra124_pins[] = {
  561. PINCTRL_PIN(PIN_OTG_0, "otg-0"),
  562. PINCTRL_PIN(PIN_OTG_1, "otg-1"),
  563. PINCTRL_PIN(PIN_OTG_2, "otg-2"),
  564. PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
  565. PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
  566. PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
  567. PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
  568. PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
  569. PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
  570. PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
  571. PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
  572. PINCTRL_PIN(PIN_SATA_0, "sata-0"),
  573. };
  574. static const char * const tegra124_snps_groups[] = {
  575. "otg-0",
  576. "otg-1",
  577. "otg-2",
  578. "ulpi-0",
  579. "hsic-0",
  580. "hsic-1",
  581. };
  582. static const char * const tegra124_xusb_groups[] = {
  583. "otg-0",
  584. "otg-1",
  585. "otg-2",
  586. "ulpi-0",
  587. "hsic-0",
  588. "hsic-1",
  589. };
  590. static const char * const tegra124_uart_groups[] = {
  591. "otg-0",
  592. "otg-1",
  593. "otg-2",
  594. };
  595. static const char * const tegra124_pcie_groups[] = {
  596. "pcie-0",
  597. "pcie-1",
  598. "pcie-2",
  599. "pcie-3",
  600. "pcie-4",
  601. };
  602. static const char * const tegra124_usb3_groups[] = {
  603. "pcie-0",
  604. "pcie-1",
  605. "sata-0",
  606. };
  607. static const char * const tegra124_sata_groups[] = {
  608. "sata-0",
  609. };
  610. static const char * const tegra124_rsvd_groups[] = {
  611. "otg-0",
  612. "otg-1",
  613. "otg-2",
  614. "pcie-0",
  615. "pcie-1",
  616. "pcie-2",
  617. "pcie-3",
  618. "pcie-4",
  619. "sata-0",
  620. };
  621. #define TEGRA124_FUNCTION(_name) \
  622. { \
  623. .name = #_name, \
  624. .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
  625. .groups = tegra124_##_name##_groups, \
  626. }
  627. static struct tegra_xusb_padctl_function tegra124_functions[] = {
  628. TEGRA124_FUNCTION(snps),
  629. TEGRA124_FUNCTION(xusb),
  630. TEGRA124_FUNCTION(uart),
  631. TEGRA124_FUNCTION(pcie),
  632. TEGRA124_FUNCTION(usb3),
  633. TEGRA124_FUNCTION(sata),
  634. TEGRA124_FUNCTION(rsvd),
  635. };
  636. enum tegra124_function {
  637. TEGRA124_FUNC_SNPS,
  638. TEGRA124_FUNC_XUSB,
  639. TEGRA124_FUNC_UART,
  640. TEGRA124_FUNC_PCIE,
  641. TEGRA124_FUNC_USB3,
  642. TEGRA124_FUNC_SATA,
  643. TEGRA124_FUNC_RSVD,
  644. };
  645. static const unsigned int tegra124_otg_functions[] = {
  646. TEGRA124_FUNC_SNPS,
  647. TEGRA124_FUNC_XUSB,
  648. TEGRA124_FUNC_UART,
  649. TEGRA124_FUNC_RSVD,
  650. };
  651. static const unsigned int tegra124_usb_functions[] = {
  652. TEGRA124_FUNC_SNPS,
  653. TEGRA124_FUNC_XUSB,
  654. };
  655. static const unsigned int tegra124_pci_functions[] = {
  656. TEGRA124_FUNC_PCIE,
  657. TEGRA124_FUNC_USB3,
  658. TEGRA124_FUNC_SATA,
  659. TEGRA124_FUNC_RSVD,
  660. };
  661. #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
  662. { \
  663. .name = _name, \
  664. .offset = _offset, \
  665. .shift = _shift, \
  666. .mask = _mask, \
  667. .iddq = _iddq, \
  668. .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
  669. .funcs = tegra124_##_funcs##_functions, \
  670. }
  671. static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
  672. TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
  673. TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
  674. TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
  675. TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
  676. TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
  677. TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
  678. TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
  679. TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
  680. TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
  681. TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
  682. TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
  683. TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
  684. };
  685. static const struct tegra_xusb_padctl_soc tegra124_soc = {
  686. .num_pins = ARRAY_SIZE(tegra124_pins),
  687. .pins = tegra124_pins,
  688. .num_functions = ARRAY_SIZE(tegra124_functions),
  689. .functions = tegra124_functions,
  690. .num_lanes = ARRAY_SIZE(tegra124_lanes),
  691. .lanes = tegra124_lanes,
  692. };
  693. static const struct of_device_id tegra_xusb_padctl_of_match[] = {
  694. { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
  695. { }
  696. };
  697. MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
  698. /* predeclare these in order to silence sparse */
  699. int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
  700. int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
  701. int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev)
  702. {
  703. struct tegra_xusb_padctl *padctl;
  704. const struct of_device_id *match;
  705. struct phy *phy;
  706. int err;
  707. padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
  708. if (!padctl)
  709. return -ENOMEM;
  710. platform_set_drvdata(pdev, padctl);
  711. mutex_init(&padctl->lock);
  712. padctl->dev = &pdev->dev;
  713. /*
  714. * Note that we can't replace this by of_device_get_match_data()
  715. * because we need the separate matching table for this legacy code on
  716. * Tegra124. of_device_get_match_data() would attempt to use the table
  717. * from the updated driver and fail.
  718. */
  719. match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
  720. padctl->soc = match->data;
  721. padctl->regs = devm_platform_ioremap_resource(pdev, 0);
  722. if (IS_ERR(padctl->regs))
  723. return PTR_ERR(padctl->regs);
  724. padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  725. if (IS_ERR(padctl->rst))
  726. return PTR_ERR(padctl->rst);
  727. err = reset_control_deassert(padctl->rst);
  728. if (err < 0)
  729. return err;
  730. memset(&padctl->desc, 0, sizeof(padctl->desc));
  731. padctl->desc.name = dev_name(padctl->dev);
  732. padctl->desc.pins = tegra124_pins;
  733. padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
  734. padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
  735. padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
  736. padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
  737. padctl->desc.owner = THIS_MODULE;
  738. padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
  739. padctl);
  740. if (IS_ERR(padctl->pinctrl)) {
  741. dev_err(&pdev->dev, "failed to register pincontrol\n");
  742. err = PTR_ERR(padctl->pinctrl);
  743. goto reset;
  744. }
  745. phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
  746. if (IS_ERR(phy)) {
  747. err = PTR_ERR(phy);
  748. goto reset;
  749. }
  750. padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
  751. phy_set_drvdata(phy, padctl);
  752. phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
  753. if (IS_ERR(phy)) {
  754. err = PTR_ERR(phy);
  755. goto reset;
  756. }
  757. padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
  758. phy_set_drvdata(phy, padctl);
  759. padctl->provider = devm_of_phy_provider_register(&pdev->dev,
  760. tegra_xusb_padctl_xlate);
  761. if (IS_ERR(padctl->provider)) {
  762. err = PTR_ERR(padctl->provider);
  763. dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
  764. goto reset;
  765. }
  766. return 0;
  767. reset:
  768. reset_control_assert(padctl->rst);
  769. return err;
  770. }
  771. EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_probe);
  772. int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev)
  773. {
  774. struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
  775. int err;
  776. err = reset_control_assert(padctl->rst);
  777. if (err < 0)
  778. dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
  779. return err;
  780. }
  781. EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_remove);