pinctrl-spear320.c 89 KB

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  1. /*
  2. * Driver for the ST Microelectronics SPEAr320 pinmux
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Viresh Kumar <vireshk@kernel.org>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include "pinctrl-spear3xx.h"
  16. #define DRIVER_NAME "spear320-pinmux"
  17. /* addresses */
  18. #define PMX_CONFIG_REG 0x0C
  19. #define MODE_CONFIG_REG 0x10
  20. #define MODE_EXT_CONFIG_REG 0x18
  21. /* modes */
  22. #define AUTO_NET_SMII_MODE (1 << 0)
  23. #define AUTO_NET_MII_MODE (1 << 1)
  24. #define AUTO_EXP_MODE (1 << 2)
  25. #define SMALL_PRINTERS_MODE (1 << 3)
  26. #define EXTENDED_MODE (1 << 4)
  27. static struct spear_pmx_mode pmx_mode_auto_net_smii = {
  28. .name = "Automation Networking SMII mode",
  29. .mode = AUTO_NET_SMII_MODE,
  30. .reg = MODE_CONFIG_REG,
  31. .mask = 0x00000007,
  32. .val = 0x0,
  33. };
  34. static struct spear_pmx_mode pmx_mode_auto_net_mii = {
  35. .name = "Automation Networking MII mode",
  36. .mode = AUTO_NET_MII_MODE,
  37. .reg = MODE_CONFIG_REG,
  38. .mask = 0x00000007,
  39. .val = 0x1,
  40. };
  41. static struct spear_pmx_mode pmx_mode_auto_exp = {
  42. .name = "Automation Expanded mode",
  43. .mode = AUTO_EXP_MODE,
  44. .reg = MODE_CONFIG_REG,
  45. .mask = 0x00000007,
  46. .val = 0x2,
  47. };
  48. static struct spear_pmx_mode pmx_mode_small_printers = {
  49. .name = "Small Printers mode",
  50. .mode = SMALL_PRINTERS_MODE,
  51. .reg = MODE_CONFIG_REG,
  52. .mask = 0x00000007,
  53. .val = 0x3,
  54. };
  55. static struct spear_pmx_mode pmx_mode_extended = {
  56. .name = "extended mode",
  57. .mode = EXTENDED_MODE,
  58. .reg = MODE_EXT_CONFIG_REG,
  59. .mask = 0x00000001,
  60. .val = 0x1,
  61. };
  62. static struct spear_pmx_mode *spear320_pmx_modes[] = {
  63. &pmx_mode_auto_net_smii,
  64. &pmx_mode_auto_net_mii,
  65. &pmx_mode_auto_exp,
  66. &pmx_mode_small_printers,
  67. &pmx_mode_extended,
  68. };
  69. /* Extended mode registers and their offsets */
  70. #define EXT_CTRL_REG 0x0018
  71. #define MII_MDIO_MASK (1 << 4)
  72. #define MII_MDIO_10_11_VAL 0
  73. #define MII_MDIO_81_VAL (1 << 4)
  74. #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
  75. #define MAC_MODE_MII 0
  76. #define MAC_MODE_RMII 1
  77. #define MAC_MODE_SMII 2
  78. #define MAC_MODE_SS_SMII 3
  79. #define MAC_MODE_MASK 0x3
  80. #define MAC1_MODE_SHIFT 16
  81. #define MAC2_MODE_SHIFT 18
  82. #define IP_SEL_PAD_0_9_REG 0x00A4
  83. #define PMX_PL_0_1_MASK (0x3F << 0)
  84. #define PMX_UART2_PL_0_1_VAL 0x0
  85. #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
  86. #define PMX_PL_2_3_MASK (0x3F << 6)
  87. #define PMX_I2C2_PL_2_3_VAL 0x0
  88. #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
  89. #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
  90. #define PMX_PL_4_5_MASK (0x3F << 12)
  91. #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
  92. #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
  93. #define PMX_PL_5_MASK (0x7 << 15)
  94. #define PMX_TOUCH_Y_PL_5_VAL 0x0
  95. #define PMX_PL_6_7_MASK (0x3F << 18)
  96. #define PMX_PL_6_MASK (0x7 << 18)
  97. #define PMX_PL_7_MASK (0x7 << 21)
  98. #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
  99. #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
  100. #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
  101. #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
  102. #define PMX_PL_8_9_MASK (0x3F << 24)
  103. #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
  104. #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
  105. #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
  106. #define IP_SEL_PAD_10_19_REG 0x00A8
  107. #define PMX_PL_10_11_MASK (0x3F << 0)
  108. #define PMX_SMII_PL_10_11_VAL 0
  109. #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
  110. #define PMX_PL_12_MASK (0x7 << 6)
  111. #define PMX_PWM3_PL_12_VAL 0
  112. #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
  113. #define PMX_PL_13_14_MASK (0x3F << 9)
  114. #define PMX_PL_13_MASK (0x7 << 9)
  115. #define PMX_PL_14_MASK (0x7 << 12)
  116. #define PMX_SSP2_PL_13_14_15_16_VAL 0
  117. #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
  118. #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
  119. #define PMX_PWM2_PL_13_VAL (0x2 << 9)
  120. #define PMX_PWM1_PL_14_VAL (0x2 << 12)
  121. #define PMX_PL_15_MASK (0x7 << 15)
  122. #define PMX_PWM0_PL_15_VAL (0x2 << 15)
  123. #define PMX_PL_15_16_MASK (0x3F << 15)
  124. #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
  125. #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
  126. #define PMX_PL_17_18_MASK (0x3F << 21)
  127. #define PMX_SSP1_PL_17_18_19_20_VAL 0
  128. #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
  129. #define PMX_PL_19_MASK (0x7 << 27)
  130. #define PMX_I2C2_PL_19_VAL (0x1 << 27)
  131. #define PMX_RMII_PL_19_VAL (0x4 << 27)
  132. #define IP_SEL_PAD_20_29_REG 0x00AC
  133. #define PMX_PL_20_MASK (0x7 << 0)
  134. #define PMX_I2C2_PL_20_VAL (0x1 << 0)
  135. #define PMX_RMII_PL_20_VAL (0x4 << 0)
  136. #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
  137. #define PMX_SMII_PL_21_TO_27_VAL 0
  138. #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
  139. #define PMX_PL_28_29_MASK (0x3F << 24)
  140. #define PMX_PL_28_MASK (0x7 << 24)
  141. #define PMX_PL_29_MASK (0x7 << 27)
  142. #define PMX_UART1_PL_28_29_VAL 0
  143. #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
  144. #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
  145. #define IP_SEL_PAD_30_39_REG 0x00B0
  146. #define PMX_PL_30_31_MASK (0x3F << 0)
  147. #define PMX_CAN1_PL_30_31_VAL (0)
  148. #define PMX_PL_30_MASK (0x7 << 0)
  149. #define PMX_PL_31_MASK (0x7 << 3)
  150. #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
  151. #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
  152. #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
  153. #define PMX_PL_32_33_MASK (0x3F << 6)
  154. #define PMX_CAN0_PL_32_33_VAL 0
  155. #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
  156. #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
  157. #define PMX_PL_34_MASK (0x7 << 12)
  158. #define PMX_PWM2_PL_34_VAL 0
  159. #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
  160. #define PMX_SSP2_PL_34_VAL (0x4 << 12)
  161. #define PMX_PL_35_MASK (0x7 << 15)
  162. #define PMX_I2S_REF_CLK_PL_35_VAL 0
  163. #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
  164. #define PMX_SSP2_PL_35_VAL (0x4 << 15)
  165. #define PMX_PL_36_MASK (0x7 << 18)
  166. #define PMX_TOUCH_X_PL_36_VAL 0
  167. #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
  168. #define PMX_SSP1_PL_36_VAL (0x4 << 18)
  169. #define PMX_PL_37_38_MASK (0x3F << 21)
  170. #define PMX_PWM0_1_PL_37_38_VAL 0
  171. #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
  172. #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
  173. #define PMX_PL_39_MASK (0x7 << 27)
  174. #define PMX_I2S_PL_39_VAL 0
  175. #define PMX_UART4_PL_39_VAL (0x2 << 27)
  176. #define PMX_SSP1_PL_39_VAL (0x4 << 27)
  177. #define IP_SEL_PAD_40_49_REG 0x00B4
  178. #define PMX_PL_40_MASK (0x7 << 0)
  179. #define PMX_I2S_PL_40_VAL 0
  180. #define PMX_UART4_PL_40_VAL (0x2 << 0)
  181. #define PMX_PWM3_PL_40_VAL (0x4 << 0)
  182. #define PMX_PL_41_42_MASK (0x3F << 3)
  183. #define PMX_PL_41_MASK (0x7 << 3)
  184. #define PMX_PL_42_MASK (0x7 << 6)
  185. #define PMX_I2S_PL_41_42_VAL 0
  186. #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
  187. #define PMX_PWM2_PL_41_VAL (0x4 << 3)
  188. #define PMX_PWM1_PL_42_VAL (0x4 << 6)
  189. #define PMX_PL_43_MASK (0x7 << 9)
  190. #define PMX_SDHCI_PL_43_VAL 0
  191. #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
  192. #define PMX_PWM0_PL_43_VAL (0x4 << 9)
  193. #define PMX_PL_44_45_MASK (0x3F << 12)
  194. #define PMX_SDHCI_PL_44_45_VAL 0
  195. #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
  196. #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
  197. #define PMX_PL_46_47_MASK (0x3F << 18)
  198. #define PMX_SDHCI_PL_46_47_VAL 0
  199. #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
  200. #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
  201. #define PMX_PL_48_49_MASK (0x3F << 24)
  202. #define PMX_SDHCI_PL_48_49_VAL 0
  203. #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
  204. #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
  205. #define IP_SEL_PAD_50_59_REG 0x00B8
  206. #define PMX_PL_50_51_MASK (0x3F << 0)
  207. #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
  208. #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
  209. #define PMX_PL_50_MASK (0x7 << 0)
  210. #define PMX_PL_51_MASK (0x7 << 3)
  211. #define PMX_SDHCI_PL_50_VAL 0
  212. #define PMX_SDHCI_CD_PL_51_VAL 0
  213. #define PMX_PL_52_53_MASK (0x3F << 6)
  214. #define PMX_FSMC_PL_52_53_VAL 0
  215. #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
  216. #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
  217. #define PMX_PL_54_55_56_MASK (0x1FF << 12)
  218. #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
  219. #define PMX_PL_57_MASK (0x7 << 21)
  220. #define PMX_FSMC_PL_57_VAL 0
  221. #define PMX_PWM3_PL_57_VAL (0x4 << 21)
  222. #define PMX_PL_58_59_MASK (0x3F << 24)
  223. #define PMX_PL_58_MASK (0x7 << 24)
  224. #define PMX_PL_59_MASK (0x7 << 27)
  225. #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
  226. #define PMX_PWM2_PL_58_VAL (0x4 << 24)
  227. #define PMX_PWM1_PL_59_VAL (0x4 << 27)
  228. #define IP_SEL_PAD_60_69_REG 0x00BC
  229. #define PMX_PL_60_MASK (0x7 << 0)
  230. #define PMX_FSMC_PL_60_VAL 0
  231. #define PMX_PWM0_PL_60_VAL (0x4 << 0)
  232. #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
  233. #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
  234. #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
  235. #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
  236. #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
  237. #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
  238. #define PMX_PL_69_MASK (0x7 << 27)
  239. #define PMX_CLCD_PL_69_VAL (0)
  240. #define PMX_EMI_PL_69_VAL (0x2 << 27)
  241. #define PMX_SPP_PL_69_VAL (0x3 << 27)
  242. #define PMX_UART5_PL_69_VAL (0x4 << 27)
  243. #define IP_SEL_PAD_70_79_REG 0x00C0
  244. #define PMX_PL_70_MASK (0x7 << 0)
  245. #define PMX_CLCD_PL_70_VAL (0)
  246. #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
  247. #define PMX_SPP_PL_70_VAL (0x3 << 0)
  248. #define PMX_UART5_PL_70_VAL (0x4 << 0)
  249. #define PMX_PL_71_72_MASK (0x3F << 3)
  250. #define PMX_CLCD_PL_71_72_VAL (0)
  251. #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
  252. #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
  253. #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
  254. #define PMX_PL_73_MASK (0x7 << 9)
  255. #define PMX_CLCD_PL_73_VAL (0)
  256. #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
  257. #define PMX_SPP_PL_73_VAL (0x3 << 9)
  258. #define PMX_UART3_PL_73_VAL (0x4 << 9)
  259. #define PMX_PL_74_MASK (0x7 << 12)
  260. #define PMX_CLCD_PL_74_VAL (0)
  261. #define PMX_EMI_PL_74_VAL (0x2 << 12)
  262. #define PMX_SPP_PL_74_VAL (0x3 << 12)
  263. #define PMX_UART3_PL_74_VAL (0x4 << 12)
  264. #define PMX_PL_75_76_MASK (0x3F << 15)
  265. #define PMX_CLCD_PL_75_76_VAL (0)
  266. #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
  267. #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
  268. #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
  269. #define PMX_PL_77_78_79_MASK (0x1FF << 21)
  270. #define PMX_CLCD_PL_77_78_79_VAL (0)
  271. #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
  272. #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
  273. #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
  274. #define IP_SEL_PAD_80_89_REG 0x00C4
  275. #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
  276. #define PMX_CLCD_PL_80_TO_85_VAL 0
  277. #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
  278. #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
  279. #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
  280. #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
  281. #define PMX_PL_86_87_MASK (0x3F << 18)
  282. #define PMX_PL_86_MASK (0x7 << 18)
  283. #define PMX_PL_87_MASK (0x7 << 21)
  284. #define PMX_CLCD_PL_86_87_VAL 0
  285. #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
  286. #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
  287. #define PMX_PWM3_PL_86_VAL (0x4 << 18)
  288. #define PMX_PWM2_PL_87_VAL (0x4 << 21)
  289. #define PMX_PL_88_89_MASK (0x3F << 24)
  290. #define PMX_CLCD_PL_88_89_VAL 0
  291. #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
  292. #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
  293. #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
  294. #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
  295. #define IP_SEL_PAD_90_99_REG 0x00C8
  296. #define PMX_PL_90_91_MASK (0x3F << 0)
  297. #define PMX_CLCD_PL_90_91_VAL 0
  298. #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
  299. #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
  300. #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
  301. #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
  302. #define PMX_PL_92_93_MASK (0x3F << 6)
  303. #define PMX_CLCD_PL_92_93_VAL 0
  304. #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
  305. #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
  306. #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
  307. #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
  308. #define PMX_PL_94_95_MASK (0x3F << 12)
  309. #define PMX_CLCD_PL_94_95_VAL 0
  310. #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
  311. #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
  312. #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
  313. #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
  314. #define PMX_PL_96_97_MASK (0x3F << 18)
  315. #define PMX_CLCD_PL_96_97_VAL 0
  316. #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
  317. #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
  318. #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
  319. #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
  320. #define PMX_PL_98_MASK (0x7 << 24)
  321. #define PMX_CLCD_PL_98_VAL 0
  322. #define PMX_I2C1_PL_98_VAL (0x2 << 24)
  323. #define PMX_UART3_PL_98_VAL (0x4 << 24)
  324. #define PMX_PL_99_MASK (0x7 << 27)
  325. #define PMX_SDHCI_PL_99_VAL 0
  326. #define PMX_I2C1_PL_99_VAL (0x2 << 27)
  327. #define PMX_UART3_PL_99_VAL (0x4 << 27)
  328. #define IP_SEL_MIX_PAD_REG 0x00CC
  329. #define PMX_PL_100_101_MASK (0x3F << 0)
  330. #define PMX_SDHCI_PL_100_101_VAL 0
  331. #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
  332. #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
  333. #define PMX_SSP1_PORT_94_TO_97_VAL 0
  334. #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
  335. #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
  336. #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
  337. #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
  338. #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
  339. #define PMX_SSP2_PORT_90_TO_93_VAL 0
  340. #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
  341. #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
  342. #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
  343. #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
  344. #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
  345. #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
  346. #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
  347. #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
  348. #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
  349. #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
  350. #define PMX_UART3_PORT_94_VAL 0
  351. #define PMX_UART3_PORT_73_VAL (0x1 << 16)
  352. #define PMX_UART3_PORT_52_VAL (0x2 << 16)
  353. #define PMX_UART3_PORT_41_VAL (0x3 << 16)
  354. #define PMX_UART3_PORT_15_VAL (0x4 << 16)
  355. #define PMX_UART3_PORT_8_VAL (0x5 << 16)
  356. #define PMX_UART3_PORT_99_VAL (0x6 << 16)
  357. #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
  358. #define PMX_UART4_PORT_92_VAL 0
  359. #define PMX_UART4_PORT_71_VAL (0x1 << 19)
  360. #define PMX_UART4_PORT_39_VAL (0x2 << 19)
  361. #define PMX_UART4_PORT_13_VAL (0x3 << 19)
  362. #define PMX_UART4_PORT_6_VAL (0x4 << 19)
  363. #define PMX_UART4_PORT_101_VAL (0x5 << 19)
  364. #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
  365. #define PMX_UART5_PORT_90_VAL 0
  366. #define PMX_UART5_PORT_69_VAL (0x1 << 22)
  367. #define PMX_UART5_PORT_37_VAL (0x2 << 22)
  368. #define PMX_UART5_PORT_4_VAL (0x3 << 22)
  369. #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
  370. #define PMX_UART6_PORT_88_VAL 0
  371. #define PMX_UART6_PORT_2_VAL (0x1 << 24)
  372. #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
  373. #define PMX_I2C1_PORT_8_9_VAL 0
  374. #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
  375. #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
  376. #define PMX_I2C2_PORT_96_97_VAL 0
  377. #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
  378. #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
  379. #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
  380. #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
  381. #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
  382. #define PMX_SDHCI_CD_PORT_12_VAL 0
  383. #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
  384. /* Pad multiplexing for CLCD device */
  385. static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
  386. 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
  387. 97 };
  388. static struct spear_muxreg clcd_muxreg[] = {
  389. {
  390. .reg = IP_SEL_PAD_60_69_REG,
  391. .mask = PMX_PL_69_MASK,
  392. .val = PMX_CLCD_PL_69_VAL,
  393. }, {
  394. .reg = IP_SEL_PAD_70_79_REG,
  395. .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
  396. PMX_PL_74_MASK | PMX_PL_75_76_MASK |
  397. PMX_PL_77_78_79_MASK,
  398. .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
  399. PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
  400. PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
  401. }, {
  402. .reg = IP_SEL_PAD_80_89_REG,
  403. .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
  404. PMX_PL_88_89_MASK,
  405. .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
  406. PMX_CLCD_PL_88_89_VAL,
  407. }, {
  408. .reg = IP_SEL_PAD_90_99_REG,
  409. .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
  410. PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
  411. .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
  412. PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
  413. PMX_CLCD_PL_98_VAL,
  414. },
  415. };
  416. static struct spear_modemux clcd_modemux[] = {
  417. {
  418. .modes = EXTENDED_MODE,
  419. .muxregs = clcd_muxreg,
  420. .nmuxregs = ARRAY_SIZE(clcd_muxreg),
  421. },
  422. };
  423. static struct spear_pingroup clcd_pingroup = {
  424. .name = "clcd_grp",
  425. .pins = clcd_pins,
  426. .npins = ARRAY_SIZE(clcd_pins),
  427. .modemuxs = clcd_modemux,
  428. .nmodemuxs = ARRAY_SIZE(clcd_modemux),
  429. };
  430. static const char *const clcd_grps[] = { "clcd_grp" };
  431. static struct spear_function clcd_function = {
  432. .name = "clcd",
  433. .groups = clcd_grps,
  434. .ngroups = ARRAY_SIZE(clcd_grps),
  435. };
  436. /* Pad multiplexing for EMI (Parallel NOR flash) device */
  437. static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
  438. 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
  439. 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
  440. 93, 94, 95, 96, 97 };
  441. static struct spear_muxreg emi_muxreg[] = {
  442. {
  443. .reg = PMX_CONFIG_REG,
  444. .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
  445. .val = 0,
  446. },
  447. };
  448. static struct spear_muxreg emi_ext_muxreg[] = {
  449. {
  450. .reg = IP_SEL_PAD_40_49_REG,
  451. .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
  452. .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
  453. }, {
  454. .reg = IP_SEL_PAD_50_59_REG,
  455. .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
  456. PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
  457. .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
  458. PMX_FSMC_EMI_PL_54_55_56_VAL |
  459. PMX_FSMC_EMI_PL_58_59_VAL,
  460. }, {
  461. .reg = IP_SEL_PAD_60_69_REG,
  462. .mask = PMX_PL_69_MASK,
  463. .val = PMX_EMI_PL_69_VAL,
  464. }, {
  465. .reg = IP_SEL_PAD_70_79_REG,
  466. .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
  467. PMX_PL_74_MASK | PMX_PL_75_76_MASK |
  468. PMX_PL_77_78_79_MASK,
  469. .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
  470. PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
  471. PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
  472. }, {
  473. .reg = IP_SEL_PAD_80_89_REG,
  474. .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
  475. PMX_PL_88_89_MASK,
  476. .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
  477. PMX_EMI_PL_88_89_VAL,
  478. }, {
  479. .reg = IP_SEL_PAD_90_99_REG,
  480. .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
  481. PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
  482. .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
  483. PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
  484. }, {
  485. .reg = EXT_CTRL_REG,
  486. .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
  487. .val = EMI_FSMC_DYNAMIC_MUX_MASK,
  488. },
  489. };
  490. static struct spear_modemux emi_modemux[] = {
  491. {
  492. .modes = AUTO_EXP_MODE | EXTENDED_MODE,
  493. .muxregs = emi_muxreg,
  494. .nmuxregs = ARRAY_SIZE(emi_muxreg),
  495. }, {
  496. .modes = EXTENDED_MODE,
  497. .muxregs = emi_ext_muxreg,
  498. .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
  499. },
  500. };
  501. static struct spear_pingroup emi_pingroup = {
  502. .name = "emi_grp",
  503. .pins = emi_pins,
  504. .npins = ARRAY_SIZE(emi_pins),
  505. .modemuxs = emi_modemux,
  506. .nmodemuxs = ARRAY_SIZE(emi_modemux),
  507. };
  508. static const char *const emi_grps[] = { "emi_grp" };
  509. static struct spear_function emi_function = {
  510. .name = "emi",
  511. .groups = emi_grps,
  512. .ngroups = ARRAY_SIZE(emi_grps),
  513. };
  514. /* Pad multiplexing for FSMC (NAND flash) device */
  515. static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
  516. 61, 62, 63, 64, 65, 66, 67, 68 };
  517. static struct spear_muxreg fsmc_8bit_muxreg[] = {
  518. {
  519. .reg = IP_SEL_PAD_50_59_REG,
  520. .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
  521. PMX_PL_57_MASK | PMX_PL_58_59_MASK,
  522. .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
  523. PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
  524. }, {
  525. .reg = IP_SEL_PAD_60_69_REG,
  526. .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
  527. PMX_PL_65_TO_68_MASK,
  528. .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
  529. PMX_FSMC_PL_65_TO_68_VAL,
  530. }, {
  531. .reg = EXT_CTRL_REG,
  532. .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
  533. .val = EMI_FSMC_DYNAMIC_MUX_MASK,
  534. },
  535. };
  536. static struct spear_modemux fsmc_8bit_modemux[] = {
  537. {
  538. .modes = EXTENDED_MODE,
  539. .muxregs = fsmc_8bit_muxreg,
  540. .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
  541. },
  542. };
  543. static struct spear_pingroup fsmc_8bit_pingroup = {
  544. .name = "fsmc_8bit_grp",
  545. .pins = fsmc_8bit_pins,
  546. .npins = ARRAY_SIZE(fsmc_8bit_pins),
  547. .modemuxs = fsmc_8bit_modemux,
  548. .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
  549. };
  550. static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
  551. 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
  552. static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
  553. {
  554. .reg = PMX_CONFIG_REG,
  555. .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
  556. .val = 0,
  557. },
  558. };
  559. static struct spear_muxreg fsmc_16bit_muxreg[] = {
  560. {
  561. .reg = IP_SEL_PAD_40_49_REG,
  562. .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
  563. .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
  564. }, {
  565. .reg = IP_SEL_PAD_70_79_REG,
  566. .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
  567. .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
  568. PMX_FSMC_EMI_PL_73_VAL,
  569. }
  570. };
  571. static struct spear_modemux fsmc_16bit_modemux[] = {
  572. {
  573. .modes = EXTENDED_MODE,
  574. .muxregs = fsmc_8bit_muxreg,
  575. .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
  576. }, {
  577. .modes = AUTO_EXP_MODE | EXTENDED_MODE,
  578. .muxregs = fsmc_16bit_autoexp_muxreg,
  579. .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
  580. }, {
  581. .modes = EXTENDED_MODE,
  582. .muxregs = fsmc_16bit_muxreg,
  583. .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
  584. },
  585. };
  586. static struct spear_pingroup fsmc_16bit_pingroup = {
  587. .name = "fsmc_16bit_grp",
  588. .pins = fsmc_16bit_pins,
  589. .npins = ARRAY_SIZE(fsmc_16bit_pins),
  590. .modemuxs = fsmc_16bit_modemux,
  591. .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
  592. };
  593. static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
  594. static struct spear_function fsmc_function = {
  595. .name = "fsmc",
  596. .groups = fsmc_grps,
  597. .ngroups = ARRAY_SIZE(fsmc_grps),
  598. };
  599. /* Pad multiplexing for SPP device */
  600. static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
  601. 80, 81, 82, 83, 84, 85 };
  602. static struct spear_muxreg spp_muxreg[] = {
  603. {
  604. .reg = IP_SEL_PAD_60_69_REG,
  605. .mask = PMX_PL_69_MASK,
  606. .val = PMX_SPP_PL_69_VAL,
  607. }, {
  608. .reg = IP_SEL_PAD_70_79_REG,
  609. .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
  610. PMX_PL_74_MASK | PMX_PL_75_76_MASK |
  611. PMX_PL_77_78_79_MASK,
  612. .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
  613. PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
  614. PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
  615. }, {
  616. .reg = IP_SEL_PAD_80_89_REG,
  617. .mask = PMX_PL_80_TO_85_MASK,
  618. .val = PMX_SPP_PL_80_TO_85_VAL,
  619. },
  620. };
  621. static struct spear_modemux spp_modemux[] = {
  622. {
  623. .modes = EXTENDED_MODE,
  624. .muxregs = spp_muxreg,
  625. .nmuxregs = ARRAY_SIZE(spp_muxreg),
  626. },
  627. };
  628. static struct spear_pingroup spp_pingroup = {
  629. .name = "spp_grp",
  630. .pins = spp_pins,
  631. .npins = ARRAY_SIZE(spp_pins),
  632. .modemuxs = spp_modemux,
  633. .nmodemuxs = ARRAY_SIZE(spp_modemux),
  634. };
  635. static const char *const spp_grps[] = { "spp_grp" };
  636. static struct spear_function spp_function = {
  637. .name = "spp",
  638. .groups = spp_grps,
  639. .ngroups = ARRAY_SIZE(spp_grps),
  640. };
  641. /* Pad multiplexing for SDHCI device */
  642. static const unsigned sdhci_led_pins[] = { 34 };
  643. static struct spear_muxreg sdhci_led_muxreg[] = {
  644. {
  645. .reg = PMX_CONFIG_REG,
  646. .mask = PMX_SSP_CS_MASK,
  647. .val = 0,
  648. },
  649. };
  650. static struct spear_muxreg sdhci_led_ext_muxreg[] = {
  651. {
  652. .reg = IP_SEL_PAD_30_39_REG,
  653. .mask = PMX_PL_34_MASK,
  654. .val = PMX_PWM2_PL_34_VAL,
  655. },
  656. };
  657. static struct spear_modemux sdhci_led_modemux[] = {
  658. {
  659. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
  660. .muxregs = sdhci_led_muxreg,
  661. .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
  662. }, {
  663. .modes = EXTENDED_MODE,
  664. .muxregs = sdhci_led_ext_muxreg,
  665. .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
  666. },
  667. };
  668. static struct spear_pingroup sdhci_led_pingroup = {
  669. .name = "sdhci_led_grp",
  670. .pins = sdhci_led_pins,
  671. .npins = ARRAY_SIZE(sdhci_led_pins),
  672. .modemuxs = sdhci_led_modemux,
  673. .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
  674. };
  675. static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
  676. 50};
  677. static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
  678. };
  679. static struct spear_muxreg sdhci_muxreg[] = {
  680. {
  681. .reg = PMX_CONFIG_REG,
  682. .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
  683. .val = 0,
  684. },
  685. };
  686. static struct spear_muxreg sdhci_ext_muxreg[] = {
  687. {
  688. .reg = IP_SEL_PAD_40_49_REG,
  689. .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
  690. PMX_PL_48_49_MASK,
  691. .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
  692. PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
  693. }, {
  694. .reg = IP_SEL_PAD_50_59_REG,
  695. .mask = PMX_PL_50_MASK,
  696. .val = PMX_SDHCI_PL_50_VAL,
  697. }, {
  698. .reg = IP_SEL_PAD_90_99_REG,
  699. .mask = PMX_PL_99_MASK,
  700. .val = PMX_SDHCI_PL_99_VAL,
  701. }, {
  702. .reg = IP_SEL_MIX_PAD_REG,
  703. .mask = PMX_PL_100_101_MASK,
  704. .val = PMX_SDHCI_PL_100_101_VAL,
  705. },
  706. };
  707. static struct spear_muxreg sdhci_cd_12_muxreg[] = {
  708. {
  709. .reg = PMX_CONFIG_REG,
  710. .mask = PMX_MII_MASK,
  711. .val = 0,
  712. }, {
  713. .reg = IP_SEL_PAD_10_19_REG,
  714. .mask = PMX_PL_12_MASK,
  715. .val = PMX_SDHCI_CD_PL_12_VAL,
  716. }, {
  717. .reg = IP_SEL_MIX_PAD_REG,
  718. .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
  719. .val = PMX_SDHCI_CD_PORT_12_VAL,
  720. },
  721. };
  722. static struct spear_muxreg sdhci_cd_51_muxreg[] = {
  723. {
  724. .reg = IP_SEL_PAD_50_59_REG,
  725. .mask = PMX_PL_51_MASK,
  726. .val = PMX_SDHCI_CD_PL_51_VAL,
  727. }, {
  728. .reg = IP_SEL_MIX_PAD_REG,
  729. .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
  730. .val = PMX_SDHCI_CD_PORT_51_VAL,
  731. },
  732. };
  733. #define pmx_sdhci_common_modemux \
  734. { \
  735. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
  736. SMALL_PRINTERS_MODE | EXTENDED_MODE, \
  737. .muxregs = sdhci_muxreg, \
  738. .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
  739. }, { \
  740. .modes = EXTENDED_MODE, \
  741. .muxregs = sdhci_ext_muxreg, \
  742. .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
  743. }
  744. static struct spear_modemux sdhci_modemux[][3] = {
  745. {
  746. /* select pin 12 for cd */
  747. pmx_sdhci_common_modemux,
  748. {
  749. .modes = EXTENDED_MODE,
  750. .muxregs = sdhci_cd_12_muxreg,
  751. .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
  752. },
  753. }, {
  754. /* select pin 51 for cd */
  755. pmx_sdhci_common_modemux,
  756. {
  757. .modes = EXTENDED_MODE,
  758. .muxregs = sdhci_cd_51_muxreg,
  759. .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
  760. },
  761. }
  762. };
  763. static struct spear_pingroup sdhci_pingroup[] = {
  764. {
  765. .name = "sdhci_cd_12_grp",
  766. .pins = sdhci_cd_12_pins,
  767. .npins = ARRAY_SIZE(sdhci_cd_12_pins),
  768. .modemuxs = sdhci_modemux[0],
  769. .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
  770. }, {
  771. .name = "sdhci_cd_51_grp",
  772. .pins = sdhci_cd_51_pins,
  773. .npins = ARRAY_SIZE(sdhci_cd_51_pins),
  774. .modemuxs = sdhci_modemux[1],
  775. .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
  776. },
  777. };
  778. static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
  779. "sdhci_led_grp" };
  780. static struct spear_function sdhci_function = {
  781. .name = "sdhci",
  782. .groups = sdhci_grps,
  783. .ngroups = ARRAY_SIZE(sdhci_grps),
  784. };
  785. /* Pad multiplexing for I2S device */
  786. static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
  787. static struct spear_muxreg i2s_muxreg[] = {
  788. {
  789. .reg = PMX_CONFIG_REG,
  790. .mask = PMX_SSP_CS_MASK,
  791. .val = 0,
  792. }, {
  793. .reg = PMX_CONFIG_REG,
  794. .mask = PMX_UART0_MODEM_MASK,
  795. .val = 0,
  796. },
  797. };
  798. static struct spear_muxreg i2s_ext_muxreg[] = {
  799. {
  800. .reg = IP_SEL_PAD_30_39_REG,
  801. .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
  802. .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
  803. }, {
  804. .reg = IP_SEL_PAD_40_49_REG,
  805. .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
  806. .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
  807. },
  808. };
  809. static struct spear_modemux i2s_modemux[] = {
  810. {
  811. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
  812. .muxregs = i2s_muxreg,
  813. .nmuxregs = ARRAY_SIZE(i2s_muxreg),
  814. }, {
  815. .modes = EXTENDED_MODE,
  816. .muxregs = i2s_ext_muxreg,
  817. .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
  818. },
  819. };
  820. static struct spear_pingroup i2s_pingroup = {
  821. .name = "i2s_grp",
  822. .pins = i2s_pins,
  823. .npins = ARRAY_SIZE(i2s_pins),
  824. .modemuxs = i2s_modemux,
  825. .nmodemuxs = ARRAY_SIZE(i2s_modemux),
  826. };
  827. static const char *const i2s_grps[] = { "i2s_grp" };
  828. static struct spear_function i2s_function = {
  829. .name = "i2s",
  830. .groups = i2s_grps,
  831. .ngroups = ARRAY_SIZE(i2s_grps),
  832. };
  833. /* Pad multiplexing for UART1 device */
  834. static const unsigned uart1_pins[] = { 28, 29 };
  835. static struct spear_muxreg uart1_muxreg[] = {
  836. {
  837. .reg = PMX_CONFIG_REG,
  838. .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
  839. .val = 0,
  840. },
  841. };
  842. static struct spear_muxreg uart1_ext_muxreg[] = {
  843. {
  844. .reg = IP_SEL_PAD_20_29_REG,
  845. .mask = PMX_PL_28_29_MASK,
  846. .val = PMX_UART1_PL_28_29_VAL,
  847. },
  848. };
  849. static struct spear_modemux uart1_modemux[] = {
  850. {
  851. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
  852. | SMALL_PRINTERS_MODE | EXTENDED_MODE,
  853. .muxregs = uart1_muxreg,
  854. .nmuxregs = ARRAY_SIZE(uart1_muxreg),
  855. }, {
  856. .modes = EXTENDED_MODE,
  857. .muxregs = uart1_ext_muxreg,
  858. .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
  859. },
  860. };
  861. static struct spear_pingroup uart1_pingroup = {
  862. .name = "uart1_grp",
  863. .pins = uart1_pins,
  864. .npins = ARRAY_SIZE(uart1_pins),
  865. .modemuxs = uart1_modemux,
  866. .nmodemuxs = ARRAY_SIZE(uart1_modemux),
  867. };
  868. static const char *const uart1_grps[] = { "uart1_grp" };
  869. static struct spear_function uart1_function = {
  870. .name = "uart1",
  871. .groups = uart1_grps,
  872. .ngroups = ARRAY_SIZE(uart1_grps),
  873. };
  874. /* Pad multiplexing for UART1 Modem device */
  875. static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
  876. static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
  877. static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
  878. static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
  879. static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
  880. {
  881. .reg = PMX_CONFIG_REG,
  882. .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
  883. .val = 0,
  884. }, {
  885. .reg = IP_SEL_PAD_0_9_REG,
  886. .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
  887. .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
  888. PMX_UART1_ENH_PL_6_7_VAL,
  889. }, {
  890. .reg = IP_SEL_MIX_PAD_REG,
  891. .mask = PMX_UART1_ENH_PORT_SEL_MASK,
  892. .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
  893. },
  894. };
  895. static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
  896. {
  897. .reg = PMX_CONFIG_REG,
  898. .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
  899. PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
  900. .val = 0,
  901. },
  902. };
  903. static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
  904. {
  905. .reg = IP_SEL_PAD_30_39_REG,
  906. .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
  907. PMX_PL_35_MASK | PMX_PL_36_MASK,
  908. .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
  909. PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
  910. PMX_UART1_ENH_PL_36_VAL,
  911. }, {
  912. .reg = IP_SEL_MIX_PAD_REG,
  913. .mask = PMX_UART1_ENH_PORT_SEL_MASK,
  914. .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
  915. },
  916. };
  917. static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
  918. {
  919. .reg = PMX_CONFIG_REG,
  920. .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
  921. PMX_SSP_CS_MASK,
  922. .val = 0,
  923. },
  924. };
  925. static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
  926. {
  927. .reg = IP_SEL_PAD_30_39_REG,
  928. .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
  929. .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
  930. PMX_UART1_ENH_PL_36_VAL,
  931. }, {
  932. .reg = IP_SEL_PAD_40_49_REG,
  933. .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
  934. .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
  935. }, {
  936. .reg = IP_SEL_MIX_PAD_REG,
  937. .mask = PMX_UART1_ENH_PORT_SEL_MASK,
  938. .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
  939. },
  940. };
  941. static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
  942. {
  943. .reg = IP_SEL_PAD_80_89_REG,
  944. .mask = PMX_PL_80_TO_85_MASK,
  945. .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
  946. }, {
  947. .reg = IP_SEL_PAD_40_49_REG,
  948. .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
  949. .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
  950. }, {
  951. .reg = IP_SEL_MIX_PAD_REG,
  952. .mask = PMX_UART1_ENH_PORT_SEL_MASK,
  953. .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
  954. },
  955. };
  956. static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
  957. {
  958. .modes = EXTENDED_MODE,
  959. .muxregs = uart1_modem_ext_2_to_7_muxreg,
  960. .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
  961. },
  962. };
  963. static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
  964. {
  965. .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
  966. .muxregs = uart1_modem_31_to_36_muxreg,
  967. .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
  968. }, {
  969. .modes = EXTENDED_MODE,
  970. .muxregs = uart1_modem_ext_31_to_36_muxreg,
  971. .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
  972. },
  973. };
  974. static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
  975. {
  976. .modes = AUTO_EXP_MODE | EXTENDED_MODE,
  977. .muxregs = uart1_modem_34_to_45_muxreg,
  978. .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
  979. }, {
  980. .modes = EXTENDED_MODE,
  981. .muxregs = uart1_modem_ext_34_to_45_muxreg,
  982. .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
  983. },
  984. };
  985. static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
  986. {
  987. .modes = EXTENDED_MODE,
  988. .muxregs = uart1_modem_ext_80_to_85_muxreg,
  989. .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
  990. },
  991. };
  992. static struct spear_pingroup uart1_modem_pingroup[] = {
  993. {
  994. .name = "uart1_modem_2_to_7_grp",
  995. .pins = uart1_modem_2_to_7_pins,
  996. .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
  997. .modemuxs = uart1_modem_2_to_7_modemux,
  998. .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
  999. }, {
  1000. .name = "uart1_modem_31_to_36_grp",
  1001. .pins = uart1_modem_31_to_36_pins,
  1002. .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
  1003. .modemuxs = uart1_modem_31_to_36_modemux,
  1004. .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
  1005. }, {
  1006. .name = "uart1_modem_34_to_45_grp",
  1007. .pins = uart1_modem_34_to_45_pins,
  1008. .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
  1009. .modemuxs = uart1_modem_34_to_45_modemux,
  1010. .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
  1011. }, {
  1012. .name = "uart1_modem_80_to_85_grp",
  1013. .pins = uart1_modem_80_to_85_pins,
  1014. .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
  1015. .modemuxs = uart1_modem_80_to_85_modemux,
  1016. .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
  1017. },
  1018. };
  1019. static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
  1020. "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
  1021. "uart1_modem_80_to_85_grp" };
  1022. static struct spear_function uart1_modem_function = {
  1023. .name = "uart1_modem",
  1024. .groups = uart1_modem_grps,
  1025. .ngroups = ARRAY_SIZE(uart1_modem_grps),
  1026. };
  1027. /* Pad multiplexing for UART2 device */
  1028. static const unsigned uart2_pins[] = { 0, 1 };
  1029. static struct spear_muxreg uart2_muxreg[] = {
  1030. {
  1031. .reg = PMX_CONFIG_REG,
  1032. .mask = PMX_FIRDA_MASK,
  1033. .val = 0,
  1034. },
  1035. };
  1036. static struct spear_muxreg uart2_ext_muxreg[] = {
  1037. {
  1038. .reg = IP_SEL_PAD_0_9_REG,
  1039. .mask = PMX_PL_0_1_MASK,
  1040. .val = PMX_UART2_PL_0_1_VAL,
  1041. },
  1042. };
  1043. static struct spear_modemux uart2_modemux[] = {
  1044. {
  1045. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
  1046. | SMALL_PRINTERS_MODE | EXTENDED_MODE,
  1047. .muxregs = uart2_muxreg,
  1048. .nmuxregs = ARRAY_SIZE(uart2_muxreg),
  1049. }, {
  1050. .modes = EXTENDED_MODE,
  1051. .muxregs = uart2_ext_muxreg,
  1052. .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
  1053. },
  1054. };
  1055. static struct spear_pingroup uart2_pingroup = {
  1056. .name = "uart2_grp",
  1057. .pins = uart2_pins,
  1058. .npins = ARRAY_SIZE(uart2_pins),
  1059. .modemuxs = uart2_modemux,
  1060. .nmodemuxs = ARRAY_SIZE(uart2_modemux),
  1061. };
  1062. static const char *const uart2_grps[] = { "uart2_grp" };
  1063. static struct spear_function uart2_function = {
  1064. .name = "uart2",
  1065. .groups = uart2_grps,
  1066. .ngroups = ARRAY_SIZE(uart2_grps),
  1067. };
  1068. /* Pad multiplexing for uart3 device */
  1069. static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
  1070. { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
  1071. static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
  1072. {
  1073. .reg = PMX_CONFIG_REG,
  1074. .mask = PMX_SSP_MASK,
  1075. .val = 0,
  1076. }, {
  1077. .reg = IP_SEL_PAD_0_9_REG,
  1078. .mask = PMX_PL_8_9_MASK,
  1079. .val = PMX_UART3_PL_8_9_VAL,
  1080. }, {
  1081. .reg = IP_SEL_MIX_PAD_REG,
  1082. .mask = PMX_UART3_PORT_SEL_MASK,
  1083. .val = PMX_UART3_PORT_8_VAL,
  1084. },
  1085. };
  1086. static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
  1087. {
  1088. .reg = PMX_CONFIG_REG,
  1089. .mask = PMX_MII_MASK,
  1090. .val = 0,
  1091. }, {
  1092. .reg = IP_SEL_PAD_10_19_REG,
  1093. .mask = PMX_PL_15_16_MASK,
  1094. .val = PMX_UART3_PL_15_16_VAL,
  1095. }, {
  1096. .reg = IP_SEL_MIX_PAD_REG,
  1097. .mask = PMX_UART3_PORT_SEL_MASK,
  1098. .val = PMX_UART3_PORT_15_VAL,
  1099. },
  1100. };
  1101. static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
  1102. {
  1103. .reg = PMX_CONFIG_REG,
  1104. .mask = PMX_UART0_MODEM_MASK,
  1105. .val = 0,
  1106. }, {
  1107. .reg = IP_SEL_PAD_40_49_REG,
  1108. .mask = PMX_PL_41_42_MASK,
  1109. .val = PMX_UART3_PL_41_42_VAL,
  1110. }, {
  1111. .reg = IP_SEL_MIX_PAD_REG,
  1112. .mask = PMX_UART3_PORT_SEL_MASK,
  1113. .val = PMX_UART3_PORT_41_VAL,
  1114. },
  1115. };
  1116. static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
  1117. {
  1118. .reg = IP_SEL_PAD_50_59_REG,
  1119. .mask = PMX_PL_52_53_MASK,
  1120. .val = PMX_UART3_PL_52_53_VAL,
  1121. }, {
  1122. .reg = IP_SEL_MIX_PAD_REG,
  1123. .mask = PMX_UART3_PORT_SEL_MASK,
  1124. .val = PMX_UART3_PORT_52_VAL,
  1125. },
  1126. };
  1127. static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
  1128. {
  1129. .reg = IP_SEL_PAD_70_79_REG,
  1130. .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
  1131. .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
  1132. }, {
  1133. .reg = IP_SEL_MIX_PAD_REG,
  1134. .mask = PMX_UART3_PORT_SEL_MASK,
  1135. .val = PMX_UART3_PORT_73_VAL,
  1136. },
  1137. };
  1138. static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
  1139. {
  1140. .reg = IP_SEL_PAD_90_99_REG,
  1141. .mask = PMX_PL_94_95_MASK,
  1142. .val = PMX_UART3_PL_94_95_VAL,
  1143. }, {
  1144. .reg = IP_SEL_MIX_PAD_REG,
  1145. .mask = PMX_UART3_PORT_SEL_MASK,
  1146. .val = PMX_UART3_PORT_94_VAL,
  1147. },
  1148. };
  1149. static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
  1150. {
  1151. .reg = IP_SEL_PAD_90_99_REG,
  1152. .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
  1153. .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
  1154. }, {
  1155. .reg = IP_SEL_MIX_PAD_REG,
  1156. .mask = PMX_UART3_PORT_SEL_MASK,
  1157. .val = PMX_UART3_PORT_99_VAL,
  1158. },
  1159. };
  1160. static struct spear_modemux uart3_modemux[][1] = {
  1161. {
  1162. /* Select signals on pins 8_9 */
  1163. {
  1164. .modes = EXTENDED_MODE,
  1165. .muxregs = uart3_ext_8_9_muxreg,
  1166. .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
  1167. },
  1168. }, {
  1169. /* Select signals on pins 15_16 */
  1170. {
  1171. .modes = EXTENDED_MODE,
  1172. .muxregs = uart3_ext_15_16_muxreg,
  1173. .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
  1174. },
  1175. }, {
  1176. /* Select signals on pins 41_42 */
  1177. {
  1178. .modes = EXTENDED_MODE,
  1179. .muxregs = uart3_ext_41_42_muxreg,
  1180. .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
  1181. },
  1182. }, {
  1183. /* Select signals on pins 52_53 */
  1184. {
  1185. .modes = EXTENDED_MODE,
  1186. .muxregs = uart3_ext_52_53_muxreg,
  1187. .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
  1188. },
  1189. }, {
  1190. /* Select signals on pins 73_74 */
  1191. {
  1192. .modes = EXTENDED_MODE,
  1193. .muxregs = uart3_ext_73_74_muxreg,
  1194. .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
  1195. },
  1196. }, {
  1197. /* Select signals on pins 94_95 */
  1198. {
  1199. .modes = EXTENDED_MODE,
  1200. .muxregs = uart3_ext_94_95_muxreg,
  1201. .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
  1202. },
  1203. }, {
  1204. /* Select signals on pins 98_99 */
  1205. {
  1206. .modes = EXTENDED_MODE,
  1207. .muxregs = uart3_ext_98_99_muxreg,
  1208. .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
  1209. },
  1210. },
  1211. };
  1212. static struct spear_pingroup uart3_pingroup[] = {
  1213. {
  1214. .name = "uart3_8_9_grp",
  1215. .pins = uart3_pins[0],
  1216. .npins = ARRAY_SIZE(uart3_pins[0]),
  1217. .modemuxs = uart3_modemux[0],
  1218. .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
  1219. }, {
  1220. .name = "uart3_15_16_grp",
  1221. .pins = uart3_pins[1],
  1222. .npins = ARRAY_SIZE(uart3_pins[1]),
  1223. .modemuxs = uart3_modemux[1],
  1224. .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
  1225. }, {
  1226. .name = "uart3_41_42_grp",
  1227. .pins = uart3_pins[2],
  1228. .npins = ARRAY_SIZE(uart3_pins[2]),
  1229. .modemuxs = uart3_modemux[2],
  1230. .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
  1231. }, {
  1232. .name = "uart3_52_53_grp",
  1233. .pins = uart3_pins[3],
  1234. .npins = ARRAY_SIZE(uart3_pins[3]),
  1235. .modemuxs = uart3_modemux[3],
  1236. .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
  1237. }, {
  1238. .name = "uart3_73_74_grp",
  1239. .pins = uart3_pins[4],
  1240. .npins = ARRAY_SIZE(uart3_pins[4]),
  1241. .modemuxs = uart3_modemux[4],
  1242. .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
  1243. }, {
  1244. .name = "uart3_94_95_grp",
  1245. .pins = uart3_pins[5],
  1246. .npins = ARRAY_SIZE(uart3_pins[5]),
  1247. .modemuxs = uart3_modemux[5],
  1248. .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
  1249. }, {
  1250. .name = "uart3_98_99_grp",
  1251. .pins = uart3_pins[6],
  1252. .npins = ARRAY_SIZE(uart3_pins[6]),
  1253. .modemuxs = uart3_modemux[6],
  1254. .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
  1255. },
  1256. };
  1257. static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
  1258. "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
  1259. "uart3_94_95_grp", "uart3_98_99_grp" };
  1260. static struct spear_function uart3_function = {
  1261. .name = "uart3",
  1262. .groups = uart3_grps,
  1263. .ngroups = ARRAY_SIZE(uart3_grps),
  1264. };
  1265. /* Pad multiplexing for uart4 device */
  1266. static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
  1267. { 71, 72 }, { 92, 93 }, { 100, 101 } };
  1268. static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
  1269. {
  1270. .reg = PMX_CONFIG_REG,
  1271. .mask = PMX_SSP_MASK,
  1272. .val = 0,
  1273. }, {
  1274. .reg = IP_SEL_PAD_0_9_REG,
  1275. .mask = PMX_PL_6_7_MASK,
  1276. .val = PMX_UART4_PL_6_7_VAL,
  1277. }, {
  1278. .reg = IP_SEL_MIX_PAD_REG,
  1279. .mask = PMX_UART4_PORT_SEL_MASK,
  1280. .val = PMX_UART4_PORT_6_VAL,
  1281. },
  1282. };
  1283. static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
  1284. {
  1285. .reg = PMX_CONFIG_REG,
  1286. .mask = PMX_MII_MASK,
  1287. .val = 0,
  1288. }, {
  1289. .reg = IP_SEL_PAD_10_19_REG,
  1290. .mask = PMX_PL_13_14_MASK,
  1291. .val = PMX_UART4_PL_13_14_VAL,
  1292. }, {
  1293. .reg = IP_SEL_MIX_PAD_REG,
  1294. .mask = PMX_UART4_PORT_SEL_MASK,
  1295. .val = PMX_UART4_PORT_13_VAL,
  1296. },
  1297. };
  1298. static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
  1299. {
  1300. .reg = PMX_CONFIG_REG,
  1301. .mask = PMX_UART0_MODEM_MASK,
  1302. .val = 0,
  1303. }, {
  1304. .reg = IP_SEL_PAD_30_39_REG,
  1305. .mask = PMX_PL_39_MASK,
  1306. .val = PMX_UART4_PL_39_VAL,
  1307. }, {
  1308. .reg = IP_SEL_PAD_40_49_REG,
  1309. .mask = PMX_PL_40_MASK,
  1310. .val = PMX_UART4_PL_40_VAL,
  1311. }, {
  1312. .reg = IP_SEL_MIX_PAD_REG,
  1313. .mask = PMX_UART4_PORT_SEL_MASK,
  1314. .val = PMX_UART4_PORT_39_VAL,
  1315. },
  1316. };
  1317. static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
  1318. {
  1319. .reg = IP_SEL_PAD_70_79_REG,
  1320. .mask = PMX_PL_71_72_MASK,
  1321. .val = PMX_UART4_PL_71_72_VAL,
  1322. }, {
  1323. .reg = IP_SEL_MIX_PAD_REG,
  1324. .mask = PMX_UART4_PORT_SEL_MASK,
  1325. .val = PMX_UART4_PORT_71_VAL,
  1326. },
  1327. };
  1328. static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
  1329. {
  1330. .reg = IP_SEL_PAD_90_99_REG,
  1331. .mask = PMX_PL_92_93_MASK,
  1332. .val = PMX_UART4_PL_92_93_VAL,
  1333. }, {
  1334. .reg = IP_SEL_MIX_PAD_REG,
  1335. .mask = PMX_UART4_PORT_SEL_MASK,
  1336. .val = PMX_UART4_PORT_92_VAL,
  1337. },
  1338. };
  1339. static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
  1340. {
  1341. .reg = IP_SEL_MIX_PAD_REG,
  1342. .mask = PMX_PL_100_101_MASK |
  1343. PMX_UART4_PORT_SEL_MASK,
  1344. .val = PMX_UART4_PL_100_101_VAL |
  1345. PMX_UART4_PORT_101_VAL,
  1346. },
  1347. };
  1348. static struct spear_modemux uart4_modemux[][1] = {
  1349. {
  1350. /* Select signals on pins 6_7 */
  1351. {
  1352. .modes = EXTENDED_MODE,
  1353. .muxregs = uart4_ext_6_7_muxreg,
  1354. .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
  1355. },
  1356. }, {
  1357. /* Select signals on pins 13_14 */
  1358. {
  1359. .modes = EXTENDED_MODE,
  1360. .muxregs = uart4_ext_13_14_muxreg,
  1361. .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
  1362. },
  1363. }, {
  1364. /* Select signals on pins 39_40 */
  1365. {
  1366. .modes = EXTENDED_MODE,
  1367. .muxregs = uart4_ext_39_40_muxreg,
  1368. .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
  1369. },
  1370. }, {
  1371. /* Select signals on pins 71_72 */
  1372. {
  1373. .modes = EXTENDED_MODE,
  1374. .muxregs = uart4_ext_71_72_muxreg,
  1375. .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
  1376. },
  1377. }, {
  1378. /* Select signals on pins 92_93 */
  1379. {
  1380. .modes = EXTENDED_MODE,
  1381. .muxregs = uart4_ext_92_93_muxreg,
  1382. .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
  1383. },
  1384. }, {
  1385. /* Select signals on pins 100_101_ */
  1386. {
  1387. .modes = EXTENDED_MODE,
  1388. .muxregs = uart4_ext_100_101_muxreg,
  1389. .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
  1390. },
  1391. },
  1392. };
  1393. static struct spear_pingroup uart4_pingroup[] = {
  1394. {
  1395. .name = "uart4_6_7_grp",
  1396. .pins = uart4_pins[0],
  1397. .npins = ARRAY_SIZE(uart4_pins[0]),
  1398. .modemuxs = uart4_modemux[0],
  1399. .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
  1400. }, {
  1401. .name = "uart4_13_14_grp",
  1402. .pins = uart4_pins[1],
  1403. .npins = ARRAY_SIZE(uart4_pins[1]),
  1404. .modemuxs = uart4_modemux[1],
  1405. .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
  1406. }, {
  1407. .name = "uart4_39_40_grp",
  1408. .pins = uart4_pins[2],
  1409. .npins = ARRAY_SIZE(uart4_pins[2]),
  1410. .modemuxs = uart4_modemux[2],
  1411. .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
  1412. }, {
  1413. .name = "uart4_71_72_grp",
  1414. .pins = uart4_pins[3],
  1415. .npins = ARRAY_SIZE(uart4_pins[3]),
  1416. .modemuxs = uart4_modemux[3],
  1417. .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
  1418. }, {
  1419. .name = "uart4_92_93_grp",
  1420. .pins = uart4_pins[4],
  1421. .npins = ARRAY_SIZE(uart4_pins[4]),
  1422. .modemuxs = uart4_modemux[4],
  1423. .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
  1424. }, {
  1425. .name = "uart4_100_101_grp",
  1426. .pins = uart4_pins[5],
  1427. .npins = ARRAY_SIZE(uart4_pins[5]),
  1428. .modemuxs = uart4_modemux[5],
  1429. .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
  1430. },
  1431. };
  1432. static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
  1433. "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
  1434. "uart4_100_101_grp" };
  1435. static struct spear_function uart4_function = {
  1436. .name = "uart4",
  1437. .groups = uart4_grps,
  1438. .ngroups = ARRAY_SIZE(uart4_grps),
  1439. };
  1440. /* Pad multiplexing for uart5 device */
  1441. static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
  1442. { 90, 91 } };
  1443. static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
  1444. {
  1445. .reg = PMX_CONFIG_REG,
  1446. .mask = PMX_I2C_MASK,
  1447. .val = 0,
  1448. }, {
  1449. .reg = IP_SEL_PAD_0_9_REG,
  1450. .mask = PMX_PL_4_5_MASK,
  1451. .val = PMX_UART5_PL_4_5_VAL,
  1452. }, {
  1453. .reg = IP_SEL_MIX_PAD_REG,
  1454. .mask = PMX_UART5_PORT_SEL_MASK,
  1455. .val = PMX_UART5_PORT_4_VAL,
  1456. },
  1457. };
  1458. static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
  1459. {
  1460. .reg = PMX_CONFIG_REG,
  1461. .mask = PMX_UART0_MODEM_MASK,
  1462. .val = 0,
  1463. }, {
  1464. .reg = IP_SEL_PAD_30_39_REG,
  1465. .mask = PMX_PL_37_38_MASK,
  1466. .val = PMX_UART5_PL_37_38_VAL,
  1467. }, {
  1468. .reg = IP_SEL_MIX_PAD_REG,
  1469. .mask = PMX_UART5_PORT_SEL_MASK,
  1470. .val = PMX_UART5_PORT_37_VAL,
  1471. },
  1472. };
  1473. static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
  1474. {
  1475. .reg = IP_SEL_PAD_60_69_REG,
  1476. .mask = PMX_PL_69_MASK,
  1477. .val = PMX_UART5_PL_69_VAL,
  1478. }, {
  1479. .reg = IP_SEL_PAD_70_79_REG,
  1480. .mask = PMX_PL_70_MASK,
  1481. .val = PMX_UART5_PL_70_VAL,
  1482. }, {
  1483. .reg = IP_SEL_MIX_PAD_REG,
  1484. .mask = PMX_UART5_PORT_SEL_MASK,
  1485. .val = PMX_UART5_PORT_69_VAL,
  1486. },
  1487. };
  1488. static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
  1489. {
  1490. .reg = IP_SEL_PAD_90_99_REG,
  1491. .mask = PMX_PL_90_91_MASK,
  1492. .val = PMX_UART5_PL_90_91_VAL,
  1493. }, {
  1494. .reg = IP_SEL_MIX_PAD_REG,
  1495. .mask = PMX_UART5_PORT_SEL_MASK,
  1496. .val = PMX_UART5_PORT_90_VAL,
  1497. },
  1498. };
  1499. static struct spear_modemux uart5_modemux[][1] = {
  1500. {
  1501. /* Select signals on pins 4_5 */
  1502. {
  1503. .modes = EXTENDED_MODE,
  1504. .muxregs = uart5_ext_4_5_muxreg,
  1505. .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
  1506. },
  1507. }, {
  1508. /* Select signals on pins 37_38 */
  1509. {
  1510. .modes = EXTENDED_MODE,
  1511. .muxregs = uart5_ext_37_38_muxreg,
  1512. .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
  1513. },
  1514. }, {
  1515. /* Select signals on pins 69_70 */
  1516. {
  1517. .modes = EXTENDED_MODE,
  1518. .muxregs = uart5_ext_69_70_muxreg,
  1519. .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
  1520. },
  1521. }, {
  1522. /* Select signals on pins 90_91 */
  1523. {
  1524. .modes = EXTENDED_MODE,
  1525. .muxregs = uart5_ext_90_91_muxreg,
  1526. .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
  1527. },
  1528. },
  1529. };
  1530. static struct spear_pingroup uart5_pingroup[] = {
  1531. {
  1532. .name = "uart5_4_5_grp",
  1533. .pins = uart5_pins[0],
  1534. .npins = ARRAY_SIZE(uart5_pins[0]),
  1535. .modemuxs = uart5_modemux[0],
  1536. .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
  1537. }, {
  1538. .name = "uart5_37_38_grp",
  1539. .pins = uart5_pins[1],
  1540. .npins = ARRAY_SIZE(uart5_pins[1]),
  1541. .modemuxs = uart5_modemux[1],
  1542. .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
  1543. }, {
  1544. .name = "uart5_69_70_grp",
  1545. .pins = uart5_pins[2],
  1546. .npins = ARRAY_SIZE(uart5_pins[2]),
  1547. .modemuxs = uart5_modemux[2],
  1548. .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
  1549. }, {
  1550. .name = "uart5_90_91_grp",
  1551. .pins = uart5_pins[3],
  1552. .npins = ARRAY_SIZE(uart5_pins[3]),
  1553. .modemuxs = uart5_modemux[3],
  1554. .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
  1555. },
  1556. };
  1557. static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
  1558. "uart5_69_70_grp", "uart5_90_91_grp" };
  1559. static struct spear_function uart5_function = {
  1560. .name = "uart5",
  1561. .groups = uart5_grps,
  1562. .ngroups = ARRAY_SIZE(uart5_grps),
  1563. };
  1564. /* Pad multiplexing for uart6 device */
  1565. static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
  1566. static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
  1567. {
  1568. .reg = PMX_CONFIG_REG,
  1569. .mask = PMX_UART0_MASK,
  1570. .val = 0,
  1571. }, {
  1572. .reg = IP_SEL_PAD_0_9_REG,
  1573. .mask = PMX_PL_2_3_MASK,
  1574. .val = PMX_UART6_PL_2_3_VAL,
  1575. }, {
  1576. .reg = IP_SEL_MIX_PAD_REG,
  1577. .mask = PMX_UART6_PORT_SEL_MASK,
  1578. .val = PMX_UART6_PORT_2_VAL,
  1579. },
  1580. };
  1581. static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
  1582. {
  1583. .reg = IP_SEL_PAD_80_89_REG,
  1584. .mask = PMX_PL_88_89_MASK,
  1585. .val = PMX_UART6_PL_88_89_VAL,
  1586. }, {
  1587. .reg = IP_SEL_MIX_PAD_REG,
  1588. .mask = PMX_UART6_PORT_SEL_MASK,
  1589. .val = PMX_UART6_PORT_88_VAL,
  1590. },
  1591. };
  1592. static struct spear_modemux uart6_modemux[][1] = {
  1593. {
  1594. /* Select signals on pins 2_3 */
  1595. {
  1596. .modes = EXTENDED_MODE,
  1597. .muxregs = uart6_ext_2_3_muxreg,
  1598. .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
  1599. },
  1600. }, {
  1601. /* Select signals on pins 88_89 */
  1602. {
  1603. .modes = EXTENDED_MODE,
  1604. .muxregs = uart6_ext_88_89_muxreg,
  1605. .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
  1606. },
  1607. },
  1608. };
  1609. static struct spear_pingroup uart6_pingroup[] = {
  1610. {
  1611. .name = "uart6_2_3_grp",
  1612. .pins = uart6_pins[0],
  1613. .npins = ARRAY_SIZE(uart6_pins[0]),
  1614. .modemuxs = uart6_modemux[0],
  1615. .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
  1616. }, {
  1617. .name = "uart6_88_89_grp",
  1618. .pins = uart6_pins[1],
  1619. .npins = ARRAY_SIZE(uart6_pins[1]),
  1620. .modemuxs = uart6_modemux[1],
  1621. .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
  1622. },
  1623. };
  1624. static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
  1625. static struct spear_function uart6_function = {
  1626. .name = "uart6",
  1627. .groups = uart6_grps,
  1628. .ngroups = ARRAY_SIZE(uart6_grps),
  1629. };
  1630. /* UART - RS485 pmx */
  1631. static const unsigned rs485_pins[] = { 77, 78, 79 };
  1632. static struct spear_muxreg rs485_muxreg[] = {
  1633. {
  1634. .reg = IP_SEL_PAD_70_79_REG,
  1635. .mask = PMX_PL_77_78_79_MASK,
  1636. .val = PMX_RS485_PL_77_78_79_VAL,
  1637. },
  1638. };
  1639. static struct spear_modemux rs485_modemux[] = {
  1640. {
  1641. .modes = EXTENDED_MODE,
  1642. .muxregs = rs485_muxreg,
  1643. .nmuxregs = ARRAY_SIZE(rs485_muxreg),
  1644. },
  1645. };
  1646. static struct spear_pingroup rs485_pingroup = {
  1647. .name = "rs485_grp",
  1648. .pins = rs485_pins,
  1649. .npins = ARRAY_SIZE(rs485_pins),
  1650. .modemuxs = rs485_modemux,
  1651. .nmodemuxs = ARRAY_SIZE(rs485_modemux),
  1652. };
  1653. static const char *const rs485_grps[] = { "rs485_grp" };
  1654. static struct spear_function rs485_function = {
  1655. .name = "rs485",
  1656. .groups = rs485_grps,
  1657. .ngroups = ARRAY_SIZE(rs485_grps),
  1658. };
  1659. /* Pad multiplexing for Touchscreen device */
  1660. static const unsigned touchscreen_pins[] = { 5, 36 };
  1661. static struct spear_muxreg touchscreen_muxreg[] = {
  1662. {
  1663. .reg = PMX_CONFIG_REG,
  1664. .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
  1665. .val = 0,
  1666. },
  1667. };
  1668. static struct spear_muxreg touchscreen_ext_muxreg[] = {
  1669. {
  1670. .reg = IP_SEL_PAD_0_9_REG,
  1671. .mask = PMX_PL_5_MASK,
  1672. .val = PMX_TOUCH_Y_PL_5_VAL,
  1673. }, {
  1674. .reg = IP_SEL_PAD_30_39_REG,
  1675. .mask = PMX_PL_36_MASK,
  1676. .val = PMX_TOUCH_X_PL_36_VAL,
  1677. },
  1678. };
  1679. static struct spear_modemux touchscreen_modemux[] = {
  1680. {
  1681. .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
  1682. .muxregs = touchscreen_muxreg,
  1683. .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
  1684. }, {
  1685. .modes = EXTENDED_MODE,
  1686. .muxregs = touchscreen_ext_muxreg,
  1687. .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
  1688. },
  1689. };
  1690. static struct spear_pingroup touchscreen_pingroup = {
  1691. .name = "touchscreen_grp",
  1692. .pins = touchscreen_pins,
  1693. .npins = ARRAY_SIZE(touchscreen_pins),
  1694. .modemuxs = touchscreen_modemux,
  1695. .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
  1696. };
  1697. static const char *const touchscreen_grps[] = { "touchscreen_grp" };
  1698. static struct spear_function touchscreen_function = {
  1699. .name = "touchscreen",
  1700. .groups = touchscreen_grps,
  1701. .ngroups = ARRAY_SIZE(touchscreen_grps),
  1702. };
  1703. /* Pad multiplexing for CAN device */
  1704. static const unsigned can0_pins[] = { 32, 33 };
  1705. static struct spear_muxreg can0_muxreg[] = {
  1706. {
  1707. .reg = PMX_CONFIG_REG,
  1708. .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
  1709. .val = 0,
  1710. },
  1711. };
  1712. static struct spear_muxreg can0_ext_muxreg[] = {
  1713. {
  1714. .reg = IP_SEL_PAD_30_39_REG,
  1715. .mask = PMX_PL_32_33_MASK,
  1716. .val = PMX_CAN0_PL_32_33_VAL,
  1717. },
  1718. };
  1719. static struct spear_modemux can0_modemux[] = {
  1720. {
  1721. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
  1722. | EXTENDED_MODE,
  1723. .muxregs = can0_muxreg,
  1724. .nmuxregs = ARRAY_SIZE(can0_muxreg),
  1725. }, {
  1726. .modes = EXTENDED_MODE,
  1727. .muxregs = can0_ext_muxreg,
  1728. .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
  1729. },
  1730. };
  1731. static struct spear_pingroup can0_pingroup = {
  1732. .name = "can0_grp",
  1733. .pins = can0_pins,
  1734. .npins = ARRAY_SIZE(can0_pins),
  1735. .modemuxs = can0_modemux,
  1736. .nmodemuxs = ARRAY_SIZE(can0_modemux),
  1737. };
  1738. static const char *const can0_grps[] = { "can0_grp" };
  1739. static struct spear_function can0_function = {
  1740. .name = "can0",
  1741. .groups = can0_grps,
  1742. .ngroups = ARRAY_SIZE(can0_grps),
  1743. };
  1744. static const unsigned can1_pins[] = { 30, 31 };
  1745. static struct spear_muxreg can1_muxreg[] = {
  1746. {
  1747. .reg = PMX_CONFIG_REG,
  1748. .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
  1749. .val = 0,
  1750. },
  1751. };
  1752. static struct spear_muxreg can1_ext_muxreg[] = {
  1753. {
  1754. .reg = IP_SEL_PAD_30_39_REG,
  1755. .mask = PMX_PL_30_31_MASK,
  1756. .val = PMX_CAN1_PL_30_31_VAL,
  1757. },
  1758. };
  1759. static struct spear_modemux can1_modemux[] = {
  1760. {
  1761. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
  1762. | EXTENDED_MODE,
  1763. .muxregs = can1_muxreg,
  1764. .nmuxregs = ARRAY_SIZE(can1_muxreg),
  1765. }, {
  1766. .modes = EXTENDED_MODE,
  1767. .muxregs = can1_ext_muxreg,
  1768. .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
  1769. },
  1770. };
  1771. static struct spear_pingroup can1_pingroup = {
  1772. .name = "can1_grp",
  1773. .pins = can1_pins,
  1774. .npins = ARRAY_SIZE(can1_pins),
  1775. .modemuxs = can1_modemux,
  1776. .nmodemuxs = ARRAY_SIZE(can1_modemux),
  1777. };
  1778. static const char *const can1_grps[] = { "can1_grp" };
  1779. static struct spear_function can1_function = {
  1780. .name = "can1",
  1781. .groups = can1_grps,
  1782. .ngroups = ARRAY_SIZE(can1_grps),
  1783. };
  1784. /* Pad multiplexing for PWM0_1 device */
  1785. static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
  1786. { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
  1787. static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
  1788. {
  1789. .reg = PMX_CONFIG_REG,
  1790. .mask = PMX_SSP_MASK,
  1791. .val = 0,
  1792. }, {
  1793. .reg = IP_SEL_PAD_0_9_REG,
  1794. .mask = PMX_PL_8_9_MASK,
  1795. .val = PMX_PWM_0_1_PL_8_9_VAL,
  1796. },
  1797. };
  1798. static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
  1799. {
  1800. .reg = PMX_CONFIG_REG,
  1801. .mask = PMX_MII_MASK,
  1802. .val = 0,
  1803. },
  1804. };
  1805. static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
  1806. {
  1807. .reg = IP_SEL_PAD_10_19_REG,
  1808. .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
  1809. .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
  1810. },
  1811. };
  1812. static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
  1813. {
  1814. .reg = PMX_CONFIG_REG,
  1815. .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
  1816. .val = 0,
  1817. }, {
  1818. .reg = IP_SEL_PAD_30_39_REG,
  1819. .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
  1820. .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
  1821. },
  1822. };
  1823. static struct spear_muxreg pwm0_1_net_muxreg[] = {
  1824. {
  1825. .reg = PMX_CONFIG_REG,
  1826. .mask = PMX_UART0_MODEM_MASK,
  1827. .val = 0,
  1828. },
  1829. };
  1830. static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
  1831. {
  1832. .reg = IP_SEL_PAD_30_39_REG,
  1833. .mask = PMX_PL_37_38_MASK,
  1834. .val = PMX_PWM0_1_PL_37_38_VAL,
  1835. },
  1836. };
  1837. static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
  1838. {
  1839. .reg = PMX_CONFIG_REG,
  1840. .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
  1841. .val = 0,
  1842. }, {
  1843. .reg = IP_SEL_PAD_40_49_REG,
  1844. .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
  1845. .val = PMX_PWM1_PL_42_VAL |
  1846. PMX_PWM0_PL_43_VAL,
  1847. },
  1848. };
  1849. static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
  1850. {
  1851. .reg = IP_SEL_PAD_50_59_REG,
  1852. .mask = PMX_PL_59_MASK,
  1853. .val = PMX_PWM1_PL_59_VAL,
  1854. }, {
  1855. .reg = IP_SEL_PAD_60_69_REG,
  1856. .mask = PMX_PL_60_MASK,
  1857. .val = PMX_PWM0_PL_60_VAL,
  1858. },
  1859. };
  1860. static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
  1861. {
  1862. .reg = IP_SEL_PAD_80_89_REG,
  1863. .mask = PMX_PL_88_89_MASK,
  1864. .val = PMX_PWM0_1_PL_88_89_VAL,
  1865. },
  1866. };
  1867. static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
  1868. {
  1869. .modes = EXTENDED_MODE,
  1870. .muxregs = pwm0_1_pin_8_9_muxreg,
  1871. .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
  1872. },
  1873. };
  1874. static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
  1875. {
  1876. .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
  1877. .muxregs = pwm0_1_autoexpsmallpri_muxreg,
  1878. .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
  1879. }, {
  1880. .modes = EXTENDED_MODE,
  1881. .muxregs = pwm0_1_pin_14_15_muxreg,
  1882. .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
  1883. },
  1884. };
  1885. static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
  1886. {
  1887. .modes = EXTENDED_MODE,
  1888. .muxregs = pwm0_1_pin_30_31_muxreg,
  1889. .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
  1890. },
  1891. };
  1892. static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
  1893. {
  1894. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
  1895. .muxregs = pwm0_1_net_muxreg,
  1896. .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
  1897. }, {
  1898. .modes = EXTENDED_MODE,
  1899. .muxregs = pwm0_1_pin_37_38_muxreg,
  1900. .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
  1901. },
  1902. };
  1903. static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
  1904. {
  1905. .modes = EXTENDED_MODE,
  1906. .muxregs = pwm0_1_pin_42_43_muxreg,
  1907. .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
  1908. },
  1909. };
  1910. static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
  1911. {
  1912. .modes = EXTENDED_MODE,
  1913. .muxregs = pwm0_1_pin_59_60_muxreg,
  1914. .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
  1915. },
  1916. };
  1917. static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
  1918. {
  1919. .modes = EXTENDED_MODE,
  1920. .muxregs = pwm0_1_pin_88_89_muxreg,
  1921. .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
  1922. },
  1923. };
  1924. static struct spear_pingroup pwm0_1_pingroup[] = {
  1925. {
  1926. .name = "pwm0_1_pin_8_9_grp",
  1927. .pins = pwm0_1_pins[0],
  1928. .npins = ARRAY_SIZE(pwm0_1_pins[0]),
  1929. .modemuxs = pwm0_1_pin_8_9_modemux,
  1930. .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
  1931. }, {
  1932. .name = "pwm0_1_pin_14_15_grp",
  1933. .pins = pwm0_1_pins[1],
  1934. .npins = ARRAY_SIZE(pwm0_1_pins[1]),
  1935. .modemuxs = pwm0_1_pin_14_15_modemux,
  1936. .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
  1937. }, {
  1938. .name = "pwm0_1_pin_30_31_grp",
  1939. .pins = pwm0_1_pins[2],
  1940. .npins = ARRAY_SIZE(pwm0_1_pins[2]),
  1941. .modemuxs = pwm0_1_pin_30_31_modemux,
  1942. .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
  1943. }, {
  1944. .name = "pwm0_1_pin_37_38_grp",
  1945. .pins = pwm0_1_pins[3],
  1946. .npins = ARRAY_SIZE(pwm0_1_pins[3]),
  1947. .modemuxs = pwm0_1_pin_37_38_modemux,
  1948. .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
  1949. }, {
  1950. .name = "pwm0_1_pin_42_43_grp",
  1951. .pins = pwm0_1_pins[4],
  1952. .npins = ARRAY_SIZE(pwm0_1_pins[4]),
  1953. .modemuxs = pwm0_1_pin_42_43_modemux,
  1954. .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
  1955. }, {
  1956. .name = "pwm0_1_pin_59_60_grp",
  1957. .pins = pwm0_1_pins[5],
  1958. .npins = ARRAY_SIZE(pwm0_1_pins[5]),
  1959. .modemuxs = pwm0_1_pin_59_60_modemux,
  1960. .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
  1961. }, {
  1962. .name = "pwm0_1_pin_88_89_grp",
  1963. .pins = pwm0_1_pins[6],
  1964. .npins = ARRAY_SIZE(pwm0_1_pins[6]),
  1965. .modemuxs = pwm0_1_pin_88_89_modemux,
  1966. .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
  1967. },
  1968. };
  1969. static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
  1970. "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
  1971. "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
  1972. };
  1973. static struct spear_function pwm0_1_function = {
  1974. .name = "pwm0_1",
  1975. .groups = pwm0_1_grps,
  1976. .ngroups = ARRAY_SIZE(pwm0_1_grps),
  1977. };
  1978. /* Pad multiplexing for PWM2 device */
  1979. static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
  1980. { 58 }, { 87 } };
  1981. static struct spear_muxreg pwm2_net_muxreg[] = {
  1982. {
  1983. .reg = PMX_CONFIG_REG,
  1984. .mask = PMX_SSP_CS_MASK,
  1985. .val = 0,
  1986. },
  1987. };
  1988. static struct spear_muxreg pwm2_pin_7_muxreg[] = {
  1989. {
  1990. .reg = IP_SEL_PAD_0_9_REG,
  1991. .mask = PMX_PL_7_MASK,
  1992. .val = PMX_PWM_2_PL_7_VAL,
  1993. },
  1994. };
  1995. static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
  1996. {
  1997. .reg = PMX_CONFIG_REG,
  1998. .mask = PMX_MII_MASK,
  1999. .val = 0,
  2000. },
  2001. };
  2002. static struct spear_muxreg pwm2_pin_13_muxreg[] = {
  2003. {
  2004. .reg = IP_SEL_PAD_10_19_REG,
  2005. .mask = PMX_PL_13_MASK,
  2006. .val = PMX_PWM2_PL_13_VAL,
  2007. },
  2008. };
  2009. static struct spear_muxreg pwm2_pin_29_muxreg[] = {
  2010. {
  2011. .reg = PMX_CONFIG_REG,
  2012. .mask = PMX_GPIO_PIN1_MASK,
  2013. .val = 0,
  2014. }, {
  2015. .reg = IP_SEL_PAD_20_29_REG,
  2016. .mask = PMX_PL_29_MASK,
  2017. .val = PMX_PWM_2_PL_29_VAL,
  2018. },
  2019. };
  2020. static struct spear_muxreg pwm2_pin_34_muxreg[] = {
  2021. {
  2022. .reg = PMX_CONFIG_REG,
  2023. .mask = PMX_SSP_CS_MASK,
  2024. .val = 0,
  2025. }, {
  2026. .reg = MODE_CONFIG_REG,
  2027. .mask = PMX_PWM_MASK,
  2028. .val = PMX_PWM_MASK,
  2029. }, {
  2030. .reg = IP_SEL_PAD_30_39_REG,
  2031. .mask = PMX_PL_34_MASK,
  2032. .val = PMX_PWM2_PL_34_VAL,
  2033. },
  2034. };
  2035. static struct spear_muxreg pwm2_pin_41_muxreg[] = {
  2036. {
  2037. .reg = PMX_CONFIG_REG,
  2038. .mask = PMX_UART0_MODEM_MASK,
  2039. .val = 0,
  2040. }, {
  2041. .reg = IP_SEL_PAD_40_49_REG,
  2042. .mask = PMX_PL_41_MASK,
  2043. .val = PMX_PWM2_PL_41_VAL,
  2044. },
  2045. };
  2046. static struct spear_muxreg pwm2_pin_58_muxreg[] = {
  2047. {
  2048. .reg = IP_SEL_PAD_50_59_REG,
  2049. .mask = PMX_PL_58_MASK,
  2050. .val = PMX_PWM2_PL_58_VAL,
  2051. },
  2052. };
  2053. static struct spear_muxreg pwm2_pin_87_muxreg[] = {
  2054. {
  2055. .reg = IP_SEL_PAD_80_89_REG,
  2056. .mask = PMX_PL_87_MASK,
  2057. .val = PMX_PWM2_PL_87_VAL,
  2058. },
  2059. };
  2060. static struct spear_modemux pwm2_pin_7_modemux[] = {
  2061. {
  2062. .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
  2063. .muxregs = pwm2_net_muxreg,
  2064. .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
  2065. }, {
  2066. .modes = EXTENDED_MODE,
  2067. .muxregs = pwm2_pin_7_muxreg,
  2068. .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
  2069. },
  2070. };
  2071. static struct spear_modemux pwm2_pin_13_modemux[] = {
  2072. {
  2073. .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
  2074. .muxregs = pwm2_autoexpsmallpri_muxreg,
  2075. .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
  2076. }, {
  2077. .modes = EXTENDED_MODE,
  2078. .muxregs = pwm2_pin_13_muxreg,
  2079. .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
  2080. },
  2081. };
  2082. static struct spear_modemux pwm2_pin_29_modemux[] = {
  2083. {
  2084. .modes = EXTENDED_MODE,
  2085. .muxregs = pwm2_pin_29_muxreg,
  2086. .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
  2087. },
  2088. };
  2089. static struct spear_modemux pwm2_pin_34_modemux[] = {
  2090. {
  2091. .modes = EXTENDED_MODE,
  2092. .muxregs = pwm2_pin_34_muxreg,
  2093. .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
  2094. },
  2095. };
  2096. static struct spear_modemux pwm2_pin_41_modemux[] = {
  2097. {
  2098. .modes = EXTENDED_MODE,
  2099. .muxregs = pwm2_pin_41_muxreg,
  2100. .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
  2101. },
  2102. };
  2103. static struct spear_modemux pwm2_pin_58_modemux[] = {
  2104. {
  2105. .modes = EXTENDED_MODE,
  2106. .muxregs = pwm2_pin_58_muxreg,
  2107. .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
  2108. },
  2109. };
  2110. static struct spear_modemux pwm2_pin_87_modemux[] = {
  2111. {
  2112. .modes = EXTENDED_MODE,
  2113. .muxregs = pwm2_pin_87_muxreg,
  2114. .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
  2115. },
  2116. };
  2117. static struct spear_pingroup pwm2_pingroup[] = {
  2118. {
  2119. .name = "pwm2_pin_7_grp",
  2120. .pins = pwm2_pins[0],
  2121. .npins = ARRAY_SIZE(pwm2_pins[0]),
  2122. .modemuxs = pwm2_pin_7_modemux,
  2123. .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
  2124. }, {
  2125. .name = "pwm2_pin_13_grp",
  2126. .pins = pwm2_pins[1],
  2127. .npins = ARRAY_SIZE(pwm2_pins[1]),
  2128. .modemuxs = pwm2_pin_13_modemux,
  2129. .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
  2130. }, {
  2131. .name = "pwm2_pin_29_grp",
  2132. .pins = pwm2_pins[2],
  2133. .npins = ARRAY_SIZE(pwm2_pins[2]),
  2134. .modemuxs = pwm2_pin_29_modemux,
  2135. .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
  2136. }, {
  2137. .name = "pwm2_pin_34_grp",
  2138. .pins = pwm2_pins[3],
  2139. .npins = ARRAY_SIZE(pwm2_pins[3]),
  2140. .modemuxs = pwm2_pin_34_modemux,
  2141. .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
  2142. }, {
  2143. .name = "pwm2_pin_41_grp",
  2144. .pins = pwm2_pins[4],
  2145. .npins = ARRAY_SIZE(pwm2_pins[4]),
  2146. .modemuxs = pwm2_pin_41_modemux,
  2147. .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
  2148. }, {
  2149. .name = "pwm2_pin_58_grp",
  2150. .pins = pwm2_pins[5],
  2151. .npins = ARRAY_SIZE(pwm2_pins[5]),
  2152. .modemuxs = pwm2_pin_58_modemux,
  2153. .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
  2154. }, {
  2155. .name = "pwm2_pin_87_grp",
  2156. .pins = pwm2_pins[6],
  2157. .npins = ARRAY_SIZE(pwm2_pins[6]),
  2158. .modemuxs = pwm2_pin_87_modemux,
  2159. .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
  2160. },
  2161. };
  2162. static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
  2163. "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
  2164. "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
  2165. static struct spear_function pwm2_function = {
  2166. .name = "pwm2",
  2167. .groups = pwm2_grps,
  2168. .ngroups = ARRAY_SIZE(pwm2_grps),
  2169. };
  2170. /* Pad multiplexing for PWM3 device */
  2171. static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
  2172. { 86 } };
  2173. static struct spear_muxreg pwm3_pin_6_muxreg[] = {
  2174. {
  2175. .reg = PMX_CONFIG_REG,
  2176. .mask = PMX_SSP_MASK,
  2177. .val = 0,
  2178. }, {
  2179. .reg = IP_SEL_PAD_0_9_REG,
  2180. .mask = PMX_PL_6_MASK,
  2181. .val = PMX_PWM_3_PL_6_VAL,
  2182. },
  2183. };
  2184. static struct spear_muxreg pwm3_muxreg[] = {
  2185. {
  2186. .reg = PMX_CONFIG_REG,
  2187. .mask = PMX_MII_MASK,
  2188. .val = 0,
  2189. },
  2190. };
  2191. static struct spear_muxreg pwm3_pin_12_muxreg[] = {
  2192. {
  2193. .reg = IP_SEL_PAD_10_19_REG,
  2194. .mask = PMX_PL_12_MASK,
  2195. .val = PMX_PWM3_PL_12_VAL,
  2196. },
  2197. };
  2198. static struct spear_muxreg pwm3_pin_28_muxreg[] = {
  2199. {
  2200. .reg = PMX_CONFIG_REG,
  2201. .mask = PMX_GPIO_PIN0_MASK,
  2202. .val = 0,
  2203. }, {
  2204. .reg = IP_SEL_PAD_20_29_REG,
  2205. .mask = PMX_PL_28_MASK,
  2206. .val = PMX_PWM_3_PL_28_VAL,
  2207. },
  2208. };
  2209. static struct spear_muxreg pwm3_pin_40_muxreg[] = {
  2210. {
  2211. .reg = PMX_CONFIG_REG,
  2212. .mask = PMX_UART0_MODEM_MASK,
  2213. .val = 0,
  2214. }, {
  2215. .reg = IP_SEL_PAD_40_49_REG,
  2216. .mask = PMX_PL_40_MASK,
  2217. .val = PMX_PWM3_PL_40_VAL,
  2218. },
  2219. };
  2220. static struct spear_muxreg pwm3_pin_57_muxreg[] = {
  2221. {
  2222. .reg = IP_SEL_PAD_50_59_REG,
  2223. .mask = PMX_PL_57_MASK,
  2224. .val = PMX_PWM3_PL_57_VAL,
  2225. },
  2226. };
  2227. static struct spear_muxreg pwm3_pin_86_muxreg[] = {
  2228. {
  2229. .reg = IP_SEL_PAD_80_89_REG,
  2230. .mask = PMX_PL_86_MASK,
  2231. .val = PMX_PWM3_PL_86_VAL,
  2232. },
  2233. };
  2234. static struct spear_modemux pwm3_pin_6_modemux[] = {
  2235. {
  2236. .modes = EXTENDED_MODE,
  2237. .muxregs = pwm3_pin_6_muxreg,
  2238. .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
  2239. },
  2240. };
  2241. static struct spear_modemux pwm3_pin_12_modemux[] = {
  2242. {
  2243. .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
  2244. AUTO_NET_SMII_MODE | EXTENDED_MODE,
  2245. .muxregs = pwm3_muxreg,
  2246. .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
  2247. }, {
  2248. .modes = EXTENDED_MODE,
  2249. .muxregs = pwm3_pin_12_muxreg,
  2250. .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
  2251. },
  2252. };
  2253. static struct spear_modemux pwm3_pin_28_modemux[] = {
  2254. {
  2255. .modes = EXTENDED_MODE,
  2256. .muxregs = pwm3_pin_28_muxreg,
  2257. .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
  2258. },
  2259. };
  2260. static struct spear_modemux pwm3_pin_40_modemux[] = {
  2261. {
  2262. .modes = EXTENDED_MODE,
  2263. .muxregs = pwm3_pin_40_muxreg,
  2264. .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
  2265. },
  2266. };
  2267. static struct spear_modemux pwm3_pin_57_modemux[] = {
  2268. {
  2269. .modes = EXTENDED_MODE,
  2270. .muxregs = pwm3_pin_57_muxreg,
  2271. .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
  2272. },
  2273. };
  2274. static struct spear_modemux pwm3_pin_86_modemux[] = {
  2275. {
  2276. .modes = EXTENDED_MODE,
  2277. .muxregs = pwm3_pin_86_muxreg,
  2278. .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
  2279. },
  2280. };
  2281. static struct spear_pingroup pwm3_pingroup[] = {
  2282. {
  2283. .name = "pwm3_pin_6_grp",
  2284. .pins = pwm3_pins[0],
  2285. .npins = ARRAY_SIZE(pwm3_pins[0]),
  2286. .modemuxs = pwm3_pin_6_modemux,
  2287. .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
  2288. }, {
  2289. .name = "pwm3_pin_12_grp",
  2290. .pins = pwm3_pins[1],
  2291. .npins = ARRAY_SIZE(pwm3_pins[1]),
  2292. .modemuxs = pwm3_pin_12_modemux,
  2293. .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
  2294. }, {
  2295. .name = "pwm3_pin_28_grp",
  2296. .pins = pwm3_pins[2],
  2297. .npins = ARRAY_SIZE(pwm3_pins[2]),
  2298. .modemuxs = pwm3_pin_28_modemux,
  2299. .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
  2300. }, {
  2301. .name = "pwm3_pin_40_grp",
  2302. .pins = pwm3_pins[3],
  2303. .npins = ARRAY_SIZE(pwm3_pins[3]),
  2304. .modemuxs = pwm3_pin_40_modemux,
  2305. .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
  2306. }, {
  2307. .name = "pwm3_pin_57_grp",
  2308. .pins = pwm3_pins[4],
  2309. .npins = ARRAY_SIZE(pwm3_pins[4]),
  2310. .modemuxs = pwm3_pin_57_modemux,
  2311. .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
  2312. }, {
  2313. .name = "pwm3_pin_86_grp",
  2314. .pins = pwm3_pins[5],
  2315. .npins = ARRAY_SIZE(pwm3_pins[5]),
  2316. .modemuxs = pwm3_pin_86_modemux,
  2317. .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
  2318. },
  2319. };
  2320. static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
  2321. "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
  2322. "pwm3_pin_86_grp" };
  2323. static struct spear_function pwm3_function = {
  2324. .name = "pwm3",
  2325. .groups = pwm3_grps,
  2326. .ngroups = ARRAY_SIZE(pwm3_grps),
  2327. };
  2328. /* Pad multiplexing for SSP1 device */
  2329. static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
  2330. { 65, 68 }, { 94, 97 } };
  2331. static struct spear_muxreg ssp1_muxreg[] = {
  2332. {
  2333. .reg = PMX_CONFIG_REG,
  2334. .mask = PMX_MII_MASK,
  2335. .val = 0,
  2336. },
  2337. };
  2338. static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
  2339. {
  2340. .reg = IP_SEL_PAD_10_19_REG,
  2341. .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
  2342. .val = PMX_SSP1_PL_17_18_19_20_VAL,
  2343. }, {
  2344. .reg = IP_SEL_PAD_20_29_REG,
  2345. .mask = PMX_PL_20_MASK,
  2346. .val = PMX_SSP1_PL_17_18_19_20_VAL,
  2347. }, {
  2348. .reg = IP_SEL_MIX_PAD_REG,
  2349. .mask = PMX_SSP1_PORT_SEL_MASK,
  2350. .val = PMX_SSP1_PORT_17_TO_20_VAL,
  2351. },
  2352. };
  2353. static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
  2354. {
  2355. .reg = PMX_CONFIG_REG,
  2356. .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
  2357. .val = 0,
  2358. }, {
  2359. .reg = IP_SEL_PAD_30_39_REG,
  2360. .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
  2361. .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
  2362. PMX_SSP1_PL_39_VAL,
  2363. }, {
  2364. .reg = IP_SEL_MIX_PAD_REG,
  2365. .mask = PMX_SSP1_PORT_SEL_MASK,
  2366. .val = PMX_SSP1_PORT_36_TO_39_VAL,
  2367. },
  2368. };
  2369. static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
  2370. {
  2371. .reg = PMX_CONFIG_REG,
  2372. .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
  2373. .val = 0,
  2374. }, {
  2375. .reg = IP_SEL_PAD_40_49_REG,
  2376. .mask = PMX_PL_48_49_MASK,
  2377. .val = PMX_SSP1_PL_48_49_VAL,
  2378. }, {
  2379. .reg = IP_SEL_PAD_50_59_REG,
  2380. .mask = PMX_PL_50_51_MASK,
  2381. .val = PMX_SSP1_PL_50_51_VAL,
  2382. }, {
  2383. .reg = IP_SEL_MIX_PAD_REG,
  2384. .mask = PMX_SSP1_PORT_SEL_MASK,
  2385. .val = PMX_SSP1_PORT_48_TO_51_VAL,
  2386. },
  2387. };
  2388. static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
  2389. {
  2390. .reg = IP_SEL_PAD_60_69_REG,
  2391. .mask = PMX_PL_65_TO_68_MASK,
  2392. .val = PMX_SSP1_PL_65_TO_68_VAL,
  2393. }, {
  2394. .reg = IP_SEL_MIX_PAD_REG,
  2395. .mask = PMX_SSP1_PORT_SEL_MASK,
  2396. .val = PMX_SSP1_PORT_65_TO_68_VAL,
  2397. },
  2398. };
  2399. static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
  2400. {
  2401. .reg = IP_SEL_PAD_90_99_REG,
  2402. .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
  2403. .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
  2404. }, {
  2405. .reg = IP_SEL_MIX_PAD_REG,
  2406. .mask = PMX_SSP1_PORT_SEL_MASK,
  2407. .val = PMX_SSP1_PORT_94_TO_97_VAL,
  2408. },
  2409. };
  2410. static struct spear_modemux ssp1_17_20_modemux[] = {
  2411. {
  2412. .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
  2413. EXTENDED_MODE,
  2414. .muxregs = ssp1_muxreg,
  2415. .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
  2416. }, {
  2417. .modes = EXTENDED_MODE,
  2418. .muxregs = ssp1_ext_17_20_muxreg,
  2419. .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
  2420. },
  2421. };
  2422. static struct spear_modemux ssp1_36_39_modemux[] = {
  2423. {
  2424. .modes = EXTENDED_MODE,
  2425. .muxregs = ssp1_ext_36_39_muxreg,
  2426. .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
  2427. },
  2428. };
  2429. static struct spear_modemux ssp1_48_51_modemux[] = {
  2430. {
  2431. .modes = EXTENDED_MODE,
  2432. .muxregs = ssp1_ext_48_51_muxreg,
  2433. .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
  2434. },
  2435. };
  2436. static struct spear_modemux ssp1_65_68_modemux[] = {
  2437. {
  2438. .modes = EXTENDED_MODE,
  2439. .muxregs = ssp1_ext_65_68_muxreg,
  2440. .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
  2441. },
  2442. };
  2443. static struct spear_modemux ssp1_94_97_modemux[] = {
  2444. {
  2445. .modes = EXTENDED_MODE,
  2446. .muxregs = ssp1_ext_94_97_muxreg,
  2447. .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
  2448. },
  2449. };
  2450. static struct spear_pingroup ssp1_pingroup[] = {
  2451. {
  2452. .name = "ssp1_17_20_grp",
  2453. .pins = ssp1_pins[0],
  2454. .npins = ARRAY_SIZE(ssp1_pins[0]),
  2455. .modemuxs = ssp1_17_20_modemux,
  2456. .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
  2457. }, {
  2458. .name = "ssp1_36_39_grp",
  2459. .pins = ssp1_pins[1],
  2460. .npins = ARRAY_SIZE(ssp1_pins[1]),
  2461. .modemuxs = ssp1_36_39_modemux,
  2462. .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
  2463. }, {
  2464. .name = "ssp1_48_51_grp",
  2465. .pins = ssp1_pins[2],
  2466. .npins = ARRAY_SIZE(ssp1_pins[2]),
  2467. .modemuxs = ssp1_48_51_modemux,
  2468. .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
  2469. }, {
  2470. .name = "ssp1_65_68_grp",
  2471. .pins = ssp1_pins[3],
  2472. .npins = ARRAY_SIZE(ssp1_pins[3]),
  2473. .modemuxs = ssp1_65_68_modemux,
  2474. .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
  2475. }, {
  2476. .name = "ssp1_94_97_grp",
  2477. .pins = ssp1_pins[4],
  2478. .npins = ARRAY_SIZE(ssp1_pins[4]),
  2479. .modemuxs = ssp1_94_97_modemux,
  2480. .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
  2481. },
  2482. };
  2483. static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
  2484. "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
  2485. };
  2486. static struct spear_function ssp1_function = {
  2487. .name = "ssp1",
  2488. .groups = ssp1_grps,
  2489. .ngroups = ARRAY_SIZE(ssp1_grps),
  2490. };
  2491. /* Pad multiplexing for SSP2 device */
  2492. static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
  2493. { 61, 64 }, { 90, 93 } };
  2494. static struct spear_muxreg ssp2_muxreg[] = {
  2495. {
  2496. .reg = PMX_CONFIG_REG,
  2497. .mask = PMX_MII_MASK,
  2498. .val = 0,
  2499. },
  2500. };
  2501. static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
  2502. {
  2503. .reg = IP_SEL_PAD_10_19_REG,
  2504. .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
  2505. .val = PMX_SSP2_PL_13_14_15_16_VAL,
  2506. }, {
  2507. .reg = IP_SEL_MIX_PAD_REG,
  2508. .mask = PMX_SSP2_PORT_SEL_MASK,
  2509. .val = PMX_SSP2_PORT_13_TO_16_VAL,
  2510. },
  2511. };
  2512. static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
  2513. {
  2514. .reg = PMX_CONFIG_REG,
  2515. .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
  2516. PMX_GPIO_PIN5_MASK,
  2517. .val = 0,
  2518. }, {
  2519. .reg = IP_SEL_PAD_30_39_REG,
  2520. .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
  2521. .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
  2522. PMX_SSP2_PL_35_VAL,
  2523. }, {
  2524. .reg = IP_SEL_MIX_PAD_REG,
  2525. .mask = PMX_SSP2_PORT_SEL_MASK,
  2526. .val = PMX_SSP2_PORT_32_TO_35_VAL,
  2527. },
  2528. };
  2529. static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
  2530. {
  2531. .reg = PMX_CONFIG_REG,
  2532. .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
  2533. .val = 0,
  2534. }, {
  2535. .reg = IP_SEL_PAD_40_49_REG,
  2536. .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
  2537. .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
  2538. }, {
  2539. .reg = IP_SEL_MIX_PAD_REG,
  2540. .mask = PMX_SSP2_PORT_SEL_MASK,
  2541. .val = PMX_SSP2_PORT_44_TO_47_VAL,
  2542. },
  2543. };
  2544. static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
  2545. {
  2546. .reg = IP_SEL_PAD_60_69_REG,
  2547. .mask = PMX_PL_61_TO_64_MASK,
  2548. .val = PMX_SSP2_PL_61_TO_64_VAL,
  2549. }, {
  2550. .reg = IP_SEL_MIX_PAD_REG,
  2551. .mask = PMX_SSP2_PORT_SEL_MASK,
  2552. .val = PMX_SSP2_PORT_61_TO_64_VAL,
  2553. },
  2554. };
  2555. static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
  2556. {
  2557. .reg = IP_SEL_PAD_90_99_REG,
  2558. .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
  2559. .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
  2560. }, {
  2561. .reg = IP_SEL_MIX_PAD_REG,
  2562. .mask = PMX_SSP2_PORT_SEL_MASK,
  2563. .val = PMX_SSP2_PORT_90_TO_93_VAL,
  2564. },
  2565. };
  2566. static struct spear_modemux ssp2_13_16_modemux[] = {
  2567. {
  2568. .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
  2569. .muxregs = ssp2_muxreg,
  2570. .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
  2571. }, {
  2572. .modes = EXTENDED_MODE,
  2573. .muxregs = ssp2_ext_13_16_muxreg,
  2574. .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
  2575. },
  2576. };
  2577. static struct spear_modemux ssp2_32_35_modemux[] = {
  2578. {
  2579. .modes = EXTENDED_MODE,
  2580. .muxregs = ssp2_ext_32_35_muxreg,
  2581. .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
  2582. },
  2583. };
  2584. static struct spear_modemux ssp2_44_47_modemux[] = {
  2585. {
  2586. .modes = EXTENDED_MODE,
  2587. .muxregs = ssp2_ext_44_47_muxreg,
  2588. .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
  2589. },
  2590. };
  2591. static struct spear_modemux ssp2_61_64_modemux[] = {
  2592. {
  2593. .modes = EXTENDED_MODE,
  2594. .muxregs = ssp2_ext_61_64_muxreg,
  2595. .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
  2596. },
  2597. };
  2598. static struct spear_modemux ssp2_90_93_modemux[] = {
  2599. {
  2600. .modes = EXTENDED_MODE,
  2601. .muxregs = ssp2_ext_90_93_muxreg,
  2602. .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
  2603. },
  2604. };
  2605. static struct spear_pingroup ssp2_pingroup[] = {
  2606. {
  2607. .name = "ssp2_13_16_grp",
  2608. .pins = ssp2_pins[0],
  2609. .npins = ARRAY_SIZE(ssp2_pins[0]),
  2610. .modemuxs = ssp2_13_16_modemux,
  2611. .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
  2612. }, {
  2613. .name = "ssp2_32_35_grp",
  2614. .pins = ssp2_pins[1],
  2615. .npins = ARRAY_SIZE(ssp2_pins[1]),
  2616. .modemuxs = ssp2_32_35_modemux,
  2617. .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
  2618. }, {
  2619. .name = "ssp2_44_47_grp",
  2620. .pins = ssp2_pins[2],
  2621. .npins = ARRAY_SIZE(ssp2_pins[2]),
  2622. .modemuxs = ssp2_44_47_modemux,
  2623. .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
  2624. }, {
  2625. .name = "ssp2_61_64_grp",
  2626. .pins = ssp2_pins[3],
  2627. .npins = ARRAY_SIZE(ssp2_pins[3]),
  2628. .modemuxs = ssp2_61_64_modemux,
  2629. .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
  2630. }, {
  2631. .name = "ssp2_90_93_grp",
  2632. .pins = ssp2_pins[4],
  2633. .npins = ARRAY_SIZE(ssp2_pins[4]),
  2634. .modemuxs = ssp2_90_93_modemux,
  2635. .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
  2636. },
  2637. };
  2638. static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
  2639. "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
  2640. static struct spear_function ssp2_function = {
  2641. .name = "ssp2",
  2642. .groups = ssp2_grps,
  2643. .ngroups = ARRAY_SIZE(ssp2_grps),
  2644. };
  2645. /* Pad multiplexing for cadence mii2 as mii device */
  2646. static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
  2647. 90, 91, 92, 93, 94, 95, 96, 97 };
  2648. static struct spear_muxreg mii2_muxreg[] = {
  2649. {
  2650. .reg = IP_SEL_PAD_80_89_REG,
  2651. .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
  2652. PMX_PL_88_89_MASK,
  2653. .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
  2654. PMX_MII2_PL_88_89_VAL,
  2655. }, {
  2656. .reg = IP_SEL_PAD_90_99_REG,
  2657. .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
  2658. PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
  2659. .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
  2660. PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
  2661. }, {
  2662. .reg = EXT_CTRL_REG,
  2663. .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
  2664. (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
  2665. MII_MDIO_MASK,
  2666. .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
  2667. (MAC_MODE_MII << MAC1_MODE_SHIFT) |
  2668. MII_MDIO_81_VAL,
  2669. },
  2670. };
  2671. static struct spear_modemux mii2_modemux[] = {
  2672. {
  2673. .modes = EXTENDED_MODE,
  2674. .muxregs = mii2_muxreg,
  2675. .nmuxregs = ARRAY_SIZE(mii2_muxreg),
  2676. },
  2677. };
  2678. static struct spear_pingroup mii2_pingroup = {
  2679. .name = "mii2_grp",
  2680. .pins = mii2_pins,
  2681. .npins = ARRAY_SIZE(mii2_pins),
  2682. .modemuxs = mii2_modemux,
  2683. .nmodemuxs = ARRAY_SIZE(mii2_modemux),
  2684. };
  2685. static const char *const mii2_grps[] = { "mii2_grp" };
  2686. static struct spear_function mii2_function = {
  2687. .name = "mii2",
  2688. .groups = mii2_grps,
  2689. .ngroups = ARRAY_SIZE(mii2_grps),
  2690. };
  2691. /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
  2692. static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
  2693. 21, 22, 23, 24, 25, 26, 27 };
  2694. static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
  2695. static struct spear_muxreg mii0_1_muxreg[] = {
  2696. {
  2697. .reg = PMX_CONFIG_REG,
  2698. .mask = PMX_MII_MASK,
  2699. .val = 0,
  2700. },
  2701. };
  2702. static struct spear_muxreg smii0_1_ext_muxreg[] = {
  2703. {
  2704. .reg = IP_SEL_PAD_10_19_REG,
  2705. .mask = PMX_PL_10_11_MASK,
  2706. .val = PMX_SMII_PL_10_11_VAL,
  2707. }, {
  2708. .reg = IP_SEL_PAD_20_29_REG,
  2709. .mask = PMX_PL_21_TO_27_MASK,
  2710. .val = PMX_SMII_PL_21_TO_27_VAL,
  2711. }, {
  2712. .reg = EXT_CTRL_REG,
  2713. .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
  2714. (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
  2715. MII_MDIO_MASK,
  2716. .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
  2717. | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
  2718. | MII_MDIO_10_11_VAL,
  2719. },
  2720. };
  2721. static struct spear_muxreg rmii0_1_ext_muxreg[] = {
  2722. {
  2723. .reg = IP_SEL_PAD_10_19_REG,
  2724. .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
  2725. PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
  2726. .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
  2727. PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
  2728. PMX_RMII_PL_19_VAL,
  2729. }, {
  2730. .reg = IP_SEL_PAD_20_29_REG,
  2731. .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
  2732. .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
  2733. }, {
  2734. .reg = EXT_CTRL_REG,
  2735. .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
  2736. (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
  2737. MII_MDIO_MASK,
  2738. .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
  2739. | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
  2740. | MII_MDIO_10_11_VAL,
  2741. },
  2742. };
  2743. static struct spear_modemux mii0_1_modemux[][2] = {
  2744. {
  2745. /* configure as smii */
  2746. {
  2747. .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
  2748. SMALL_PRINTERS_MODE | EXTENDED_MODE,
  2749. .muxregs = mii0_1_muxreg,
  2750. .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
  2751. }, {
  2752. .modes = EXTENDED_MODE,
  2753. .muxregs = smii0_1_ext_muxreg,
  2754. .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
  2755. },
  2756. }, {
  2757. /* configure as rmii */
  2758. {
  2759. .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
  2760. SMALL_PRINTERS_MODE | EXTENDED_MODE,
  2761. .muxregs = mii0_1_muxreg,
  2762. .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
  2763. }, {
  2764. .modes = EXTENDED_MODE,
  2765. .muxregs = rmii0_1_ext_muxreg,
  2766. .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
  2767. },
  2768. },
  2769. };
  2770. static struct spear_pingroup mii0_1_pingroup[] = {
  2771. {
  2772. .name = "smii0_1_grp",
  2773. .pins = smii0_1_pins,
  2774. .npins = ARRAY_SIZE(smii0_1_pins),
  2775. .modemuxs = mii0_1_modemux[0],
  2776. .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
  2777. }, {
  2778. .name = "rmii0_1_grp",
  2779. .pins = rmii0_1_pins,
  2780. .npins = ARRAY_SIZE(rmii0_1_pins),
  2781. .modemuxs = mii0_1_modemux[1],
  2782. .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
  2783. },
  2784. };
  2785. static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
  2786. static struct spear_function mii0_1_function = {
  2787. .name = "mii0_1",
  2788. .groups = mii0_1_grps,
  2789. .ngroups = ARRAY_SIZE(mii0_1_grps),
  2790. };
  2791. /* Pad multiplexing for i2c1 device */
  2792. static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
  2793. static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
  2794. {
  2795. .reg = PMX_CONFIG_REG,
  2796. .mask = PMX_SSP_CS_MASK,
  2797. .val = 0,
  2798. }, {
  2799. .reg = IP_SEL_PAD_0_9_REG,
  2800. .mask = PMX_PL_8_9_MASK,
  2801. .val = PMX_I2C1_PL_8_9_VAL,
  2802. }, {
  2803. .reg = IP_SEL_MIX_PAD_REG,
  2804. .mask = PMX_I2C1_PORT_SEL_MASK,
  2805. .val = PMX_I2C1_PORT_8_9_VAL,
  2806. },
  2807. };
  2808. static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
  2809. {
  2810. .reg = IP_SEL_PAD_90_99_REG,
  2811. .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
  2812. .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
  2813. }, {
  2814. .reg = IP_SEL_MIX_PAD_REG,
  2815. .mask = PMX_I2C1_PORT_SEL_MASK,
  2816. .val = PMX_I2C1_PORT_98_99_VAL,
  2817. },
  2818. };
  2819. static struct spear_modemux i2c1_modemux[][1] = {
  2820. {
  2821. /* Select signals on pins 8-9 */
  2822. {
  2823. .modes = EXTENDED_MODE,
  2824. .muxregs = i2c1_ext_8_9_muxreg,
  2825. .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
  2826. },
  2827. }, {
  2828. /* Select signals on pins 98-99 */
  2829. {
  2830. .modes = EXTENDED_MODE,
  2831. .muxregs = i2c1_ext_98_99_muxreg,
  2832. .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
  2833. },
  2834. },
  2835. };
  2836. static struct spear_pingroup i2c1_pingroup[] = {
  2837. {
  2838. .name = "i2c1_8_9_grp",
  2839. .pins = i2c1_pins[0],
  2840. .npins = ARRAY_SIZE(i2c1_pins[0]),
  2841. .modemuxs = i2c1_modemux[0],
  2842. .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
  2843. }, {
  2844. .name = "i2c1_98_99_grp",
  2845. .pins = i2c1_pins[1],
  2846. .npins = ARRAY_SIZE(i2c1_pins[1]),
  2847. .modemuxs = i2c1_modemux[1],
  2848. .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
  2849. },
  2850. };
  2851. static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
  2852. static struct spear_function i2c1_function = {
  2853. .name = "i2c1",
  2854. .groups = i2c1_grps,
  2855. .ngroups = ARRAY_SIZE(i2c1_grps),
  2856. };
  2857. /* Pad multiplexing for i2c2 device */
  2858. static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
  2859. { 75, 76 }, { 96, 97 } };
  2860. static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
  2861. {
  2862. .reg = PMX_CONFIG_REG,
  2863. .mask = PMX_FIRDA_MASK,
  2864. .val = 0,
  2865. }, {
  2866. .reg = IP_SEL_PAD_0_9_REG,
  2867. .mask = PMX_PL_0_1_MASK,
  2868. .val = PMX_I2C2_PL_0_1_VAL,
  2869. }, {
  2870. .reg = IP_SEL_MIX_PAD_REG,
  2871. .mask = PMX_I2C2_PORT_SEL_MASK,
  2872. .val = PMX_I2C2_PORT_0_1_VAL,
  2873. },
  2874. };
  2875. static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
  2876. {
  2877. .reg = PMX_CONFIG_REG,
  2878. .mask = PMX_UART0_MASK,
  2879. .val = 0,
  2880. }, {
  2881. .reg = IP_SEL_PAD_0_9_REG,
  2882. .mask = PMX_PL_2_3_MASK,
  2883. .val = PMX_I2C2_PL_2_3_VAL,
  2884. }, {
  2885. .reg = IP_SEL_MIX_PAD_REG,
  2886. .mask = PMX_I2C2_PORT_SEL_MASK,
  2887. .val = PMX_I2C2_PORT_2_3_VAL,
  2888. },
  2889. };
  2890. static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
  2891. {
  2892. .reg = PMX_CONFIG_REG,
  2893. .mask = PMX_MII_MASK,
  2894. .val = 0,
  2895. }, {
  2896. .reg = IP_SEL_PAD_10_19_REG,
  2897. .mask = PMX_PL_19_MASK,
  2898. .val = PMX_I2C2_PL_19_VAL,
  2899. }, {
  2900. .reg = IP_SEL_PAD_20_29_REG,
  2901. .mask = PMX_PL_20_MASK,
  2902. .val = PMX_I2C2_PL_20_VAL,
  2903. }, {
  2904. .reg = IP_SEL_MIX_PAD_REG,
  2905. .mask = PMX_I2C2_PORT_SEL_MASK,
  2906. .val = PMX_I2C2_PORT_19_20_VAL,
  2907. },
  2908. };
  2909. static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
  2910. {
  2911. .reg = IP_SEL_PAD_70_79_REG,
  2912. .mask = PMX_PL_75_76_MASK,
  2913. .val = PMX_I2C2_PL_75_76_VAL,
  2914. }, {
  2915. .reg = IP_SEL_MIX_PAD_REG,
  2916. .mask = PMX_I2C2_PORT_SEL_MASK,
  2917. .val = PMX_I2C2_PORT_75_76_VAL,
  2918. },
  2919. };
  2920. static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
  2921. {
  2922. .reg = IP_SEL_PAD_90_99_REG,
  2923. .mask = PMX_PL_96_97_MASK,
  2924. .val = PMX_I2C2_PL_96_97_VAL,
  2925. }, {
  2926. .reg = IP_SEL_MIX_PAD_REG,
  2927. .mask = PMX_I2C2_PORT_SEL_MASK,
  2928. .val = PMX_I2C2_PORT_96_97_VAL,
  2929. },
  2930. };
  2931. static struct spear_modemux i2c2_modemux[][1] = {
  2932. {
  2933. /* Select signals on pins 0_1 */
  2934. {
  2935. .modes = EXTENDED_MODE,
  2936. .muxregs = i2c2_ext_0_1_muxreg,
  2937. .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
  2938. },
  2939. }, {
  2940. /* Select signals on pins 2_3 */
  2941. {
  2942. .modes = EXTENDED_MODE,
  2943. .muxregs = i2c2_ext_2_3_muxreg,
  2944. .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
  2945. },
  2946. }, {
  2947. /* Select signals on pins 19_20 */
  2948. {
  2949. .modes = EXTENDED_MODE,
  2950. .muxregs = i2c2_ext_19_20_muxreg,
  2951. .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
  2952. },
  2953. }, {
  2954. /* Select signals on pins 75_76 */
  2955. {
  2956. .modes = EXTENDED_MODE,
  2957. .muxregs = i2c2_ext_75_76_muxreg,
  2958. .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
  2959. },
  2960. }, {
  2961. /* Select signals on pins 96_97 */
  2962. {
  2963. .modes = EXTENDED_MODE,
  2964. .muxregs = i2c2_ext_96_97_muxreg,
  2965. .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
  2966. },
  2967. },
  2968. };
  2969. static struct spear_pingroup i2c2_pingroup[] = {
  2970. {
  2971. .name = "i2c2_0_1_grp",
  2972. .pins = i2c2_pins[0],
  2973. .npins = ARRAY_SIZE(i2c2_pins[0]),
  2974. .modemuxs = i2c2_modemux[0],
  2975. .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
  2976. }, {
  2977. .name = "i2c2_2_3_grp",
  2978. .pins = i2c2_pins[1],
  2979. .npins = ARRAY_SIZE(i2c2_pins[1]),
  2980. .modemuxs = i2c2_modemux[1],
  2981. .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
  2982. }, {
  2983. .name = "i2c2_19_20_grp",
  2984. .pins = i2c2_pins[2],
  2985. .npins = ARRAY_SIZE(i2c2_pins[2]),
  2986. .modemuxs = i2c2_modemux[2],
  2987. .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
  2988. }, {
  2989. .name = "i2c2_75_76_grp",
  2990. .pins = i2c2_pins[3],
  2991. .npins = ARRAY_SIZE(i2c2_pins[3]),
  2992. .modemuxs = i2c2_modemux[3],
  2993. .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
  2994. }, {
  2995. .name = "i2c2_96_97_grp",
  2996. .pins = i2c2_pins[4],
  2997. .npins = ARRAY_SIZE(i2c2_pins[4]),
  2998. .modemuxs = i2c2_modemux[4],
  2999. .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
  3000. },
  3001. };
  3002. static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
  3003. "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
  3004. static struct spear_function i2c2_function = {
  3005. .name = "i2c2",
  3006. .groups = i2c2_grps,
  3007. .ngroups = ARRAY_SIZE(i2c2_grps),
  3008. };
  3009. /* pingroups */
  3010. static struct spear_pingroup *spear320_pingroups[] = {
  3011. SPEAR3XX_COMMON_PINGROUPS,
  3012. &clcd_pingroup,
  3013. &emi_pingroup,
  3014. &fsmc_8bit_pingroup,
  3015. &fsmc_16bit_pingroup,
  3016. &spp_pingroup,
  3017. &sdhci_led_pingroup,
  3018. &sdhci_pingroup[0],
  3019. &sdhci_pingroup[1],
  3020. &i2s_pingroup,
  3021. &uart1_pingroup,
  3022. &uart1_modem_pingroup[0],
  3023. &uart1_modem_pingroup[1],
  3024. &uart1_modem_pingroup[2],
  3025. &uart1_modem_pingroup[3],
  3026. &uart2_pingroup,
  3027. &uart3_pingroup[0],
  3028. &uart3_pingroup[1],
  3029. &uart3_pingroup[2],
  3030. &uart3_pingroup[3],
  3031. &uart3_pingroup[4],
  3032. &uart3_pingroup[5],
  3033. &uart3_pingroup[6],
  3034. &uart4_pingroup[0],
  3035. &uart4_pingroup[1],
  3036. &uart4_pingroup[2],
  3037. &uart4_pingroup[3],
  3038. &uart4_pingroup[4],
  3039. &uart4_pingroup[5],
  3040. &uart5_pingroup[0],
  3041. &uart5_pingroup[1],
  3042. &uart5_pingroup[2],
  3043. &uart5_pingroup[3],
  3044. &uart6_pingroup[0],
  3045. &uart6_pingroup[1],
  3046. &rs485_pingroup,
  3047. &touchscreen_pingroup,
  3048. &can0_pingroup,
  3049. &can1_pingroup,
  3050. &pwm0_1_pingroup[0],
  3051. &pwm0_1_pingroup[1],
  3052. &pwm0_1_pingroup[2],
  3053. &pwm0_1_pingroup[3],
  3054. &pwm0_1_pingroup[4],
  3055. &pwm0_1_pingroup[5],
  3056. &pwm0_1_pingroup[6],
  3057. &pwm2_pingroup[0],
  3058. &pwm2_pingroup[1],
  3059. &pwm2_pingroup[2],
  3060. &pwm2_pingroup[3],
  3061. &pwm2_pingroup[4],
  3062. &pwm2_pingroup[5],
  3063. &pwm2_pingroup[6],
  3064. &pwm3_pingroup[0],
  3065. &pwm3_pingroup[1],
  3066. &pwm3_pingroup[2],
  3067. &pwm3_pingroup[3],
  3068. &pwm3_pingroup[4],
  3069. &pwm3_pingroup[5],
  3070. &ssp1_pingroup[0],
  3071. &ssp1_pingroup[1],
  3072. &ssp1_pingroup[2],
  3073. &ssp1_pingroup[3],
  3074. &ssp1_pingroup[4],
  3075. &ssp2_pingroup[0],
  3076. &ssp2_pingroup[1],
  3077. &ssp2_pingroup[2],
  3078. &ssp2_pingroup[3],
  3079. &ssp2_pingroup[4],
  3080. &mii2_pingroup,
  3081. &mii0_1_pingroup[0],
  3082. &mii0_1_pingroup[1],
  3083. &i2c1_pingroup[0],
  3084. &i2c1_pingroup[1],
  3085. &i2c2_pingroup[0],
  3086. &i2c2_pingroup[1],
  3087. &i2c2_pingroup[2],
  3088. &i2c2_pingroup[3],
  3089. &i2c2_pingroup[4],
  3090. };
  3091. /* functions */
  3092. static struct spear_function *spear320_functions[] = {
  3093. SPEAR3XX_COMMON_FUNCTIONS,
  3094. &clcd_function,
  3095. &emi_function,
  3096. &fsmc_function,
  3097. &spp_function,
  3098. &sdhci_function,
  3099. &i2s_function,
  3100. &uart1_function,
  3101. &uart1_modem_function,
  3102. &uart2_function,
  3103. &uart3_function,
  3104. &uart4_function,
  3105. &uart5_function,
  3106. &uart6_function,
  3107. &rs485_function,
  3108. &touchscreen_function,
  3109. &can0_function,
  3110. &can1_function,
  3111. &pwm0_1_function,
  3112. &pwm2_function,
  3113. &pwm3_function,
  3114. &ssp1_function,
  3115. &ssp2_function,
  3116. &mii2_function,
  3117. &mii0_1_function,
  3118. &i2c1_function,
  3119. &i2c2_function,
  3120. };
  3121. static const struct of_device_id spear320_pinctrl_of_match[] = {
  3122. {
  3123. .compatible = "st,spear320-pinmux",
  3124. },
  3125. {},
  3126. };
  3127. static int spear320_pinctrl_probe(struct platform_device *pdev)
  3128. {
  3129. spear3xx_machdata.groups = spear320_pingroups;
  3130. spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
  3131. spear3xx_machdata.functions = spear320_functions;
  3132. spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
  3133. spear3xx_machdata.modes_supported = true;
  3134. spear3xx_machdata.pmx_modes = spear320_pmx_modes;
  3135. spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
  3136. pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
  3137. pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
  3138. spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
  3139. return spear_pinctrl_probe(pdev, &spear3xx_machdata);
  3140. }
  3141. static struct platform_driver spear320_pinctrl_driver = {
  3142. .driver = {
  3143. .name = DRIVER_NAME,
  3144. .of_match_table = spear320_pinctrl_of_match,
  3145. },
  3146. .probe = spear320_pinctrl_probe,
  3147. };
  3148. static int __init spear320_pinctrl_init(void)
  3149. {
  3150. return platform_driver_register(&spear320_pinctrl_driver);
  3151. }
  3152. arch_initcall(spear320_pinctrl_init);