pinctrl-spear1340.c 49 KB

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  1. /*
  2. * Driver for the ST Microelectronics SPEAr1340 pinmux
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Viresh Kumar <vireshk@kernel.org>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include "pinctrl-spear.h"
  16. #define DRIVER_NAME "spear1340-pinmux"
  17. /* pins */
  18. static const struct pinctrl_pin_desc spear1340_pins[] = {
  19. SPEAR_PIN_0_TO_101,
  20. SPEAR_PIN_102_TO_245,
  21. PINCTRL_PIN(246, "PLGPIO246"),
  22. PINCTRL_PIN(247, "PLGPIO247"),
  23. PINCTRL_PIN(248, "PLGPIO248"),
  24. PINCTRL_PIN(249, "PLGPIO249"),
  25. PINCTRL_PIN(250, "PLGPIO250"),
  26. PINCTRL_PIN(251, "PLGPIO251"),
  27. };
  28. /* In SPEAr1340 there are two levels of pad muxing */
  29. /* - pads as gpio OR peripherals */
  30. #define PAD_FUNCTION_EN_1 0x668
  31. #define PAD_FUNCTION_EN_2 0x66C
  32. #define PAD_FUNCTION_EN_3 0x670
  33. #define PAD_FUNCTION_EN_4 0x674
  34. #define PAD_FUNCTION_EN_5 0x690
  35. #define PAD_FUNCTION_EN_6 0x694
  36. #define PAD_FUNCTION_EN_7 0x698
  37. #define PAD_FUNCTION_EN_8 0x69C
  38. /* - If peripherals, then primary OR alternate peripheral */
  39. #define PAD_SHARED_IP_EN_1 0x6A0
  40. #define PAD_SHARED_IP_EN_2 0x6A4
  41. /*
  42. * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
  43. * registers with 32 bits each for handling gpio pads, register 8 has only 26
  44. * relevant bits.
  45. */
  46. /* macro's for making pads as gpio's */
  47. #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
  48. #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
  49. #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
  50. /* macro's for making pads as peripherals */
  51. #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
  52. #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
  53. #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
  54. #define I2C1_REG0_MASK 0x01080000
  55. #define SPDIF_IN_REG0_MASK 0x00100000
  56. #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
  57. #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
  58. #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
  59. #define VIP_AND_CAM3_REG0_MASK 0xFC200000
  60. #define VIP_AND_CAM3_REG1_MASK 0x0000000F
  61. #define VIP_REG1_MASK 0x00001EF0
  62. #define VIP_AND_CAM2_REG1_MASK 0x007FE100
  63. #define VIP_AND_CAM1_REG1_MASK 0xFF800000
  64. #define VIP_AND_CAM1_REG2_MASK 0x00000003
  65. #define VIP_AND_CAM0_REG2_MASK 0x00001FFC
  66. #define SMI_REG2_MASK 0x0021E000
  67. #define SSP0_REG2_MASK 0x001E0000
  68. #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
  69. #define UART0_REG2_MASK 0x01800000
  70. #define UART1_REG2_MASK 0x06000000
  71. #define I2S_IN_REG2_MASK 0xF8000000
  72. #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
  73. #define I2S_OUT_REG3_MASK 0x000001EF
  74. #define I2S_IN_REG3_MASK 0x00000010
  75. #define GMAC_REG3_MASK 0xFFFFFE00
  76. #define GMAC_REG4_MASK 0x0000001F
  77. #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
  78. #define SSP0_CS3_REG4_MASK 0x00000020
  79. #define I2C0_REG4_MASK 0x000000C0
  80. #define CEC0_REG4_MASK 0x00000100
  81. #define CEC1_REG4_MASK 0x00000200
  82. #define SPDIF_OUT_REG4_MASK 0x00000400
  83. #define CLCD_REG4_MASK 0x7FFFF800
  84. #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
  85. #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
  86. #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
  87. #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
  88. #define MCIF_REG6_MASK 0xF8C00000
  89. #define MCIF_REG7_MASK 0x000043FF
  90. #define FSMC_8BIT_REG7_MASK 0x07FFBC00
  91. /* other registers */
  92. #define PERIP_CFG 0x42C
  93. /* PERIP_CFG register masks */
  94. #define SSP_CS_CTL_HW 0
  95. #define SSP_CS_CTL_SW 1
  96. #define SSP_CS_CTL_MASK 1
  97. #define SSP_CS_CTL_SHIFT 21
  98. #define SSP_CS_VAL_MASK 1
  99. #define SSP_CS_VAL_SHIFT 20
  100. #define SSP_CS_SEL_CS0 0
  101. #define SSP_CS_SEL_CS1 1
  102. #define SSP_CS_SEL_CS2 2
  103. #define SSP_CS_SEL_MASK 3
  104. #define SSP_CS_SEL_SHIFT 18
  105. #define I2S_CHNL_2_0 (0)
  106. #define I2S_CHNL_3_1 (1)
  107. #define I2S_CHNL_5_1 (2)
  108. #define I2S_CHNL_7_1 (3)
  109. #define I2S_CHNL_PLAY_SHIFT (4)
  110. #define I2S_CHNL_PLAY_MASK (3 << 4)
  111. #define I2S_CHNL_REC_SHIFT (6)
  112. #define I2S_CHNL_REC_MASK (3 << 6)
  113. #define SPDIF_OUT_ENB_MASK (1 << 2)
  114. #define SPDIF_OUT_ENB_SHIFT 2
  115. #define MCIF_SEL_SD 1
  116. #define MCIF_SEL_CF 2
  117. #define MCIF_SEL_XD 3
  118. #define MCIF_SEL_MASK 3
  119. #define MCIF_SEL_SHIFT 0
  120. #define GMAC_CLK_CFG 0x248
  121. #define GMAC_PHY_IF_GMII_VAL (0 << 3)
  122. #define GMAC_PHY_IF_RGMII_VAL (1 << 3)
  123. #define GMAC_PHY_IF_SGMII_VAL (2 << 3)
  124. #define GMAC_PHY_IF_RMII_VAL (4 << 3)
  125. #define GMAC_PHY_IF_SEL_MASK (7 << 3)
  126. #define GMAC_PHY_INPUT_ENB_VAL 0
  127. #define GMAC_PHY_SYNT_ENB_VAL 1
  128. #define GMAC_PHY_CLK_MASK 1
  129. #define GMAC_PHY_CLK_SHIFT 2
  130. #define GMAC_PHY_125M_PAD_VAL 0
  131. #define GMAC_PHY_PLL2_VAL 1
  132. #define GMAC_PHY_OSC3_VAL 2
  133. #define GMAC_PHY_INPUT_CLK_MASK 3
  134. #define GMAC_PHY_INPUT_CLK_SHIFT 0
  135. #define PCIE_SATA_CFG 0x424
  136. /* PCIE CFG MASks */
  137. #define PCIE_CFG_DEVICE_PRESENT (1 << 11)
  138. #define PCIE_CFG_POWERUP_RESET (1 << 10)
  139. #define PCIE_CFG_CORE_CLK_EN (1 << 9)
  140. #define PCIE_CFG_AUX_CLK_EN (1 << 8)
  141. #define SATA_CFG_TX_CLK_EN (1 << 4)
  142. #define SATA_CFG_RX_CLK_EN (1 << 3)
  143. #define SATA_CFG_POWERUP_RESET (1 << 2)
  144. #define SATA_CFG_PM_CLK_EN (1 << 1)
  145. #define PCIE_SATA_SEL_PCIE (0)
  146. #define PCIE_SATA_SEL_SATA (1)
  147. #define SATA_PCIE_CFG_MASK 0xF1F
  148. #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
  149. PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
  150. PCIE_CFG_DEVICE_PRESENT)
  151. #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
  152. SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
  153. SATA_CFG_TX_CLK_EN)
  154. /* Macro's for second level of pmx - pads as primary OR alternate peripheral */
  155. /* Write 0 to enable FSMC_16_BIT */
  156. #define KBD_ROW_COL_MASK (1 << 0)
  157. /* Write 0 to enable UART0_ENH */
  158. #define GPT_MASK (1 << 1) /* Only clk & cpt */
  159. /* Write 0 to enable PWM1 */
  160. #define KBD_COL5_MASK (1 << 2)
  161. /* Write 0 to enable PWM2 */
  162. #define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
  163. /* Write 0 to enable PWM3 */
  164. #define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
  165. /* Write 0 to enable PWM0 */
  166. #define SSP0_CS1_MASK (1 << 5)
  167. /* Write 0 to enable VIP */
  168. #define CAM3_MASK (1 << 6)
  169. /* Write 0 to enable VIP */
  170. #define CAM2_MASK (1 << 7)
  171. /* Write 0 to enable VIP */
  172. #define CAM1_MASK (1 << 8)
  173. /* Write 0 to enable VIP */
  174. #define CAM0_MASK (1 << 9)
  175. /* Write 0 to enable TS */
  176. #define SSP0_CS2_MASK (1 << 10)
  177. /* Write 0 to enable FSMC PNOR */
  178. #define MCIF_MASK (1 << 11)
  179. /* Write 0 to enable CLCD */
  180. #define ARM_TRACE_MASK (1 << 12)
  181. /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
  182. #define MIPHY_DBG_MASK (1 << 13)
  183. /*
  184. * Pad multiplexing for making all pads as gpio's. This is done to override the
  185. * values passed from bootloader and start from scratch.
  186. */
  187. static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 };
  188. static struct spear_muxreg pads_as_gpio_muxreg[] = {
  189. {
  190. .reg = PAD_FUNCTION_EN_1,
  191. .mask = PADS_AS_GPIO_REG0_MASK,
  192. .val = 0x0,
  193. }, {
  194. .reg = PAD_FUNCTION_EN_2,
  195. .mask = PADS_AS_GPIO_REGS_MASK,
  196. .val = 0x0,
  197. }, {
  198. .reg = PAD_FUNCTION_EN_3,
  199. .mask = PADS_AS_GPIO_REGS_MASK,
  200. .val = 0x0,
  201. }, {
  202. .reg = PAD_FUNCTION_EN_4,
  203. .mask = PADS_AS_GPIO_REGS_MASK,
  204. .val = 0x0,
  205. }, {
  206. .reg = PAD_FUNCTION_EN_5,
  207. .mask = PADS_AS_GPIO_REGS_MASK,
  208. .val = 0x0,
  209. }, {
  210. .reg = PAD_FUNCTION_EN_6,
  211. .mask = PADS_AS_GPIO_REGS_MASK,
  212. .val = 0x0,
  213. }, {
  214. .reg = PAD_FUNCTION_EN_7,
  215. .mask = PADS_AS_GPIO_REGS_MASK,
  216. .val = 0x0,
  217. }, {
  218. .reg = PAD_FUNCTION_EN_8,
  219. .mask = PADS_AS_GPIO_REG7_MASK,
  220. .val = 0x0,
  221. },
  222. };
  223. static struct spear_modemux pads_as_gpio_modemux[] = {
  224. {
  225. .muxregs = pads_as_gpio_muxreg,
  226. .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
  227. },
  228. };
  229. static struct spear_pingroup pads_as_gpio_pingroup = {
  230. .name = "pads_as_gpio_grp",
  231. .pins = pads_as_gpio_pins,
  232. .npins = ARRAY_SIZE(pads_as_gpio_pins),
  233. .modemuxs = pads_as_gpio_modemux,
  234. .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
  235. };
  236. static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
  237. static struct spear_function pads_as_gpio_function = {
  238. .name = "pads_as_gpio",
  239. .groups = pads_as_gpio_grps,
  240. .ngroups = ARRAY_SIZE(pads_as_gpio_grps),
  241. };
  242. /* Pad multiplexing for fsmc_8bit device */
  243. static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
  244. 241, 242, 243, 244, 245, 246, 247, 248, 249 };
  245. static struct spear_muxreg fsmc_8bit_muxreg[] = {
  246. {
  247. .reg = PAD_FUNCTION_EN_8,
  248. .mask = FSMC_8BIT_REG7_MASK,
  249. .val = FSMC_8BIT_REG7_MASK,
  250. }
  251. };
  252. static struct spear_modemux fsmc_8bit_modemux[] = {
  253. {
  254. .muxregs = fsmc_8bit_muxreg,
  255. .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
  256. },
  257. };
  258. static struct spear_pingroup fsmc_8bit_pingroup = {
  259. .name = "fsmc_8bit_grp",
  260. .pins = fsmc_8bit_pins,
  261. .npins = ARRAY_SIZE(fsmc_8bit_pins),
  262. .modemuxs = fsmc_8bit_modemux,
  263. .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
  264. };
  265. /* Pad multiplexing for fsmc_16bit device */
  266. static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
  267. static struct spear_muxreg fsmc_16bit_muxreg[] = {
  268. {
  269. .reg = PAD_SHARED_IP_EN_1,
  270. .mask = KBD_ROW_COL_MASK,
  271. .val = 0,
  272. }, {
  273. .reg = PAD_FUNCTION_EN_1,
  274. .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
  275. .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
  276. },
  277. };
  278. static struct spear_modemux fsmc_16bit_modemux[] = {
  279. {
  280. .muxregs = fsmc_16bit_muxreg,
  281. .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
  282. },
  283. };
  284. static struct spear_pingroup fsmc_16bit_pingroup = {
  285. .name = "fsmc_16bit_grp",
  286. .pins = fsmc_16bit_pins,
  287. .npins = ARRAY_SIZE(fsmc_16bit_pins),
  288. .modemuxs = fsmc_16bit_modemux,
  289. .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
  290. };
  291. /* pad multiplexing for fsmc_pnor device */
  292. static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
  293. 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
  294. 215, 216, 217 };
  295. static struct spear_muxreg fsmc_pnor_muxreg[] = {
  296. {
  297. .reg = PAD_SHARED_IP_EN_1,
  298. .mask = MCIF_MASK,
  299. .val = 0,
  300. }, {
  301. .reg = PAD_FUNCTION_EN_7,
  302. .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
  303. .val = FSMC_PNOR_AND_MCIF_REG6_MASK,
  304. },
  305. };
  306. static struct spear_modemux fsmc_pnor_modemux[] = {
  307. {
  308. .muxregs = fsmc_pnor_muxreg,
  309. .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
  310. },
  311. };
  312. static struct spear_pingroup fsmc_pnor_pingroup = {
  313. .name = "fsmc_pnor_grp",
  314. .pins = fsmc_pnor_pins,
  315. .npins = ARRAY_SIZE(fsmc_pnor_pins),
  316. .modemuxs = fsmc_pnor_modemux,
  317. .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
  318. };
  319. static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
  320. "fsmc_pnor_grp" };
  321. static struct spear_function fsmc_function = {
  322. .name = "fsmc",
  323. .groups = fsmc_grps,
  324. .ngroups = ARRAY_SIZE(fsmc_grps),
  325. };
  326. /* pad multiplexing for keyboard rows-cols device */
  327. static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
  328. 10 };
  329. static struct spear_muxreg keyboard_row_col_muxreg[] = {
  330. {
  331. .reg = PAD_SHARED_IP_EN_1,
  332. .mask = KBD_ROW_COL_MASK,
  333. .val = KBD_ROW_COL_MASK,
  334. }, {
  335. .reg = PAD_FUNCTION_EN_1,
  336. .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
  337. .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
  338. },
  339. };
  340. static struct spear_modemux keyboard_row_col_modemux[] = {
  341. {
  342. .muxregs = keyboard_row_col_muxreg,
  343. .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
  344. },
  345. };
  346. static struct spear_pingroup keyboard_row_col_pingroup = {
  347. .name = "keyboard_row_col_grp",
  348. .pins = keyboard_row_col_pins,
  349. .npins = ARRAY_SIZE(keyboard_row_col_pins),
  350. .modemuxs = keyboard_row_col_modemux,
  351. .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
  352. };
  353. /* pad multiplexing for keyboard col5 device */
  354. static const unsigned keyboard_col5_pins[] = { 17 };
  355. static struct spear_muxreg keyboard_col5_muxreg[] = {
  356. {
  357. .reg = PAD_SHARED_IP_EN_1,
  358. .mask = KBD_COL5_MASK,
  359. .val = KBD_COL5_MASK,
  360. }, {
  361. .reg = PAD_FUNCTION_EN_1,
  362. .mask = PWM1_AND_KBD_COL5_REG0_MASK,
  363. .val = PWM1_AND_KBD_COL5_REG0_MASK,
  364. },
  365. };
  366. static struct spear_modemux keyboard_col5_modemux[] = {
  367. {
  368. .muxregs = keyboard_col5_muxreg,
  369. .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
  370. },
  371. };
  372. static struct spear_pingroup keyboard_col5_pingroup = {
  373. .name = "keyboard_col5_grp",
  374. .pins = keyboard_col5_pins,
  375. .npins = ARRAY_SIZE(keyboard_col5_pins),
  376. .modemuxs = keyboard_col5_modemux,
  377. .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
  378. };
  379. static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
  380. "keyboard_col5_grp" };
  381. static struct spear_function keyboard_function = {
  382. .name = "keyboard",
  383. .groups = keyboard_grps,
  384. .ngroups = ARRAY_SIZE(keyboard_grps),
  385. };
  386. /* pad multiplexing for spdif_in device */
  387. static const unsigned spdif_in_pins[] = { 19 };
  388. static struct spear_muxreg spdif_in_muxreg[] = {
  389. {
  390. .reg = PAD_FUNCTION_EN_1,
  391. .mask = SPDIF_IN_REG0_MASK,
  392. .val = SPDIF_IN_REG0_MASK,
  393. },
  394. };
  395. static struct spear_modemux spdif_in_modemux[] = {
  396. {
  397. .muxregs = spdif_in_muxreg,
  398. .nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
  399. },
  400. };
  401. static struct spear_pingroup spdif_in_pingroup = {
  402. .name = "spdif_in_grp",
  403. .pins = spdif_in_pins,
  404. .npins = ARRAY_SIZE(spdif_in_pins),
  405. .modemuxs = spdif_in_modemux,
  406. .nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
  407. };
  408. static const char *const spdif_in_grps[] = { "spdif_in_grp" };
  409. static struct spear_function spdif_in_function = {
  410. .name = "spdif_in",
  411. .groups = spdif_in_grps,
  412. .ngroups = ARRAY_SIZE(spdif_in_grps),
  413. };
  414. /* pad multiplexing for spdif_out device */
  415. static const unsigned spdif_out_pins[] = { 137 };
  416. static struct spear_muxreg spdif_out_muxreg[] = {
  417. {
  418. .reg = PAD_FUNCTION_EN_5,
  419. .mask = SPDIF_OUT_REG4_MASK,
  420. .val = SPDIF_OUT_REG4_MASK,
  421. }, {
  422. .reg = PERIP_CFG,
  423. .mask = SPDIF_OUT_ENB_MASK,
  424. .val = SPDIF_OUT_ENB_MASK,
  425. }
  426. };
  427. static struct spear_modemux spdif_out_modemux[] = {
  428. {
  429. .muxregs = spdif_out_muxreg,
  430. .nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
  431. },
  432. };
  433. static struct spear_pingroup spdif_out_pingroup = {
  434. .name = "spdif_out_grp",
  435. .pins = spdif_out_pins,
  436. .npins = ARRAY_SIZE(spdif_out_pins),
  437. .modemuxs = spdif_out_modemux,
  438. .nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
  439. };
  440. static const char *const spdif_out_grps[] = { "spdif_out_grp" };
  441. static struct spear_function spdif_out_function = {
  442. .name = "spdif_out",
  443. .groups = spdif_out_grps,
  444. .ngroups = ARRAY_SIZE(spdif_out_grps),
  445. };
  446. /* pad multiplexing for gpt_0_1 device */
  447. static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
  448. static struct spear_muxreg gpt_0_1_muxreg[] = {
  449. {
  450. .reg = PAD_SHARED_IP_EN_1,
  451. .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
  452. .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
  453. }, {
  454. .reg = PAD_FUNCTION_EN_1,
  455. .mask = UART0_ENH_AND_GPT_REG0_MASK |
  456. PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
  457. PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
  458. .val = UART0_ENH_AND_GPT_REG0_MASK |
  459. PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
  460. PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
  461. },
  462. };
  463. static struct spear_modemux gpt_0_1_modemux[] = {
  464. {
  465. .muxregs = gpt_0_1_muxreg,
  466. .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
  467. },
  468. };
  469. static struct spear_pingroup gpt_0_1_pingroup = {
  470. .name = "gpt_0_1_grp",
  471. .pins = gpt_0_1_pins,
  472. .npins = ARRAY_SIZE(gpt_0_1_pins),
  473. .modemuxs = gpt_0_1_modemux,
  474. .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
  475. };
  476. static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
  477. static struct spear_function gpt_0_1_function = {
  478. .name = "gpt_0_1",
  479. .groups = gpt_0_1_grps,
  480. .ngroups = ARRAY_SIZE(gpt_0_1_grps),
  481. };
  482. /* pad multiplexing for pwm0 device */
  483. static const unsigned pwm0_pins[] = { 24 };
  484. static struct spear_muxreg pwm0_muxreg[] = {
  485. {
  486. .reg = PAD_SHARED_IP_EN_1,
  487. .mask = SSP0_CS1_MASK,
  488. .val = 0,
  489. }, {
  490. .reg = PAD_FUNCTION_EN_1,
  491. .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
  492. .val = PWM0_AND_SSP0_CS1_REG0_MASK,
  493. },
  494. };
  495. static struct spear_modemux pwm0_modemux[] = {
  496. {
  497. .muxregs = pwm0_muxreg,
  498. .nmuxregs = ARRAY_SIZE(pwm0_muxreg),
  499. },
  500. };
  501. static struct spear_pingroup pwm0_pingroup = {
  502. .name = "pwm0_grp",
  503. .pins = pwm0_pins,
  504. .npins = ARRAY_SIZE(pwm0_pins),
  505. .modemuxs = pwm0_modemux,
  506. .nmodemuxs = ARRAY_SIZE(pwm0_modemux),
  507. };
  508. /* pad multiplexing for pwm1 device */
  509. static const unsigned pwm1_pins[] = { 17 };
  510. static struct spear_muxreg pwm1_muxreg[] = {
  511. {
  512. .reg = PAD_SHARED_IP_EN_1,
  513. .mask = KBD_COL5_MASK,
  514. .val = 0,
  515. }, {
  516. .reg = PAD_FUNCTION_EN_1,
  517. .mask = PWM1_AND_KBD_COL5_REG0_MASK,
  518. .val = PWM1_AND_KBD_COL5_REG0_MASK,
  519. },
  520. };
  521. static struct spear_modemux pwm1_modemux[] = {
  522. {
  523. .muxregs = pwm1_muxreg,
  524. .nmuxregs = ARRAY_SIZE(pwm1_muxreg),
  525. },
  526. };
  527. static struct spear_pingroup pwm1_pingroup = {
  528. .name = "pwm1_grp",
  529. .pins = pwm1_pins,
  530. .npins = ARRAY_SIZE(pwm1_pins),
  531. .modemuxs = pwm1_modemux,
  532. .nmodemuxs = ARRAY_SIZE(pwm1_modemux),
  533. };
  534. /* pad multiplexing for pwm2 device */
  535. static const unsigned pwm2_pins[] = { 21 };
  536. static struct spear_muxreg pwm2_muxreg[] = {
  537. {
  538. .reg = PAD_SHARED_IP_EN_1,
  539. .mask = GPT0_TMR0_CPT_MASK,
  540. .val = 0,
  541. }, {
  542. .reg = PAD_FUNCTION_EN_1,
  543. .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
  544. .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
  545. },
  546. };
  547. static struct spear_modemux pwm2_modemux[] = {
  548. {
  549. .muxregs = pwm2_muxreg,
  550. .nmuxregs = ARRAY_SIZE(pwm2_muxreg),
  551. },
  552. };
  553. static struct spear_pingroup pwm2_pingroup = {
  554. .name = "pwm2_grp",
  555. .pins = pwm2_pins,
  556. .npins = ARRAY_SIZE(pwm2_pins),
  557. .modemuxs = pwm2_modemux,
  558. .nmodemuxs = ARRAY_SIZE(pwm2_modemux),
  559. };
  560. /* pad multiplexing for pwm3 device */
  561. static const unsigned pwm3_pins[] = { 22 };
  562. static struct spear_muxreg pwm3_muxreg[] = {
  563. {
  564. .reg = PAD_SHARED_IP_EN_1,
  565. .mask = GPT0_TMR1_CLK_MASK,
  566. .val = 0,
  567. }, {
  568. .reg = PAD_FUNCTION_EN_1,
  569. .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
  570. .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
  571. },
  572. };
  573. static struct spear_modemux pwm3_modemux[] = {
  574. {
  575. .muxregs = pwm3_muxreg,
  576. .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
  577. },
  578. };
  579. static struct spear_pingroup pwm3_pingroup = {
  580. .name = "pwm3_grp",
  581. .pins = pwm3_pins,
  582. .npins = ARRAY_SIZE(pwm3_pins),
  583. .modemuxs = pwm3_modemux,
  584. .nmodemuxs = ARRAY_SIZE(pwm3_modemux),
  585. };
  586. static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
  587. "pwm3_grp" };
  588. static struct spear_function pwm_function = {
  589. .name = "pwm",
  590. .groups = pwm_grps,
  591. .ngroups = ARRAY_SIZE(pwm_grps),
  592. };
  593. /* pad multiplexing for vip_mux device */
  594. static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
  595. static struct spear_muxreg vip_mux_muxreg[] = {
  596. {
  597. .reg = PAD_FUNCTION_EN_2,
  598. .mask = VIP_REG1_MASK,
  599. .val = VIP_REG1_MASK,
  600. },
  601. };
  602. static struct spear_modemux vip_mux_modemux[] = {
  603. {
  604. .muxregs = vip_mux_muxreg,
  605. .nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
  606. },
  607. };
  608. static struct spear_pingroup vip_mux_pingroup = {
  609. .name = "vip_mux_grp",
  610. .pins = vip_mux_pins,
  611. .npins = ARRAY_SIZE(vip_mux_pins),
  612. .modemuxs = vip_mux_modemux,
  613. .nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
  614. };
  615. /* pad multiplexing for vip_mux_cam0 (disables cam0) device */
  616. static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
  617. 73, 74, 75 };
  618. static struct spear_muxreg vip_mux_cam0_muxreg[] = {
  619. {
  620. .reg = PAD_SHARED_IP_EN_1,
  621. .mask = CAM0_MASK,
  622. .val = 0,
  623. }, {
  624. .reg = PAD_FUNCTION_EN_3,
  625. .mask = VIP_AND_CAM0_REG2_MASK,
  626. .val = VIP_AND_CAM0_REG2_MASK,
  627. },
  628. };
  629. static struct spear_modemux vip_mux_cam0_modemux[] = {
  630. {
  631. .muxregs = vip_mux_cam0_muxreg,
  632. .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
  633. },
  634. };
  635. static struct spear_pingroup vip_mux_cam0_pingroup = {
  636. .name = "vip_mux_cam0_grp",
  637. .pins = vip_mux_cam0_pins,
  638. .npins = ARRAY_SIZE(vip_mux_cam0_pins),
  639. .modemuxs = vip_mux_cam0_modemux,
  640. .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
  641. };
  642. /* pad multiplexing for vip_mux_cam1 (disables cam1) device */
  643. static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
  644. 62, 63, 64 };
  645. static struct spear_muxreg vip_mux_cam1_muxreg[] = {
  646. {
  647. .reg = PAD_SHARED_IP_EN_1,
  648. .mask = CAM1_MASK,
  649. .val = 0,
  650. }, {
  651. .reg = PAD_FUNCTION_EN_2,
  652. .mask = VIP_AND_CAM1_REG1_MASK,
  653. .val = VIP_AND_CAM1_REG1_MASK,
  654. }, {
  655. .reg = PAD_FUNCTION_EN_3,
  656. .mask = VIP_AND_CAM1_REG2_MASK,
  657. .val = VIP_AND_CAM1_REG2_MASK,
  658. },
  659. };
  660. static struct spear_modemux vip_mux_cam1_modemux[] = {
  661. {
  662. .muxregs = vip_mux_cam1_muxreg,
  663. .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
  664. },
  665. };
  666. static struct spear_pingroup vip_mux_cam1_pingroup = {
  667. .name = "vip_mux_cam1_grp",
  668. .pins = vip_mux_cam1_pins,
  669. .npins = ARRAY_SIZE(vip_mux_cam1_pins),
  670. .modemuxs = vip_mux_cam1_modemux,
  671. .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
  672. };
  673. /* pad multiplexing for vip_mux_cam2 (disables cam2) device */
  674. static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
  675. 51, 52, 53 };
  676. static struct spear_muxreg vip_mux_cam2_muxreg[] = {
  677. {
  678. .reg = PAD_SHARED_IP_EN_1,
  679. .mask = CAM2_MASK,
  680. .val = 0,
  681. }, {
  682. .reg = PAD_FUNCTION_EN_2,
  683. .mask = VIP_AND_CAM2_REG1_MASK,
  684. .val = VIP_AND_CAM2_REG1_MASK,
  685. },
  686. };
  687. static struct spear_modemux vip_mux_cam2_modemux[] = {
  688. {
  689. .muxregs = vip_mux_cam2_muxreg,
  690. .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
  691. },
  692. };
  693. static struct spear_pingroup vip_mux_cam2_pingroup = {
  694. .name = "vip_mux_cam2_grp",
  695. .pins = vip_mux_cam2_pins,
  696. .npins = ARRAY_SIZE(vip_mux_cam2_pins),
  697. .modemuxs = vip_mux_cam2_modemux,
  698. .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
  699. };
  700. /* pad multiplexing for vip_mux_cam3 (disables cam3) device */
  701. static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
  702. 32, 33, 34 };
  703. static struct spear_muxreg vip_mux_cam3_muxreg[] = {
  704. {
  705. .reg = PAD_SHARED_IP_EN_1,
  706. .mask = CAM3_MASK,
  707. .val = 0,
  708. }, {
  709. .reg = PAD_FUNCTION_EN_1,
  710. .mask = VIP_AND_CAM3_REG0_MASK,
  711. .val = VIP_AND_CAM3_REG0_MASK,
  712. }, {
  713. .reg = PAD_FUNCTION_EN_2,
  714. .mask = VIP_AND_CAM3_REG1_MASK,
  715. .val = VIP_AND_CAM3_REG1_MASK,
  716. },
  717. };
  718. static struct spear_modemux vip_mux_cam3_modemux[] = {
  719. {
  720. .muxregs = vip_mux_cam3_muxreg,
  721. .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
  722. },
  723. };
  724. static struct spear_pingroup vip_mux_cam3_pingroup = {
  725. .name = "vip_mux_cam3_grp",
  726. .pins = vip_mux_cam3_pins,
  727. .npins = ARRAY_SIZE(vip_mux_cam3_pins),
  728. .modemuxs = vip_mux_cam3_modemux,
  729. .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
  730. };
  731. static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
  732. "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
  733. static struct spear_function vip_function = {
  734. .name = "vip",
  735. .groups = vip_grps,
  736. .ngroups = ARRAY_SIZE(vip_grps),
  737. };
  738. /* pad multiplexing for cam0 device */
  739. static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
  740. };
  741. static struct spear_muxreg cam0_muxreg[] = {
  742. {
  743. .reg = PAD_SHARED_IP_EN_1,
  744. .mask = CAM0_MASK,
  745. .val = CAM0_MASK,
  746. }, {
  747. .reg = PAD_FUNCTION_EN_3,
  748. .mask = VIP_AND_CAM0_REG2_MASK,
  749. .val = VIP_AND_CAM0_REG2_MASK,
  750. },
  751. };
  752. static struct spear_modemux cam0_modemux[] = {
  753. {
  754. .muxregs = cam0_muxreg,
  755. .nmuxregs = ARRAY_SIZE(cam0_muxreg),
  756. },
  757. };
  758. static struct spear_pingroup cam0_pingroup = {
  759. .name = "cam0_grp",
  760. .pins = cam0_pins,
  761. .npins = ARRAY_SIZE(cam0_pins),
  762. .modemuxs = cam0_modemux,
  763. .nmodemuxs = ARRAY_SIZE(cam0_modemux),
  764. };
  765. static const char *const cam0_grps[] = { "cam0_grp" };
  766. static struct spear_function cam0_function = {
  767. .name = "cam0",
  768. .groups = cam0_grps,
  769. .ngroups = ARRAY_SIZE(cam0_grps),
  770. };
  771. /* pad multiplexing for cam1 device */
  772. static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
  773. };
  774. static struct spear_muxreg cam1_muxreg[] = {
  775. {
  776. .reg = PAD_SHARED_IP_EN_1,
  777. .mask = CAM1_MASK,
  778. .val = CAM1_MASK,
  779. }, {
  780. .reg = PAD_FUNCTION_EN_2,
  781. .mask = VIP_AND_CAM1_REG1_MASK,
  782. .val = VIP_AND_CAM1_REG1_MASK,
  783. }, {
  784. .reg = PAD_FUNCTION_EN_3,
  785. .mask = VIP_AND_CAM1_REG2_MASK,
  786. .val = VIP_AND_CAM1_REG2_MASK,
  787. },
  788. };
  789. static struct spear_modemux cam1_modemux[] = {
  790. {
  791. .muxregs = cam1_muxreg,
  792. .nmuxregs = ARRAY_SIZE(cam1_muxreg),
  793. },
  794. };
  795. static struct spear_pingroup cam1_pingroup = {
  796. .name = "cam1_grp",
  797. .pins = cam1_pins,
  798. .npins = ARRAY_SIZE(cam1_pins),
  799. .modemuxs = cam1_modemux,
  800. .nmodemuxs = ARRAY_SIZE(cam1_modemux),
  801. };
  802. static const char *const cam1_grps[] = { "cam1_grp" };
  803. static struct spear_function cam1_function = {
  804. .name = "cam1",
  805. .groups = cam1_grps,
  806. .ngroups = ARRAY_SIZE(cam1_grps),
  807. };
  808. /* pad multiplexing for cam2 device */
  809. static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
  810. };
  811. static struct spear_muxreg cam2_muxreg[] = {
  812. {
  813. .reg = PAD_SHARED_IP_EN_1,
  814. .mask = CAM2_MASK,
  815. .val = CAM2_MASK,
  816. }, {
  817. .reg = PAD_FUNCTION_EN_2,
  818. .mask = VIP_AND_CAM2_REG1_MASK,
  819. .val = VIP_AND_CAM2_REG1_MASK,
  820. },
  821. };
  822. static struct spear_modemux cam2_modemux[] = {
  823. {
  824. .muxregs = cam2_muxreg,
  825. .nmuxregs = ARRAY_SIZE(cam2_muxreg),
  826. },
  827. };
  828. static struct spear_pingroup cam2_pingroup = {
  829. .name = "cam2_grp",
  830. .pins = cam2_pins,
  831. .npins = ARRAY_SIZE(cam2_pins),
  832. .modemuxs = cam2_modemux,
  833. .nmodemuxs = ARRAY_SIZE(cam2_modemux),
  834. };
  835. static const char *const cam2_grps[] = { "cam2_grp" };
  836. static struct spear_function cam2_function = {
  837. .name = "cam2",
  838. .groups = cam2_grps,
  839. .ngroups = ARRAY_SIZE(cam2_grps),
  840. };
  841. /* pad multiplexing for cam3 device */
  842. static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
  843. };
  844. static struct spear_muxreg cam3_muxreg[] = {
  845. {
  846. .reg = PAD_SHARED_IP_EN_1,
  847. .mask = CAM3_MASK,
  848. .val = CAM3_MASK,
  849. }, {
  850. .reg = PAD_FUNCTION_EN_1,
  851. .mask = VIP_AND_CAM3_REG0_MASK,
  852. .val = VIP_AND_CAM3_REG0_MASK,
  853. }, {
  854. .reg = PAD_FUNCTION_EN_2,
  855. .mask = VIP_AND_CAM3_REG1_MASK,
  856. .val = VIP_AND_CAM3_REG1_MASK,
  857. },
  858. };
  859. static struct spear_modemux cam3_modemux[] = {
  860. {
  861. .muxregs = cam3_muxreg,
  862. .nmuxregs = ARRAY_SIZE(cam3_muxreg),
  863. },
  864. };
  865. static struct spear_pingroup cam3_pingroup = {
  866. .name = "cam3_grp",
  867. .pins = cam3_pins,
  868. .npins = ARRAY_SIZE(cam3_pins),
  869. .modemuxs = cam3_modemux,
  870. .nmodemuxs = ARRAY_SIZE(cam3_modemux),
  871. };
  872. static const char *const cam3_grps[] = { "cam3_grp" };
  873. static struct spear_function cam3_function = {
  874. .name = "cam3",
  875. .groups = cam3_grps,
  876. .ngroups = ARRAY_SIZE(cam3_grps),
  877. };
  878. /* pad multiplexing for smi device */
  879. static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
  880. static struct spear_muxreg smi_muxreg[] = {
  881. {
  882. .reg = PAD_FUNCTION_EN_3,
  883. .mask = SMI_REG2_MASK,
  884. .val = SMI_REG2_MASK,
  885. },
  886. };
  887. static struct spear_modemux smi_modemux[] = {
  888. {
  889. .muxregs = smi_muxreg,
  890. .nmuxregs = ARRAY_SIZE(smi_muxreg),
  891. },
  892. };
  893. static struct spear_pingroup smi_pingroup = {
  894. .name = "smi_grp",
  895. .pins = smi_pins,
  896. .npins = ARRAY_SIZE(smi_pins),
  897. .modemuxs = smi_modemux,
  898. .nmodemuxs = ARRAY_SIZE(smi_modemux),
  899. };
  900. static const char *const smi_grps[] = { "smi_grp" };
  901. static struct spear_function smi_function = {
  902. .name = "smi",
  903. .groups = smi_grps,
  904. .ngroups = ARRAY_SIZE(smi_grps),
  905. };
  906. /* pad multiplexing for ssp0 device */
  907. static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
  908. static struct spear_muxreg ssp0_muxreg[] = {
  909. {
  910. .reg = PAD_FUNCTION_EN_3,
  911. .mask = SSP0_REG2_MASK,
  912. .val = SSP0_REG2_MASK,
  913. },
  914. };
  915. static struct spear_modemux ssp0_modemux[] = {
  916. {
  917. .muxregs = ssp0_muxreg,
  918. .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
  919. },
  920. };
  921. static struct spear_pingroup ssp0_pingroup = {
  922. .name = "ssp0_grp",
  923. .pins = ssp0_pins,
  924. .npins = ARRAY_SIZE(ssp0_pins),
  925. .modemuxs = ssp0_modemux,
  926. .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
  927. };
  928. /* pad multiplexing for ssp0_cs1 device */
  929. static const unsigned ssp0_cs1_pins[] = { 24 };
  930. static struct spear_muxreg ssp0_cs1_muxreg[] = {
  931. {
  932. .reg = PAD_SHARED_IP_EN_1,
  933. .mask = SSP0_CS1_MASK,
  934. .val = SSP0_CS1_MASK,
  935. }, {
  936. .reg = PAD_FUNCTION_EN_1,
  937. .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
  938. .val = PWM0_AND_SSP0_CS1_REG0_MASK,
  939. },
  940. };
  941. static struct spear_modemux ssp0_cs1_modemux[] = {
  942. {
  943. .muxregs = ssp0_cs1_muxreg,
  944. .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
  945. },
  946. };
  947. static struct spear_pingroup ssp0_cs1_pingroup = {
  948. .name = "ssp0_cs1_grp",
  949. .pins = ssp0_cs1_pins,
  950. .npins = ARRAY_SIZE(ssp0_cs1_pins),
  951. .modemuxs = ssp0_cs1_modemux,
  952. .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
  953. };
  954. /* pad multiplexing for ssp0_cs2 device */
  955. static const unsigned ssp0_cs2_pins[] = { 85 };
  956. static struct spear_muxreg ssp0_cs2_muxreg[] = {
  957. {
  958. .reg = PAD_SHARED_IP_EN_1,
  959. .mask = SSP0_CS2_MASK,
  960. .val = SSP0_CS2_MASK,
  961. }, {
  962. .reg = PAD_FUNCTION_EN_3,
  963. .mask = TS_AND_SSP0_CS2_REG2_MASK,
  964. .val = TS_AND_SSP0_CS2_REG2_MASK,
  965. },
  966. };
  967. static struct spear_modemux ssp0_cs2_modemux[] = {
  968. {
  969. .muxregs = ssp0_cs2_muxreg,
  970. .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
  971. },
  972. };
  973. static struct spear_pingroup ssp0_cs2_pingroup = {
  974. .name = "ssp0_cs2_grp",
  975. .pins = ssp0_cs2_pins,
  976. .npins = ARRAY_SIZE(ssp0_cs2_pins),
  977. .modemuxs = ssp0_cs2_modemux,
  978. .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
  979. };
  980. /* pad multiplexing for ssp0_cs3 device */
  981. static const unsigned ssp0_cs3_pins[] = { 132 };
  982. static struct spear_muxreg ssp0_cs3_muxreg[] = {
  983. {
  984. .reg = PAD_FUNCTION_EN_5,
  985. .mask = SSP0_CS3_REG4_MASK,
  986. .val = SSP0_CS3_REG4_MASK,
  987. },
  988. };
  989. static struct spear_modemux ssp0_cs3_modemux[] = {
  990. {
  991. .muxregs = ssp0_cs3_muxreg,
  992. .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
  993. },
  994. };
  995. static struct spear_pingroup ssp0_cs3_pingroup = {
  996. .name = "ssp0_cs3_grp",
  997. .pins = ssp0_cs3_pins,
  998. .npins = ARRAY_SIZE(ssp0_cs3_pins),
  999. .modemuxs = ssp0_cs3_modemux,
  1000. .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
  1001. };
  1002. static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
  1003. "ssp0_cs2_grp", "ssp0_cs3_grp" };
  1004. static struct spear_function ssp0_function = {
  1005. .name = "ssp0",
  1006. .groups = ssp0_grps,
  1007. .ngroups = ARRAY_SIZE(ssp0_grps),
  1008. };
  1009. /* pad multiplexing for uart0 device */
  1010. static const unsigned uart0_pins[] = { 86, 87 };
  1011. static struct spear_muxreg uart0_muxreg[] = {
  1012. {
  1013. .reg = PAD_FUNCTION_EN_3,
  1014. .mask = UART0_REG2_MASK,
  1015. .val = UART0_REG2_MASK,
  1016. },
  1017. };
  1018. static struct spear_modemux uart0_modemux[] = {
  1019. {
  1020. .muxregs = uart0_muxreg,
  1021. .nmuxregs = ARRAY_SIZE(uart0_muxreg),
  1022. },
  1023. };
  1024. static struct spear_pingroup uart0_pingroup = {
  1025. .name = "uart0_grp",
  1026. .pins = uart0_pins,
  1027. .npins = ARRAY_SIZE(uart0_pins),
  1028. .modemuxs = uart0_modemux,
  1029. .nmodemuxs = ARRAY_SIZE(uart0_modemux),
  1030. };
  1031. /* pad multiplexing for uart0_enh device */
  1032. static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
  1033. static struct spear_muxreg uart0_enh_muxreg[] = {
  1034. {
  1035. .reg = PAD_SHARED_IP_EN_1,
  1036. .mask = GPT_MASK,
  1037. .val = 0,
  1038. }, {
  1039. .reg = PAD_FUNCTION_EN_1,
  1040. .mask = UART0_ENH_AND_GPT_REG0_MASK,
  1041. .val = UART0_ENH_AND_GPT_REG0_MASK,
  1042. },
  1043. };
  1044. static struct spear_modemux uart0_enh_modemux[] = {
  1045. {
  1046. .muxregs = uart0_enh_muxreg,
  1047. .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
  1048. },
  1049. };
  1050. static struct spear_pingroup uart0_enh_pingroup = {
  1051. .name = "uart0_enh_grp",
  1052. .pins = uart0_enh_pins,
  1053. .npins = ARRAY_SIZE(uart0_enh_pins),
  1054. .modemuxs = uart0_enh_modemux,
  1055. .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
  1056. };
  1057. static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
  1058. static struct spear_function uart0_function = {
  1059. .name = "uart0",
  1060. .groups = uart0_grps,
  1061. .ngroups = ARRAY_SIZE(uart0_grps),
  1062. };
  1063. /* pad multiplexing for uart1 device */
  1064. static const unsigned uart1_pins[] = { 88, 89 };
  1065. static struct spear_muxreg uart1_muxreg[] = {
  1066. {
  1067. .reg = PAD_FUNCTION_EN_3,
  1068. .mask = UART1_REG2_MASK,
  1069. .val = UART1_REG2_MASK,
  1070. },
  1071. };
  1072. static struct spear_modemux uart1_modemux[] = {
  1073. {
  1074. .muxregs = uart1_muxreg,
  1075. .nmuxregs = ARRAY_SIZE(uart1_muxreg),
  1076. },
  1077. };
  1078. static struct spear_pingroup uart1_pingroup = {
  1079. .name = "uart1_grp",
  1080. .pins = uart1_pins,
  1081. .npins = ARRAY_SIZE(uart1_pins),
  1082. .modemuxs = uart1_modemux,
  1083. .nmodemuxs = ARRAY_SIZE(uart1_modemux),
  1084. };
  1085. static const char *const uart1_grps[] = { "uart1_grp" };
  1086. static struct spear_function uart1_function = {
  1087. .name = "uart1",
  1088. .groups = uart1_grps,
  1089. .ngroups = ARRAY_SIZE(uart1_grps),
  1090. };
  1091. /* pad multiplexing for i2s_in device */
  1092. static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
  1093. static struct spear_muxreg i2s_in_muxreg[] = {
  1094. {
  1095. .reg = PAD_FUNCTION_EN_3,
  1096. .mask = I2S_IN_REG2_MASK,
  1097. .val = I2S_IN_REG2_MASK,
  1098. }, {
  1099. .reg = PAD_FUNCTION_EN_4,
  1100. .mask = I2S_IN_REG3_MASK,
  1101. .val = I2S_IN_REG3_MASK,
  1102. },
  1103. };
  1104. static struct spear_modemux i2s_in_modemux[] = {
  1105. {
  1106. .muxregs = i2s_in_muxreg,
  1107. .nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
  1108. },
  1109. };
  1110. static struct spear_pingroup i2s_in_pingroup = {
  1111. .name = "i2s_in_grp",
  1112. .pins = i2s_in_pins,
  1113. .npins = ARRAY_SIZE(i2s_in_pins),
  1114. .modemuxs = i2s_in_modemux,
  1115. .nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
  1116. };
  1117. /* pad multiplexing for i2s_out device */
  1118. static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
  1119. static struct spear_muxreg i2s_out_muxreg[] = {
  1120. {
  1121. .reg = PAD_FUNCTION_EN_4,
  1122. .mask = I2S_OUT_REG3_MASK,
  1123. .val = I2S_OUT_REG3_MASK,
  1124. },
  1125. };
  1126. static struct spear_modemux i2s_out_modemux[] = {
  1127. {
  1128. .muxregs = i2s_out_muxreg,
  1129. .nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
  1130. },
  1131. };
  1132. static struct spear_pingroup i2s_out_pingroup = {
  1133. .name = "i2s_out_grp",
  1134. .pins = i2s_out_pins,
  1135. .npins = ARRAY_SIZE(i2s_out_pins),
  1136. .modemuxs = i2s_out_modemux,
  1137. .nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
  1138. };
  1139. static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
  1140. static struct spear_function i2s_function = {
  1141. .name = "i2s",
  1142. .groups = i2s_grps,
  1143. .ngroups = ARRAY_SIZE(i2s_grps),
  1144. };
  1145. /* pad multiplexing for gmac device */
  1146. static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
  1147. 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
  1148. 126, 127, 128, 129, 130, 131 };
  1149. #define GMAC_MUXREG \
  1150. { \
  1151. .reg = PAD_FUNCTION_EN_4, \
  1152. .mask = GMAC_REG3_MASK, \
  1153. .val = GMAC_REG3_MASK, \
  1154. }, { \
  1155. .reg = PAD_FUNCTION_EN_5, \
  1156. .mask = GMAC_REG4_MASK, \
  1157. .val = GMAC_REG4_MASK, \
  1158. }
  1159. /* pad multiplexing for gmii device */
  1160. static struct spear_muxreg gmii_muxreg[] = {
  1161. GMAC_MUXREG,
  1162. {
  1163. .reg = GMAC_CLK_CFG,
  1164. .mask = GMAC_PHY_IF_SEL_MASK,
  1165. .val = GMAC_PHY_IF_GMII_VAL,
  1166. },
  1167. };
  1168. static struct spear_modemux gmii_modemux[] = {
  1169. {
  1170. .muxregs = gmii_muxreg,
  1171. .nmuxregs = ARRAY_SIZE(gmii_muxreg),
  1172. },
  1173. };
  1174. static struct spear_pingroup gmii_pingroup = {
  1175. .name = "gmii_grp",
  1176. .pins = gmac_pins,
  1177. .npins = ARRAY_SIZE(gmac_pins),
  1178. .modemuxs = gmii_modemux,
  1179. .nmodemuxs = ARRAY_SIZE(gmii_modemux),
  1180. };
  1181. /* pad multiplexing for rgmii device */
  1182. static struct spear_muxreg rgmii_muxreg[] = {
  1183. GMAC_MUXREG,
  1184. {
  1185. .reg = GMAC_CLK_CFG,
  1186. .mask = GMAC_PHY_IF_SEL_MASK,
  1187. .val = GMAC_PHY_IF_RGMII_VAL,
  1188. },
  1189. };
  1190. static struct spear_modemux rgmii_modemux[] = {
  1191. {
  1192. .muxregs = rgmii_muxreg,
  1193. .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
  1194. },
  1195. };
  1196. static struct spear_pingroup rgmii_pingroup = {
  1197. .name = "rgmii_grp",
  1198. .pins = gmac_pins,
  1199. .npins = ARRAY_SIZE(gmac_pins),
  1200. .modemuxs = rgmii_modemux,
  1201. .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
  1202. };
  1203. /* pad multiplexing for rmii device */
  1204. static struct spear_muxreg rmii_muxreg[] = {
  1205. GMAC_MUXREG,
  1206. {
  1207. .reg = GMAC_CLK_CFG,
  1208. .mask = GMAC_PHY_IF_SEL_MASK,
  1209. .val = GMAC_PHY_IF_RMII_VAL,
  1210. },
  1211. };
  1212. static struct spear_modemux rmii_modemux[] = {
  1213. {
  1214. .muxregs = rmii_muxreg,
  1215. .nmuxregs = ARRAY_SIZE(rmii_muxreg),
  1216. },
  1217. };
  1218. static struct spear_pingroup rmii_pingroup = {
  1219. .name = "rmii_grp",
  1220. .pins = gmac_pins,
  1221. .npins = ARRAY_SIZE(gmac_pins),
  1222. .modemuxs = rmii_modemux,
  1223. .nmodemuxs = ARRAY_SIZE(rmii_modemux),
  1224. };
  1225. /* pad multiplexing for sgmii device */
  1226. static struct spear_muxreg sgmii_muxreg[] = {
  1227. GMAC_MUXREG,
  1228. {
  1229. .reg = GMAC_CLK_CFG,
  1230. .mask = GMAC_PHY_IF_SEL_MASK,
  1231. .val = GMAC_PHY_IF_SGMII_VAL,
  1232. },
  1233. };
  1234. static struct spear_modemux sgmii_modemux[] = {
  1235. {
  1236. .muxregs = sgmii_muxreg,
  1237. .nmuxregs = ARRAY_SIZE(sgmii_muxreg),
  1238. },
  1239. };
  1240. static struct spear_pingroup sgmii_pingroup = {
  1241. .name = "sgmii_grp",
  1242. .pins = gmac_pins,
  1243. .npins = ARRAY_SIZE(gmac_pins),
  1244. .modemuxs = sgmii_modemux,
  1245. .nmodemuxs = ARRAY_SIZE(sgmii_modemux),
  1246. };
  1247. static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
  1248. "sgmii_grp" };
  1249. static struct spear_function gmac_function = {
  1250. .name = "gmac",
  1251. .groups = gmac_grps,
  1252. .ngroups = ARRAY_SIZE(gmac_grps),
  1253. };
  1254. /* pad multiplexing for i2c0 device */
  1255. static const unsigned i2c0_pins[] = { 133, 134 };
  1256. static struct spear_muxreg i2c0_muxreg[] = {
  1257. {
  1258. .reg = PAD_FUNCTION_EN_5,
  1259. .mask = I2C0_REG4_MASK,
  1260. .val = I2C0_REG4_MASK,
  1261. },
  1262. };
  1263. static struct spear_modemux i2c0_modemux[] = {
  1264. {
  1265. .muxregs = i2c0_muxreg,
  1266. .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
  1267. },
  1268. };
  1269. static struct spear_pingroup i2c0_pingroup = {
  1270. .name = "i2c0_grp",
  1271. .pins = i2c0_pins,
  1272. .npins = ARRAY_SIZE(i2c0_pins),
  1273. .modemuxs = i2c0_modemux,
  1274. .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
  1275. };
  1276. static const char *const i2c0_grps[] = { "i2c0_grp" };
  1277. static struct spear_function i2c0_function = {
  1278. .name = "i2c0",
  1279. .groups = i2c0_grps,
  1280. .ngroups = ARRAY_SIZE(i2c0_grps),
  1281. };
  1282. /* pad multiplexing for i2c1 device */
  1283. static const unsigned i2c1_pins[] = { 18, 23 };
  1284. static struct spear_muxreg i2c1_muxreg[] = {
  1285. {
  1286. .reg = PAD_FUNCTION_EN_1,
  1287. .mask = I2C1_REG0_MASK,
  1288. .val = I2C1_REG0_MASK,
  1289. },
  1290. };
  1291. static struct spear_modemux i2c1_modemux[] = {
  1292. {
  1293. .muxregs = i2c1_muxreg,
  1294. .nmuxregs = ARRAY_SIZE(i2c1_muxreg),
  1295. },
  1296. };
  1297. static struct spear_pingroup i2c1_pingroup = {
  1298. .name = "i2c1_grp",
  1299. .pins = i2c1_pins,
  1300. .npins = ARRAY_SIZE(i2c1_pins),
  1301. .modemuxs = i2c1_modemux,
  1302. .nmodemuxs = ARRAY_SIZE(i2c1_modemux),
  1303. };
  1304. static const char *const i2c1_grps[] = { "i2c1_grp" };
  1305. static struct spear_function i2c1_function = {
  1306. .name = "i2c1",
  1307. .groups = i2c1_grps,
  1308. .ngroups = ARRAY_SIZE(i2c1_grps),
  1309. };
  1310. /* pad multiplexing for cec0 device */
  1311. static const unsigned cec0_pins[] = { 135 };
  1312. static struct spear_muxreg cec0_muxreg[] = {
  1313. {
  1314. .reg = PAD_FUNCTION_EN_5,
  1315. .mask = CEC0_REG4_MASK,
  1316. .val = CEC0_REG4_MASK,
  1317. },
  1318. };
  1319. static struct spear_modemux cec0_modemux[] = {
  1320. {
  1321. .muxregs = cec0_muxreg,
  1322. .nmuxregs = ARRAY_SIZE(cec0_muxreg),
  1323. },
  1324. };
  1325. static struct spear_pingroup cec0_pingroup = {
  1326. .name = "cec0_grp",
  1327. .pins = cec0_pins,
  1328. .npins = ARRAY_SIZE(cec0_pins),
  1329. .modemuxs = cec0_modemux,
  1330. .nmodemuxs = ARRAY_SIZE(cec0_modemux),
  1331. };
  1332. static const char *const cec0_grps[] = { "cec0_grp" };
  1333. static struct spear_function cec0_function = {
  1334. .name = "cec0",
  1335. .groups = cec0_grps,
  1336. .ngroups = ARRAY_SIZE(cec0_grps),
  1337. };
  1338. /* pad multiplexing for cec1 device */
  1339. static const unsigned cec1_pins[] = { 136 };
  1340. static struct spear_muxreg cec1_muxreg[] = {
  1341. {
  1342. .reg = PAD_FUNCTION_EN_5,
  1343. .mask = CEC1_REG4_MASK,
  1344. .val = CEC1_REG4_MASK,
  1345. },
  1346. };
  1347. static struct spear_modemux cec1_modemux[] = {
  1348. {
  1349. .muxregs = cec1_muxreg,
  1350. .nmuxregs = ARRAY_SIZE(cec1_muxreg),
  1351. },
  1352. };
  1353. static struct spear_pingroup cec1_pingroup = {
  1354. .name = "cec1_grp",
  1355. .pins = cec1_pins,
  1356. .npins = ARRAY_SIZE(cec1_pins),
  1357. .modemuxs = cec1_modemux,
  1358. .nmodemuxs = ARRAY_SIZE(cec1_modemux),
  1359. };
  1360. static const char *const cec1_grps[] = { "cec1_grp" };
  1361. static struct spear_function cec1_function = {
  1362. .name = "cec1",
  1363. .groups = cec1_grps,
  1364. .ngroups = ARRAY_SIZE(cec1_grps),
  1365. };
  1366. /* pad multiplexing for mcif devices */
  1367. static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
  1368. 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
  1369. 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
  1370. 229, 230, 231, 232, 237 };
  1371. #define MCIF_MUXREG \
  1372. { \
  1373. .reg = PAD_SHARED_IP_EN_1, \
  1374. .mask = MCIF_MASK, \
  1375. .val = MCIF_MASK, \
  1376. }, { \
  1377. .reg = PAD_FUNCTION_EN_7, \
  1378. .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
  1379. .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
  1380. }, { \
  1381. .reg = PAD_FUNCTION_EN_8, \
  1382. .mask = MCIF_REG7_MASK, \
  1383. .val = MCIF_REG7_MASK, \
  1384. }
  1385. /* Pad multiplexing for sdhci device */
  1386. static struct spear_muxreg sdhci_muxreg[] = {
  1387. MCIF_MUXREG,
  1388. {
  1389. .reg = PERIP_CFG,
  1390. .mask = MCIF_SEL_MASK,
  1391. .val = MCIF_SEL_SD,
  1392. },
  1393. };
  1394. static struct spear_modemux sdhci_modemux[] = {
  1395. {
  1396. .muxregs = sdhci_muxreg,
  1397. .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
  1398. },
  1399. };
  1400. static struct spear_pingroup sdhci_pingroup = {
  1401. .name = "sdhci_grp",
  1402. .pins = mcif_pins,
  1403. .npins = ARRAY_SIZE(mcif_pins),
  1404. .modemuxs = sdhci_modemux,
  1405. .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
  1406. };
  1407. static const char *const sdhci_grps[] = { "sdhci_grp" };
  1408. static struct spear_function sdhci_function = {
  1409. .name = "sdhci",
  1410. .groups = sdhci_grps,
  1411. .ngroups = ARRAY_SIZE(sdhci_grps),
  1412. };
  1413. /* Pad multiplexing for cf device */
  1414. static struct spear_muxreg cf_muxreg[] = {
  1415. MCIF_MUXREG,
  1416. {
  1417. .reg = PERIP_CFG,
  1418. .mask = MCIF_SEL_MASK,
  1419. .val = MCIF_SEL_CF,
  1420. },
  1421. };
  1422. static struct spear_modemux cf_modemux[] = {
  1423. {
  1424. .muxregs = cf_muxreg,
  1425. .nmuxregs = ARRAY_SIZE(cf_muxreg),
  1426. },
  1427. };
  1428. static struct spear_pingroup cf_pingroup = {
  1429. .name = "cf_grp",
  1430. .pins = mcif_pins,
  1431. .npins = ARRAY_SIZE(mcif_pins),
  1432. .modemuxs = cf_modemux,
  1433. .nmodemuxs = ARRAY_SIZE(cf_modemux),
  1434. };
  1435. static const char *const cf_grps[] = { "cf_grp" };
  1436. static struct spear_function cf_function = {
  1437. .name = "cf",
  1438. .groups = cf_grps,
  1439. .ngroups = ARRAY_SIZE(cf_grps),
  1440. };
  1441. /* Pad multiplexing for xd device */
  1442. static struct spear_muxreg xd_muxreg[] = {
  1443. MCIF_MUXREG,
  1444. {
  1445. .reg = PERIP_CFG,
  1446. .mask = MCIF_SEL_MASK,
  1447. .val = MCIF_SEL_XD,
  1448. },
  1449. };
  1450. static struct spear_modemux xd_modemux[] = {
  1451. {
  1452. .muxregs = xd_muxreg,
  1453. .nmuxregs = ARRAY_SIZE(xd_muxreg),
  1454. },
  1455. };
  1456. static struct spear_pingroup xd_pingroup = {
  1457. .name = "xd_grp",
  1458. .pins = mcif_pins,
  1459. .npins = ARRAY_SIZE(mcif_pins),
  1460. .modemuxs = xd_modemux,
  1461. .nmodemuxs = ARRAY_SIZE(xd_modemux),
  1462. };
  1463. static const char *const xd_grps[] = { "xd_grp" };
  1464. static struct spear_function xd_function = {
  1465. .name = "xd",
  1466. .groups = xd_grps,
  1467. .ngroups = ARRAY_SIZE(xd_grps),
  1468. };
  1469. /* pad multiplexing for clcd device */
  1470. static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
  1471. 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
  1472. 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
  1473. 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
  1474. 188, 189, 190, 191 };
  1475. static struct spear_muxreg clcd_muxreg[] = {
  1476. {
  1477. .reg = PAD_SHARED_IP_EN_1,
  1478. .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
  1479. .val = 0,
  1480. }, {
  1481. .reg = PAD_FUNCTION_EN_5,
  1482. .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
  1483. .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
  1484. }, {
  1485. .reg = PAD_FUNCTION_EN_6,
  1486. .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
  1487. .val = CLCD_AND_ARM_TRACE_REG5_MASK,
  1488. }, {
  1489. .reg = PAD_FUNCTION_EN_7,
  1490. .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
  1491. .val = CLCD_AND_ARM_TRACE_REG6_MASK,
  1492. },
  1493. };
  1494. static struct spear_modemux clcd_modemux[] = {
  1495. {
  1496. .muxregs = clcd_muxreg,
  1497. .nmuxregs = ARRAY_SIZE(clcd_muxreg),
  1498. },
  1499. };
  1500. static struct spear_pingroup clcd_pingroup = {
  1501. .name = "clcd_grp",
  1502. .pins = clcd_pins,
  1503. .npins = ARRAY_SIZE(clcd_pins),
  1504. .modemuxs = clcd_modemux,
  1505. .nmodemuxs = ARRAY_SIZE(clcd_modemux),
  1506. };
  1507. /* Disable cld runtime to save panel damage */
  1508. static struct spear_muxreg clcd_sleep_muxreg[] = {
  1509. {
  1510. .reg = PAD_SHARED_IP_EN_1,
  1511. .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
  1512. .val = 0,
  1513. }, {
  1514. .reg = PAD_FUNCTION_EN_5,
  1515. .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
  1516. .val = 0x0,
  1517. }, {
  1518. .reg = PAD_FUNCTION_EN_6,
  1519. .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
  1520. .val = 0x0,
  1521. }, {
  1522. .reg = PAD_FUNCTION_EN_7,
  1523. .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
  1524. .val = 0x0,
  1525. },
  1526. };
  1527. static struct spear_modemux clcd_sleep_modemux[] = {
  1528. {
  1529. .muxregs = clcd_sleep_muxreg,
  1530. .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg),
  1531. },
  1532. };
  1533. static struct spear_pingroup clcd_sleep_pingroup = {
  1534. .name = "clcd_sleep_grp",
  1535. .pins = clcd_pins,
  1536. .npins = ARRAY_SIZE(clcd_pins),
  1537. .modemuxs = clcd_sleep_modemux,
  1538. .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux),
  1539. };
  1540. static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" };
  1541. static struct spear_function clcd_function = {
  1542. .name = "clcd",
  1543. .groups = clcd_grps,
  1544. .ngroups = ARRAY_SIZE(clcd_grps),
  1545. };
  1546. /* pad multiplexing for arm_trace device */
  1547. static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
  1548. 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
  1549. 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
  1550. 193, 194, 195, 196, 197, 198, 199, 200 };
  1551. static struct spear_muxreg arm_trace_muxreg[] = {
  1552. {
  1553. .reg = PAD_SHARED_IP_EN_1,
  1554. .mask = ARM_TRACE_MASK,
  1555. .val = ARM_TRACE_MASK,
  1556. }, {
  1557. .reg = PAD_FUNCTION_EN_5,
  1558. .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
  1559. .val = CLCD_AND_ARM_TRACE_REG4_MASK,
  1560. }, {
  1561. .reg = PAD_FUNCTION_EN_6,
  1562. .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
  1563. .val = CLCD_AND_ARM_TRACE_REG5_MASK,
  1564. }, {
  1565. .reg = PAD_FUNCTION_EN_7,
  1566. .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
  1567. .val = CLCD_AND_ARM_TRACE_REG6_MASK,
  1568. },
  1569. };
  1570. static struct spear_modemux arm_trace_modemux[] = {
  1571. {
  1572. .muxregs = arm_trace_muxreg,
  1573. .nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
  1574. },
  1575. };
  1576. static struct spear_pingroup arm_trace_pingroup = {
  1577. .name = "arm_trace_grp",
  1578. .pins = arm_trace_pins,
  1579. .npins = ARRAY_SIZE(arm_trace_pins),
  1580. .modemuxs = arm_trace_modemux,
  1581. .nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
  1582. };
  1583. static const char *const arm_trace_grps[] = { "arm_trace_grp" };
  1584. static struct spear_function arm_trace_function = {
  1585. .name = "arm_trace",
  1586. .groups = arm_trace_grps,
  1587. .ngroups = ARRAY_SIZE(arm_trace_grps),
  1588. };
  1589. /* pad multiplexing for miphy_dbg device */
  1590. static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
  1591. 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
  1592. 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
  1593. static struct spear_muxreg miphy_dbg_muxreg[] = {
  1594. {
  1595. .reg = PAD_SHARED_IP_EN_1,
  1596. .mask = MIPHY_DBG_MASK,
  1597. .val = MIPHY_DBG_MASK,
  1598. }, {
  1599. .reg = PAD_FUNCTION_EN_5,
  1600. .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
  1601. .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
  1602. },
  1603. };
  1604. static struct spear_modemux miphy_dbg_modemux[] = {
  1605. {
  1606. .muxregs = miphy_dbg_muxreg,
  1607. .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
  1608. },
  1609. };
  1610. static struct spear_pingroup miphy_dbg_pingroup = {
  1611. .name = "miphy_dbg_grp",
  1612. .pins = miphy_dbg_pins,
  1613. .npins = ARRAY_SIZE(miphy_dbg_pins),
  1614. .modemuxs = miphy_dbg_modemux,
  1615. .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
  1616. };
  1617. static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
  1618. static struct spear_function miphy_dbg_function = {
  1619. .name = "miphy_dbg",
  1620. .groups = miphy_dbg_grps,
  1621. .ngroups = ARRAY_SIZE(miphy_dbg_grps),
  1622. };
  1623. /* pad multiplexing for pcie device */
  1624. static const unsigned pcie_pins[] = { 250 };
  1625. static struct spear_muxreg pcie_muxreg[] = {
  1626. {
  1627. .reg = PCIE_SATA_CFG,
  1628. .mask = SATA_PCIE_CFG_MASK,
  1629. .val = PCIE_CFG_VAL,
  1630. },
  1631. };
  1632. static struct spear_modemux pcie_modemux[] = {
  1633. {
  1634. .muxregs = pcie_muxreg,
  1635. .nmuxregs = ARRAY_SIZE(pcie_muxreg),
  1636. },
  1637. };
  1638. static struct spear_pingroup pcie_pingroup = {
  1639. .name = "pcie_grp",
  1640. .pins = pcie_pins,
  1641. .npins = ARRAY_SIZE(pcie_pins),
  1642. .modemuxs = pcie_modemux,
  1643. .nmodemuxs = ARRAY_SIZE(pcie_modemux),
  1644. };
  1645. static const char *const pcie_grps[] = { "pcie_grp" };
  1646. static struct spear_function pcie_function = {
  1647. .name = "pcie",
  1648. .groups = pcie_grps,
  1649. .ngroups = ARRAY_SIZE(pcie_grps),
  1650. };
  1651. /* pad multiplexing for sata device */
  1652. static const unsigned sata_pins[] = { 250 };
  1653. static struct spear_muxreg sata_muxreg[] = {
  1654. {
  1655. .reg = PCIE_SATA_CFG,
  1656. .mask = SATA_PCIE_CFG_MASK,
  1657. .val = SATA_CFG_VAL,
  1658. },
  1659. };
  1660. static struct spear_modemux sata_modemux[] = {
  1661. {
  1662. .muxregs = sata_muxreg,
  1663. .nmuxregs = ARRAY_SIZE(sata_muxreg),
  1664. },
  1665. };
  1666. static struct spear_pingroup sata_pingroup = {
  1667. .name = "sata_grp",
  1668. .pins = sata_pins,
  1669. .npins = ARRAY_SIZE(sata_pins),
  1670. .modemuxs = sata_modemux,
  1671. .nmodemuxs = ARRAY_SIZE(sata_modemux),
  1672. };
  1673. static const char *const sata_grps[] = { "sata_grp" };
  1674. static struct spear_function sata_function = {
  1675. .name = "sata",
  1676. .groups = sata_grps,
  1677. .ngroups = ARRAY_SIZE(sata_grps),
  1678. };
  1679. /* pingroups */
  1680. static struct spear_pingroup *spear1340_pingroups[] = {
  1681. &pads_as_gpio_pingroup,
  1682. &fsmc_8bit_pingroup,
  1683. &fsmc_16bit_pingroup,
  1684. &fsmc_pnor_pingroup,
  1685. &keyboard_row_col_pingroup,
  1686. &keyboard_col5_pingroup,
  1687. &spdif_in_pingroup,
  1688. &spdif_out_pingroup,
  1689. &gpt_0_1_pingroup,
  1690. &pwm0_pingroup,
  1691. &pwm1_pingroup,
  1692. &pwm2_pingroup,
  1693. &pwm3_pingroup,
  1694. &vip_mux_pingroup,
  1695. &vip_mux_cam0_pingroup,
  1696. &vip_mux_cam1_pingroup,
  1697. &vip_mux_cam2_pingroup,
  1698. &vip_mux_cam3_pingroup,
  1699. &cam0_pingroup,
  1700. &cam1_pingroup,
  1701. &cam2_pingroup,
  1702. &cam3_pingroup,
  1703. &smi_pingroup,
  1704. &ssp0_pingroup,
  1705. &ssp0_cs1_pingroup,
  1706. &ssp0_cs2_pingroup,
  1707. &ssp0_cs3_pingroup,
  1708. &uart0_pingroup,
  1709. &uart0_enh_pingroup,
  1710. &uart1_pingroup,
  1711. &i2s_in_pingroup,
  1712. &i2s_out_pingroup,
  1713. &gmii_pingroup,
  1714. &rgmii_pingroup,
  1715. &rmii_pingroup,
  1716. &sgmii_pingroup,
  1717. &i2c0_pingroup,
  1718. &i2c1_pingroup,
  1719. &cec0_pingroup,
  1720. &cec1_pingroup,
  1721. &sdhci_pingroup,
  1722. &cf_pingroup,
  1723. &xd_pingroup,
  1724. &clcd_sleep_pingroup,
  1725. &clcd_pingroup,
  1726. &arm_trace_pingroup,
  1727. &miphy_dbg_pingroup,
  1728. &pcie_pingroup,
  1729. &sata_pingroup,
  1730. };
  1731. /* functions */
  1732. static struct spear_function *spear1340_functions[] = {
  1733. &pads_as_gpio_function,
  1734. &fsmc_function,
  1735. &keyboard_function,
  1736. &spdif_in_function,
  1737. &spdif_out_function,
  1738. &gpt_0_1_function,
  1739. &pwm_function,
  1740. &vip_function,
  1741. &cam0_function,
  1742. &cam1_function,
  1743. &cam2_function,
  1744. &cam3_function,
  1745. &smi_function,
  1746. &ssp0_function,
  1747. &uart0_function,
  1748. &uart1_function,
  1749. &i2s_function,
  1750. &gmac_function,
  1751. &i2c0_function,
  1752. &i2c1_function,
  1753. &cec0_function,
  1754. &cec1_function,
  1755. &sdhci_function,
  1756. &cf_function,
  1757. &xd_function,
  1758. &clcd_function,
  1759. &arm_trace_function,
  1760. &miphy_dbg_function,
  1761. &pcie_function,
  1762. &sata_function,
  1763. };
  1764. static void gpio_request_endisable(struct spear_pmx *pmx, int pin,
  1765. bool enable)
  1766. {
  1767. unsigned int regoffset, regindex, bitoffset;
  1768. unsigned int val;
  1769. /* pin++ as gpio configuration starts from 2nd bit of base register */
  1770. pin++;
  1771. regindex = pin / 32;
  1772. bitoffset = pin % 32;
  1773. if (regindex <= 3)
  1774. regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *);
  1775. else
  1776. regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *);
  1777. val = pmx_readl(pmx, regoffset);
  1778. if (enable)
  1779. val &= ~(0x1 << bitoffset);
  1780. else
  1781. val |= 0x1 << bitoffset;
  1782. pmx_writel(pmx, val, regoffset);
  1783. }
  1784. static struct spear_pinctrl_machdata spear1340_machdata = {
  1785. .pins = spear1340_pins,
  1786. .npins = ARRAY_SIZE(spear1340_pins),
  1787. .groups = spear1340_pingroups,
  1788. .ngroups = ARRAY_SIZE(spear1340_pingroups),
  1789. .functions = spear1340_functions,
  1790. .nfunctions = ARRAY_SIZE(spear1340_functions),
  1791. .gpio_request_endisable = gpio_request_endisable,
  1792. .modes_supported = false,
  1793. };
  1794. static const struct of_device_id spear1340_pinctrl_of_match[] = {
  1795. {
  1796. .compatible = "st,spear1340-pinmux",
  1797. },
  1798. {},
  1799. };
  1800. static int spear1340_pinctrl_probe(struct platform_device *pdev)
  1801. {
  1802. return spear_pinctrl_probe(pdev, &spear1340_machdata);
  1803. }
  1804. static struct platform_driver spear1340_pinctrl_driver = {
  1805. .driver = {
  1806. .name = DRIVER_NAME,
  1807. .of_match_table = spear1340_pinctrl_of_match,
  1808. },
  1809. .probe = spear1340_pinctrl_probe,
  1810. };
  1811. static int __init spear1340_pinctrl_init(void)
  1812. {
  1813. return platform_driver_register(&spear1340_pinctrl_driver);
  1814. }
  1815. arch_initcall(spear1340_pinctrl_init);