pinctrl-spear.h 13 KB

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  1. /*
  2. * Driver header file for the ST Microelectronics SPEAr pinmux
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Viresh Kumar <vireshk@kernel.org>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #ifndef __PINMUX_SPEAR_H__
  12. #define __PINMUX_SPEAR_H__
  13. #include <linux/gpio/driver.h>
  14. #include <linux/io.h>
  15. #include <linux/pinctrl/pinctrl.h>
  16. #include <linux/types.h>
  17. struct platform_device;
  18. struct device;
  19. struct spear_pmx;
  20. /**
  21. * struct spear_pmx_mode - SPEAr pmx mode
  22. * @name: name of pmx mode
  23. * @mode: mode id
  24. * @reg: register for configuring this mode
  25. * @mask: mask of this mode in reg
  26. * @val: val to be configured at reg after doing (val & mask)
  27. */
  28. struct spear_pmx_mode {
  29. const char *const name;
  30. u16 mode;
  31. u16 reg;
  32. u16 mask;
  33. u32 val;
  34. };
  35. /**
  36. * struct spear_muxreg - SPEAr mux reg configuration
  37. * @reg: register offset
  38. * @mask: mask bits
  39. * @val: val to be written on mask bits
  40. */
  41. struct spear_muxreg {
  42. u16 reg;
  43. u32 mask;
  44. u32 val;
  45. };
  46. struct spear_gpio_pingroup {
  47. const unsigned *pins;
  48. unsigned npins;
  49. struct spear_muxreg *muxregs;
  50. u8 nmuxregs;
  51. };
  52. /* ste: set to enable */
  53. #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \
  54. static struct spear_muxreg __pins##_muxregs[] = { \
  55. { \
  56. .reg = __muxreg, \
  57. .mask = __mask, \
  58. .val = __ste ? __mask : 0, \
  59. }, \
  60. }
  61. #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
  62. static struct spear_muxreg __pins##_muxregs[] = { \
  63. { \
  64. .reg = __muxreg1, \
  65. .mask = __mask, \
  66. .val = __ste1 ? __mask : 0, \
  67. }, { \
  68. .reg = __muxreg2, \
  69. .mask = __mask, \
  70. .val = __ste2 ? __mask : 0, \
  71. }, \
  72. }
  73. #define GPIO_PINGROUP(__pins) \
  74. { \
  75. .pins = __pins, \
  76. .npins = ARRAY_SIZE(__pins), \
  77. .muxregs = __pins##_muxregs, \
  78. .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \
  79. }
  80. /**
  81. * struct spear_modemux - SPEAr mode mux configuration
  82. * @modes: mode ids supported by this group of muxregs
  83. * @nmuxregs: number of muxreg configurations to be done for modes
  84. * @muxregs: array of muxreg configurations to be done for modes
  85. */
  86. struct spear_modemux {
  87. u16 modes;
  88. u8 nmuxregs;
  89. struct spear_muxreg *muxregs;
  90. };
  91. /**
  92. * struct spear_pingroup - SPEAr pin group configurations
  93. * @name: name of pin group
  94. * @pins: array containing pin numbers
  95. * @npins: size of pins array
  96. * @modemuxs: array of modemux configurations for this pin group
  97. * @nmodemuxs: size of array modemuxs
  98. *
  99. * A representation of a group of pins in the SPEAr pin controller. Each group
  100. * allows some parameter or parameters to be configured.
  101. */
  102. struct spear_pingroup {
  103. const char *name;
  104. const unsigned *pins;
  105. unsigned npins;
  106. struct spear_modemux *modemuxs;
  107. unsigned nmodemuxs;
  108. };
  109. /**
  110. * struct spear_function - SPEAr pinctrl mux function
  111. * @name: The name of the function, exported to pinctrl core.
  112. * @groups: An array of pin groups that may select this function.
  113. * @ngroups: The number of entries in @groups.
  114. */
  115. struct spear_function {
  116. const char *name;
  117. const char *const *groups;
  118. unsigned ngroups;
  119. };
  120. /**
  121. * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
  122. * configuration
  123. * @pins: An array describing all pins the pin controller affects.
  124. * All pins which are also GPIOs must be listed first within the *array,
  125. * and be numbered identically to the GPIO controller's *numbering.
  126. * @npins: The numbmer of entries in @pins.
  127. * @functions: An array describing all mux functions the SoC supports.
  128. * @nfunctions: The numbmer of entries in @functions.
  129. * @groups: An array describing all pin groups the pin SoC supports.
  130. * @ngroups: The numbmer of entries in @groups.
  131. * @gpio_pingroups: gpio pingroups
  132. * @ngpio_pingroups: gpio pingroups count
  133. *
  134. * @modes_supported: Does SoC support modes
  135. * @mode: mode configured from probe
  136. * @pmx_modes: array of modes supported by SoC
  137. * @npmx_modes: number of entries in pmx_modes.
  138. */
  139. struct spear_pinctrl_machdata {
  140. const struct pinctrl_pin_desc *pins;
  141. unsigned npins;
  142. struct spear_function **functions;
  143. unsigned nfunctions;
  144. struct spear_pingroup **groups;
  145. unsigned ngroups;
  146. struct spear_gpio_pingroup *gpio_pingroups;
  147. void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset,
  148. bool enable);
  149. unsigned ngpio_pingroups;
  150. bool modes_supported;
  151. u16 mode;
  152. struct spear_pmx_mode **pmx_modes;
  153. unsigned npmx_modes;
  154. };
  155. /**
  156. * struct spear_pmx - SPEAr pinctrl mux
  157. * @dev: pointer to struct dev of platform_device registered
  158. * @pctl: pointer to struct pinctrl_dev
  159. * @machdata: pointer to SoC or machine specific structure
  160. * @vbase: virtual base address of pinmux controller
  161. */
  162. struct spear_pmx {
  163. struct device *dev;
  164. struct pinctrl_dev *pctl;
  165. struct spear_pinctrl_machdata *machdata;
  166. void __iomem *vbase;
  167. };
  168. /* exported routines */
  169. static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
  170. {
  171. return readl_relaxed(pmx->vbase + reg);
  172. }
  173. static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
  174. {
  175. writel_relaxed(val, pmx->vbase + reg);
  176. }
  177. void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
  178. void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
  179. unsigned count, u16 reg);
  180. int spear_pinctrl_probe(struct platform_device *pdev,
  181. struct spear_pinctrl_machdata *machdata);
  182. #define SPEAR_PIN_0_TO_101 \
  183. PINCTRL_PIN(0, "PLGPIO0"), \
  184. PINCTRL_PIN(1, "PLGPIO1"), \
  185. PINCTRL_PIN(2, "PLGPIO2"), \
  186. PINCTRL_PIN(3, "PLGPIO3"), \
  187. PINCTRL_PIN(4, "PLGPIO4"), \
  188. PINCTRL_PIN(5, "PLGPIO5"), \
  189. PINCTRL_PIN(6, "PLGPIO6"), \
  190. PINCTRL_PIN(7, "PLGPIO7"), \
  191. PINCTRL_PIN(8, "PLGPIO8"), \
  192. PINCTRL_PIN(9, "PLGPIO9"), \
  193. PINCTRL_PIN(10, "PLGPIO10"), \
  194. PINCTRL_PIN(11, "PLGPIO11"), \
  195. PINCTRL_PIN(12, "PLGPIO12"), \
  196. PINCTRL_PIN(13, "PLGPIO13"), \
  197. PINCTRL_PIN(14, "PLGPIO14"), \
  198. PINCTRL_PIN(15, "PLGPIO15"), \
  199. PINCTRL_PIN(16, "PLGPIO16"), \
  200. PINCTRL_PIN(17, "PLGPIO17"), \
  201. PINCTRL_PIN(18, "PLGPIO18"), \
  202. PINCTRL_PIN(19, "PLGPIO19"), \
  203. PINCTRL_PIN(20, "PLGPIO20"), \
  204. PINCTRL_PIN(21, "PLGPIO21"), \
  205. PINCTRL_PIN(22, "PLGPIO22"), \
  206. PINCTRL_PIN(23, "PLGPIO23"), \
  207. PINCTRL_PIN(24, "PLGPIO24"), \
  208. PINCTRL_PIN(25, "PLGPIO25"), \
  209. PINCTRL_PIN(26, "PLGPIO26"), \
  210. PINCTRL_PIN(27, "PLGPIO27"), \
  211. PINCTRL_PIN(28, "PLGPIO28"), \
  212. PINCTRL_PIN(29, "PLGPIO29"), \
  213. PINCTRL_PIN(30, "PLGPIO30"), \
  214. PINCTRL_PIN(31, "PLGPIO31"), \
  215. PINCTRL_PIN(32, "PLGPIO32"), \
  216. PINCTRL_PIN(33, "PLGPIO33"), \
  217. PINCTRL_PIN(34, "PLGPIO34"), \
  218. PINCTRL_PIN(35, "PLGPIO35"), \
  219. PINCTRL_PIN(36, "PLGPIO36"), \
  220. PINCTRL_PIN(37, "PLGPIO37"), \
  221. PINCTRL_PIN(38, "PLGPIO38"), \
  222. PINCTRL_PIN(39, "PLGPIO39"), \
  223. PINCTRL_PIN(40, "PLGPIO40"), \
  224. PINCTRL_PIN(41, "PLGPIO41"), \
  225. PINCTRL_PIN(42, "PLGPIO42"), \
  226. PINCTRL_PIN(43, "PLGPIO43"), \
  227. PINCTRL_PIN(44, "PLGPIO44"), \
  228. PINCTRL_PIN(45, "PLGPIO45"), \
  229. PINCTRL_PIN(46, "PLGPIO46"), \
  230. PINCTRL_PIN(47, "PLGPIO47"), \
  231. PINCTRL_PIN(48, "PLGPIO48"), \
  232. PINCTRL_PIN(49, "PLGPIO49"), \
  233. PINCTRL_PIN(50, "PLGPIO50"), \
  234. PINCTRL_PIN(51, "PLGPIO51"), \
  235. PINCTRL_PIN(52, "PLGPIO52"), \
  236. PINCTRL_PIN(53, "PLGPIO53"), \
  237. PINCTRL_PIN(54, "PLGPIO54"), \
  238. PINCTRL_PIN(55, "PLGPIO55"), \
  239. PINCTRL_PIN(56, "PLGPIO56"), \
  240. PINCTRL_PIN(57, "PLGPIO57"), \
  241. PINCTRL_PIN(58, "PLGPIO58"), \
  242. PINCTRL_PIN(59, "PLGPIO59"), \
  243. PINCTRL_PIN(60, "PLGPIO60"), \
  244. PINCTRL_PIN(61, "PLGPIO61"), \
  245. PINCTRL_PIN(62, "PLGPIO62"), \
  246. PINCTRL_PIN(63, "PLGPIO63"), \
  247. PINCTRL_PIN(64, "PLGPIO64"), \
  248. PINCTRL_PIN(65, "PLGPIO65"), \
  249. PINCTRL_PIN(66, "PLGPIO66"), \
  250. PINCTRL_PIN(67, "PLGPIO67"), \
  251. PINCTRL_PIN(68, "PLGPIO68"), \
  252. PINCTRL_PIN(69, "PLGPIO69"), \
  253. PINCTRL_PIN(70, "PLGPIO70"), \
  254. PINCTRL_PIN(71, "PLGPIO71"), \
  255. PINCTRL_PIN(72, "PLGPIO72"), \
  256. PINCTRL_PIN(73, "PLGPIO73"), \
  257. PINCTRL_PIN(74, "PLGPIO74"), \
  258. PINCTRL_PIN(75, "PLGPIO75"), \
  259. PINCTRL_PIN(76, "PLGPIO76"), \
  260. PINCTRL_PIN(77, "PLGPIO77"), \
  261. PINCTRL_PIN(78, "PLGPIO78"), \
  262. PINCTRL_PIN(79, "PLGPIO79"), \
  263. PINCTRL_PIN(80, "PLGPIO80"), \
  264. PINCTRL_PIN(81, "PLGPIO81"), \
  265. PINCTRL_PIN(82, "PLGPIO82"), \
  266. PINCTRL_PIN(83, "PLGPIO83"), \
  267. PINCTRL_PIN(84, "PLGPIO84"), \
  268. PINCTRL_PIN(85, "PLGPIO85"), \
  269. PINCTRL_PIN(86, "PLGPIO86"), \
  270. PINCTRL_PIN(87, "PLGPIO87"), \
  271. PINCTRL_PIN(88, "PLGPIO88"), \
  272. PINCTRL_PIN(89, "PLGPIO89"), \
  273. PINCTRL_PIN(90, "PLGPIO90"), \
  274. PINCTRL_PIN(91, "PLGPIO91"), \
  275. PINCTRL_PIN(92, "PLGPIO92"), \
  276. PINCTRL_PIN(93, "PLGPIO93"), \
  277. PINCTRL_PIN(94, "PLGPIO94"), \
  278. PINCTRL_PIN(95, "PLGPIO95"), \
  279. PINCTRL_PIN(96, "PLGPIO96"), \
  280. PINCTRL_PIN(97, "PLGPIO97"), \
  281. PINCTRL_PIN(98, "PLGPIO98"), \
  282. PINCTRL_PIN(99, "PLGPIO99"), \
  283. PINCTRL_PIN(100, "PLGPIO100"), \
  284. PINCTRL_PIN(101, "PLGPIO101")
  285. #define SPEAR_PIN_102_TO_245 \
  286. PINCTRL_PIN(102, "PLGPIO102"), \
  287. PINCTRL_PIN(103, "PLGPIO103"), \
  288. PINCTRL_PIN(104, "PLGPIO104"), \
  289. PINCTRL_PIN(105, "PLGPIO105"), \
  290. PINCTRL_PIN(106, "PLGPIO106"), \
  291. PINCTRL_PIN(107, "PLGPIO107"), \
  292. PINCTRL_PIN(108, "PLGPIO108"), \
  293. PINCTRL_PIN(109, "PLGPIO109"), \
  294. PINCTRL_PIN(110, "PLGPIO110"), \
  295. PINCTRL_PIN(111, "PLGPIO111"), \
  296. PINCTRL_PIN(112, "PLGPIO112"), \
  297. PINCTRL_PIN(113, "PLGPIO113"), \
  298. PINCTRL_PIN(114, "PLGPIO114"), \
  299. PINCTRL_PIN(115, "PLGPIO115"), \
  300. PINCTRL_PIN(116, "PLGPIO116"), \
  301. PINCTRL_PIN(117, "PLGPIO117"), \
  302. PINCTRL_PIN(118, "PLGPIO118"), \
  303. PINCTRL_PIN(119, "PLGPIO119"), \
  304. PINCTRL_PIN(120, "PLGPIO120"), \
  305. PINCTRL_PIN(121, "PLGPIO121"), \
  306. PINCTRL_PIN(122, "PLGPIO122"), \
  307. PINCTRL_PIN(123, "PLGPIO123"), \
  308. PINCTRL_PIN(124, "PLGPIO124"), \
  309. PINCTRL_PIN(125, "PLGPIO125"), \
  310. PINCTRL_PIN(126, "PLGPIO126"), \
  311. PINCTRL_PIN(127, "PLGPIO127"), \
  312. PINCTRL_PIN(128, "PLGPIO128"), \
  313. PINCTRL_PIN(129, "PLGPIO129"), \
  314. PINCTRL_PIN(130, "PLGPIO130"), \
  315. PINCTRL_PIN(131, "PLGPIO131"), \
  316. PINCTRL_PIN(132, "PLGPIO132"), \
  317. PINCTRL_PIN(133, "PLGPIO133"), \
  318. PINCTRL_PIN(134, "PLGPIO134"), \
  319. PINCTRL_PIN(135, "PLGPIO135"), \
  320. PINCTRL_PIN(136, "PLGPIO136"), \
  321. PINCTRL_PIN(137, "PLGPIO137"), \
  322. PINCTRL_PIN(138, "PLGPIO138"), \
  323. PINCTRL_PIN(139, "PLGPIO139"), \
  324. PINCTRL_PIN(140, "PLGPIO140"), \
  325. PINCTRL_PIN(141, "PLGPIO141"), \
  326. PINCTRL_PIN(142, "PLGPIO142"), \
  327. PINCTRL_PIN(143, "PLGPIO143"), \
  328. PINCTRL_PIN(144, "PLGPIO144"), \
  329. PINCTRL_PIN(145, "PLGPIO145"), \
  330. PINCTRL_PIN(146, "PLGPIO146"), \
  331. PINCTRL_PIN(147, "PLGPIO147"), \
  332. PINCTRL_PIN(148, "PLGPIO148"), \
  333. PINCTRL_PIN(149, "PLGPIO149"), \
  334. PINCTRL_PIN(150, "PLGPIO150"), \
  335. PINCTRL_PIN(151, "PLGPIO151"), \
  336. PINCTRL_PIN(152, "PLGPIO152"), \
  337. PINCTRL_PIN(153, "PLGPIO153"), \
  338. PINCTRL_PIN(154, "PLGPIO154"), \
  339. PINCTRL_PIN(155, "PLGPIO155"), \
  340. PINCTRL_PIN(156, "PLGPIO156"), \
  341. PINCTRL_PIN(157, "PLGPIO157"), \
  342. PINCTRL_PIN(158, "PLGPIO158"), \
  343. PINCTRL_PIN(159, "PLGPIO159"), \
  344. PINCTRL_PIN(160, "PLGPIO160"), \
  345. PINCTRL_PIN(161, "PLGPIO161"), \
  346. PINCTRL_PIN(162, "PLGPIO162"), \
  347. PINCTRL_PIN(163, "PLGPIO163"), \
  348. PINCTRL_PIN(164, "PLGPIO164"), \
  349. PINCTRL_PIN(165, "PLGPIO165"), \
  350. PINCTRL_PIN(166, "PLGPIO166"), \
  351. PINCTRL_PIN(167, "PLGPIO167"), \
  352. PINCTRL_PIN(168, "PLGPIO168"), \
  353. PINCTRL_PIN(169, "PLGPIO169"), \
  354. PINCTRL_PIN(170, "PLGPIO170"), \
  355. PINCTRL_PIN(171, "PLGPIO171"), \
  356. PINCTRL_PIN(172, "PLGPIO172"), \
  357. PINCTRL_PIN(173, "PLGPIO173"), \
  358. PINCTRL_PIN(174, "PLGPIO174"), \
  359. PINCTRL_PIN(175, "PLGPIO175"), \
  360. PINCTRL_PIN(176, "PLGPIO176"), \
  361. PINCTRL_PIN(177, "PLGPIO177"), \
  362. PINCTRL_PIN(178, "PLGPIO178"), \
  363. PINCTRL_PIN(179, "PLGPIO179"), \
  364. PINCTRL_PIN(180, "PLGPIO180"), \
  365. PINCTRL_PIN(181, "PLGPIO181"), \
  366. PINCTRL_PIN(182, "PLGPIO182"), \
  367. PINCTRL_PIN(183, "PLGPIO183"), \
  368. PINCTRL_PIN(184, "PLGPIO184"), \
  369. PINCTRL_PIN(185, "PLGPIO185"), \
  370. PINCTRL_PIN(186, "PLGPIO186"), \
  371. PINCTRL_PIN(187, "PLGPIO187"), \
  372. PINCTRL_PIN(188, "PLGPIO188"), \
  373. PINCTRL_PIN(189, "PLGPIO189"), \
  374. PINCTRL_PIN(190, "PLGPIO190"), \
  375. PINCTRL_PIN(191, "PLGPIO191"), \
  376. PINCTRL_PIN(192, "PLGPIO192"), \
  377. PINCTRL_PIN(193, "PLGPIO193"), \
  378. PINCTRL_PIN(194, "PLGPIO194"), \
  379. PINCTRL_PIN(195, "PLGPIO195"), \
  380. PINCTRL_PIN(196, "PLGPIO196"), \
  381. PINCTRL_PIN(197, "PLGPIO197"), \
  382. PINCTRL_PIN(198, "PLGPIO198"), \
  383. PINCTRL_PIN(199, "PLGPIO199"), \
  384. PINCTRL_PIN(200, "PLGPIO200"), \
  385. PINCTRL_PIN(201, "PLGPIO201"), \
  386. PINCTRL_PIN(202, "PLGPIO202"), \
  387. PINCTRL_PIN(203, "PLGPIO203"), \
  388. PINCTRL_PIN(204, "PLGPIO204"), \
  389. PINCTRL_PIN(205, "PLGPIO205"), \
  390. PINCTRL_PIN(206, "PLGPIO206"), \
  391. PINCTRL_PIN(207, "PLGPIO207"), \
  392. PINCTRL_PIN(208, "PLGPIO208"), \
  393. PINCTRL_PIN(209, "PLGPIO209"), \
  394. PINCTRL_PIN(210, "PLGPIO210"), \
  395. PINCTRL_PIN(211, "PLGPIO211"), \
  396. PINCTRL_PIN(212, "PLGPIO212"), \
  397. PINCTRL_PIN(213, "PLGPIO213"), \
  398. PINCTRL_PIN(214, "PLGPIO214"), \
  399. PINCTRL_PIN(215, "PLGPIO215"), \
  400. PINCTRL_PIN(216, "PLGPIO216"), \
  401. PINCTRL_PIN(217, "PLGPIO217"), \
  402. PINCTRL_PIN(218, "PLGPIO218"), \
  403. PINCTRL_PIN(219, "PLGPIO219"), \
  404. PINCTRL_PIN(220, "PLGPIO220"), \
  405. PINCTRL_PIN(221, "PLGPIO221"), \
  406. PINCTRL_PIN(222, "PLGPIO222"), \
  407. PINCTRL_PIN(223, "PLGPIO223"), \
  408. PINCTRL_PIN(224, "PLGPIO224"), \
  409. PINCTRL_PIN(225, "PLGPIO225"), \
  410. PINCTRL_PIN(226, "PLGPIO226"), \
  411. PINCTRL_PIN(227, "PLGPIO227"), \
  412. PINCTRL_PIN(228, "PLGPIO228"), \
  413. PINCTRL_PIN(229, "PLGPIO229"), \
  414. PINCTRL_PIN(230, "PLGPIO230"), \
  415. PINCTRL_PIN(231, "PLGPIO231"), \
  416. PINCTRL_PIN(232, "PLGPIO232"), \
  417. PINCTRL_PIN(233, "PLGPIO233"), \
  418. PINCTRL_PIN(234, "PLGPIO234"), \
  419. PINCTRL_PIN(235, "PLGPIO235"), \
  420. PINCTRL_PIN(236, "PLGPIO236"), \
  421. PINCTRL_PIN(237, "PLGPIO237"), \
  422. PINCTRL_PIN(238, "PLGPIO238"), \
  423. PINCTRL_PIN(239, "PLGPIO239"), \
  424. PINCTRL_PIN(240, "PLGPIO240"), \
  425. PINCTRL_PIN(241, "PLGPIO241"), \
  426. PINCTRL_PIN(242, "PLGPIO242"), \
  427. PINCTRL_PIN(243, "PLGPIO243"), \
  428. PINCTRL_PIN(244, "PLGPIO244"), \
  429. PINCTRL_PIN(245, "PLGPIO245")
  430. #endif /* __PINMUX_SPEAR_H__ */