sh_pfc.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * SuperH Pin Function Controller Support
  4. *
  5. * Copyright (c) 2008 Magnus Damm
  6. */
  7. #ifndef __SH_PFC_H
  8. #define __SH_PFC_H
  9. #include <linux/bug.h>
  10. #include <linux/pinctrl/pinconf-generic.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/stringify.h>
  13. enum {
  14. PINMUX_TYPE_NONE,
  15. PINMUX_TYPE_FUNCTION,
  16. PINMUX_TYPE_GPIO,
  17. PINMUX_TYPE_OUTPUT,
  18. PINMUX_TYPE_INPUT,
  19. };
  20. #define SH_PFC_PIN_NONE U16_MAX
  21. #define SH_PFC_PIN_CFG_INPUT (1 << 0)
  22. #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
  23. #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
  24. #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
  25. #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
  26. SH_PFC_PIN_CFG_PULL_DOWN)
  27. #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
  28. #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
  29. #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
  30. struct sh_pfc_pin {
  31. u16 pin;
  32. u16 enum_id;
  33. const char *name;
  34. unsigned int configs;
  35. };
  36. #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
  37. { \
  38. .name = #alias, \
  39. .pins = n##_pins, \
  40. .mux = n##_mux, \
  41. .nr_pins = ARRAY_SIZE(n##_pins) + \
  42. BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
  43. }
  44. #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
  45. struct sh_pfc_pin_group {
  46. const char *name;
  47. const unsigned int *pins;
  48. const unsigned int *mux;
  49. unsigned int nr_pins;
  50. };
  51. /*
  52. * Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
  53. * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
  54. * in this case. It accepts an optional 'version' argument used when the
  55. * same group can appear on a different set of pins.
  56. */
  57. #define VIN_DATA_PIN_GROUP(n, s, ...) \
  58. { \
  59. .name = #n#s#__VA_ARGS__, \
  60. .pins = n##__VA_ARGS__##_pins.data##s, \
  61. .mux = n##__VA_ARGS__##_mux.data##s, \
  62. .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
  63. }
  64. union vin_data12 {
  65. unsigned int data12[12];
  66. unsigned int data10[10];
  67. unsigned int data8[8];
  68. };
  69. union vin_data16 {
  70. unsigned int data16[16];
  71. unsigned int data12[12];
  72. unsigned int data10[10];
  73. unsigned int data8[8];
  74. };
  75. union vin_data {
  76. unsigned int data24[24];
  77. unsigned int data20[20];
  78. unsigned int data16[16];
  79. unsigned int data12[12];
  80. unsigned int data10[10];
  81. unsigned int data8[8];
  82. unsigned int data4[4];
  83. };
  84. #define SH_PFC_FUNCTION(n) \
  85. { \
  86. .name = #n, \
  87. .groups = n##_groups, \
  88. .nr_groups = ARRAY_SIZE(n##_groups), \
  89. }
  90. struct sh_pfc_function {
  91. const char *name;
  92. const char * const *groups;
  93. unsigned int nr_groups;
  94. };
  95. struct pinmux_func {
  96. u16 enum_id;
  97. const char *name;
  98. };
  99. struct pinmux_cfg_reg {
  100. u32 reg;
  101. u8 reg_width, field_width;
  102. #ifdef DEBUG
  103. u16 nr_enum_ids; /* for variable width regs only */
  104. #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
  105. #else
  106. #define SET_NR_ENUM_IDS(n)
  107. #endif
  108. const u16 *enum_ids;
  109. const u8 *var_field_width;
  110. };
  111. #define GROUP(...) __VA_ARGS__
  112. /*
  113. * Describe a config register consisting of several fields of the same width
  114. * - name: Register name (unused, for documentation purposes only)
  115. * - r: Physical register address
  116. * - r_width: Width of the register (in bits)
  117. * - f_width: Width of the fixed-width register fields (in bits)
  118. * - ids: For each register field (from left to right, i.e. MSB to LSB),
  119. * 2^f_width enum IDs must be specified, one for each possible
  120. * combination of the register field bit values, all wrapped using
  121. * the GROUP() macro.
  122. */
  123. #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
  124. .reg = r, .reg_width = r_width, \
  125. .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
  126. BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
  127. (r_width / f_width) * (1 << f_width)), \
  128. .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
  129. { ids }
  130. /*
  131. * Describe a config register consisting of several fields of different widths
  132. * - name: Register name (unused, for documentation purposes only)
  133. * - r: Physical register address
  134. * - r_width: Width of the register (in bits)
  135. * - f_widths: List of widths of the register fields (in bits), from left
  136. * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
  137. * - ids: For each register field (from left to right, i.e. MSB to LSB),
  138. * 2^f_widths[i] enum IDs must be specified, one for each possible
  139. * combination of the register field bit values, all wrapped using
  140. * the GROUP() macro.
  141. */
  142. #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
  143. .reg = r, .reg_width = r_width, \
  144. .var_field_width = (const u8 []) { f_widths, 0 }, \
  145. SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
  146. .enum_ids = (const u16 []) { ids }
  147. struct pinmux_drive_reg_field {
  148. u16 pin;
  149. u8 offset;
  150. u8 size;
  151. };
  152. struct pinmux_drive_reg {
  153. u32 reg;
  154. const struct pinmux_drive_reg_field fields[8];
  155. };
  156. #define PINMUX_DRIVE_REG(name, r) \
  157. .reg = r, \
  158. .fields =
  159. struct pinmux_bias_reg {
  160. u32 puen; /* Pull-enable or pull-up control register */
  161. u32 pud; /* Pull-up/down control register (optional) */
  162. const u16 pins[32];
  163. };
  164. #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
  165. .puen = r1, \
  166. .pud = r2, \
  167. .pins =
  168. struct pinmux_ioctrl_reg {
  169. u32 reg;
  170. };
  171. struct pinmux_data_reg {
  172. u32 reg;
  173. u8 reg_width;
  174. const u16 *enum_ids;
  175. };
  176. /*
  177. * Describe a data register
  178. * - name: Register name (unused, for documentation purposes only)
  179. * - r: Physical register address
  180. * - r_width: Width of the register (in bits)
  181. * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
  182. * enum ID must be specified, all wrapped using the GROUP() macro.
  183. */
  184. #define PINMUX_DATA_REG(name, r, r_width, ids) \
  185. .reg = r, .reg_width = r_width + \
  186. BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
  187. r_width), \
  188. .enum_ids = (const u16 [r_width]) { ids }
  189. struct pinmux_irq {
  190. const short *gpios;
  191. };
  192. /*
  193. * Describe the mapping from GPIOs to a single IRQ
  194. * - ids...: List of GPIOs that are mapped to the same IRQ
  195. */
  196. #define PINMUX_IRQ(ids...) \
  197. { .gpios = (const short []) { ids, -1 } }
  198. struct pinmux_range {
  199. u16 begin;
  200. u16 end;
  201. u16 force;
  202. };
  203. struct sh_pfc_window {
  204. phys_addr_t phys;
  205. void __iomem *virt;
  206. unsigned long size;
  207. };
  208. struct sh_pfc_pin_range;
  209. struct sh_pfc {
  210. struct device *dev;
  211. const struct sh_pfc_soc_info *info;
  212. spinlock_t lock;
  213. unsigned int num_windows;
  214. struct sh_pfc_window *windows;
  215. unsigned int num_irqs;
  216. unsigned int *irqs;
  217. struct sh_pfc_pin_range *ranges;
  218. unsigned int nr_ranges;
  219. unsigned int nr_gpio_pins;
  220. struct sh_pfc_chip *gpio;
  221. u32 *saved_regs;
  222. };
  223. struct sh_pfc_soc_operations {
  224. int (*init)(struct sh_pfc *pfc);
  225. unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
  226. void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
  227. unsigned int bias);
  228. int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
  229. };
  230. struct sh_pfc_soc_info {
  231. const char *name;
  232. const struct sh_pfc_soc_operations *ops;
  233. struct pinmux_range input;
  234. struct pinmux_range output;
  235. struct pinmux_range function;
  236. const struct sh_pfc_pin *pins;
  237. unsigned int nr_pins;
  238. const struct sh_pfc_pin_group *groups;
  239. unsigned int nr_groups;
  240. const struct sh_pfc_function *functions;
  241. unsigned int nr_functions;
  242. #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
  243. const struct pinmux_func *func_gpios;
  244. unsigned int nr_func_gpios;
  245. #endif
  246. const struct pinmux_cfg_reg *cfg_regs;
  247. const struct pinmux_drive_reg *drive_regs;
  248. const struct pinmux_bias_reg *bias_regs;
  249. const struct pinmux_ioctrl_reg *ioctrl_regs;
  250. const struct pinmux_data_reg *data_regs;
  251. const u16 *pinmux_data;
  252. unsigned int pinmux_data_size;
  253. const struct pinmux_irq *gpio_irq;
  254. unsigned int gpio_irq_size;
  255. u32 unlock_reg;
  256. };
  257. extern const struct sh_pfc_soc_info emev2_pinmux_info;
  258. extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
  259. extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
  260. extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
  261. extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
  262. extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
  263. extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
  264. extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
  265. extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
  266. extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
  267. extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
  268. extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
  269. extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
  270. extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
  271. extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
  272. extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
  273. extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
  274. extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
  275. extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
  276. extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
  277. extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
  278. extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
  279. extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
  280. extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
  281. extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
  282. extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
  283. extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
  284. extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
  285. extern const struct sh_pfc_soc_info sh7203_pinmux_info;
  286. extern const struct sh_pfc_soc_info sh7264_pinmux_info;
  287. extern const struct sh_pfc_soc_info sh7269_pinmux_info;
  288. extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
  289. extern const struct sh_pfc_soc_info sh7720_pinmux_info;
  290. extern const struct sh_pfc_soc_info sh7722_pinmux_info;
  291. extern const struct sh_pfc_soc_info sh7723_pinmux_info;
  292. extern const struct sh_pfc_soc_info sh7724_pinmux_info;
  293. extern const struct sh_pfc_soc_info sh7734_pinmux_info;
  294. extern const struct sh_pfc_soc_info sh7757_pinmux_info;
  295. extern const struct sh_pfc_soc_info sh7785_pinmux_info;
  296. extern const struct sh_pfc_soc_info sh7786_pinmux_info;
  297. extern const struct sh_pfc_soc_info shx3_pinmux_info;
  298. /* -----------------------------------------------------------------------------
  299. * Helper macros to create pin and port lists
  300. */
  301. /*
  302. * sh_pfc_soc_info pinmux_data array macros
  303. */
  304. /*
  305. * Describe generic pinmux data
  306. * - data_or_mark: *_DATA or *_MARK enum ID
  307. * - ids...: List of enum IDs to associate with data_or_mark
  308. */
  309. #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
  310. /*
  311. * Describe a pinmux configuration without GPIO function that needs
  312. * configuration in a Peripheral Function Select Register (IPSR)
  313. * - ipsr: IPSR field (unused, for documentation purposes only)
  314. * - fn: Function name, referring to a field in the IPSR
  315. */
  316. #define PINMUX_IPSR_NOGP(ipsr, fn) \
  317. PINMUX_DATA(fn##_MARK, FN_##fn)
  318. /*
  319. * Describe a pinmux configuration with GPIO function that needs configuration
  320. * in both a Peripheral Function Select Register (IPSR) and in a
  321. * GPIO/Peripheral Function Select Register (GPSR)
  322. * - ipsr: IPSR field
  323. * - fn: Function name, also referring to the IPSR field
  324. */
  325. #define PINMUX_IPSR_GPSR(ipsr, fn) \
  326. PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
  327. /*
  328. * Describe a pinmux configuration without GPIO function that needs
  329. * configuration in a Peripheral Function Select Register (IPSR), and where the
  330. * pinmux function has a representation in a Module Select Register (MOD_SEL).
  331. * - ipsr: IPSR field (unused, for documentation purposes only)
  332. * - fn: Function name, also referring to the IPSR field
  333. * - msel: Module selector
  334. */
  335. #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
  336. PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
  337. /*
  338. * Describe a pinmux configuration with GPIO function where the pinmux function
  339. * has no representation in a Peripheral Function Select Register (IPSR), but
  340. * instead solely depends on a group selection.
  341. * - gpsr: GPSR field
  342. * - fn: Function name, also referring to the GPSR field
  343. * - gsel: Group selector
  344. */
  345. #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
  346. PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
  347. /*
  348. * Describe a pinmux configuration with GPIO function that needs configuration
  349. * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
  350. * Function Select Register (GPSR), and where the pinmux function has a
  351. * representation in a Module Select Register (MOD_SEL).
  352. * - ipsr: IPSR field
  353. * - fn: Function name, also referring to the IPSR field
  354. * - msel: Module selector
  355. */
  356. #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
  357. PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
  358. /*
  359. * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
  360. * an additional select register that controls physical multiplexing
  361. * with another pin.
  362. * - ipsr: IPSR field
  363. * - fn: Function name, also referring to the IPSR field
  364. * - psel: Physical multiplexing selector
  365. * - msel: Module selector
  366. */
  367. #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
  368. PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
  369. /*
  370. * Describe a pinmux configuration in which a pin is physically multiplexed
  371. * with other pins.
  372. * - ipsr: IPSR field
  373. * - fn: Function name
  374. * - psel: Physical multiplexing selector
  375. */
  376. #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
  377. PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
  378. /*
  379. * Describe a pinmux configuration for a single-function pin with GPIO
  380. * capability.
  381. * - fn: Function name
  382. */
  383. #define PINMUX_SINGLE(fn) \
  384. PINMUX_DATA(fn##_MARK, FN_##fn)
  385. /*
  386. * GP port style (32 ports banks)
  387. */
  388. #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
  389. fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
  390. #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
  391. #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
  392. PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
  393. PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
  394. PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
  395. PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
  396. #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
  397. #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
  398. PORT_GP_CFG_4(bank, fn, sfx, cfg), \
  399. PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
  400. PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
  401. #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
  402. #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
  403. PORT_GP_CFG_6(bank, fn, sfx, cfg), \
  404. PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
  405. PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
  406. #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
  407. #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
  408. PORT_GP_CFG_8(bank, fn, sfx, cfg), \
  409. PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
  410. #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
  411. #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
  412. PORT_GP_CFG_9(bank, fn, sfx, cfg), \
  413. PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
  414. #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
  415. #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
  416. PORT_GP_CFG_10(bank, fn, sfx, cfg), \
  417. PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
  418. #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
  419. #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
  420. PORT_GP_CFG_11(bank, fn, sfx, cfg), \
  421. PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
  422. #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
  423. #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
  424. PORT_GP_CFG_12(bank, fn, sfx, cfg), \
  425. PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
  426. PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
  427. #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
  428. #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
  429. PORT_GP_CFG_14(bank, fn, sfx, cfg), \
  430. PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
  431. #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
  432. #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
  433. PORT_GP_CFG_15(bank, fn, sfx, cfg), \
  434. PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
  435. #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
  436. #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
  437. PORT_GP_CFG_16(bank, fn, sfx, cfg), \
  438. PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
  439. #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
  440. #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
  441. PORT_GP_CFG_17(bank, fn, sfx, cfg), \
  442. PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
  443. #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
  444. #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
  445. PORT_GP_CFG_18(bank, fn, sfx, cfg), \
  446. PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
  447. PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
  448. #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
  449. #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
  450. PORT_GP_CFG_20(bank, fn, sfx, cfg), \
  451. PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
  452. #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
  453. #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
  454. PORT_GP_CFG_21(bank, fn, sfx, cfg), \
  455. PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
  456. #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
  457. #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
  458. PORT_GP_CFG_22(bank, fn, sfx, cfg), \
  459. PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
  460. #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
  461. #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
  462. PORT_GP_CFG_23(bank, fn, sfx, cfg), \
  463. PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
  464. #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
  465. #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
  466. PORT_GP_CFG_24(bank, fn, sfx, cfg), \
  467. PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
  468. #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
  469. #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
  470. PORT_GP_CFG_25(bank, fn, sfx, cfg), \
  471. PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
  472. #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
  473. #define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
  474. PORT_GP_CFG_26(bank, fn, sfx, cfg), \
  475. PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
  476. #define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
  477. #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
  478. PORT_GP_CFG_27(bank, fn, sfx, cfg), \
  479. PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
  480. #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
  481. #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
  482. PORT_GP_CFG_28(bank, fn, sfx, cfg), \
  483. PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
  484. #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
  485. #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
  486. PORT_GP_CFG_29(bank, fn, sfx, cfg), \
  487. PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
  488. #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
  489. #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
  490. PORT_GP_CFG_30(bank, fn, sfx, cfg), \
  491. PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
  492. PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
  493. #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
  494. #define PORT_GP_32_REV(bank, fn, sfx) \
  495. PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
  496. PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
  497. PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
  498. PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
  499. PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
  500. PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
  501. PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
  502. PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
  503. PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
  504. PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
  505. PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
  506. PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
  507. PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
  508. PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
  509. PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
  510. PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
  511. /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
  512. #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
  513. #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
  514. /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
  515. #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
  516. { \
  517. .pin = (bank * 32) + _pin, \
  518. .name = __stringify(_name), \
  519. .enum_id = _name##_DATA, \
  520. .configs = cfg, \
  521. }
  522. #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
  523. /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
  524. #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
  525. #define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
  526. /*
  527. * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
  528. *
  529. * The largest GP pin index is obtained by taking the size of a union,
  530. * containing one array per GP pin, sized by the corresponding pin index.
  531. * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
  532. * while the members of a union must be terminated by semicolons, the commas
  533. * are absorbed by wrapping them inside dummy attributes.
  534. */
  535. #define _GP_ENTRY(bank, pin, name, sfx, cfg) \
  536. deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
  537. #define GP_ASSIGN_LAST() \
  538. GP_LAST = sizeof(union { \
  539. char dummy[0] __attribute__((deprecated, \
  540. CPU_ALL_GP(_GP_ENTRY, unused), \
  541. deprecated)); \
  542. })
  543. /*
  544. * PORT style (linear pin space)
  545. */
  546. #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
  547. #define PORT_10(pn, fn, pfx, sfx) \
  548. PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
  549. PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
  550. PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
  551. PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
  552. PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
  553. #define PORT_90(pn, fn, pfx, sfx) \
  554. PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
  555. PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
  556. PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
  557. PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
  558. PORT_10(pn+90, fn, pfx##9, sfx)
  559. /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
  560. #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
  561. #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
  562. /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
  563. #define PINMUX_GPIO(_pin) \
  564. [GPIO_##_pin] = { \
  565. .pin = (u16)-1, \
  566. .name = __stringify(GPIO_##_pin), \
  567. .enum_id = _pin##_DATA, \
  568. }
  569. /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
  570. #define SH_PFC_PIN_CFG(_pin, cfgs) \
  571. { \
  572. .pin = _pin, \
  573. .name = __stringify(PORT##_pin), \
  574. .enum_id = PORT##_pin##_DATA, \
  575. .configs = cfgs, \
  576. }
  577. /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
  578. * PORT_name_OUT, PORT_name_IN marks
  579. */
  580. #define _PORT_DATA(pn, pfx, sfx) \
  581. PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
  582. PORT##pfx##_OUT, PORT##pfx##_IN)
  583. #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
  584. /*
  585. * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
  586. *
  587. * The largest PORT pin index is obtained by taking the size of a union,
  588. * containing one array per PORT pin, sized by the corresponding pin index.
  589. * As the fields in the CPU_ALL_PORT() macro definition are separated by
  590. * commas, while the members of a union must be terminated by semicolons, the
  591. * commas are absorbed by wrapping them inside dummy attributes.
  592. */
  593. #define _PORT_ENTRY(pn, pfx, sfx) \
  594. deprecated)); char pfx[pn] __attribute__((deprecated
  595. #define PORT_ASSIGN_LAST() \
  596. PORT_LAST = sizeof(union { \
  597. char dummy[0] __attribute__((deprecated, \
  598. CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
  599. deprecated)); \
  600. })
  601. /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
  602. #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
  603. [gpio - (base)] = { \
  604. .name = __stringify(gpio), \
  605. .enum_id = data_or_mark, \
  606. }
  607. #define GPIO_FN(str) \
  608. PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
  609. /*
  610. * Pins not associated with a GPIO port
  611. */
  612. #define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
  613. #define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
  614. /* NOGP_ALL - Expand to a list of PIN_id */
  615. #define _NOGP_ALL(pin, name, cfg) PIN_##pin
  616. #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
  617. /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
  618. #define _NOGP_PINMUX(_pin, _name, cfg) \
  619. { \
  620. .pin = PIN_##_pin, \
  621. .name = "PIN_" _name, \
  622. .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
  623. }
  624. #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
  625. /*
  626. * PORTnCR helper macro for SH-Mobile/R-Mobile
  627. */
  628. #define PORTCR(nr, reg) \
  629. { \
  630. PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
  631. GROUP(2, 2, 1, 3), \
  632. GROUP( \
  633. /* PULMD[1:0], handled by .set_bias() */ \
  634. 0, 0, 0, 0, \
  635. /* IE and OE */ \
  636. 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
  637. /* SEC, not supported */ \
  638. 0, 0, \
  639. /* PTMD[2:0] */ \
  640. PORT##nr##_FN0, PORT##nr##_FN1, \
  641. PORT##nr##_FN2, PORT##nr##_FN3, \
  642. PORT##nr##_FN4, PORT##nr##_FN5, \
  643. PORT##nr##_FN6, PORT##nr##_FN7 \
  644. )) \
  645. }
  646. /*
  647. * GPIO number helper macro for R-Car
  648. */
  649. #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
  650. #endif /* __SH_PFC_H */