pinctrl-rzn1.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
  4. *
  5. * Phil Edworthy <phil.edworthy@renesas.com>
  6. * Based on a driver originally written by Michel Pollet at Renesas.
  7. */
  8. #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
  9. #include <linux/clk.h>
  10. #include <linux/device.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/pinctrl/pinconf-generic.h>
  15. #include <linux/pinctrl/pinctrl.h>
  16. #include <linux/pinctrl/pinmux.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/slab.h>
  19. #include "../core.h"
  20. #include "../pinconf.h"
  21. #include "../pinctrl-utils.h"
  22. /* Field positions and masks in the pinmux registers */
  23. #define RZN1_L1_PIN_DRIVE_STRENGTH 10
  24. #define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
  25. #define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
  26. #define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
  27. #define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
  28. #define RZN1_L1_PIN_PULL 8
  29. #define RZN1_L1_PIN_PULL_NONE 0
  30. #define RZN1_L1_PIN_PULL_UP 1
  31. #define RZN1_L1_PIN_PULL_DOWN 3
  32. #define RZN1_L1_FUNCTION 0
  33. #define RZN1_L1_FUNC_MASK 0xf
  34. #define RZN1_L1_FUNCTION_L2 0xf
  35. /*
  36. * The hardware manual describes two levels of multiplexing, but it's more
  37. * logical to think of the hardware as three levels, with level 3 consisting of
  38. * the multiplexing for Ethernet MDIO signals.
  39. *
  40. * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
  41. * that level 2 functions are used instead. Level 2 has a lot more options,
  42. * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
  43. * floating, or one of seven internal peripherals. Unfortunately, there are two
  44. * level 2 functions that can select MDIO, and two MDIO channels so we have four
  45. * sets of level 3 functions.
  46. *
  47. * For this driver, we've compounded the numbers together, so:
  48. * 0 to 9 is level 1
  49. * 10 to 71 is 10 + level 2 number
  50. * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
  51. * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
  52. * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
  53. * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
  54. * Examples:
  55. * Function 28 corresponds UART0
  56. * Function 73 corresponds to MDIO0 to GMAC0
  57. *
  58. * There are 170 configurable pins (called PL_GPIO in the datasheet).
  59. */
  60. /*
  61. * Structure detailing the HW registers on the RZ/N1 devices.
  62. * Both the Level 1 mux registers and Level 2 mux registers have the same
  63. * structure. The only difference is that Level 2 has additional MDIO registers
  64. * at the end.
  65. */
  66. struct rzn1_pinctrl_regs {
  67. u32 conf[170];
  68. u32 pad0[86];
  69. u32 status_protect; /* 0x400 */
  70. /* MDIO mux registers, level2 only */
  71. u32 l2_mdio[2];
  72. };
  73. /**
  74. * struct rzn1_pmx_func - describes rzn1 pinmux functions
  75. * @name: the name of this specific function
  76. * @groups: corresponding pin groups
  77. * @num_groups: the number of groups
  78. */
  79. struct rzn1_pmx_func {
  80. const char *name;
  81. const char **groups;
  82. unsigned int num_groups;
  83. };
  84. /**
  85. * struct rzn1_pin_group - describes an rzn1 pin group
  86. * @name: the name of this specific pin group
  87. * @func: the name of the function selected by this group
  88. * @npins: the number of pins in this group array, i.e. the number of
  89. * elements in .pins so we can iterate over that array
  90. * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
  91. * @pin_ids: array of pin_ids, i.e. the value used to select the mux
  92. */
  93. struct rzn1_pin_group {
  94. const char *name;
  95. const char *func;
  96. unsigned int npins;
  97. unsigned int *pins;
  98. u8 *pin_ids;
  99. };
  100. struct rzn1_pinctrl {
  101. struct device *dev;
  102. struct clk *clk;
  103. struct pinctrl_dev *pctl;
  104. struct rzn1_pinctrl_regs __iomem *lev1;
  105. struct rzn1_pinctrl_regs __iomem *lev2;
  106. u32 lev1_protect_phys;
  107. u32 lev2_protect_phys;
  108. int mdio_func[2];
  109. struct rzn1_pin_group *groups;
  110. unsigned int ngroups;
  111. struct rzn1_pmx_func *functions;
  112. unsigned int nfunctions;
  113. };
  114. #define RZN1_PINS_PROP "pinmux"
  115. #define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin)
  116. static const struct pinctrl_pin_desc rzn1_pins[] = {
  117. RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4),
  118. RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9),
  119. RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14),
  120. RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19),
  121. RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24),
  122. RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29),
  123. RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34),
  124. RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39),
  125. RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44),
  126. RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49),
  127. RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54),
  128. RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59),
  129. RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64),
  130. RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69),
  131. RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74),
  132. RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79),
  133. RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84),
  134. RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89),
  135. RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94),
  136. RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99),
  137. RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103),
  138. RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107),
  139. RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111),
  140. RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115),
  141. RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119),
  142. RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123),
  143. RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127),
  144. RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131),
  145. RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135),
  146. RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139),
  147. RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143),
  148. RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147),
  149. RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151),
  150. RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155),
  151. RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159),
  152. RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163),
  153. RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167),
  154. RZN1_PIN(168), RZN1_PIN(169),
  155. };
  156. enum {
  157. LOCK_LEVEL1 = 0x1,
  158. LOCK_LEVEL2 = 0x2,
  159. LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
  160. };
  161. static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value)
  162. {
  163. /*
  164. * The pinmux configuration is locked by writing the physical address of
  165. * the status_protect register to itself. It is unlocked by writing the
  166. * address | 1.
  167. */
  168. if (lock & LOCK_LEVEL1) {
  169. u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1);
  170. writel(val, &ipctl->lev1->status_protect);
  171. }
  172. if (lock & LOCK_LEVEL2) {
  173. u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2);
  174. writel(val, &ipctl->lev2->status_protect);
  175. }
  176. }
  177. static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
  178. u32 func)
  179. {
  180. if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
  181. dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
  182. ipctl->mdio_func[mdio] = func;
  183. dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
  184. writel(func, &ipctl->lev2->l2_mdio[mdio]);
  185. }
  186. /*
  187. * Using a composite pin description, set the hardware pinmux registers
  188. * with the corresponding values.
  189. * Make sure to unlock write protection and reset it afterward.
  190. *
  191. * NOTE: There is no protection for potential concurrency, it is assumed these
  192. * calls are serialized already.
  193. */
  194. static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin,
  195. u32 pin_config, u8 use_locks)
  196. {
  197. u32 l1_cache;
  198. u32 l2_cache;
  199. u32 l1;
  200. u32 l2;
  201. /* Level 3 MDIO multiplexing */
  202. if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ &&
  203. pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) {
  204. int mdio_channel;
  205. u32 mdio_func;
  206. if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ)
  207. mdio_channel = 0;
  208. else
  209. mdio_channel = 1;
  210. /* Get MDIO func, and convert the func to the level 2 number */
  211. if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) {
  212. mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ;
  213. pin_config = RZN1_FUNC_ETH_MDIO;
  214. } else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) {
  215. mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ;
  216. pin_config = RZN1_FUNC_ETH_MDIO_E1;
  217. } else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) {
  218. mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ;
  219. pin_config = RZN1_FUNC_ETH_MDIO;
  220. } else {
  221. mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ;
  222. pin_config = RZN1_FUNC_ETH_MDIO_E1;
  223. }
  224. rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func);
  225. }
  226. /* Note here, we do not allow anything past the MDIO Mux values */
  227. if (pin >= ARRAY_SIZE(ipctl->lev1->conf) ||
  228. pin_config >= RZN1_FUNC_MDIO0_HIGHZ)
  229. return -EINVAL;
  230. l1 = readl(&ipctl->lev1->conf[pin]);
  231. l1_cache = l1;
  232. l2 = readl(&ipctl->lev2->conf[pin]);
  233. l2_cache = l2;
  234. dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config);
  235. l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
  236. if (pin_config < RZN1_FUNC_L2_OFFSET) {
  237. l1 |= (pin_config << RZN1_L1_FUNCTION);
  238. } else {
  239. l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
  240. l2 = pin_config - RZN1_FUNC_L2_OFFSET;
  241. }
  242. /* If either configuration changes, we update both anyway */
  243. if (l1 != l1_cache || l2 != l2_cache) {
  244. writel(l1, &ipctl->lev1->conf[pin]);
  245. writel(l2, &ipctl->lev2->conf[pin]);
  246. }
  247. return 0;
  248. }
  249. static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name(
  250. const struct rzn1_pinctrl *ipctl, const char *name)
  251. {
  252. unsigned int i;
  253. for (i = 0; i < ipctl->ngroups; i++) {
  254. if (!strcmp(ipctl->groups[i].name, name))
  255. return &ipctl->groups[i];
  256. }
  257. return NULL;
  258. }
  259. static int rzn1_get_groups_count(struct pinctrl_dev *pctldev)
  260. {
  261. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  262. return ipctl->ngroups;
  263. }
  264. static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev,
  265. unsigned int selector)
  266. {
  267. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  268. return ipctl->groups[selector].name;
  269. }
  270. static int rzn1_get_group_pins(struct pinctrl_dev *pctldev,
  271. unsigned int selector, const unsigned int **pins,
  272. unsigned int *npins)
  273. {
  274. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  275. if (selector >= ipctl->ngroups)
  276. return -EINVAL;
  277. *pins = ipctl->groups[selector].pins;
  278. *npins = ipctl->groups[selector].npins;
  279. return 0;
  280. }
  281. /*
  282. * This function is called for each pinctl 'Function' node.
  283. * Sub-nodes can be used to describe multiple 'Groups' for the 'Function'
  284. * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'.
  285. * Each 'Group' uses pinmux = <...> to detail the pins and data used to select
  286. * the functionality. Each 'Group' has optional pin configurations that apply
  287. * to all pins in the 'Group'.
  288. */
  289. static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev,
  290. struct device_node *np,
  291. struct pinctrl_map **map,
  292. unsigned int *num_maps)
  293. {
  294. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  295. const struct rzn1_pin_group *grp;
  296. unsigned long *configs = NULL;
  297. unsigned int reserved_maps = *num_maps;
  298. unsigned int num_configs = 0;
  299. unsigned int reserve = 1;
  300. int ret;
  301. dev_dbg(ipctl->dev, "processing node %pOF\n", np);
  302. grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name);
  303. if (!grp) {
  304. dev_err(ipctl->dev, "unable to find group for node %pOF\n", np);
  305. return -EINVAL;
  306. }
  307. /* Get the group's pin configuration */
  308. ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
  309. &num_configs);
  310. if (ret < 0) {
  311. dev_err(ipctl->dev, "%pOF: could not parse property\n", np);
  312. return ret;
  313. }
  314. if (num_configs)
  315. reserve++;
  316. /* Increase the number of maps to cover this group */
  317. ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
  318. reserve);
  319. if (ret < 0)
  320. goto out;
  321. /* Associate the group with the function */
  322. ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps,
  323. grp->name, grp->func);
  324. if (ret < 0)
  325. goto out;
  326. if (num_configs) {
  327. /* Associate the group's pin configuration with the group */
  328. ret = pinctrl_utils_add_map_configs(pctldev, map,
  329. &reserved_maps, num_maps, grp->name,
  330. configs, num_configs,
  331. PIN_MAP_TYPE_CONFIGS_GROUP);
  332. if (ret < 0)
  333. goto out;
  334. }
  335. dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n",
  336. grp->func, grp->name, grp->npins);
  337. out:
  338. kfree(configs);
  339. return ret;
  340. }
  341. static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
  342. struct device_node *np,
  343. struct pinctrl_map **map,
  344. unsigned int *num_maps)
  345. {
  346. struct device_node *child;
  347. int ret;
  348. *map = NULL;
  349. *num_maps = 0;
  350. ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps);
  351. if (ret < 0)
  352. return ret;
  353. for_each_child_of_node(np, child) {
  354. ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
  355. if (ret < 0) {
  356. of_node_put(child);
  357. return ret;
  358. }
  359. }
  360. return 0;
  361. }
  362. static const struct pinctrl_ops rzn1_pctrl_ops = {
  363. .get_groups_count = rzn1_get_groups_count,
  364. .get_group_name = rzn1_get_group_name,
  365. .get_group_pins = rzn1_get_group_pins,
  366. .dt_node_to_map = rzn1_dt_node_to_map,
  367. .dt_free_map = pinctrl_utils_free_map,
  368. };
  369. static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
  370. {
  371. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  372. return ipctl->nfunctions;
  373. }
  374. static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev,
  375. unsigned int selector)
  376. {
  377. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  378. return ipctl->functions[selector].name;
  379. }
  380. static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev,
  381. unsigned int selector,
  382. const char * const **groups,
  383. unsigned int * const num_groups)
  384. {
  385. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  386. *groups = ipctl->functions[selector].groups;
  387. *num_groups = ipctl->functions[selector].num_groups;
  388. return 0;
  389. }
  390. static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
  391. unsigned int group)
  392. {
  393. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  394. struct rzn1_pin_group *grp = &ipctl->groups[group];
  395. unsigned int i, grp_pins = grp->npins;
  396. dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n",
  397. ipctl->functions[selector].name, selector, grp->name, group);
  398. rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL);
  399. for (i = 0; i < grp_pins; i++)
  400. rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0);
  401. rzn1_hw_set_lock(ipctl, LOCK_ALL, 0);
  402. return 0;
  403. }
  404. static const struct pinmux_ops rzn1_pmx_ops = {
  405. .get_functions_count = rzn1_pmx_get_funcs_count,
  406. .get_function_name = rzn1_pmx_get_func_name,
  407. .get_function_groups = rzn1_pmx_get_groups,
  408. .set_mux = rzn1_set_mux,
  409. };
  410. static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
  411. unsigned long *config)
  412. {
  413. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  414. enum pin_config_param param = pinconf_to_config_param(*config);
  415. static const u32 reg_drive[4] = { 4, 6, 8, 12 };
  416. u32 pull, drive, l1mux;
  417. u32 l1, l2, arg = 0;
  418. if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
  419. return -EINVAL;
  420. l1 = readl(&ipctl->lev1->conf[pin]);
  421. l1mux = l1 & RZN1_L1_FUNC_MASK;
  422. pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3;
  423. drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3;
  424. switch (param) {
  425. case PIN_CONFIG_BIAS_PULL_UP:
  426. if (pull != RZN1_L1_PIN_PULL_UP)
  427. return -EINVAL;
  428. break;
  429. case PIN_CONFIG_BIAS_PULL_DOWN:
  430. if (pull != RZN1_L1_PIN_PULL_DOWN)
  431. return -EINVAL;
  432. break;
  433. case PIN_CONFIG_BIAS_DISABLE:
  434. if (pull != RZN1_L1_PIN_PULL_NONE)
  435. return -EINVAL;
  436. break;
  437. case PIN_CONFIG_DRIVE_STRENGTH:
  438. arg = reg_drive[drive];
  439. break;
  440. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  441. l2 = readl(&ipctl->lev2->conf[pin]);
  442. if (l1mux == RZN1_L1_FUNCTION_L2) {
  443. if (l2 != 0)
  444. return -EINVAL;
  445. } else if (l1mux != RZN1_FUNC_HIGHZ) {
  446. return -EINVAL;
  447. }
  448. break;
  449. default:
  450. return -ENOTSUPP;
  451. }
  452. *config = pinconf_to_config_packed(param, arg);
  453. return 0;
  454. }
  455. static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  456. unsigned long *configs, unsigned int num_configs)
  457. {
  458. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  459. enum pin_config_param param;
  460. unsigned int i;
  461. u32 l1, l1_cache;
  462. u32 drv;
  463. u32 arg;
  464. if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
  465. return -EINVAL;
  466. l1 = readl(&ipctl->lev1->conf[pin]);
  467. l1_cache = l1;
  468. for (i = 0; i < num_configs; i++) {
  469. param = pinconf_to_config_param(configs[i]);
  470. arg = pinconf_to_config_argument(configs[i]);
  471. switch (param) {
  472. case PIN_CONFIG_BIAS_PULL_UP:
  473. dev_dbg(ipctl->dev, "set pin %d pull up\n", pin);
  474. l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
  475. l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
  476. break;
  477. case PIN_CONFIG_BIAS_PULL_DOWN:
  478. dev_dbg(ipctl->dev, "set pin %d pull down\n", pin);
  479. l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
  480. l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
  481. break;
  482. case PIN_CONFIG_BIAS_DISABLE:
  483. dev_dbg(ipctl->dev, "set pin %d bias off\n", pin);
  484. l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
  485. l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
  486. break;
  487. case PIN_CONFIG_DRIVE_STRENGTH:
  488. dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg);
  489. switch (arg) {
  490. case 4:
  491. drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
  492. break;
  493. case 6:
  494. drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
  495. break;
  496. case 8:
  497. drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
  498. break;
  499. case 12:
  500. drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
  501. break;
  502. default:
  503. dev_err(ipctl->dev,
  504. "Drive strength %umA not supported\n",
  505. arg);
  506. return -EINVAL;
  507. }
  508. l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
  509. l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
  510. break;
  511. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  512. dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin);
  513. l1 &= ~RZN1_L1_FUNC_MASK;
  514. l1 |= RZN1_FUNC_HIGHZ;
  515. break;
  516. default:
  517. return -ENOTSUPP;
  518. }
  519. }
  520. if (l1 != l1_cache) {
  521. rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1);
  522. writel(l1, &ipctl->lev1->conf[pin]);
  523. rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0);
  524. }
  525. return 0;
  526. }
  527. static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev,
  528. unsigned int selector,
  529. unsigned long *config)
  530. {
  531. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  532. struct rzn1_pin_group *grp = &ipctl->groups[selector];
  533. unsigned long old = 0;
  534. unsigned int i;
  535. dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector);
  536. for (i = 0; i < grp->npins; i++) {
  537. if (rzn1_pinconf_get(pctldev, grp->pins[i], config))
  538. return -ENOTSUPP;
  539. /* configs do not match between two pins */
  540. if (i && (old != *config))
  541. return -ENOTSUPP;
  542. old = *config;
  543. }
  544. return 0;
  545. }
  546. static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev,
  547. unsigned int selector,
  548. unsigned long *configs,
  549. unsigned int num_configs)
  550. {
  551. struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  552. struct rzn1_pin_group *grp = &ipctl->groups[selector];
  553. unsigned int i;
  554. int ret;
  555. dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n",
  556. grp->name, selector, configs, num_configs);
  557. for (i = 0; i < grp->npins; i++) {
  558. unsigned int pin = grp->pins[i];
  559. ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs);
  560. if (ret)
  561. return ret;
  562. }
  563. return 0;
  564. }
  565. static const struct pinconf_ops rzn1_pinconf_ops = {
  566. .is_generic = true,
  567. .pin_config_get = rzn1_pinconf_get,
  568. .pin_config_set = rzn1_pinconf_set,
  569. .pin_config_group_get = rzn1_pinconf_group_get,
  570. .pin_config_group_set = rzn1_pinconf_group_set,
  571. .pin_config_config_dbg_show = pinconf_generic_dump_config,
  572. };
  573. static struct pinctrl_desc rzn1_pinctrl_desc = {
  574. .pctlops = &rzn1_pctrl_ops,
  575. .pmxops = &rzn1_pmx_ops,
  576. .confops = &rzn1_pinconf_ops,
  577. .owner = THIS_MODULE,
  578. };
  579. static int rzn1_pinctrl_parse_groups(struct device_node *np,
  580. struct rzn1_pin_group *grp,
  581. struct rzn1_pinctrl *ipctl)
  582. {
  583. const __be32 *list;
  584. unsigned int i;
  585. int size;
  586. dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name);
  587. /* Initialise group */
  588. grp->name = np->name;
  589. /*
  590. * The binding format is
  591. * pinmux = <PIN_FUNC_ID CONFIG ...>,
  592. * do sanity check and calculate pins number
  593. */
  594. list = of_get_property(np, RZN1_PINS_PROP, &size);
  595. if (!list) {
  596. dev_err(ipctl->dev,
  597. "no " RZN1_PINS_PROP " property in node %pOF\n", np);
  598. return -EINVAL;
  599. }
  600. if (!size) {
  601. dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n",
  602. np);
  603. return -EINVAL;
  604. }
  605. grp->npins = size / sizeof(list[0]);
  606. grp->pin_ids = devm_kmalloc_array(ipctl->dev,
  607. grp->npins, sizeof(grp->pin_ids[0]),
  608. GFP_KERNEL);
  609. grp->pins = devm_kmalloc_array(ipctl->dev,
  610. grp->npins, sizeof(grp->pins[0]),
  611. GFP_KERNEL);
  612. if (!grp->pin_ids || !grp->pins)
  613. return -ENOMEM;
  614. for (i = 0; i < grp->npins; i++) {
  615. u32 pin_id = be32_to_cpu(*list++);
  616. grp->pins[i] = pin_id & 0xff;
  617. grp->pin_ids[i] = (pin_id >> 8) & 0x7f;
  618. }
  619. return grp->npins;
  620. }
  621. static int rzn1_pinctrl_count_function_groups(struct device_node *np)
  622. {
  623. struct device_node *child;
  624. int count = 0;
  625. if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
  626. count++;
  627. for_each_child_of_node(np, child) {
  628. if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
  629. count++;
  630. }
  631. return count;
  632. }
  633. static int rzn1_pinctrl_parse_functions(struct device_node *np,
  634. struct rzn1_pinctrl *ipctl,
  635. unsigned int index)
  636. {
  637. struct rzn1_pmx_func *func;
  638. struct rzn1_pin_group *grp;
  639. struct device_node *child;
  640. unsigned int i = 0;
  641. int ret;
  642. func = &ipctl->functions[index];
  643. /* Initialise function */
  644. func->name = np->name;
  645. func->num_groups = rzn1_pinctrl_count_function_groups(np);
  646. if (func->num_groups == 0) {
  647. dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
  648. return -EINVAL;
  649. }
  650. dev_dbg(ipctl->dev, "function %s has %d groups\n",
  651. np->name, func->num_groups);
  652. func->groups = devm_kmalloc_array(ipctl->dev,
  653. func->num_groups, sizeof(char *),
  654. GFP_KERNEL);
  655. if (!func->groups)
  656. return -ENOMEM;
  657. if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) {
  658. func->groups[i] = np->name;
  659. grp = &ipctl->groups[ipctl->ngroups];
  660. grp->func = func->name;
  661. ret = rzn1_pinctrl_parse_groups(np, grp, ipctl);
  662. if (ret < 0)
  663. return ret;
  664. i++;
  665. ipctl->ngroups++;
  666. }
  667. for_each_child_of_node(np, child) {
  668. func->groups[i] = child->name;
  669. grp = &ipctl->groups[ipctl->ngroups];
  670. grp->func = func->name;
  671. ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
  672. if (ret < 0) {
  673. of_node_put(child);
  674. return ret;
  675. }
  676. i++;
  677. ipctl->ngroups++;
  678. }
  679. dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n",
  680. np->name, i, func->num_groups);
  681. return 0;
  682. }
  683. static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
  684. struct rzn1_pinctrl *ipctl)
  685. {
  686. struct device_node *np = pdev->dev.of_node;
  687. struct device_node *child;
  688. unsigned int maxgroups = 0;
  689. unsigned int i = 0;
  690. int nfuncs = 0;
  691. int ret;
  692. nfuncs = of_get_child_count(np);
  693. if (nfuncs <= 0)
  694. return 0;
  695. ipctl->nfunctions = nfuncs;
  696. ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs,
  697. sizeof(*ipctl->functions),
  698. GFP_KERNEL);
  699. if (!ipctl->functions)
  700. return -ENOMEM;
  701. ipctl->ngroups = 0;
  702. for_each_child_of_node(np, child)
  703. maxgroups += rzn1_pinctrl_count_function_groups(child);
  704. ipctl->groups = devm_kmalloc_array(&pdev->dev,
  705. maxgroups,
  706. sizeof(*ipctl->groups),
  707. GFP_KERNEL);
  708. if (!ipctl->groups)
  709. return -ENOMEM;
  710. for_each_child_of_node(np, child) {
  711. ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
  712. if (ret < 0) {
  713. of_node_put(child);
  714. return ret;
  715. }
  716. }
  717. return 0;
  718. }
  719. static int rzn1_pinctrl_probe(struct platform_device *pdev)
  720. {
  721. struct rzn1_pinctrl *ipctl;
  722. struct resource *res;
  723. int ret;
  724. /* Create state holders etc for this driver */
  725. ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
  726. if (!ipctl)
  727. return -ENOMEM;
  728. ipctl->mdio_func[0] = -1;
  729. ipctl->mdio_func[1] = -1;
  730. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  731. ipctl->lev1_protect_phys = (u32)res->start + 0x400;
  732. ipctl->lev1 = devm_ioremap_resource(&pdev->dev, res);
  733. if (IS_ERR(ipctl->lev1))
  734. return PTR_ERR(ipctl->lev1);
  735. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  736. ipctl->lev2_protect_phys = (u32)res->start + 0x400;
  737. ipctl->lev2 = devm_ioremap_resource(&pdev->dev, res);
  738. if (IS_ERR(ipctl->lev2))
  739. return PTR_ERR(ipctl->lev2);
  740. ipctl->clk = devm_clk_get(&pdev->dev, NULL);
  741. if (IS_ERR(ipctl->clk))
  742. return PTR_ERR(ipctl->clk);
  743. ret = clk_prepare_enable(ipctl->clk);
  744. if (ret)
  745. return ret;
  746. ipctl->dev = &pdev->dev;
  747. rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
  748. rzn1_pinctrl_desc.pins = rzn1_pins;
  749. rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
  750. ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
  751. if (ret) {
  752. dev_err(&pdev->dev, "fail to probe dt properties\n");
  753. goto err_clk;
  754. }
  755. platform_set_drvdata(pdev, ipctl);
  756. ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc,
  757. ipctl, &ipctl->pctl);
  758. if (ret) {
  759. dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n");
  760. goto err_clk;
  761. }
  762. ret = pinctrl_enable(ipctl->pctl);
  763. if (ret)
  764. goto err_clk;
  765. dev_info(&pdev->dev, "probed\n");
  766. return 0;
  767. err_clk:
  768. clk_disable_unprepare(ipctl->clk);
  769. return ret;
  770. }
  771. static int rzn1_pinctrl_remove(struct platform_device *pdev)
  772. {
  773. struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
  774. clk_disable_unprepare(ipctl->clk);
  775. return 0;
  776. }
  777. static const struct of_device_id rzn1_pinctrl_match[] = {
  778. { .compatible = "renesas,rzn1-pinctrl", },
  779. {}
  780. };
  781. MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
  782. static struct platform_driver rzn1_pinctrl_driver = {
  783. .probe = rzn1_pinctrl_probe,
  784. .remove = rzn1_pinctrl_remove,
  785. .driver = {
  786. .name = "rzn1-pinctrl",
  787. .of_match_table = rzn1_pinctrl_match,
  788. },
  789. };
  790. static int __init _pinctrl_drv_register(void)
  791. {
  792. return platform_driver_register(&rzn1_pinctrl_driver);
  793. }
  794. subsys_initcall(_pinctrl_drv_register);
  795. MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
  796. MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver");
  797. MODULE_LICENSE("GPL v2");