pinctrl-rza1.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
  4. *
  5. * Copyright (C) 2017 Jacopo Mondi
  6. */
  7. /*
  8. * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
  9. * family.
  10. * This includes SoCs which are sub- or super- sets of this particular line,
  11. * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
  12. */
  13. #include <linux/bitops.h>
  14. #include <linux/err.h>
  15. #include <linux/gpio/driver.h>
  16. #include <linux/init.h>
  17. #include <linux/ioport.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_device.h>
  22. #include <linux/pinctrl/pinconf-generic.h>
  23. #include <linux/pinctrl/pinctrl.h>
  24. #include <linux/pinctrl/pinmux.h>
  25. #include <linux/slab.h>
  26. #include "../core.h"
  27. #include "../devicetree.h"
  28. #include "../pinconf.h"
  29. #include "../pinmux.h"
  30. #define DRIVER_NAME "pinctrl-rza1"
  31. #define RZA1_P_REG 0x0000
  32. #define RZA1_PPR_REG 0x0200
  33. #define RZA1_PM_REG 0x0300
  34. #define RZA1_PMC_REG 0x0400
  35. #define RZA1_PFC_REG 0x0500
  36. #define RZA1_PFCE_REG 0x0600
  37. #define RZA1_PFCEA_REG 0x0a00
  38. #define RZA1_PIBC_REG 0x4000
  39. #define RZA1_PBDC_REG 0x4100
  40. #define RZA1_PIPC_REG 0x4200
  41. #define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
  42. #define RZA1_NPORTS 12
  43. #define RZA1_PINS_PER_PORT 16
  44. #define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
  45. #define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)
  46. #define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)
  47. /*
  48. * Use 16 lower bits [15:0] for pin identifier
  49. * Use 16 higher bits [31:16] for pin mux function
  50. */
  51. #define MUX_PIN_ID_MASK GENMASK(15, 0)
  52. #define MUX_FUNC_MASK GENMASK(31, 16)
  53. #define MUX_FUNC_OFFS 16
  54. #define MUX_FUNC(pinconf) \
  55. ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
  56. #define MUX_FUNC_PFC_MASK BIT(0)
  57. #define MUX_FUNC_PFCE_MASK BIT(1)
  58. #define MUX_FUNC_PFCEA_MASK BIT(2)
  59. /* Pin mux flags */
  60. #define MUX_FLAGS_BIDIR BIT(0)
  61. #define MUX_FLAGS_SWIO_INPUT BIT(1)
  62. #define MUX_FLAGS_SWIO_OUTPUT BIT(2)
  63. /* ----------------------------------------------------------------------------
  64. * RZ/A1 pinmux flags
  65. */
  66. /*
  67. * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
  68. */
  69. struct rza1_bidir_pin {
  70. u8 pin: 4;
  71. u8 func: 4;
  72. };
  73. /*
  74. * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
  75. * Each struct rza1_bidir_entry describes a port.
  76. */
  77. struct rza1_bidir_entry {
  78. const unsigned int npins;
  79. const struct rza1_bidir_pin *pins;
  80. };
  81. /*
  82. * rza1_swio_pin - describe a single pin that needs swio flag applied.
  83. */
  84. struct rza1_swio_pin {
  85. u16 pin: 4;
  86. u16 port: 4;
  87. u16 func: 4;
  88. u16 input: 1;
  89. };
  90. /*
  91. * rza1_swio_entry - describe a list of pins that needs swio flag applied
  92. */
  93. struct rza1_swio_entry {
  94. const unsigned int npins;
  95. const struct rza1_swio_pin *pins;
  96. };
  97. /*
  98. * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
  99. */
  100. struct rza1_pinmux_conf {
  101. const struct rza1_bidir_entry *bidir_entries;
  102. const struct rza1_swio_entry *swio_entries;
  103. };
  104. /* ----------------------------------------------------------------------------
  105. * RZ/A1H (r7s72100) pinmux flags
  106. */
  107. static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
  108. { .pin = 0, .func = 1 },
  109. { .pin = 1, .func = 1 },
  110. { .pin = 2, .func = 1 },
  111. { .pin = 3, .func = 1 },
  112. { .pin = 4, .func = 1 },
  113. { .pin = 5, .func = 1 },
  114. { .pin = 6, .func = 1 },
  115. { .pin = 7, .func = 1 },
  116. };
  117. static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
  118. { .pin = 0, .func = 1 },
  119. { .pin = 1, .func = 1 },
  120. { .pin = 2, .func = 1 },
  121. { .pin = 3, .func = 1 },
  122. { .pin = 4, .func = 1 },
  123. { .pin = 0, .func = 4 },
  124. { .pin = 1, .func = 4 },
  125. { .pin = 2, .func = 4 },
  126. { .pin = 3, .func = 4 },
  127. { .pin = 5, .func = 1 },
  128. { .pin = 6, .func = 1 },
  129. { .pin = 7, .func = 1 },
  130. { .pin = 8, .func = 1 },
  131. { .pin = 9, .func = 1 },
  132. { .pin = 10, .func = 1 },
  133. { .pin = 11, .func = 1 },
  134. { .pin = 12, .func = 1 },
  135. { .pin = 13, .func = 1 },
  136. { .pin = 14, .func = 1 },
  137. { .pin = 15, .func = 1 },
  138. { .pin = 12, .func = 4 },
  139. { .pin = 13, .func = 4 },
  140. { .pin = 14, .func = 4 },
  141. { .pin = 15, .func = 4 },
  142. };
  143. static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
  144. { .pin = 3, .func = 2 },
  145. { .pin = 10, .func = 7 },
  146. { .pin = 11, .func = 7 },
  147. { .pin = 13, .func = 7 },
  148. { .pin = 14, .func = 7 },
  149. { .pin = 15, .func = 7 },
  150. { .pin = 10, .func = 8 },
  151. { .pin = 11, .func = 8 },
  152. { .pin = 13, .func = 8 },
  153. { .pin = 14, .func = 8 },
  154. { .pin = 15, .func = 8 },
  155. };
  156. static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
  157. { .pin = 0, .func = 8 },
  158. { .pin = 1, .func = 8 },
  159. { .pin = 2, .func = 8 },
  160. { .pin = 3, .func = 8 },
  161. { .pin = 10, .func = 3 },
  162. { .pin = 11, .func = 3 },
  163. { .pin = 13, .func = 3 },
  164. { .pin = 14, .func = 3 },
  165. { .pin = 15, .func = 3 },
  166. { .pin = 10, .func = 4 },
  167. { .pin = 11, .func = 4 },
  168. { .pin = 13, .func = 4 },
  169. { .pin = 14, .func = 4 },
  170. { .pin = 15, .func = 4 },
  171. { .pin = 12, .func = 5 },
  172. { .pin = 13, .func = 5 },
  173. { .pin = 14, .func = 5 },
  174. { .pin = 15, .func = 5 },
  175. };
  176. static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
  177. { .pin = 0, .func = 1 },
  178. { .pin = 1, .func = 1 },
  179. { .pin = 2, .func = 1 },
  180. { .pin = 3, .func = 1 },
  181. { .pin = 4, .func = 1 },
  182. { .pin = 5, .func = 1 },
  183. { .pin = 6, .func = 1 },
  184. { .pin = 7, .func = 1 },
  185. { .pin = 8, .func = 1 },
  186. { .pin = 9, .func = 1 },
  187. { .pin = 10, .func = 1 },
  188. { .pin = 11, .func = 1 },
  189. { .pin = 12, .func = 1 },
  190. { .pin = 13, .func = 1 },
  191. { .pin = 14, .func = 1 },
  192. { .pin = 15, .func = 1 },
  193. };
  194. static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
  195. { .pin = 13, .func = 3 },
  196. };
  197. static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
  198. { .pin = 8, .func = 3 },
  199. { .pin = 9, .func = 3 },
  200. { .pin = 10, .func = 3 },
  201. { .pin = 11, .func = 3 },
  202. { .pin = 14, .func = 2 },
  203. { .pin = 15, .func = 2 },
  204. { .pin = 14, .func = 3 },
  205. { .pin = 15, .func = 3 },
  206. };
  207. static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
  208. { .pin = 0, .func = 2 },
  209. { .pin = 1, .func = 2 },
  210. { .pin = 4, .func = 2 },
  211. { .pin = 5, .func = 2 },
  212. { .pin = 6, .func = 2 },
  213. { .pin = 7, .func = 2 },
  214. };
  215. static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
  216. { .pin = 6, .func = 2 },
  217. { .pin = 7, .func = 2 },
  218. { .pin = 9, .func = 2 },
  219. { .pin = 6, .func = 4 },
  220. { .pin = 7, .func = 4 },
  221. { .pin = 9, .func = 4 },
  222. { .pin = 10, .func = 2 },
  223. { .pin = 11, .func = 2 },
  224. { .pin = 10, .func = 4 },
  225. { .pin = 11, .func = 4 },
  226. { .pin = 12, .func = 4 },
  227. { .pin = 13, .func = 4 },
  228. { .pin = 14, .func = 4 },
  229. { .pin = 15, .func = 4 },
  230. };
  231. static const struct rza1_swio_pin rza1h_swio_pins[] = {
  232. { .port = 2, .pin = 7, .func = 4, .input = 0 },
  233. { .port = 2, .pin = 11, .func = 4, .input = 0 },
  234. { .port = 3, .pin = 7, .func = 3, .input = 0 },
  235. { .port = 3, .pin = 7, .func = 8, .input = 0 },
  236. { .port = 4, .pin = 7, .func = 5, .input = 0 },
  237. { .port = 4, .pin = 7, .func = 11, .input = 0 },
  238. { .port = 4, .pin = 15, .func = 6, .input = 0 },
  239. { .port = 5, .pin = 0, .func = 1, .input = 1 },
  240. { .port = 5, .pin = 1, .func = 1, .input = 1 },
  241. { .port = 5, .pin = 2, .func = 1, .input = 1 },
  242. { .port = 5, .pin = 3, .func = 1, .input = 1 },
  243. { .port = 5, .pin = 4, .func = 1, .input = 1 },
  244. { .port = 5, .pin = 5, .func = 1, .input = 1 },
  245. { .port = 5, .pin = 6, .func = 1, .input = 1 },
  246. { .port = 5, .pin = 7, .func = 1, .input = 1 },
  247. { .port = 7, .pin = 4, .func = 6, .input = 0 },
  248. { .port = 7, .pin = 11, .func = 2, .input = 0 },
  249. { .port = 8, .pin = 10, .func = 8, .input = 0 },
  250. { .port = 10, .pin = 15, .func = 2, .input = 0 },
  251. };
  252. static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
  253. [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
  254. [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
  255. [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
  256. [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
  257. [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
  258. [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
  259. [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
  260. [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
  261. [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
  262. };
  263. static const struct rza1_swio_entry rza1h_swio_entries[] = {
  264. [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
  265. };
  266. /* RZ/A1H (r7s72100x) pinmux flags table */
  267. static const struct rza1_pinmux_conf rza1h_pmx_conf = {
  268. .bidir_entries = rza1h_bidir_entries,
  269. .swio_entries = rza1h_swio_entries,
  270. };
  271. /* ----------------------------------------------------------------------------
  272. * RZ/A1L (r7s72102) pinmux flags
  273. */
  274. static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
  275. { .pin = 0, .func = 1 },
  276. { .pin = 1, .func = 1 },
  277. { .pin = 2, .func = 1 },
  278. { .pin = 3, .func = 1 },
  279. { .pin = 4, .func = 1 },
  280. { .pin = 5, .func = 1 },
  281. { .pin = 6, .func = 1 },
  282. { .pin = 7, .func = 1 },
  283. };
  284. static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
  285. { .pin = 0, .func = 2 },
  286. { .pin = 1, .func = 2 },
  287. { .pin = 2, .func = 2 },
  288. { .pin = 4, .func = 2 },
  289. { .pin = 5, .func = 2 },
  290. { .pin = 10, .func = 2 },
  291. { .pin = 11, .func = 2 },
  292. { .pin = 12, .func = 2 },
  293. { .pin = 13, .func = 2 },
  294. };
  295. static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
  296. { .pin = 1, .func = 4 },
  297. { .pin = 2, .func = 2 },
  298. { .pin = 3, .func = 2 },
  299. { .pin = 6, .func = 2 },
  300. { .pin = 7, .func = 2 },
  301. };
  302. static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
  303. { .pin = 0, .func = 1 },
  304. { .pin = 1, .func = 1 },
  305. { .pin = 2, .func = 1 },
  306. { .pin = 3, .func = 1 },
  307. { .pin = 4, .func = 1 },
  308. { .pin = 5, .func = 1 },
  309. { .pin = 6, .func = 1 },
  310. { .pin = 7, .func = 1 },
  311. { .pin = 8, .func = 1 },
  312. { .pin = 9, .func = 1 },
  313. { .pin = 10, .func = 1 },
  314. { .pin = 11, .func = 1 },
  315. { .pin = 12, .func = 1 },
  316. { .pin = 13, .func = 1 },
  317. { .pin = 14, .func = 1 },
  318. { .pin = 15, .func = 1 },
  319. { .pin = 0, .func = 2 },
  320. { .pin = 1, .func = 2 },
  321. { .pin = 2, .func = 2 },
  322. { .pin = 3, .func = 2 },
  323. };
  324. static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
  325. { .pin = 0, .func = 1 },
  326. { .pin = 1, .func = 1 },
  327. { .pin = 2, .func = 1 },
  328. { .pin = 3, .func = 1 },
  329. { .pin = 4, .func = 1 },
  330. { .pin = 5, .func = 1 },
  331. { .pin = 6, .func = 1 },
  332. { .pin = 7, .func = 1 },
  333. { .pin = 8, .func = 1 },
  334. { .pin = 9, .func = 1 },
  335. { .pin = 10, .func = 1 },
  336. { .pin = 11, .func = 1 },
  337. { .pin = 12, .func = 1 },
  338. { .pin = 13, .func = 1 },
  339. { .pin = 14, .func = 1 },
  340. { .pin = 15, .func = 1 },
  341. };
  342. static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
  343. { .pin = 2, .func = 2 },
  344. { .pin = 3, .func = 2 },
  345. { .pin = 5, .func = 2 },
  346. { .pin = 6, .func = 2 },
  347. { .pin = 7, .func = 2 },
  348. { .pin = 2, .func = 3 },
  349. { .pin = 3, .func = 3 },
  350. { .pin = 5, .func = 3 },
  351. { .pin = 6, .func = 3 },
  352. { .pin = 7, .func = 3 },
  353. };
  354. static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
  355. { .pin = 1, .func = 2 },
  356. { .pin = 0, .func = 3 },
  357. { .pin = 1, .func = 3 },
  358. { .pin = 3, .func = 3 },
  359. { .pin = 4, .func = 3 },
  360. { .pin = 5, .func = 3 },
  361. };
  362. static const struct rza1_swio_pin rza1l_swio_pins[] = {
  363. { .port = 2, .pin = 8, .func = 2, .input = 0 },
  364. { .port = 5, .pin = 6, .func = 3, .input = 0 },
  365. { .port = 6, .pin = 6, .func = 3, .input = 0 },
  366. { .port = 6, .pin = 10, .func = 3, .input = 0 },
  367. { .port = 7, .pin = 10, .func = 2, .input = 0 },
  368. { .port = 8, .pin = 2, .func = 3, .input = 0 },
  369. };
  370. static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
  371. [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
  372. [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
  373. [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
  374. [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
  375. [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
  376. [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
  377. [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
  378. };
  379. static const struct rza1_swio_entry rza1l_swio_entries[] = {
  380. [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins },
  381. };
  382. /* RZ/A1L (r7s72102x) pinmux flags table */
  383. static const struct rza1_pinmux_conf rza1l_pmx_conf = {
  384. .bidir_entries = rza1l_bidir_entries,
  385. .swio_entries = rza1l_swio_entries,
  386. };
  387. /* ----------------------------------------------------------------------------
  388. * RZ/A1 types
  389. */
  390. /**
  391. * struct rza1_mux_conf - describes a pin multiplexing operation
  392. *
  393. * @id: the pin identifier from 0 to RZA1_NPINS
  394. * @port: the port where pin sits on
  395. * @pin: pin id
  396. * @mux_func: alternate function id number
  397. * @mux_flags: alternate function flags
  398. * @value: output value to set the pin to
  399. */
  400. struct rza1_mux_conf {
  401. u16 id;
  402. u8 port;
  403. u8 pin;
  404. u8 mux_func;
  405. u8 mux_flags;
  406. u8 value;
  407. };
  408. /**
  409. * struct rza1_port - describes a pin port
  410. *
  411. * This is mostly useful to lock register writes per-bank and not globally.
  412. *
  413. * @lock: protect access to HW registers
  414. * @id: port number
  415. * @base: logical address base
  416. * @pins: pins sitting on this port
  417. */
  418. struct rza1_port {
  419. spinlock_t lock;
  420. unsigned int id;
  421. void __iomem *base;
  422. struct pinctrl_pin_desc *pins;
  423. };
  424. /**
  425. * struct rza1_pinctrl - RZ pincontroller device
  426. *
  427. * @dev: parent device structure
  428. * @mutex: protect [pinctrl|pinmux]_generic functions
  429. * @base: logical address base
  430. * @nport: number of pin controller ports
  431. * @ports: pin controller banks
  432. * @pins: pin array for pinctrl core
  433. * @desc: pincontroller desc for pinctrl core
  434. * @pctl: pinctrl device
  435. * @data: device specific data
  436. */
  437. struct rza1_pinctrl {
  438. struct device *dev;
  439. struct mutex mutex;
  440. void __iomem *base;
  441. unsigned int nport;
  442. struct rza1_port *ports;
  443. struct pinctrl_pin_desc *pins;
  444. struct pinctrl_desc desc;
  445. struct pinctrl_dev *pctl;
  446. const void *data;
  447. };
  448. /* ----------------------------------------------------------------------------
  449. * RZ/A1 pinmux flags
  450. */
  451. static inline bool rza1_pinmux_get_bidir(unsigned int port,
  452. unsigned int pin,
  453. unsigned int func,
  454. const struct rza1_bidir_entry *table)
  455. {
  456. const struct rza1_bidir_entry *entry = &table[port];
  457. const struct rza1_bidir_pin *bidir_pin;
  458. unsigned int i;
  459. for (i = 0; i < entry->npins; ++i) {
  460. bidir_pin = &entry->pins[i];
  461. if (bidir_pin->pin == pin && bidir_pin->func == func)
  462. return true;
  463. }
  464. return false;
  465. }
  466. static inline int rza1_pinmux_get_swio(unsigned int port,
  467. unsigned int pin,
  468. unsigned int func,
  469. const struct rza1_swio_entry *table)
  470. {
  471. const struct rza1_swio_pin *swio_pin;
  472. unsigned int i;
  473. for (i = 0; i < table->npins; ++i) {
  474. swio_pin = &table->pins[i];
  475. if (swio_pin->port == port && swio_pin->pin == pin &&
  476. swio_pin->func == func)
  477. return swio_pin->input;
  478. }
  479. return -ENOENT;
  480. }
  481. /*
  482. * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
  483. */
  484. static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
  485. unsigned int func,
  486. struct rza1_pinctrl *rza1_pctl)
  487. {
  488. const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
  489. const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
  490. const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
  491. unsigned int pmx_flags = 0;
  492. int ret;
  493. if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
  494. pmx_flags |= MUX_FLAGS_BIDIR;
  495. ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
  496. if (ret == 0)
  497. pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
  498. else if (ret > 0)
  499. pmx_flags |= MUX_FLAGS_SWIO_INPUT;
  500. return pmx_flags;
  501. }
  502. /* ----------------------------------------------------------------------------
  503. * RZ/A1 SoC operations
  504. */
  505. /*
  506. * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
  507. * registers
  508. */
  509. static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
  510. unsigned int bit, bool set)
  511. {
  512. void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
  513. u16 val = ioread16(mem);
  514. if (set)
  515. val |= BIT(bit);
  516. else
  517. val &= ~BIT(bit);
  518. iowrite16(val, mem);
  519. }
  520. static inline unsigned int rza1_get_bit(struct rza1_port *port,
  521. unsigned int reg, unsigned int bit)
  522. {
  523. void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
  524. return ioread16(mem) & BIT(bit);
  525. }
  526. /**
  527. * rza1_pin_reset() - reset a pin to default initial state
  528. *
  529. * Reset pin state disabling input buffer and bi-directional control,
  530. * and configure it as input port.
  531. * Note that pin is now configured with direction as input but with input
  532. * buffer disabled. This implies the pin value cannot be read in this state.
  533. *
  534. * @port: port where pin sits on
  535. * @pin: pin offset
  536. */
  537. static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
  538. {
  539. unsigned long irqflags;
  540. spin_lock_irqsave(&port->lock, irqflags);
  541. rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
  542. rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
  543. rza1_set_bit(port, RZA1_PM_REG, pin, 1);
  544. rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
  545. rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
  546. spin_unlock_irqrestore(&port->lock, irqflags);
  547. }
  548. /**
  549. * rza1_pin_set_direction() - set I/O direction on a pin in port mode
  550. *
  551. * When running in output port mode keep PBDC enabled to allow reading the
  552. * pin value from PPR.
  553. *
  554. * @port: port where pin sits on
  555. * @pin: pin offset
  556. * @input: input enable/disable flag
  557. */
  558. static inline void rza1_pin_set_direction(struct rza1_port *port,
  559. unsigned int pin, bool input)
  560. {
  561. unsigned long irqflags;
  562. spin_lock_irqsave(&port->lock, irqflags);
  563. rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
  564. if (input) {
  565. rza1_set_bit(port, RZA1_PM_REG, pin, 1);
  566. rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
  567. } else {
  568. rza1_set_bit(port, RZA1_PM_REG, pin, 0);
  569. rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
  570. }
  571. spin_unlock_irqrestore(&port->lock, irqflags);
  572. }
  573. static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
  574. unsigned int value)
  575. {
  576. unsigned long irqflags;
  577. spin_lock_irqsave(&port->lock, irqflags);
  578. rza1_set_bit(port, RZA1_P_REG, pin, !!value);
  579. spin_unlock_irqrestore(&port->lock, irqflags);
  580. }
  581. static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
  582. {
  583. return rza1_get_bit(port, RZA1_PPR_REG, pin);
  584. }
  585. /**
  586. * rza1_pin_mux_single() - configure pin multiplexing on a single pin
  587. *
  588. * @rza1_pctl: RZ/A1 pin controller device
  589. * @mux_conf: pin multiplexing descriptor
  590. */
  591. static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
  592. struct rza1_mux_conf *mux_conf)
  593. {
  594. struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
  595. unsigned int pin = mux_conf->pin;
  596. u8 mux_func = mux_conf->mux_func;
  597. u8 mux_flags = mux_conf->mux_flags;
  598. u8 mux_flags_from_table;
  599. rza1_pin_reset(port, pin);
  600. /* SWIO pinmux flags coming from DT are high precedence */
  601. mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
  602. rza1_pctl);
  603. if (mux_flags)
  604. mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
  605. else
  606. mux_flags = mux_flags_from_table;
  607. if (mux_flags & MUX_FLAGS_BIDIR)
  608. rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
  609. /*
  610. * Enable alternate function mode and select it.
  611. *
  612. * Be careful here: the pin mux sub-nodes in device tree
  613. * enumerate alternate functions from 1 to 8;
  614. * subtract 1 before using macros to match registers configuration
  615. * which expects numbers from 0 to 7 instead.
  616. *
  617. * ----------------------------------------------------
  618. * Alternate mode selection table:
  619. *
  620. * PMC PFC PFCE PFCAE (mux_func - 1)
  621. * 1 0 0 0 0
  622. * 1 1 0 0 1
  623. * 1 0 1 0 2
  624. * 1 1 1 0 3
  625. * 1 0 0 1 4
  626. * 1 1 0 1 5
  627. * 1 0 1 1 6
  628. * 1 1 1 1 7
  629. * ----------------------------------------------------
  630. */
  631. mux_func -= 1;
  632. rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
  633. rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
  634. rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
  635. /*
  636. * All alternate functions except a few need PIPCn = 1.
  637. * If PIPCn has to stay disabled (SW IO mode), configure PMn according
  638. * to I/O direction specified by pin configuration -after- PMC has been
  639. * set to one.
  640. */
  641. if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
  642. rza1_set_bit(port, RZA1_PM_REG, pin,
  643. mux_flags & MUX_FLAGS_SWIO_INPUT);
  644. else
  645. rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
  646. rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
  647. return 0;
  648. }
  649. /* ----------------------------------------------------------------------------
  650. * gpio operations
  651. */
  652. /**
  653. * rza1_gpio_request() - configure pin in port mode
  654. *
  655. * Configure a pin as gpio (port mode).
  656. * After reset, the pin is in input mode with input buffer disabled.
  657. * To use the pin as input or output, set_direction shall be called first
  658. *
  659. * @chip: gpio chip where the gpio sits on
  660. * @gpio: gpio offset
  661. */
  662. static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
  663. {
  664. struct rza1_port *port = gpiochip_get_data(chip);
  665. rza1_pin_reset(port, gpio);
  666. return 0;
  667. }
  668. /**
  669. * rza1_gpio_disable_free() - reset a pin
  670. *
  671. * Surprisingly, disable_free a gpio, is equivalent to request it.
  672. * Reset pin to port mode, with input buffer disabled. This overwrites all
  673. * port direction settings applied with set_direction
  674. *
  675. * @chip: gpio chip where the gpio sits on
  676. * @gpio: gpio offset
  677. */
  678. static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
  679. {
  680. struct rza1_port *port = gpiochip_get_data(chip);
  681. rza1_pin_reset(port, gpio);
  682. }
  683. static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
  684. {
  685. struct rza1_port *port = gpiochip_get_data(chip);
  686. if (rza1_get_bit(port, RZA1_PM_REG, gpio))
  687. return GPIO_LINE_DIRECTION_IN;
  688. return GPIO_LINE_DIRECTION_OUT;
  689. }
  690. static int rza1_gpio_direction_input(struct gpio_chip *chip,
  691. unsigned int gpio)
  692. {
  693. struct rza1_port *port = gpiochip_get_data(chip);
  694. rza1_pin_set_direction(port, gpio, true);
  695. return 0;
  696. }
  697. static int rza1_gpio_direction_output(struct gpio_chip *chip,
  698. unsigned int gpio,
  699. int value)
  700. {
  701. struct rza1_port *port = gpiochip_get_data(chip);
  702. /* Set value before driving pin direction */
  703. rza1_pin_set(port, gpio, value);
  704. rza1_pin_set_direction(port, gpio, false);
  705. return 0;
  706. }
  707. /**
  708. * rza1_gpio_get() - read a gpio pin value
  709. *
  710. * Read gpio pin value through PPR register.
  711. * Requires bi-directional mode to work when reading the value of a pin
  712. * in output mode
  713. *
  714. * @chip: gpio chip where the gpio sits on
  715. * @gpio: gpio offset
  716. */
  717. static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
  718. {
  719. struct rza1_port *port = gpiochip_get_data(chip);
  720. return rza1_pin_get(port, gpio);
  721. }
  722. static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
  723. int value)
  724. {
  725. struct rza1_port *port = gpiochip_get_data(chip);
  726. rza1_pin_set(port, gpio, value);
  727. }
  728. static const struct gpio_chip rza1_gpiochip_template = {
  729. .request = rza1_gpio_request,
  730. .free = rza1_gpio_free,
  731. .get_direction = rza1_gpio_get_direction,
  732. .direction_input = rza1_gpio_direction_input,
  733. .direction_output = rza1_gpio_direction_output,
  734. .get = rza1_gpio_get,
  735. .set = rza1_gpio_set,
  736. };
  737. /* ----------------------------------------------------------------------------
  738. * pinctrl operations
  739. */
  740. /**
  741. * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
  742. * children sub-nodes
  743. *
  744. * @np: device tree node to parse
  745. */
  746. static int rza1_dt_node_pin_count(struct device_node *np)
  747. {
  748. struct device_node *child;
  749. struct property *of_pins;
  750. unsigned int npins;
  751. of_pins = of_find_property(np, "pinmux", NULL);
  752. if (of_pins)
  753. return of_pins->length / sizeof(u32);
  754. npins = 0;
  755. for_each_child_of_node(np, child) {
  756. of_pins = of_find_property(child, "pinmux", NULL);
  757. if (!of_pins) {
  758. of_node_put(child);
  759. return -EINVAL;
  760. }
  761. npins += of_pins->length / sizeof(u32);
  762. }
  763. return npins;
  764. }
  765. /**
  766. * rza1_parse_pmx_function() - parse a pin mux sub-node
  767. *
  768. * @rza1_pctl: RZ/A1 pin controller device
  769. * @np: of pmx sub-node
  770. * @mux_confs: array of pin mux configurations to fill with parsed info
  771. * @grpins: array of pin ids to mux
  772. */
  773. static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
  774. struct device_node *np,
  775. struct rza1_mux_conf *mux_confs,
  776. unsigned int *grpins)
  777. {
  778. struct pinctrl_dev *pctldev = rza1_pctl->pctl;
  779. char const *prop_name = "pinmux";
  780. unsigned long *pin_configs;
  781. unsigned int npin_configs;
  782. struct property *of_pins;
  783. unsigned int npins;
  784. u8 pinmux_flags;
  785. unsigned int i;
  786. int ret;
  787. of_pins = of_find_property(np, prop_name, NULL);
  788. if (!of_pins) {
  789. dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
  790. return -ENOENT;
  791. }
  792. npins = of_pins->length / sizeof(u32);
  793. /*
  794. * Collect pin configuration properties: they apply to all pins in
  795. * this sub-node
  796. */
  797. ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
  798. &npin_configs);
  799. if (ret) {
  800. dev_err(rza1_pctl->dev,
  801. "Unable to parse pin configuration options for %pOFn\n",
  802. np);
  803. return ret;
  804. }
  805. /*
  806. * Create a mask with pinmux flags from pin configuration;
  807. * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
  808. * specified in device tree.
  809. */
  810. pinmux_flags = 0;
  811. for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
  812. switch (pinconf_to_config_param(pin_configs[i])) {
  813. case PIN_CONFIG_INPUT_ENABLE:
  814. pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
  815. break;
  816. case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
  817. case PIN_CONFIG_OUTPUT_ENABLE:
  818. pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
  819. default:
  820. break;
  821. }
  822. kfree(pin_configs);
  823. /* Collect pin positions and their mux settings. */
  824. for (i = 0; i < npins; ++i) {
  825. u32 of_pinconf;
  826. struct rza1_mux_conf *mux_conf = &mux_confs[i];
  827. ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
  828. if (ret)
  829. return ret;
  830. mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;
  831. mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);
  832. mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);
  833. mux_conf->mux_func = MUX_FUNC(of_pinconf);
  834. mux_conf->mux_flags = pinmux_flags;
  835. if (mux_conf->port >= RZA1_NPORTS ||
  836. mux_conf->pin >= RZA1_PINS_PER_PORT) {
  837. dev_err(rza1_pctl->dev,
  838. "Wrong port %u pin %u for %s property\n",
  839. mux_conf->port, mux_conf->pin, prop_name);
  840. return -EINVAL;
  841. }
  842. grpins[i] = mux_conf->id;
  843. }
  844. return npins;
  845. }
  846. /**
  847. * rza1_dt_node_to_map() - map a pin mux node to a function/group
  848. *
  849. * Parse and register a pin mux function.
  850. *
  851. * @pctldev: pin controller device
  852. * @np: device tree node to parse
  853. * @map: pointer to pin map (output)
  854. * @num_maps: number of collected maps (output)
  855. */
  856. static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
  857. struct device_node *np,
  858. struct pinctrl_map **map,
  859. unsigned int *num_maps)
  860. {
  861. struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
  862. struct rza1_mux_conf *mux_confs, *mux_conf;
  863. unsigned int *grpins, *grpin;
  864. struct device_node *child;
  865. const char *grpname;
  866. const char **fngrps;
  867. int ret, npins;
  868. int gsel, fsel;
  869. npins = rza1_dt_node_pin_count(np);
  870. if (npins < 0) {
  871. dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
  872. return -EINVAL;
  873. }
  874. /*
  875. * Functions are made of 1 group only;
  876. * in fact, functions and groups are identical for this pin controller
  877. * except that functions carry an array of per-pin mux configuration
  878. * settings.
  879. */
  880. mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
  881. GFP_KERNEL);
  882. grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
  883. GFP_KERNEL);
  884. fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
  885. if (!mux_confs || !grpins || !fngrps)
  886. return -ENOMEM;
  887. /*
  888. * Parse the pinmux node.
  889. * If the node does not contain "pinmux" property (-ENOENT)
  890. * that property shall be specified in all its children sub-nodes.
  891. */
  892. mux_conf = &mux_confs[0];
  893. grpin = &grpins[0];
  894. ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
  895. if (ret == -ENOENT)
  896. for_each_child_of_node(np, child) {
  897. ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
  898. grpin);
  899. if (ret < 0) {
  900. of_node_put(child);
  901. return ret;
  902. }
  903. grpin += ret;
  904. mux_conf += ret;
  905. }
  906. else if (ret < 0)
  907. return ret;
  908. /* Register pin group and function name to pinctrl_generic */
  909. grpname = np->name;
  910. fngrps[0] = grpname;
  911. mutex_lock(&rza1_pctl->mutex);
  912. gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
  913. NULL);
  914. if (gsel < 0) {
  915. mutex_unlock(&rza1_pctl->mutex);
  916. return gsel;
  917. }
  918. fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
  919. mux_confs);
  920. if (fsel < 0) {
  921. ret = fsel;
  922. goto remove_group;
  923. }
  924. dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
  925. grpname, npins);
  926. /* Create map where to retrieve function and mux settings from */
  927. *num_maps = 0;
  928. *map = kzalloc(sizeof(**map), GFP_KERNEL);
  929. if (!*map) {
  930. ret = -ENOMEM;
  931. goto remove_function;
  932. }
  933. (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
  934. (*map)->data.mux.group = np->name;
  935. (*map)->data.mux.function = np->name;
  936. *num_maps = 1;
  937. mutex_unlock(&rza1_pctl->mutex);
  938. return 0;
  939. remove_function:
  940. pinmux_generic_remove_function(pctldev, fsel);
  941. remove_group:
  942. pinctrl_generic_remove_group(pctldev, gsel);
  943. mutex_unlock(&rza1_pctl->mutex);
  944. dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
  945. grpname);
  946. return ret;
  947. }
  948. static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
  949. struct pinctrl_map *map, unsigned int num_maps)
  950. {
  951. kfree(map);
  952. }
  953. static const struct pinctrl_ops rza1_pinctrl_ops = {
  954. .get_groups_count = pinctrl_generic_get_group_count,
  955. .get_group_name = pinctrl_generic_get_group_name,
  956. .get_group_pins = pinctrl_generic_get_group_pins,
  957. .dt_node_to_map = rza1_dt_node_to_map,
  958. .dt_free_map = rza1_dt_free_map,
  959. };
  960. /* ----------------------------------------------------------------------------
  961. * pinmux operations
  962. */
  963. /**
  964. * rza1_set_mux() - retrieve pins from a group and apply their mux settings
  965. *
  966. * @pctldev: pin controller device
  967. * @selector: function selector
  968. * @group: group selector
  969. */
  970. static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
  971. unsigned int group)
  972. {
  973. struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
  974. struct rza1_mux_conf *mux_confs;
  975. struct function_desc *func;
  976. struct group_desc *grp;
  977. int i;
  978. grp = pinctrl_generic_get_group(pctldev, group);
  979. if (!grp)
  980. return -EINVAL;
  981. func = pinmux_generic_get_function(pctldev, selector);
  982. if (!func)
  983. return -EINVAL;
  984. mux_confs = (struct rza1_mux_conf *)func->data;
  985. for (i = 0; i < grp->num_pins; ++i) {
  986. int ret;
  987. ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
  988. if (ret)
  989. return ret;
  990. }
  991. return 0;
  992. }
  993. static const struct pinmux_ops rza1_pinmux_ops = {
  994. .get_functions_count = pinmux_generic_get_function_count,
  995. .get_function_name = pinmux_generic_get_function_name,
  996. .get_function_groups = pinmux_generic_get_function_groups,
  997. .set_mux = rza1_set_mux,
  998. .strict = true,
  999. };
  1000. /* ----------------------------------------------------------------------------
  1001. * RZ/A1 pin controller driver operations
  1002. */
  1003. static unsigned int rza1_count_gpio_chips(struct device_node *np)
  1004. {
  1005. struct device_node *child;
  1006. unsigned int count = 0;
  1007. for_each_child_of_node(np, child) {
  1008. if (!of_property_read_bool(child, "gpio-controller"))
  1009. continue;
  1010. count++;
  1011. }
  1012. return count;
  1013. }
  1014. /**
  1015. * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
  1016. *
  1017. * The gpio controller subnode shall provide a "gpio-ranges" list property as
  1018. * defined by gpio device tree binding documentation.
  1019. *
  1020. * @rza1_pctl: RZ/A1 pin controller device
  1021. * @np: of gpio-controller node
  1022. * @chip: gpio chip to register to gpiolib
  1023. * @range: pin range to register to pinctrl core
  1024. */
  1025. static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
  1026. struct device_node *np,
  1027. struct gpio_chip *chip,
  1028. struct pinctrl_gpio_range *range)
  1029. {
  1030. const char *list_name = "gpio-ranges";
  1031. struct of_phandle_args of_args;
  1032. unsigned int gpioport;
  1033. u32 pinctrl_base;
  1034. int ret;
  1035. ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
  1036. if (ret) {
  1037. dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
  1038. list_name);
  1039. return ret;
  1040. }
  1041. /*
  1042. * Find out on which port this gpio-chip maps to by inspecting the
  1043. * second argument of the "gpio-ranges" property.
  1044. */
  1045. pinctrl_base = of_args.args[1];
  1046. gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
  1047. if (gpioport >= RZA1_NPORTS) {
  1048. dev_err(rza1_pctl->dev,
  1049. "Invalid values in property %s\n", list_name);
  1050. return -EINVAL;
  1051. }
  1052. *chip = rza1_gpiochip_template;
  1053. chip->base = -1;
  1054. chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn",
  1055. np);
  1056. if (!chip->label)
  1057. return -ENOMEM;
  1058. chip->ngpio = of_args.args[2];
  1059. chip->of_node = np;
  1060. chip->parent = rza1_pctl->dev;
  1061. range->id = gpioport;
  1062. range->name = chip->label;
  1063. range->pin_base = range->base = pinctrl_base;
  1064. range->npins = of_args.args[2];
  1065. range->gc = chip;
  1066. ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
  1067. &rza1_pctl->ports[gpioport]);
  1068. if (ret)
  1069. return ret;
  1070. pinctrl_add_gpio_range(rza1_pctl->pctl, range);
  1071. dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
  1072. chip->label, chip->ngpio);
  1073. return 0;
  1074. }
  1075. /**
  1076. * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
  1077. *
  1078. * @rza1_pctl: RZ/A1 pin controller device
  1079. */
  1080. static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
  1081. {
  1082. struct device_node *np = rza1_pctl->dev->of_node;
  1083. struct pinctrl_gpio_range *gpio_ranges;
  1084. struct gpio_chip *gpio_chips;
  1085. struct device_node *child;
  1086. unsigned int ngpiochips;
  1087. unsigned int i;
  1088. int ret;
  1089. ngpiochips = rza1_count_gpio_chips(np);
  1090. if (ngpiochips == 0) {
  1091. dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
  1092. return 0;
  1093. }
  1094. gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
  1095. sizeof(*gpio_chips), GFP_KERNEL);
  1096. gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
  1097. sizeof(*gpio_ranges), GFP_KERNEL);
  1098. if (!gpio_chips || !gpio_ranges)
  1099. return -ENOMEM;
  1100. i = 0;
  1101. for_each_child_of_node(np, child) {
  1102. if (!of_property_read_bool(child, "gpio-controller"))
  1103. continue;
  1104. ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
  1105. &gpio_ranges[i]);
  1106. if (ret) {
  1107. of_node_put(child);
  1108. return ret;
  1109. }
  1110. ++i;
  1111. }
  1112. dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
  1113. return 0;
  1114. }
  1115. /**
  1116. * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
  1117. * them to pinctrl and gpio cores.
  1118. *
  1119. * @rza1_pctl: RZ/A1 pin controller device
  1120. */
  1121. static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
  1122. {
  1123. struct pinctrl_pin_desc *pins;
  1124. struct rza1_port *ports;
  1125. unsigned int i;
  1126. int ret;
  1127. pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
  1128. GFP_KERNEL);
  1129. ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
  1130. GFP_KERNEL);
  1131. if (!pins || !ports)
  1132. return -ENOMEM;
  1133. rza1_pctl->pins = pins;
  1134. rza1_pctl->desc.pins = pins;
  1135. rza1_pctl->desc.npins = RZA1_NPINS;
  1136. rza1_pctl->ports = ports;
  1137. for (i = 0; i < RZA1_NPINS; ++i) {
  1138. unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
  1139. unsigned int port = RZA1_PIN_ID_TO_PORT(i);
  1140. pins[i].number = i;
  1141. pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
  1142. "P%u-%u", port, pin);
  1143. if (!pins[i].name)
  1144. return -ENOMEM;
  1145. if (i % RZA1_PINS_PER_PORT == 0) {
  1146. /*
  1147. * Setup ports;
  1148. * they provide per-port lock and logical base address.
  1149. */
  1150. unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
  1151. ports[port_id].id = port_id;
  1152. ports[port_id].base = rza1_pctl->base;
  1153. ports[port_id].pins = &pins[i];
  1154. spin_lock_init(&ports[port_id].lock);
  1155. }
  1156. }
  1157. ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
  1158. rza1_pctl, &rza1_pctl->pctl);
  1159. if (ret) {
  1160. dev_err(rza1_pctl->dev,
  1161. "RZ/A1 pin controller registration failed\n");
  1162. return ret;
  1163. }
  1164. ret = pinctrl_enable(rza1_pctl->pctl);
  1165. if (ret) {
  1166. dev_err(rza1_pctl->dev,
  1167. "RZ/A1 pin controller failed to start\n");
  1168. return ret;
  1169. }
  1170. ret = rza1_gpio_register(rza1_pctl);
  1171. if (ret) {
  1172. dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
  1173. return ret;
  1174. }
  1175. return 0;
  1176. }
  1177. static int rza1_pinctrl_probe(struct platform_device *pdev)
  1178. {
  1179. struct rza1_pinctrl *rza1_pctl;
  1180. int ret;
  1181. rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
  1182. if (!rza1_pctl)
  1183. return -ENOMEM;
  1184. rza1_pctl->dev = &pdev->dev;
  1185. rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
  1186. if (IS_ERR(rza1_pctl->base))
  1187. return PTR_ERR(rza1_pctl->base);
  1188. mutex_init(&rza1_pctl->mutex);
  1189. platform_set_drvdata(pdev, rza1_pctl);
  1190. rza1_pctl->desc.name = DRIVER_NAME;
  1191. rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
  1192. rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
  1193. rza1_pctl->desc.owner = THIS_MODULE;
  1194. rza1_pctl->data = of_device_get_match_data(&pdev->dev);
  1195. ret = rza1_pinctrl_register(rza1_pctl);
  1196. if (ret)
  1197. return ret;
  1198. dev_info(&pdev->dev,
  1199. "RZ/A1 pin controller and gpio successfully registered\n");
  1200. return 0;
  1201. }
  1202. static const struct of_device_id rza1_pinctrl_of_match[] = {
  1203. {
  1204. /* RZ/A1H, RZ/A1M */
  1205. .compatible = "renesas,r7s72100-ports",
  1206. .data = &rza1h_pmx_conf,
  1207. },
  1208. {
  1209. /* RZ/A1L */
  1210. .compatible = "renesas,r7s72102-ports",
  1211. .data = &rza1l_pmx_conf,
  1212. },
  1213. { }
  1214. };
  1215. static struct platform_driver rza1_pinctrl_driver = {
  1216. .driver = {
  1217. .name = DRIVER_NAME,
  1218. .of_match_table = rza1_pinctrl_of_match,
  1219. },
  1220. .probe = rza1_pinctrl_probe,
  1221. };
  1222. static int __init rza1_pinctrl_init(void)
  1223. {
  1224. return platform_driver_register(&rza1_pinctrl_driver);
  1225. }
  1226. core_initcall(rza1_pinctrl_init);
  1227. MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
  1228. MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
  1229. MODULE_LICENSE("GPL v2");