pfc-shx3.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH-X3 prototype CPU pinmux
  4. *
  5. * Copyright (C) 2010 Paul Mundt
  6. */
  7. #include <linux/init.h>
  8. #include <linux/kernel.h>
  9. #include <cpu/shx3.h>
  10. #include "sh_pfc.h"
  11. enum {
  12. PINMUX_RESERVED = 0,
  13. PINMUX_DATA_BEGIN,
  14. PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
  15. PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
  16. PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
  17. PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
  18. PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
  19. PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
  20. PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
  21. PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
  22. PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
  23. PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
  24. PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
  25. PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
  26. PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
  27. PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
  28. PH5_DATA, PH4_DATA,
  29. PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
  30. PINMUX_DATA_END,
  31. PINMUX_INPUT_BEGIN,
  32. PA7_IN, PA6_IN, PA5_IN, PA4_IN,
  33. PA3_IN, PA2_IN, PA1_IN, PA0_IN,
  34. PB7_IN, PB6_IN, PB5_IN, PB4_IN,
  35. PB3_IN, PB2_IN, PB1_IN, PB0_IN,
  36. PC7_IN, PC6_IN, PC5_IN, PC4_IN,
  37. PC3_IN, PC2_IN, PC1_IN, PC0_IN,
  38. PD7_IN, PD6_IN, PD5_IN, PD4_IN,
  39. PD3_IN, PD2_IN, PD1_IN, PD0_IN,
  40. PE7_IN, PE6_IN, PE5_IN, PE4_IN,
  41. PE3_IN, PE2_IN, PE1_IN, PE0_IN,
  42. PF7_IN, PF6_IN, PF5_IN, PF4_IN,
  43. PF3_IN, PF2_IN, PF1_IN, PF0_IN,
  44. PG7_IN, PG6_IN, PG5_IN, PG4_IN,
  45. PG3_IN, PG2_IN, PG1_IN, PG0_IN,
  46. PH5_IN, PH4_IN,
  47. PH3_IN, PH2_IN, PH1_IN, PH0_IN,
  48. PINMUX_INPUT_END,
  49. PINMUX_OUTPUT_BEGIN,
  50. PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
  51. PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
  52. PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
  53. PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
  54. PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
  55. PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
  56. PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
  57. PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
  58. PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
  59. PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
  60. PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
  61. PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
  62. PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
  63. PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
  64. PH5_OUT, PH4_OUT,
  65. PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
  66. PINMUX_OUTPUT_END,
  67. PINMUX_FUNCTION_BEGIN,
  68. PA7_FN, PA6_FN, PA5_FN, PA4_FN,
  69. PA3_FN, PA2_FN, PA1_FN, PA0_FN,
  70. PB7_FN, PB6_FN, PB5_FN, PB4_FN,
  71. PB3_FN, PB2_FN, PB1_FN, PB0_FN,
  72. PC7_FN, PC6_FN, PC5_FN, PC4_FN,
  73. PC3_FN, PC2_FN, PC1_FN, PC0_FN,
  74. PD7_FN, PD6_FN, PD5_FN, PD4_FN,
  75. PD3_FN, PD2_FN, PD1_FN, PD0_FN,
  76. PE7_FN, PE6_FN, PE5_FN, PE4_FN,
  77. PE3_FN, PE2_FN, PE1_FN, PE0_FN,
  78. PF7_FN, PF6_FN, PF5_FN, PF4_FN,
  79. PF3_FN, PF2_FN, PF1_FN, PF0_FN,
  80. PG7_FN, PG6_FN, PG5_FN, PG4_FN,
  81. PG3_FN, PG2_FN, PG1_FN, PG0_FN,
  82. PH5_FN, PH4_FN,
  83. PH3_FN, PH2_FN, PH1_FN, PH0_FN,
  84. PINMUX_FUNCTION_END,
  85. PINMUX_MARK_BEGIN,
  86. D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
  87. D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
  88. D19_MARK, D18_MARK, D17_MARK, D16_MARK,
  89. BACK_MARK, BREQ_MARK,
  90. WE3_MARK, WE2_MARK,
  91. CS6_MARK, CS5_MARK, CS4_MARK,
  92. CLKOUTENB_MARK,
  93. DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
  94. DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
  95. IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
  96. DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
  97. SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
  98. IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
  99. TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
  100. RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
  101. CE2B_MARK, CE2A_MARK, IOIS16_MARK,
  102. STATUS1_MARK, STATUS0_MARK,
  103. IRQOUT_MARK,
  104. PINMUX_MARK_END,
  105. };
  106. static const u16 pinmux_data[] = {
  107. /* PA GPIO */
  108. PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
  109. PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
  110. PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
  111. PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
  112. PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
  113. PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
  114. PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
  115. PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
  116. /* PB GPIO */
  117. PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
  118. PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
  119. PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
  120. PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
  121. PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
  122. PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
  123. PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
  124. PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
  125. /* PC GPIO */
  126. PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
  127. PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
  128. PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
  129. PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
  130. PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
  131. PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
  132. PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
  133. PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
  134. /* PD GPIO */
  135. PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
  136. PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
  137. PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
  138. PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
  139. PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
  140. PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
  141. PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
  142. PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
  143. /* PE GPIO */
  144. PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
  145. PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
  146. PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT),
  147. PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT),
  148. PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT),
  149. PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT),
  150. PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT),
  151. PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT),
  152. /* PF GPIO */
  153. PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
  154. PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
  155. PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
  156. PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
  157. PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
  158. PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
  159. PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
  160. PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
  161. /* PG GPIO */
  162. PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
  163. PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
  164. PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
  165. PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT),
  166. PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT),
  167. PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT),
  168. PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT),
  169. PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT),
  170. /* PH GPIO */
  171. PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
  172. PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
  173. PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
  174. PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
  175. PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
  176. PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
  177. /* PA FN */
  178. PINMUX_DATA(D31_MARK, PA7_FN),
  179. PINMUX_DATA(D30_MARK, PA6_FN),
  180. PINMUX_DATA(D29_MARK, PA5_FN),
  181. PINMUX_DATA(D28_MARK, PA4_FN),
  182. PINMUX_DATA(D27_MARK, PA3_FN),
  183. PINMUX_DATA(D26_MARK, PA2_FN),
  184. PINMUX_DATA(D25_MARK, PA1_FN),
  185. PINMUX_DATA(D24_MARK, PA0_FN),
  186. /* PB FN */
  187. PINMUX_DATA(D23_MARK, PB7_FN),
  188. PINMUX_DATA(D22_MARK, PB6_FN),
  189. PINMUX_DATA(D21_MARK, PB5_FN),
  190. PINMUX_DATA(D20_MARK, PB4_FN),
  191. PINMUX_DATA(D19_MARK, PB3_FN),
  192. PINMUX_DATA(D18_MARK, PB2_FN),
  193. PINMUX_DATA(D17_MARK, PB1_FN),
  194. PINMUX_DATA(D16_MARK, PB0_FN),
  195. /* PC FN */
  196. PINMUX_DATA(BACK_MARK, PC7_FN),
  197. PINMUX_DATA(BREQ_MARK, PC6_FN),
  198. PINMUX_DATA(WE3_MARK, PC5_FN),
  199. PINMUX_DATA(WE2_MARK, PC4_FN),
  200. PINMUX_DATA(CS6_MARK, PC3_FN),
  201. PINMUX_DATA(CS5_MARK, PC2_FN),
  202. PINMUX_DATA(CS4_MARK, PC1_FN),
  203. PINMUX_DATA(CLKOUTENB_MARK, PC0_FN),
  204. /* PD FN */
  205. PINMUX_DATA(DACK3_MARK, PD7_FN),
  206. PINMUX_DATA(DACK2_MARK, PD6_FN),
  207. PINMUX_DATA(DACK1_MARK, PD5_FN),
  208. PINMUX_DATA(DACK0_MARK, PD4_FN),
  209. PINMUX_DATA(DREQ3_MARK, PD3_FN),
  210. PINMUX_DATA(DREQ2_MARK, PD2_FN),
  211. PINMUX_DATA(DREQ1_MARK, PD1_FN),
  212. PINMUX_DATA(DREQ0_MARK, PD0_FN),
  213. /* PE FN */
  214. PINMUX_DATA(IRQ3_MARK, PE7_FN),
  215. PINMUX_DATA(IRQ2_MARK, PE6_FN),
  216. PINMUX_DATA(IRQ1_MARK, PE5_FN),
  217. PINMUX_DATA(IRQ0_MARK, PE4_FN),
  218. PINMUX_DATA(DRAK3_MARK, PE3_FN),
  219. PINMUX_DATA(DRAK2_MARK, PE2_FN),
  220. PINMUX_DATA(DRAK1_MARK, PE1_FN),
  221. PINMUX_DATA(DRAK0_MARK, PE0_FN),
  222. /* PF FN */
  223. PINMUX_DATA(SCK3_MARK, PF7_FN),
  224. PINMUX_DATA(SCK2_MARK, PF6_FN),
  225. PINMUX_DATA(SCK1_MARK, PF5_FN),
  226. PINMUX_DATA(SCK0_MARK, PF4_FN),
  227. PINMUX_DATA(IRL3_MARK, PF3_FN),
  228. PINMUX_DATA(IRL2_MARK, PF2_FN),
  229. PINMUX_DATA(IRL1_MARK, PF1_FN),
  230. PINMUX_DATA(IRL0_MARK, PF0_FN),
  231. /* PG FN */
  232. PINMUX_DATA(TXD3_MARK, PG7_FN),
  233. PINMUX_DATA(TXD2_MARK, PG6_FN),
  234. PINMUX_DATA(TXD1_MARK, PG5_FN),
  235. PINMUX_DATA(TXD0_MARK, PG4_FN),
  236. PINMUX_DATA(RXD3_MARK, PG3_FN),
  237. PINMUX_DATA(RXD2_MARK, PG2_FN),
  238. PINMUX_DATA(RXD1_MARK, PG1_FN),
  239. PINMUX_DATA(RXD0_MARK, PG0_FN),
  240. /* PH FN */
  241. PINMUX_DATA(CE2B_MARK, PH5_FN),
  242. PINMUX_DATA(CE2A_MARK, PH4_FN),
  243. PINMUX_DATA(IOIS16_MARK, PH3_FN),
  244. PINMUX_DATA(STATUS1_MARK, PH2_FN),
  245. PINMUX_DATA(STATUS0_MARK, PH1_FN),
  246. PINMUX_DATA(IRQOUT_MARK, PH0_FN),
  247. };
  248. static const struct sh_pfc_pin pinmux_pins[] = {
  249. /* PA */
  250. PINMUX_GPIO(PA7),
  251. PINMUX_GPIO(PA6),
  252. PINMUX_GPIO(PA5),
  253. PINMUX_GPIO(PA4),
  254. PINMUX_GPIO(PA3),
  255. PINMUX_GPIO(PA2),
  256. PINMUX_GPIO(PA1),
  257. PINMUX_GPIO(PA0),
  258. /* PB */
  259. PINMUX_GPIO(PB7),
  260. PINMUX_GPIO(PB6),
  261. PINMUX_GPIO(PB5),
  262. PINMUX_GPIO(PB4),
  263. PINMUX_GPIO(PB3),
  264. PINMUX_GPIO(PB2),
  265. PINMUX_GPIO(PB1),
  266. PINMUX_GPIO(PB0),
  267. /* PC */
  268. PINMUX_GPIO(PC7),
  269. PINMUX_GPIO(PC6),
  270. PINMUX_GPIO(PC5),
  271. PINMUX_GPIO(PC4),
  272. PINMUX_GPIO(PC3),
  273. PINMUX_GPIO(PC2),
  274. PINMUX_GPIO(PC1),
  275. PINMUX_GPIO(PC0),
  276. /* PD */
  277. PINMUX_GPIO(PD7),
  278. PINMUX_GPIO(PD6),
  279. PINMUX_GPIO(PD5),
  280. PINMUX_GPIO(PD4),
  281. PINMUX_GPIO(PD3),
  282. PINMUX_GPIO(PD2),
  283. PINMUX_GPIO(PD1),
  284. PINMUX_GPIO(PD0),
  285. /* PE */
  286. PINMUX_GPIO(PE7),
  287. PINMUX_GPIO(PE6),
  288. PINMUX_GPIO(PE5),
  289. PINMUX_GPIO(PE4),
  290. PINMUX_GPIO(PE3),
  291. PINMUX_GPIO(PE2),
  292. PINMUX_GPIO(PE1),
  293. PINMUX_GPIO(PE0),
  294. /* PF */
  295. PINMUX_GPIO(PF7),
  296. PINMUX_GPIO(PF6),
  297. PINMUX_GPIO(PF5),
  298. PINMUX_GPIO(PF4),
  299. PINMUX_GPIO(PF3),
  300. PINMUX_GPIO(PF2),
  301. PINMUX_GPIO(PF1),
  302. PINMUX_GPIO(PF0),
  303. /* PG */
  304. PINMUX_GPIO(PG7),
  305. PINMUX_GPIO(PG6),
  306. PINMUX_GPIO(PG5),
  307. PINMUX_GPIO(PG4),
  308. PINMUX_GPIO(PG3),
  309. PINMUX_GPIO(PG2),
  310. PINMUX_GPIO(PG1),
  311. PINMUX_GPIO(PG0),
  312. /* PH */
  313. PINMUX_GPIO(PH5),
  314. PINMUX_GPIO(PH4),
  315. PINMUX_GPIO(PH3),
  316. PINMUX_GPIO(PH2),
  317. PINMUX_GPIO(PH1),
  318. PINMUX_GPIO(PH0),
  319. };
  320. #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
  321. static const struct pinmux_func pinmux_func_gpios[] = {
  322. /* FN */
  323. GPIO_FN(D31),
  324. GPIO_FN(D30),
  325. GPIO_FN(D29),
  326. GPIO_FN(D28),
  327. GPIO_FN(D27),
  328. GPIO_FN(D26),
  329. GPIO_FN(D25),
  330. GPIO_FN(D24),
  331. GPIO_FN(D23),
  332. GPIO_FN(D22),
  333. GPIO_FN(D21),
  334. GPIO_FN(D20),
  335. GPIO_FN(D19),
  336. GPIO_FN(D18),
  337. GPIO_FN(D17),
  338. GPIO_FN(D16),
  339. GPIO_FN(BACK),
  340. GPIO_FN(BREQ),
  341. GPIO_FN(WE3),
  342. GPIO_FN(WE2),
  343. GPIO_FN(CS6),
  344. GPIO_FN(CS5),
  345. GPIO_FN(CS4),
  346. GPIO_FN(CLKOUTENB),
  347. GPIO_FN(DACK3),
  348. GPIO_FN(DACK2),
  349. GPIO_FN(DACK1),
  350. GPIO_FN(DACK0),
  351. GPIO_FN(DREQ3),
  352. GPIO_FN(DREQ2),
  353. GPIO_FN(DREQ1),
  354. GPIO_FN(DREQ0),
  355. GPIO_FN(IRQ3),
  356. GPIO_FN(IRQ2),
  357. GPIO_FN(IRQ1),
  358. GPIO_FN(IRQ0),
  359. GPIO_FN(DRAK3),
  360. GPIO_FN(DRAK2),
  361. GPIO_FN(DRAK1),
  362. GPIO_FN(DRAK0),
  363. GPIO_FN(SCK3),
  364. GPIO_FN(SCK2),
  365. GPIO_FN(SCK1),
  366. GPIO_FN(SCK0),
  367. GPIO_FN(IRL3),
  368. GPIO_FN(IRL2),
  369. GPIO_FN(IRL1),
  370. GPIO_FN(IRL0),
  371. GPIO_FN(TXD3),
  372. GPIO_FN(TXD2),
  373. GPIO_FN(TXD1),
  374. GPIO_FN(TXD0),
  375. GPIO_FN(RXD3),
  376. GPIO_FN(RXD2),
  377. GPIO_FN(RXD1),
  378. GPIO_FN(RXD0),
  379. GPIO_FN(CE2B),
  380. GPIO_FN(CE2A),
  381. GPIO_FN(IOIS16),
  382. GPIO_FN(STATUS1),
  383. GPIO_FN(STATUS0),
  384. GPIO_FN(IRQOUT),
  385. };
  386. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  387. { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2, GROUP(
  388. PA7_FN, PA7_OUT, PA7_IN, 0,
  389. PA6_FN, PA6_OUT, PA6_IN, 0,
  390. PA5_FN, PA5_OUT, PA5_IN, 0,
  391. PA4_FN, PA4_OUT, PA4_IN, 0,
  392. PA3_FN, PA3_OUT, PA3_IN, 0,
  393. PA2_FN, PA2_OUT, PA2_IN, 0,
  394. PA1_FN, PA1_OUT, PA1_IN, 0,
  395. PA0_FN, PA0_OUT, PA0_IN, 0,
  396. PB7_FN, PB7_OUT, PB7_IN, 0,
  397. PB6_FN, PB6_OUT, PB6_IN, 0,
  398. PB5_FN, PB5_OUT, PB5_IN, 0,
  399. PB4_FN, PB4_OUT, PB4_IN, 0,
  400. PB3_FN, PB3_OUT, PB3_IN, 0,
  401. PB2_FN, PB2_OUT, PB2_IN, 0,
  402. PB1_FN, PB1_OUT, PB1_IN, 0,
  403. PB0_FN, PB0_OUT, PB0_IN, 0, ))
  404. },
  405. { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2, GROUP(
  406. PC7_FN, PC7_OUT, PC7_IN, 0,
  407. PC6_FN, PC6_OUT, PC6_IN, 0,
  408. PC5_FN, PC5_OUT, PC5_IN, 0,
  409. PC4_FN, PC4_OUT, PC4_IN, 0,
  410. PC3_FN, PC3_OUT, PC3_IN, 0,
  411. PC2_FN, PC2_OUT, PC2_IN, 0,
  412. PC1_FN, PC1_OUT, PC1_IN, 0,
  413. PC0_FN, PC0_OUT, PC0_IN, 0,
  414. PD7_FN, PD7_OUT, PD7_IN, 0,
  415. PD6_FN, PD6_OUT, PD6_IN, 0,
  416. PD5_FN, PD5_OUT, PD5_IN, 0,
  417. PD4_FN, PD4_OUT, PD4_IN, 0,
  418. PD3_FN, PD3_OUT, PD3_IN, 0,
  419. PD2_FN, PD2_OUT, PD2_IN, 0,
  420. PD1_FN, PD1_OUT, PD1_IN, 0,
  421. PD0_FN, PD0_OUT, PD0_IN, 0, ))
  422. },
  423. { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2, GROUP(
  424. PE7_FN, PE7_OUT, PE7_IN, 0,
  425. PE6_FN, PE6_OUT, PE6_IN, 0,
  426. PE5_FN, PE5_OUT, PE5_IN, 0,
  427. PE4_FN, PE4_OUT, PE4_IN, 0,
  428. PE3_FN, PE3_OUT, PE3_IN, 0,
  429. PE2_FN, PE2_OUT, PE2_IN, 0,
  430. PE1_FN, PE1_OUT, PE1_IN, 0,
  431. PE0_FN, PE0_OUT, PE0_IN, 0,
  432. PF7_FN, PF7_OUT, PF7_IN, 0,
  433. PF6_FN, PF6_OUT, PF6_IN, 0,
  434. PF5_FN, PF5_OUT, PF5_IN, 0,
  435. PF4_FN, PF4_OUT, PF4_IN, 0,
  436. PF3_FN, PF3_OUT, PF3_IN, 0,
  437. PF2_FN, PF2_OUT, PF2_IN, 0,
  438. PF1_FN, PF1_OUT, PF1_IN, 0,
  439. PF0_FN, PF0_OUT, PF0_IN, 0, ))
  440. },
  441. { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2, GROUP(
  442. PG7_FN, PG7_OUT, PG7_IN, 0,
  443. PG6_FN, PG6_OUT, PG6_IN, 0,
  444. PG5_FN, PG5_OUT, PG5_IN, 0,
  445. PG4_FN, PG4_OUT, PG4_IN, 0,
  446. PG3_FN, PG3_OUT, PG3_IN, 0,
  447. PG2_FN, PG2_OUT, PG2_IN, 0,
  448. PG1_FN, PG1_OUT, PG1_IN, 0,
  449. PG0_FN, PG0_OUT, PG0_IN, 0,
  450. 0, 0, 0, 0,
  451. 0, 0, 0, 0,
  452. PH5_FN, PH5_OUT, PH5_IN, 0,
  453. PH4_FN, PH4_OUT, PH4_IN, 0,
  454. PH3_FN, PH3_OUT, PH3_IN, 0,
  455. PH2_FN, PH2_OUT, PH2_IN, 0,
  456. PH1_FN, PH1_OUT, PH1_IN, 0,
  457. PH0_FN, PH0_OUT, PH0_IN, 0, ))
  458. },
  459. { },
  460. };
  461. static const struct pinmux_data_reg pinmux_data_regs[] = {
  462. { PINMUX_DATA_REG("PABDR", 0xffc70010, 32, GROUP(
  463. 0, 0, 0, 0, 0, 0, 0, 0,
  464. PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
  465. PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
  466. 0, 0, 0, 0, 0, 0, 0, 0,
  467. PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
  468. PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, ))
  469. },
  470. { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32, GROUP(
  471. 0, 0, 0, 0, 0, 0, 0, 0,
  472. PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
  473. PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
  474. 0, 0, 0, 0, 0, 0, 0, 0,
  475. PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
  476. PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, ))
  477. },
  478. { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32, GROUP(
  479. 0, 0, 0, 0, 0, 0, 0, 0,
  480. PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
  481. PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
  482. 0, 0, 0, 0, 0, 0, 0, 0,
  483. PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
  484. PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, ))
  485. },
  486. { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32, GROUP(
  487. 0, 0, 0, 0, 0, 0, 0, 0,
  488. PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
  489. PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
  490. 0, 0, 0, 0, 0, 0, 0, 0,
  491. 0, 0, PH5_DATA, PH4_DATA,
  492. PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, ))
  493. },
  494. { },
  495. };
  496. const struct sh_pfc_soc_info shx3_pinmux_info = {
  497. .name = "shx3_pfc",
  498. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  499. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  500. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  501. .pins = pinmux_pins,
  502. .nr_pins = ARRAY_SIZE(pinmux_pins),
  503. .func_gpios = pinmux_func_gpios,
  504. .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
  505. .pinmux_data = pinmux_data,
  506. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  507. .cfg_regs = pinmux_config_regs,
  508. .data_regs = pinmux_data_regs,
  509. };