pfc-sh7786.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH7786 Pinmux
  4. *
  5. * Copyright (C) 2008, 2009 Renesas Solutions Corp.
  6. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7. *
  8. * Based on SH7785 pinmux
  9. *
  10. * Copyright (C) 2008 Magnus Damm
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <cpu/sh7786.h>
  15. #include "sh_pfc.h"
  16. enum {
  17. PINMUX_RESERVED = 0,
  18. PINMUX_DATA_BEGIN,
  19. PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
  20. PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
  21. PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
  22. PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
  23. PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
  24. PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
  25. PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
  26. PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
  27. PE7_DATA, PE6_DATA,
  28. PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
  29. PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
  30. PG7_DATA, PG6_DATA, PG5_DATA,
  31. PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
  32. PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
  33. PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
  34. PJ3_DATA, PJ2_DATA, PJ1_DATA,
  35. PINMUX_DATA_END,
  36. PINMUX_INPUT_BEGIN,
  37. PA7_IN, PA6_IN, PA5_IN, PA4_IN,
  38. PA3_IN, PA2_IN, PA1_IN, PA0_IN,
  39. PB7_IN, PB6_IN, PB5_IN, PB4_IN,
  40. PB3_IN, PB2_IN, PB1_IN, PB0_IN,
  41. PC7_IN, PC6_IN, PC5_IN, PC4_IN,
  42. PC3_IN, PC2_IN, PC1_IN, PC0_IN,
  43. PD7_IN, PD6_IN, PD5_IN, PD4_IN,
  44. PD3_IN, PD2_IN, PD1_IN, PD0_IN,
  45. PE7_IN, PE6_IN,
  46. PF7_IN, PF6_IN, PF5_IN, PF4_IN,
  47. PF3_IN, PF2_IN, PF1_IN, PF0_IN,
  48. PG7_IN, PG6_IN, PG5_IN,
  49. PH7_IN, PH6_IN, PH5_IN, PH4_IN,
  50. PH3_IN, PH2_IN, PH1_IN, PH0_IN,
  51. PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
  52. PJ3_IN, PJ2_IN, PJ1_IN,
  53. PINMUX_INPUT_END,
  54. PINMUX_OUTPUT_BEGIN,
  55. PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
  56. PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
  57. PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
  58. PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
  59. PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
  60. PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
  61. PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
  62. PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
  63. PE7_OUT, PE6_OUT,
  64. PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
  65. PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
  66. PG7_OUT, PG6_OUT, PG5_OUT,
  67. PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
  68. PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
  69. PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
  70. PJ3_OUT, PJ2_OUT, PJ1_OUT,
  71. PINMUX_OUTPUT_END,
  72. PINMUX_FUNCTION_BEGIN,
  73. PA7_FN, PA6_FN, PA5_FN, PA4_FN,
  74. PA3_FN, PA2_FN, PA1_FN, PA0_FN,
  75. PB7_FN, PB6_FN, PB5_FN, PB4_FN,
  76. PB3_FN, PB2_FN, PB1_FN, PB0_FN,
  77. PC7_FN, PC6_FN, PC5_FN, PC4_FN,
  78. PC3_FN, PC2_FN, PC1_FN, PC0_FN,
  79. PD7_FN, PD6_FN, PD5_FN, PD4_FN,
  80. PD3_FN, PD2_FN, PD1_FN, PD0_FN,
  81. PE7_FN, PE6_FN,
  82. PF7_FN, PF6_FN, PF5_FN, PF4_FN,
  83. PF3_FN, PF2_FN, PF1_FN, PF0_FN,
  84. PG7_FN, PG6_FN, PG5_FN,
  85. PH7_FN, PH6_FN, PH5_FN, PH4_FN,
  86. PH3_FN, PH2_FN, PH1_FN, PH0_FN,
  87. PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
  88. PJ3_FN, PJ2_FN, PJ1_FN,
  89. P1MSEL14_0, P1MSEL14_1,
  90. P1MSEL13_0, P1MSEL13_1,
  91. P1MSEL12_0, P1MSEL12_1,
  92. P1MSEL11_0, P1MSEL11_1,
  93. P1MSEL10_0, P1MSEL10_1,
  94. P1MSEL9_0, P1MSEL9_1,
  95. P1MSEL8_0, P1MSEL8_1,
  96. P1MSEL7_0, P1MSEL7_1,
  97. P1MSEL6_0, P1MSEL6_1,
  98. P1MSEL5_0, P1MSEL5_1,
  99. P1MSEL4_0, P1MSEL4_1,
  100. P1MSEL3_0, P1MSEL3_1,
  101. P1MSEL2_0, P1MSEL2_1,
  102. P1MSEL1_0, P1MSEL1_1,
  103. P1MSEL0_0, P1MSEL0_1,
  104. P2MSEL15_0, P2MSEL15_1,
  105. P2MSEL14_0, P2MSEL14_1,
  106. P2MSEL13_0, P2MSEL13_1,
  107. P2MSEL12_0, P2MSEL12_1,
  108. P2MSEL11_0, P2MSEL11_1,
  109. P2MSEL10_0, P2MSEL10_1,
  110. P2MSEL9_0, P2MSEL9_1,
  111. P2MSEL8_0, P2MSEL8_1,
  112. P2MSEL7_0, P2MSEL7_1,
  113. P2MSEL6_0, P2MSEL6_1,
  114. P2MSEL5_0, P2MSEL5_1,
  115. P2MSEL4_0, P2MSEL4_1,
  116. P2MSEL3_0, P2MSEL3_1,
  117. P2MSEL2_0, P2MSEL2_1,
  118. P2MSEL1_0, P2MSEL1_1,
  119. P2MSEL0_0, P2MSEL0_1,
  120. PINMUX_FUNCTION_END,
  121. PINMUX_MARK_BEGIN,
  122. DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK,
  123. VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK,
  124. DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK,
  125. DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK,
  126. DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK,
  127. ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK,
  128. ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK,
  129. ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK,
  130. ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK,
  131. ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK,
  132. HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK,
  133. SCIF0_CTS_MARK, SCIF0_RTS_MARK,
  134. SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK,
  135. SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK,
  136. SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK,
  137. SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK,
  138. SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK,
  139. BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK,
  140. FALE_MARK, FRB_MARK, FSTATUS_MARK,
  141. FSE_MARK, FCLE_MARK,
  142. DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK,
  143. DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK,
  144. DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK,
  145. USB_OVC1_MARK, USB_OVC0_MARK,
  146. USB_PENC1_MARK, USB_PENC0_MARK,
  147. HAC_RES_MARK,
  148. HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK,
  149. HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK,
  150. SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK,
  151. SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK,
  152. SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK,
  153. SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK,
  154. SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK,
  155. SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK,
  156. SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK,
  157. SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK,
  158. TCLK_MARK,
  159. IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK,
  160. PINMUX_MARK_END,
  161. };
  162. static const u16 pinmux_data[] = {
  163. /* PA GPIO */
  164. PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
  165. PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
  166. PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
  167. PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
  168. PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
  169. PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
  170. PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
  171. PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
  172. /* PB GPIO */
  173. PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
  174. PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
  175. PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
  176. PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
  177. PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
  178. PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
  179. PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
  180. PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
  181. /* PC GPIO */
  182. PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
  183. PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
  184. PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
  185. PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
  186. PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
  187. PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
  188. PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
  189. PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
  190. /* PD GPIO */
  191. PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
  192. PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
  193. PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
  194. PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
  195. PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
  196. PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
  197. PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
  198. PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
  199. /* PE GPIO */
  200. PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
  201. PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
  202. /* PF GPIO */
  203. PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
  204. PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
  205. PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
  206. PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
  207. PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
  208. PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
  209. PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
  210. PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
  211. /* PG GPIO */
  212. PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
  213. PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
  214. PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
  215. /* PH GPIO */
  216. PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
  217. PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
  218. PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
  219. PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
  220. PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
  221. PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
  222. PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
  223. PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
  224. /* PJ GPIO */
  225. PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
  226. PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
  227. PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
  228. PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
  229. PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
  230. PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
  231. PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
  232. /* PA FN */
  233. PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
  234. PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
  235. PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
  236. PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
  237. PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
  238. PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
  239. PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
  240. PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
  241. PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
  242. PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
  243. PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
  244. PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
  245. PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
  246. PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
  247. PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
  248. PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
  249. /* PB FN */
  250. PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
  251. PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
  252. PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
  253. PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
  254. PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
  255. PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
  256. PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
  257. PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
  258. PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
  259. PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
  260. PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
  261. PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
  262. PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
  263. PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
  264. PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
  265. PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
  266. /* PC FN */
  267. PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
  268. PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
  269. PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
  270. PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
  271. PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
  272. PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
  273. PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
  274. PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
  275. PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
  276. PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
  277. PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
  278. PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
  279. PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
  280. PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
  281. PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
  282. PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
  283. /* PD FN */
  284. PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
  285. PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN),
  286. PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
  287. PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
  288. PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
  289. PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
  290. PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
  291. PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
  292. PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
  293. PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
  294. PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
  295. PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
  296. PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
  297. PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
  298. /* PE FN */
  299. PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
  300. PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
  301. /* PF FN */
  302. PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
  303. PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
  304. PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
  305. PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
  306. PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
  307. PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
  308. PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
  309. PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
  310. PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
  311. PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
  312. PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
  313. PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
  314. PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
  315. PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
  316. PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
  317. PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
  318. PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
  319. PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
  320. PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
  321. PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
  322. PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
  323. PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
  324. PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
  325. PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
  326. /* PG FN */
  327. PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
  328. PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
  329. PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
  330. PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
  331. PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
  332. PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
  333. PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
  334. PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
  335. /* PH FN */
  336. PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
  337. PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
  338. PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
  339. PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
  340. PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
  341. PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
  342. PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
  343. PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
  344. PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
  345. PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
  346. PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
  347. PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
  348. PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
  349. PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
  350. PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
  351. PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
  352. PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
  353. PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
  354. PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
  355. PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
  356. PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
  357. /* PJ FN */
  358. PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
  359. PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
  360. PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
  361. PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
  362. PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
  363. PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
  364. PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
  365. PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
  366. PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
  367. PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
  368. PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
  369. PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
  370. PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
  371. PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
  372. PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
  373. PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
  374. PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
  375. PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
  376. PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
  377. };
  378. static const struct sh_pfc_pin pinmux_pins[] = {
  379. /* PA */
  380. PINMUX_GPIO(PA7),
  381. PINMUX_GPIO(PA6),
  382. PINMUX_GPIO(PA5),
  383. PINMUX_GPIO(PA4),
  384. PINMUX_GPIO(PA3),
  385. PINMUX_GPIO(PA2),
  386. PINMUX_GPIO(PA1),
  387. PINMUX_GPIO(PA0),
  388. /* PB */
  389. PINMUX_GPIO(PB7),
  390. PINMUX_GPIO(PB6),
  391. PINMUX_GPIO(PB5),
  392. PINMUX_GPIO(PB4),
  393. PINMUX_GPIO(PB3),
  394. PINMUX_GPIO(PB2),
  395. PINMUX_GPIO(PB1),
  396. PINMUX_GPIO(PB0),
  397. /* PC */
  398. PINMUX_GPIO(PC7),
  399. PINMUX_GPIO(PC6),
  400. PINMUX_GPIO(PC5),
  401. PINMUX_GPIO(PC4),
  402. PINMUX_GPIO(PC3),
  403. PINMUX_GPIO(PC2),
  404. PINMUX_GPIO(PC1),
  405. PINMUX_GPIO(PC0),
  406. /* PD */
  407. PINMUX_GPIO(PD7),
  408. PINMUX_GPIO(PD6),
  409. PINMUX_GPIO(PD5),
  410. PINMUX_GPIO(PD4),
  411. PINMUX_GPIO(PD3),
  412. PINMUX_GPIO(PD2),
  413. PINMUX_GPIO(PD1),
  414. PINMUX_GPIO(PD0),
  415. /* PE */
  416. PINMUX_GPIO(PE7),
  417. PINMUX_GPIO(PE6),
  418. /* PF */
  419. PINMUX_GPIO(PF7),
  420. PINMUX_GPIO(PF6),
  421. PINMUX_GPIO(PF5),
  422. PINMUX_GPIO(PF4),
  423. PINMUX_GPIO(PF3),
  424. PINMUX_GPIO(PF2),
  425. PINMUX_GPIO(PF1),
  426. PINMUX_GPIO(PF0),
  427. /* PG */
  428. PINMUX_GPIO(PG7),
  429. PINMUX_GPIO(PG6),
  430. PINMUX_GPIO(PG5),
  431. /* PH */
  432. PINMUX_GPIO(PH7),
  433. PINMUX_GPIO(PH6),
  434. PINMUX_GPIO(PH5),
  435. PINMUX_GPIO(PH4),
  436. PINMUX_GPIO(PH3),
  437. PINMUX_GPIO(PH2),
  438. PINMUX_GPIO(PH1),
  439. PINMUX_GPIO(PH0),
  440. /* PJ */
  441. PINMUX_GPIO(PJ7),
  442. PINMUX_GPIO(PJ6),
  443. PINMUX_GPIO(PJ5),
  444. PINMUX_GPIO(PJ4),
  445. PINMUX_GPIO(PJ3),
  446. PINMUX_GPIO(PJ2),
  447. PINMUX_GPIO(PJ1),
  448. };
  449. #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
  450. static const struct pinmux_func pinmux_func_gpios[] = {
  451. /* FN */
  452. GPIO_FN(CDE),
  453. GPIO_FN(ETH_MAGIC),
  454. GPIO_FN(DISP),
  455. GPIO_FN(ETH_LINK),
  456. GPIO_FN(DR5),
  457. GPIO_FN(ETH_TX_ER),
  458. GPIO_FN(DR4),
  459. GPIO_FN(ETH_TX_EN),
  460. GPIO_FN(DR3),
  461. GPIO_FN(ETH_TXD3),
  462. GPIO_FN(DR2),
  463. GPIO_FN(ETH_TXD2),
  464. GPIO_FN(DR1),
  465. GPIO_FN(ETH_TXD1),
  466. GPIO_FN(DR0),
  467. GPIO_FN(ETH_TXD0),
  468. GPIO_FN(VSYNC),
  469. GPIO_FN(HSPI_CLK),
  470. GPIO_FN(ODDF),
  471. GPIO_FN(HSPI_CS),
  472. GPIO_FN(DG5),
  473. GPIO_FN(ETH_MDIO),
  474. GPIO_FN(DG4),
  475. GPIO_FN(ETH_RX_CLK),
  476. GPIO_FN(DG3),
  477. GPIO_FN(ETH_MDC),
  478. GPIO_FN(DG2),
  479. GPIO_FN(ETH_COL),
  480. GPIO_FN(DG1),
  481. GPIO_FN(ETH_TX_CLK),
  482. GPIO_FN(DG0),
  483. GPIO_FN(ETH_CRS),
  484. GPIO_FN(DCLKIN),
  485. GPIO_FN(HSPI_RX),
  486. GPIO_FN(HSYNC),
  487. GPIO_FN(HSPI_TX),
  488. GPIO_FN(DB5),
  489. GPIO_FN(ETH_RXD3),
  490. GPIO_FN(DB4),
  491. GPIO_FN(ETH_RXD2),
  492. GPIO_FN(DB3),
  493. GPIO_FN(ETH_RXD1),
  494. GPIO_FN(DB2),
  495. GPIO_FN(ETH_RXD0),
  496. GPIO_FN(DB1),
  497. GPIO_FN(ETH_RX_DV),
  498. GPIO_FN(DB0),
  499. GPIO_FN(ETH_RX_ER),
  500. GPIO_FN(DCLKOUT),
  501. GPIO_FN(SCIF1_SCK),
  502. GPIO_FN(SCIF1_RXD),
  503. GPIO_FN(SCIF1_TXD),
  504. GPIO_FN(DACK1),
  505. GPIO_FN(BACK),
  506. GPIO_FN(FALE),
  507. GPIO_FN(DACK0),
  508. GPIO_FN(FCLE),
  509. GPIO_FN(DREQ1),
  510. GPIO_FN(BREQ),
  511. GPIO_FN(USB_OVC1),
  512. GPIO_FN(DREQ0),
  513. GPIO_FN(USB_OVC0),
  514. GPIO_FN(USB_PENC1),
  515. GPIO_FN(USB_PENC0),
  516. GPIO_FN(HAC1_SDOUT),
  517. GPIO_FN(SSI1_SDATA),
  518. GPIO_FN(SDIF1CMD),
  519. GPIO_FN(HAC1_SDIN),
  520. GPIO_FN(SSI1_SCK),
  521. GPIO_FN(SDIF1CD),
  522. GPIO_FN(HAC1_SYNC),
  523. GPIO_FN(SSI1_WS),
  524. GPIO_FN(SDIF1WP),
  525. GPIO_FN(HAC1_BITCLK),
  526. GPIO_FN(SSI1_CLK),
  527. GPIO_FN(SDIF1CLK),
  528. GPIO_FN(HAC0_SDOUT),
  529. GPIO_FN(SSI0_SDATA),
  530. GPIO_FN(SDIF1D3),
  531. GPIO_FN(HAC0_SDIN),
  532. GPIO_FN(SSI0_SCK),
  533. GPIO_FN(SDIF1D2),
  534. GPIO_FN(HAC0_SYNC),
  535. GPIO_FN(SSI0_WS),
  536. GPIO_FN(SDIF1D1),
  537. GPIO_FN(HAC0_BITCLK),
  538. GPIO_FN(SSI0_CLK),
  539. GPIO_FN(SDIF1D0),
  540. GPIO_FN(SCIF3_SCK),
  541. GPIO_FN(SSI2_SDATA),
  542. GPIO_FN(SCIF3_RXD),
  543. GPIO_FN(TCLK),
  544. GPIO_FN(SSI2_SCK),
  545. GPIO_FN(SCIF3_TXD),
  546. GPIO_FN(HAC_RES),
  547. GPIO_FN(SSI2_WS),
  548. GPIO_FN(DACK3),
  549. GPIO_FN(SDIF0CMD),
  550. GPIO_FN(DACK2),
  551. GPIO_FN(SDIF0CD),
  552. GPIO_FN(DREQ3),
  553. GPIO_FN(SDIF0WP),
  554. GPIO_FN(SCIF0_CTS),
  555. GPIO_FN(DREQ2),
  556. GPIO_FN(SDIF0CLK),
  557. GPIO_FN(SCIF0_RTS),
  558. GPIO_FN(IRL7),
  559. GPIO_FN(SDIF0D3),
  560. GPIO_FN(SCIF0_SCK),
  561. GPIO_FN(IRL6),
  562. GPIO_FN(SDIF0D2),
  563. GPIO_FN(SCIF0_RXD),
  564. GPIO_FN(IRL5),
  565. GPIO_FN(SDIF0D1),
  566. GPIO_FN(SCIF0_TXD),
  567. GPIO_FN(IRL4),
  568. GPIO_FN(SDIF0D0),
  569. GPIO_FN(SCIF5_SCK),
  570. GPIO_FN(FRB),
  571. GPIO_FN(SCIF5_RXD),
  572. GPIO_FN(IOIS16),
  573. GPIO_FN(SCIF5_TXD),
  574. GPIO_FN(CE2B),
  575. GPIO_FN(DRAK3),
  576. GPIO_FN(CE2A),
  577. GPIO_FN(SCIF4_SCK),
  578. GPIO_FN(DRAK2),
  579. GPIO_FN(SSI3_WS),
  580. GPIO_FN(SCIF4_RXD),
  581. GPIO_FN(DRAK1),
  582. GPIO_FN(SSI3_SDATA),
  583. GPIO_FN(FSTATUS),
  584. GPIO_FN(SCIF4_TXD),
  585. GPIO_FN(DRAK0),
  586. GPIO_FN(SSI3_SCK),
  587. GPIO_FN(FSE),
  588. };
  589. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  590. { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP(
  591. PA7_FN, PA7_OUT, PA7_IN, 0,
  592. PA6_FN, PA6_OUT, PA6_IN, 0,
  593. PA5_FN, PA5_OUT, PA5_IN, 0,
  594. PA4_FN, PA4_OUT, PA4_IN, 0,
  595. PA3_FN, PA3_OUT, PA3_IN, 0,
  596. PA2_FN, PA2_OUT, PA2_IN, 0,
  597. PA1_FN, PA1_OUT, PA1_IN, 0,
  598. PA0_FN, PA0_OUT, PA0_IN, 0 ))
  599. },
  600. { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP(
  601. PB7_FN, PB7_OUT, PB7_IN, 0,
  602. PB6_FN, PB6_OUT, PB6_IN, 0,
  603. PB5_FN, PB5_OUT, PB5_IN, 0,
  604. PB4_FN, PB4_OUT, PB4_IN, 0,
  605. PB3_FN, PB3_OUT, PB3_IN, 0,
  606. PB2_FN, PB2_OUT, PB2_IN, 0,
  607. PB1_FN, PB1_OUT, PB1_IN, 0,
  608. PB0_FN, PB0_OUT, PB0_IN, 0 ))
  609. },
  610. { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP(
  611. PC7_FN, PC7_OUT, PC7_IN, 0,
  612. PC6_FN, PC6_OUT, PC6_IN, 0,
  613. PC5_FN, PC5_OUT, PC5_IN, 0,
  614. PC4_FN, PC4_OUT, PC4_IN, 0,
  615. PC3_FN, PC3_OUT, PC3_IN, 0,
  616. PC2_FN, PC2_OUT, PC2_IN, 0,
  617. PC1_FN, PC1_OUT, PC1_IN, 0,
  618. PC0_FN, PC0_OUT, PC0_IN, 0 ))
  619. },
  620. { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP(
  621. PD7_FN, PD7_OUT, PD7_IN, 0,
  622. PD6_FN, PD6_OUT, PD6_IN, 0,
  623. PD5_FN, PD5_OUT, PD5_IN, 0,
  624. PD4_FN, PD4_OUT, PD4_IN, 0,
  625. PD3_FN, PD3_OUT, PD3_IN, 0,
  626. PD2_FN, PD2_OUT, PD2_IN, 0,
  627. PD1_FN, PD1_OUT, PD1_IN, 0,
  628. PD0_FN, PD0_OUT, PD0_IN, 0 ))
  629. },
  630. { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP(
  631. PE7_FN, PE7_OUT, PE7_IN, 0,
  632. PE6_FN, PE6_OUT, PE6_IN, 0,
  633. 0, 0, 0, 0,
  634. 0, 0, 0, 0,
  635. 0, 0, 0, 0,
  636. 0, 0, 0, 0,
  637. 0, 0, 0, 0,
  638. 0, 0, 0, 0, ))
  639. },
  640. { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP(
  641. PF7_FN, PF7_OUT, PF7_IN, 0,
  642. PF6_FN, PF6_OUT, PF6_IN, 0,
  643. PF5_FN, PF5_OUT, PF5_IN, 0,
  644. PF4_FN, PF4_OUT, PF4_IN, 0,
  645. PF3_FN, PF3_OUT, PF3_IN, 0,
  646. PF2_FN, PF2_OUT, PF2_IN, 0,
  647. PF1_FN, PF1_OUT, PF1_IN, 0,
  648. PF0_FN, PF0_OUT, PF0_IN, 0 ))
  649. },
  650. { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP(
  651. PG7_FN, PG7_OUT, PG7_IN, 0,
  652. PG6_FN, PG6_OUT, PG6_IN, 0,
  653. PG5_FN, PG5_OUT, PG5_IN, 0,
  654. 0, 0, 0, 0,
  655. 0, 0, 0, 0,
  656. 0, 0, 0, 0,
  657. 0, 0, 0, 0,
  658. 0, 0, 0, 0, ))
  659. },
  660. { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP(
  661. PH7_FN, PH7_OUT, PH7_IN, 0,
  662. PH6_FN, PH6_OUT, PH6_IN, 0,
  663. PH5_FN, PH5_OUT, PH5_IN, 0,
  664. PH4_FN, PH4_OUT, PH4_IN, 0,
  665. PH3_FN, PH3_OUT, PH3_IN, 0,
  666. PH2_FN, PH2_OUT, PH2_IN, 0,
  667. PH1_FN, PH1_OUT, PH1_IN, 0,
  668. PH0_FN, PH0_OUT, PH0_IN, 0 ))
  669. },
  670. { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP(
  671. PJ7_FN, PJ7_OUT, PJ7_IN, 0,
  672. PJ6_FN, PJ6_OUT, PJ6_IN, 0,
  673. PJ5_FN, PJ5_OUT, PJ5_IN, 0,
  674. PJ4_FN, PJ4_OUT, PJ4_IN, 0,
  675. PJ3_FN, PJ3_OUT, PJ3_IN, 0,
  676. PJ2_FN, PJ2_OUT, PJ2_IN, 0,
  677. PJ1_FN, PJ1_OUT, PJ1_IN, 0,
  678. 0, 0, 0, 0, ))
  679. },
  680. { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP(
  681. 0, 0,
  682. P1MSEL14_0, P1MSEL14_1,
  683. P1MSEL13_0, P1MSEL13_1,
  684. P1MSEL12_0, P1MSEL12_1,
  685. P1MSEL11_0, P1MSEL11_1,
  686. P1MSEL10_0, P1MSEL10_1,
  687. P1MSEL9_0, P1MSEL9_1,
  688. P1MSEL8_0, P1MSEL8_1,
  689. P1MSEL7_0, P1MSEL7_1,
  690. P1MSEL6_0, P1MSEL6_1,
  691. P1MSEL5_0, P1MSEL5_1,
  692. P1MSEL4_0, P1MSEL4_1,
  693. P1MSEL3_0, P1MSEL3_1,
  694. P1MSEL2_0, P1MSEL2_1,
  695. P1MSEL1_0, P1MSEL1_1,
  696. P1MSEL0_0, P1MSEL0_1 ))
  697. },
  698. { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP(
  699. P2MSEL15_0, P2MSEL15_1,
  700. P2MSEL14_0, P2MSEL14_1,
  701. P2MSEL13_0, P2MSEL13_1,
  702. P2MSEL12_0, P2MSEL12_1,
  703. P2MSEL11_0, P2MSEL11_1,
  704. P2MSEL10_0, P2MSEL10_1,
  705. P2MSEL9_0, P2MSEL9_1,
  706. P2MSEL8_0, P2MSEL8_1,
  707. P2MSEL7_0, P2MSEL7_1,
  708. P2MSEL6_0, P2MSEL6_1,
  709. P2MSEL5_0, P2MSEL5_1,
  710. P2MSEL4_0, P2MSEL4_1,
  711. P2MSEL3_0, P2MSEL3_1,
  712. P2MSEL2_0, P2MSEL2_1,
  713. P2MSEL1_0, P2MSEL1_1,
  714. P2MSEL0_0, P2MSEL0_1 ))
  715. },
  716. {}
  717. };
  718. static const struct pinmux_data_reg pinmux_data_regs[] = {
  719. { PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP(
  720. PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
  721. PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
  722. },
  723. { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP(
  724. PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
  725. PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
  726. },
  727. { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP(
  728. PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
  729. PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
  730. },
  731. { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP(
  732. PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
  733. PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
  734. },
  735. { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP(
  736. PE7_DATA, PE6_DATA,
  737. 0, 0, 0, 0, 0, 0 ))
  738. },
  739. { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP(
  740. PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
  741. PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
  742. },
  743. { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP(
  744. PG7_DATA, PG6_DATA, PG5_DATA, 0,
  745. 0, 0, 0, 0 ))
  746. },
  747. { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP(
  748. PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
  749. PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
  750. },
  751. { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP(
  752. PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
  753. PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
  754. },
  755. { },
  756. };
  757. const struct sh_pfc_soc_info sh7786_pinmux_info = {
  758. .name = "sh7786_pfc",
  759. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  760. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  761. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  762. .pins = pinmux_pins,
  763. .nr_pins = ARRAY_SIZE(pinmux_pins),
  764. .func_gpios = pinmux_func_gpios,
  765. .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
  766. .cfg_regs = pinmux_config_regs,
  767. .data_regs = pinmux_data_regs,
  768. .pinmux_data = pinmux_data,
  769. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  770. };