pfc-sh7785.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH7785 Pinmux
  4. *
  5. * Copyright (C) 2008 Magnus Damm
  6. */
  7. #include <linux/init.h>
  8. #include <linux/kernel.h>
  9. #include <cpu/sh7785.h>
  10. #include "sh_pfc.h"
  11. enum {
  12. PINMUX_RESERVED = 0,
  13. PINMUX_DATA_BEGIN,
  14. PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
  15. PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
  16. PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
  17. PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
  18. PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
  19. PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
  20. PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
  21. PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
  22. PE5_DATA, PE4_DATA, PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
  23. PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
  24. PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
  25. PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
  26. PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
  27. PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
  28. PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
  29. PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
  30. PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
  31. PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
  32. PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA,
  33. PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA,
  34. PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA,
  35. PM1_DATA, PM0_DATA,
  36. PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA,
  37. PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA,
  38. PP5_DATA, PP4_DATA, PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA,
  39. PQ4_DATA, PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA,
  40. PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA,
  41. PINMUX_DATA_END,
  42. PINMUX_INPUT_BEGIN,
  43. PA7_IN, PA6_IN, PA5_IN, PA4_IN,
  44. PA3_IN, PA2_IN, PA1_IN, PA0_IN,
  45. PB7_IN, PB6_IN, PB5_IN, PB4_IN,
  46. PB3_IN, PB2_IN, PB1_IN, PB0_IN,
  47. PC7_IN, PC6_IN, PC5_IN, PC4_IN,
  48. PC3_IN, PC2_IN, PC1_IN, PC0_IN,
  49. PD7_IN, PD6_IN, PD5_IN, PD4_IN,
  50. PD3_IN, PD2_IN, PD1_IN, PD0_IN,
  51. PE5_IN, PE4_IN, PE3_IN, PE2_IN, PE1_IN, PE0_IN,
  52. PF7_IN, PF6_IN, PF5_IN, PF4_IN,
  53. PF3_IN, PF2_IN, PF1_IN, PF0_IN,
  54. PG7_IN, PG6_IN, PG5_IN, PG4_IN,
  55. PG3_IN, PG2_IN, PG1_IN, PG0_IN,
  56. PH7_IN, PH6_IN, PH5_IN, PH4_IN,
  57. PH3_IN, PH2_IN, PH1_IN, PH0_IN,
  58. PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
  59. PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
  60. PK7_IN, PK6_IN, PK5_IN, PK4_IN,
  61. PK3_IN, PK2_IN, PK1_IN, PK0_IN,
  62. PL7_IN, PL6_IN, PL5_IN, PL4_IN,
  63. PL3_IN, PL2_IN, PL1_IN, PL0_IN,
  64. PM1_IN, PM0_IN,
  65. PN7_IN, PN6_IN, PN5_IN, PN4_IN,
  66. PN3_IN, PN2_IN, PN1_IN, PN0_IN,
  67. PP5_IN, PP4_IN, PP3_IN, PP2_IN, PP1_IN, PP0_IN,
  68. PQ4_IN, PQ3_IN, PQ2_IN, PQ1_IN, PQ0_IN,
  69. PR3_IN, PR2_IN, PR1_IN, PR0_IN,
  70. PINMUX_INPUT_END,
  71. PINMUX_OUTPUT_BEGIN,
  72. PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
  73. PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
  74. PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
  75. PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
  76. PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
  77. PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
  78. PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
  79. PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
  80. PE5_OUT, PE4_OUT, PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
  81. PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
  82. PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
  83. PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
  84. PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
  85. PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
  86. PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
  87. PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
  88. PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
  89. PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT,
  90. PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT,
  91. PL7_OUT, PL6_OUT, PL5_OUT, PL4_OUT,
  92. PL3_OUT, PL2_OUT, PL1_OUT, PL0_OUT,
  93. PM1_OUT, PM0_OUT,
  94. PN7_OUT, PN6_OUT, PN5_OUT, PN4_OUT,
  95. PN3_OUT, PN2_OUT, PN1_OUT, PN0_OUT,
  96. PP5_OUT, PP4_OUT, PP3_OUT, PP2_OUT, PP1_OUT, PP0_OUT,
  97. PQ4_OUT, PQ3_OUT, PQ2_OUT, PQ1_OUT, PQ0_OUT,
  98. PR3_OUT, PR2_OUT, PR1_OUT, PR0_OUT,
  99. PINMUX_OUTPUT_END,
  100. PINMUX_FUNCTION_BEGIN,
  101. PA7_FN, PA6_FN, PA5_FN, PA4_FN,
  102. PA3_FN, PA2_FN, PA1_FN, PA0_FN,
  103. PB7_FN, PB6_FN, PB5_FN, PB4_FN,
  104. PB3_FN, PB2_FN, PB1_FN, PB0_FN,
  105. PC7_FN, PC6_FN, PC5_FN, PC4_FN,
  106. PC3_FN, PC2_FN, PC1_FN, PC0_FN,
  107. PD7_FN, PD6_FN, PD5_FN, PD4_FN,
  108. PD3_FN, PD2_FN, PD1_FN, PD0_FN,
  109. PE5_FN, PE4_FN, PE3_FN, PE2_FN, PE1_FN, PE0_FN,
  110. PF7_FN, PF6_FN, PF5_FN, PF4_FN,
  111. PF3_FN, PF2_FN, PF1_FN, PF0_FN,
  112. PG7_FN, PG6_FN, PG5_FN, PG4_FN,
  113. PG3_FN, PG2_FN, PG1_FN, PG0_FN,
  114. PH7_FN, PH6_FN, PH5_FN, PH4_FN,
  115. PH3_FN, PH2_FN, PH1_FN, PH0_FN,
  116. PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
  117. PJ3_FN, PJ2_FN, PJ1_FN, PJ0_FN,
  118. PK7_FN, PK6_FN, PK5_FN, PK4_FN,
  119. PK3_FN, PK2_FN, PK1_FN, PK0_FN,
  120. PL7_FN, PL6_FN, PL5_FN, PL4_FN,
  121. PL3_FN, PL2_FN, PL1_FN, PL0_FN,
  122. PM1_FN, PM0_FN,
  123. PN7_FN, PN6_FN, PN5_FN, PN4_FN,
  124. PN3_FN, PN2_FN, PN1_FN, PN0_FN,
  125. PP5_FN, PP4_FN, PP3_FN, PP2_FN, PP1_FN, PP0_FN,
  126. PQ4_FN, PQ3_FN, PQ2_FN, PQ1_FN, PQ0_FN,
  127. PR3_FN, PR2_FN, PR1_FN, PR0_FN,
  128. P1MSEL15_0, P1MSEL15_1,
  129. P1MSEL14_0, P1MSEL14_1,
  130. P1MSEL13_0, P1MSEL13_1,
  131. P1MSEL12_0, P1MSEL12_1,
  132. P1MSEL11_0, P1MSEL11_1,
  133. P1MSEL10_0, P1MSEL10_1,
  134. P1MSEL9_0, P1MSEL9_1,
  135. P1MSEL8_0, P1MSEL8_1,
  136. P1MSEL7_0, P1MSEL7_1,
  137. P1MSEL6_0, P1MSEL6_1,
  138. P1MSEL5_0,
  139. P1MSEL4_0, P1MSEL4_1,
  140. P1MSEL3_0, P1MSEL3_1,
  141. P1MSEL2_0, P1MSEL2_1,
  142. P1MSEL1_0, P1MSEL1_1,
  143. P1MSEL0_0, P1MSEL0_1,
  144. P2MSEL2_0, P2MSEL2_1,
  145. P2MSEL1_0, P2MSEL1_1,
  146. P2MSEL0_0, P2MSEL0_1,
  147. PINMUX_FUNCTION_END,
  148. PINMUX_MARK_BEGIN,
  149. D63_AD31_MARK,
  150. D62_AD30_MARK,
  151. D61_AD29_MARK,
  152. D60_AD28_MARK,
  153. D59_AD27_MARK,
  154. D58_AD26_MARK,
  155. D57_AD25_MARK,
  156. D56_AD24_MARK,
  157. D55_AD23_MARK,
  158. D54_AD22_MARK,
  159. D53_AD21_MARK,
  160. D52_AD20_MARK,
  161. D51_AD19_MARK,
  162. D50_AD18_MARK,
  163. D49_AD17_DB5_MARK,
  164. D48_AD16_DB4_MARK,
  165. D47_AD15_DB3_MARK,
  166. D46_AD14_DB2_MARK,
  167. D45_AD13_DB1_MARK,
  168. D44_AD12_DB0_MARK,
  169. D43_AD11_DG5_MARK,
  170. D42_AD10_DG4_MARK,
  171. D41_AD9_DG3_MARK,
  172. D40_AD8_DG2_MARK,
  173. D39_AD7_DG1_MARK,
  174. D38_AD6_DG0_MARK,
  175. D37_AD5_DR5_MARK,
  176. D36_AD4_DR4_MARK,
  177. D35_AD3_DR3_MARK,
  178. D34_AD2_DR2_MARK,
  179. D33_AD1_DR1_MARK,
  180. D32_AD0_DR0_MARK,
  181. REQ1_MARK,
  182. REQ2_MARK,
  183. REQ3_MARK,
  184. GNT1_MARK,
  185. GNT2_MARK,
  186. GNT3_MARK,
  187. MMCCLK_MARK,
  188. D31_MARK,
  189. D30_MARK,
  190. D29_MARK,
  191. D28_MARK,
  192. D27_MARK,
  193. D26_MARK,
  194. D25_MARK,
  195. D24_MARK,
  196. D23_MARK,
  197. D22_MARK,
  198. D21_MARK,
  199. D20_MARK,
  200. D19_MARK,
  201. D18_MARK,
  202. D17_MARK,
  203. D16_MARK,
  204. SCIF1_SCK_MARK,
  205. SCIF1_RXD_MARK,
  206. SCIF1_TXD_MARK,
  207. SCIF0_CTS_MARK,
  208. INTD_MARK,
  209. FCE_MARK,
  210. SCIF0_RTS_MARK,
  211. HSPI_CS_MARK,
  212. FSE_MARK,
  213. SCIF0_SCK_MARK,
  214. HSPI_CLK_MARK,
  215. FRE_MARK,
  216. SCIF0_RXD_MARK,
  217. HSPI_RX_MARK,
  218. FRB_MARK,
  219. SCIF0_TXD_MARK,
  220. HSPI_TX_MARK,
  221. FWE_MARK,
  222. SCIF5_TXD_MARK,
  223. HAC1_SYNC_MARK,
  224. SSI1_WS_MARK,
  225. SIOF_TXD_PJ_MARK,
  226. HAC0_SDOUT_MARK,
  227. SSI0_SDATA_MARK,
  228. SIOF_RXD_PJ_MARK,
  229. HAC0_SDIN_MARK,
  230. SSI0_SCK_MARK,
  231. SIOF_SYNC_PJ_MARK,
  232. HAC0_SYNC_MARK,
  233. SSI0_WS_MARK,
  234. SIOF_MCLK_PJ_MARK,
  235. HAC_RES_MARK,
  236. SIOF_SCK_PJ_MARK,
  237. HAC0_BITCLK_MARK,
  238. SSI0_CLK_MARK,
  239. HAC1_BITCLK_MARK,
  240. SSI1_CLK_MARK,
  241. TCLK_MARK,
  242. IOIS16_MARK,
  243. STATUS0_MARK,
  244. DRAK0_PK3_MARK,
  245. STATUS1_MARK,
  246. DRAK1_PK2_MARK,
  247. DACK2_MARK,
  248. SCIF2_TXD_MARK,
  249. MMCCMD_MARK,
  250. SIOF_TXD_PK_MARK,
  251. DACK3_MARK,
  252. SCIF2_SCK_MARK,
  253. MMCDAT_MARK,
  254. SIOF_SCK_PK_MARK,
  255. DREQ0_MARK,
  256. DREQ1_MARK,
  257. DRAK0_PK1_MARK,
  258. DRAK1_PK0_MARK,
  259. DREQ2_MARK,
  260. INTB_MARK,
  261. DREQ3_MARK,
  262. INTC_MARK,
  263. DRAK2_MARK,
  264. CE2A_MARK,
  265. IRL4_MARK,
  266. FD4_MARK,
  267. IRL5_MARK,
  268. FD5_MARK,
  269. IRL6_MARK,
  270. FD6_MARK,
  271. IRL7_MARK,
  272. FD7_MARK,
  273. DRAK3_MARK,
  274. CE2B_MARK,
  275. BREQ_BSACK_MARK,
  276. BACK_BSREQ_MARK,
  277. SCIF5_RXD_MARK,
  278. HAC1_SDIN_MARK,
  279. SSI1_SCK_MARK,
  280. SCIF5_SCK_MARK,
  281. HAC1_SDOUT_MARK,
  282. SSI1_SDATA_MARK,
  283. SCIF3_TXD_MARK,
  284. FCLE_MARK,
  285. SCIF3_RXD_MARK,
  286. FALE_MARK,
  287. SCIF3_SCK_MARK,
  288. FD0_MARK,
  289. SCIF4_TXD_MARK,
  290. FD1_MARK,
  291. SCIF4_RXD_MARK,
  292. FD2_MARK,
  293. SCIF4_SCK_MARK,
  294. FD3_MARK,
  295. DEVSEL_DCLKOUT_MARK,
  296. STOP_CDE_MARK,
  297. LOCK_ODDF_MARK,
  298. TRDY_DISPL_MARK,
  299. IRDY_HSYNC_MARK,
  300. PCIFRAME_VSYNC_MARK,
  301. INTA_MARK,
  302. GNT0_GNTIN_MARK,
  303. REQ0_REQOUT_MARK,
  304. PERR_MARK,
  305. SERR_MARK,
  306. WE7_CBE3_MARK,
  307. WE6_CBE2_MARK,
  308. WE5_CBE1_MARK,
  309. WE4_CBE0_MARK,
  310. SCIF2_RXD_MARK,
  311. SIOF_RXD_MARK,
  312. MRESETOUT_MARK,
  313. IRQOUT_MARK,
  314. PINMUX_MARK_END,
  315. };
  316. static const u16 pinmux_data[] = {
  317. /* PA GPIO */
  318. PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
  319. PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
  320. PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
  321. PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
  322. PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
  323. PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
  324. PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
  325. PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
  326. /* PB GPIO */
  327. PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
  328. PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
  329. PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
  330. PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
  331. PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
  332. PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
  333. PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
  334. PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
  335. /* PC GPIO */
  336. PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
  337. PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
  338. PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
  339. PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
  340. PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
  341. PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
  342. PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
  343. PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
  344. /* PD GPIO */
  345. PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
  346. PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
  347. PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
  348. PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
  349. PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
  350. PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
  351. PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
  352. PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
  353. /* PE GPIO */
  354. PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT),
  355. PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT),
  356. PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT),
  357. PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT),
  358. PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT),
  359. PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT),
  360. /* PF GPIO */
  361. PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
  362. PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
  363. PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
  364. PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
  365. PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
  366. PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
  367. PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
  368. PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
  369. /* PG GPIO */
  370. PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
  371. PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
  372. PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
  373. PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT),
  374. PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT),
  375. PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT),
  376. PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT),
  377. PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT),
  378. /* PH GPIO */
  379. PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
  380. PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
  381. PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
  382. PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
  383. PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
  384. PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
  385. PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
  386. PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
  387. /* PJ GPIO */
  388. PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
  389. PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
  390. PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
  391. PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
  392. PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
  393. PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
  394. PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
  395. PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT),
  396. /* PK GPIO */
  397. PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT),
  398. PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT),
  399. PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT),
  400. PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT),
  401. PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT),
  402. PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT),
  403. PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT),
  404. PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT),
  405. /* PL GPIO */
  406. PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT),
  407. PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT),
  408. PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT),
  409. PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT),
  410. PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT),
  411. PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT),
  412. PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT),
  413. PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT),
  414. /* PM GPIO */
  415. PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT),
  416. PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT),
  417. /* PN GPIO */
  418. PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT),
  419. PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT),
  420. PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT),
  421. PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT),
  422. PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT),
  423. PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT),
  424. PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT),
  425. PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT),
  426. /* PP GPIO */
  427. PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT),
  428. PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT),
  429. PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT),
  430. PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT),
  431. PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT),
  432. PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT),
  433. /* PQ GPIO */
  434. PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT),
  435. PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT),
  436. PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT),
  437. PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT),
  438. PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT),
  439. /* PR GPIO */
  440. PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT),
  441. PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT),
  442. PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT),
  443. PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT),
  444. /* PA FN */
  445. PINMUX_DATA(D63_AD31_MARK, PA7_FN),
  446. PINMUX_DATA(D62_AD30_MARK, PA6_FN),
  447. PINMUX_DATA(D61_AD29_MARK, PA5_FN),
  448. PINMUX_DATA(D60_AD28_MARK, PA4_FN),
  449. PINMUX_DATA(D59_AD27_MARK, PA3_FN),
  450. PINMUX_DATA(D58_AD26_MARK, PA2_FN),
  451. PINMUX_DATA(D57_AD25_MARK, PA1_FN),
  452. PINMUX_DATA(D56_AD24_MARK, PA0_FN),
  453. /* PB FN */
  454. PINMUX_DATA(D55_AD23_MARK, PB7_FN),
  455. PINMUX_DATA(D54_AD22_MARK, PB6_FN),
  456. PINMUX_DATA(D53_AD21_MARK, PB5_FN),
  457. PINMUX_DATA(D52_AD20_MARK, PB4_FN),
  458. PINMUX_DATA(D51_AD19_MARK, PB3_FN),
  459. PINMUX_DATA(D50_AD18_MARK, PB2_FN),
  460. PINMUX_DATA(D49_AD17_DB5_MARK, PB1_FN),
  461. PINMUX_DATA(D48_AD16_DB4_MARK, PB0_FN),
  462. /* PC FN */
  463. PINMUX_DATA(D47_AD15_DB3_MARK, PC7_FN),
  464. PINMUX_DATA(D46_AD14_DB2_MARK, PC6_FN),
  465. PINMUX_DATA(D45_AD13_DB1_MARK, PC5_FN),
  466. PINMUX_DATA(D44_AD12_DB0_MARK, PC4_FN),
  467. PINMUX_DATA(D43_AD11_DG5_MARK, PC3_FN),
  468. PINMUX_DATA(D42_AD10_DG4_MARK, PC2_FN),
  469. PINMUX_DATA(D41_AD9_DG3_MARK, PC1_FN),
  470. PINMUX_DATA(D40_AD8_DG2_MARK, PC0_FN),
  471. /* PD FN */
  472. PINMUX_DATA(D39_AD7_DG1_MARK, PD7_FN),
  473. PINMUX_DATA(D38_AD6_DG0_MARK, PD6_FN),
  474. PINMUX_DATA(D37_AD5_DR5_MARK, PD5_FN),
  475. PINMUX_DATA(D36_AD4_DR4_MARK, PD4_FN),
  476. PINMUX_DATA(D35_AD3_DR3_MARK, PD3_FN),
  477. PINMUX_DATA(D34_AD2_DR2_MARK, PD2_FN),
  478. PINMUX_DATA(D33_AD1_DR1_MARK, PD1_FN),
  479. PINMUX_DATA(D32_AD0_DR0_MARK, PD0_FN),
  480. /* PE FN */
  481. PINMUX_DATA(REQ1_MARK, PE5_FN),
  482. PINMUX_DATA(REQ2_MARK, PE4_FN),
  483. PINMUX_DATA(REQ3_MARK, P2MSEL0_0, PE3_FN),
  484. PINMUX_DATA(GNT1_MARK, PE2_FN),
  485. PINMUX_DATA(GNT2_MARK, PE1_FN),
  486. PINMUX_DATA(GNT3_MARK, P2MSEL0_0, PE0_FN),
  487. PINMUX_DATA(MMCCLK_MARK, P2MSEL0_1, PE0_FN),
  488. /* PF FN */
  489. PINMUX_DATA(D31_MARK, PF7_FN),
  490. PINMUX_DATA(D30_MARK, PF6_FN),
  491. PINMUX_DATA(D29_MARK, PF5_FN),
  492. PINMUX_DATA(D28_MARK, PF4_FN),
  493. PINMUX_DATA(D27_MARK, PF3_FN),
  494. PINMUX_DATA(D26_MARK, PF2_FN),
  495. PINMUX_DATA(D25_MARK, PF1_FN),
  496. PINMUX_DATA(D24_MARK, PF0_FN),
  497. /* PF FN */
  498. PINMUX_DATA(D23_MARK, PG7_FN),
  499. PINMUX_DATA(D22_MARK, PG6_FN),
  500. PINMUX_DATA(D21_MARK, PG5_FN),
  501. PINMUX_DATA(D20_MARK, PG4_FN),
  502. PINMUX_DATA(D19_MARK, PG3_FN),
  503. PINMUX_DATA(D18_MARK, PG2_FN),
  504. PINMUX_DATA(D17_MARK, PG1_FN),
  505. PINMUX_DATA(D16_MARK, PG0_FN),
  506. /* PH FN */
  507. PINMUX_DATA(SCIF1_SCK_MARK, PH7_FN),
  508. PINMUX_DATA(SCIF1_RXD_MARK, PH6_FN),
  509. PINMUX_DATA(SCIF1_TXD_MARK, PH5_FN),
  510. PINMUX_DATA(SCIF0_CTS_MARK, PH4_FN),
  511. PINMUX_DATA(INTD_MARK, P1MSEL7_1, PH4_FN),
  512. PINMUX_DATA(FCE_MARK, P1MSEL8_1, P1MSEL7_0, PH4_FN),
  513. PINMUX_DATA(SCIF0_RTS_MARK, P1MSEL8_0, P1MSEL7_0, PH3_FN),
  514. PINMUX_DATA(HSPI_CS_MARK, P1MSEL8_0, P1MSEL7_1, PH3_FN),
  515. PINMUX_DATA(FSE_MARK, P1MSEL8_1, P1MSEL7_0, PH3_FN),
  516. PINMUX_DATA(SCIF0_SCK_MARK, P1MSEL8_0, P1MSEL7_0, PH2_FN),
  517. PINMUX_DATA(HSPI_CLK_MARK, P1MSEL8_0, P1MSEL7_1, PH2_FN),
  518. PINMUX_DATA(FRE_MARK, P1MSEL8_1, P1MSEL7_0, PH2_FN),
  519. PINMUX_DATA(SCIF0_RXD_MARK, P1MSEL8_0, P1MSEL7_0, PH1_FN),
  520. PINMUX_DATA(HSPI_RX_MARK, P1MSEL8_0, P1MSEL7_1, PH1_FN),
  521. PINMUX_DATA(FRB_MARK, P1MSEL8_1, P1MSEL7_0, PH1_FN),
  522. PINMUX_DATA(SCIF0_TXD_MARK, P1MSEL8_0, P1MSEL7_0, PH0_FN),
  523. PINMUX_DATA(HSPI_TX_MARK, P1MSEL8_0, P1MSEL7_1, PH0_FN),
  524. PINMUX_DATA(FWE_MARK, P1MSEL8_1, P1MSEL7_0, PH0_FN),
  525. /* PJ FN */
  526. PINMUX_DATA(SCIF5_TXD_MARK, P1MSEL2_0, P1MSEL1_0, PJ7_FN),
  527. PINMUX_DATA(HAC1_SYNC_MARK, P1MSEL2_0, P1MSEL1_1, PJ7_FN),
  528. PINMUX_DATA(SSI1_WS_MARK, P1MSEL2_1, P1MSEL1_0, PJ7_FN),
  529. PINMUX_DATA(SIOF_TXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ6_FN),
  530. PINMUX_DATA(HAC0_SDOUT_MARK, P1MSEL4_0, P1MSEL3_1, PJ6_FN),
  531. PINMUX_DATA(SSI0_SDATA_MARK, P1MSEL4_1, P1MSEL3_0, PJ6_FN),
  532. PINMUX_DATA(SIOF_RXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ5_FN),
  533. PINMUX_DATA(HAC0_SDIN_MARK, P1MSEL4_0, P1MSEL3_1, PJ5_FN),
  534. PINMUX_DATA(SSI0_SCK_MARK, P1MSEL4_1, P1MSEL3_0, PJ5_FN),
  535. PINMUX_DATA(SIOF_SYNC_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ4_FN),
  536. PINMUX_DATA(HAC0_SYNC_MARK, P1MSEL4_0, P1MSEL3_1, PJ4_FN),
  537. PINMUX_DATA(SSI0_WS_MARK, P1MSEL4_1, P1MSEL3_0, PJ4_FN),
  538. PINMUX_DATA(SIOF_MCLK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ3_FN),
  539. PINMUX_DATA(HAC_RES_MARK, P1MSEL4_0, P1MSEL3_1, PJ3_FN),
  540. PINMUX_DATA(SIOF_SCK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ2_FN),
  541. PINMUX_DATA(HAC0_BITCLK_MARK, P1MSEL4_0, P1MSEL3_1, PJ2_FN),
  542. PINMUX_DATA(SSI0_CLK_MARK, P1MSEL4_1, P1MSEL3_0, PJ2_FN),
  543. PINMUX_DATA(HAC1_BITCLK_MARK, P1MSEL2_0, PJ1_FN),
  544. PINMUX_DATA(SSI1_CLK_MARK, P1MSEL2_1, P1MSEL1_0, PJ1_FN),
  545. PINMUX_DATA(TCLK_MARK, P1MSEL9_0, PJ0_FN),
  546. PINMUX_DATA(IOIS16_MARK, P1MSEL9_1, PJ0_FN),
  547. /* PK FN */
  548. PINMUX_DATA(STATUS0_MARK, P1MSEL15_0, PK7_FN),
  549. PINMUX_DATA(DRAK0_PK3_MARK, P1MSEL15_1, PK7_FN),
  550. PINMUX_DATA(STATUS1_MARK, P1MSEL15_0, PK6_FN),
  551. PINMUX_DATA(DRAK1_PK2_MARK, P1MSEL15_1, PK6_FN),
  552. PINMUX_DATA(DACK2_MARK, P1MSEL12_0, P1MSEL11_0, PK5_FN),
  553. PINMUX_DATA(SCIF2_TXD_MARK, P1MSEL12_1, P1MSEL11_0, PK5_FN),
  554. PINMUX_DATA(MMCCMD_MARK, P1MSEL12_1, P1MSEL11_1, PK5_FN),
  555. PINMUX_DATA(SIOF_TXD_PK_MARK, P2MSEL1_1,
  556. P1MSEL12_0, P1MSEL11_1, PK5_FN),
  557. PINMUX_DATA(DACK3_MARK, P1MSEL12_0, P1MSEL11_0, PK4_FN),
  558. PINMUX_DATA(SCIF2_SCK_MARK, P1MSEL12_1, P1MSEL11_0, PK4_FN),
  559. PINMUX_DATA(MMCDAT_MARK, P1MSEL12_1, P1MSEL11_1, PK4_FN),
  560. PINMUX_DATA(SIOF_SCK_PK_MARK, P2MSEL1_1,
  561. P1MSEL12_0, P1MSEL11_1, PK4_FN),
  562. PINMUX_DATA(DREQ0_MARK, PK3_FN),
  563. PINMUX_DATA(DREQ1_MARK, PK2_FN),
  564. PINMUX_DATA(DRAK0_PK1_MARK, PK1_FN),
  565. PINMUX_DATA(DRAK1_PK0_MARK, PK0_FN),
  566. /* PL FN */
  567. PINMUX_DATA(DREQ2_MARK, P1MSEL13_0, PL7_FN),
  568. PINMUX_DATA(INTB_MARK, P1MSEL13_1, PL7_FN),
  569. PINMUX_DATA(DREQ3_MARK, P1MSEL13_0, PL6_FN),
  570. PINMUX_DATA(INTC_MARK, P1MSEL13_1, PL6_FN),
  571. PINMUX_DATA(DRAK2_MARK, P1MSEL10_0, PL5_FN),
  572. PINMUX_DATA(CE2A_MARK, P1MSEL10_1, PL5_FN),
  573. PINMUX_DATA(IRL4_MARK, P1MSEL14_0, PL4_FN),
  574. PINMUX_DATA(FD4_MARK, P1MSEL14_1, PL4_FN),
  575. PINMUX_DATA(IRL5_MARK, P1MSEL14_0, PL3_FN),
  576. PINMUX_DATA(FD5_MARK, P1MSEL14_1, PL3_FN),
  577. PINMUX_DATA(IRL6_MARK, P1MSEL14_0, PL2_FN),
  578. PINMUX_DATA(FD6_MARK, P1MSEL14_1, PL2_FN),
  579. PINMUX_DATA(IRL7_MARK, P1MSEL14_0, PL1_FN),
  580. PINMUX_DATA(FD7_MARK, P1MSEL14_1, PL1_FN),
  581. PINMUX_DATA(DRAK3_MARK, P1MSEL10_0, PL0_FN),
  582. PINMUX_DATA(CE2B_MARK, P1MSEL10_1, PL0_FN),
  583. /* PM FN */
  584. PINMUX_DATA(BREQ_BSACK_MARK, PM1_FN),
  585. PINMUX_DATA(BACK_BSREQ_MARK, PM0_FN),
  586. /* PN FN */
  587. PINMUX_DATA(SCIF5_RXD_MARK, P1MSEL2_0, P1MSEL1_0, PN7_FN),
  588. PINMUX_DATA(HAC1_SDIN_MARK, P1MSEL2_0, P1MSEL1_1, PN7_FN),
  589. PINMUX_DATA(SSI1_SCK_MARK, P1MSEL2_1, P1MSEL1_0, PN7_FN),
  590. PINMUX_DATA(SCIF5_SCK_MARK, P1MSEL2_0, P1MSEL1_0, PN6_FN),
  591. PINMUX_DATA(HAC1_SDOUT_MARK, P1MSEL2_0, P1MSEL1_1, PN6_FN),
  592. PINMUX_DATA(SSI1_SDATA_MARK, P1MSEL2_1, P1MSEL1_0, PN6_FN),
  593. PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL0_0, PN5_FN),
  594. PINMUX_DATA(FCLE_MARK, P1MSEL0_1, PN5_FN),
  595. PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL0_0, PN4_FN),
  596. PINMUX_DATA(FALE_MARK, P1MSEL0_1, PN4_FN),
  597. PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL0_0, PN3_FN),
  598. PINMUX_DATA(FD0_MARK, P1MSEL0_1, PN3_FN),
  599. PINMUX_DATA(SCIF4_TXD_MARK, P1MSEL0_0, PN2_FN),
  600. PINMUX_DATA(FD1_MARK, P1MSEL0_1, PN2_FN),
  601. PINMUX_DATA(SCIF4_RXD_MARK, P1MSEL0_0, PN1_FN),
  602. PINMUX_DATA(FD2_MARK, P1MSEL0_1, PN1_FN),
  603. PINMUX_DATA(SCIF4_SCK_MARK, P1MSEL0_0, PN0_FN),
  604. PINMUX_DATA(FD3_MARK, P1MSEL0_1, PN0_FN),
  605. /* PP FN */
  606. PINMUX_DATA(DEVSEL_DCLKOUT_MARK, PP5_FN),
  607. PINMUX_DATA(STOP_CDE_MARK, PP4_FN),
  608. PINMUX_DATA(LOCK_ODDF_MARK, PP3_FN),
  609. PINMUX_DATA(TRDY_DISPL_MARK, PP2_FN),
  610. PINMUX_DATA(IRDY_HSYNC_MARK, PP1_FN),
  611. PINMUX_DATA(PCIFRAME_VSYNC_MARK, PP0_FN),
  612. /* PQ FN */
  613. PINMUX_DATA(INTA_MARK, PQ4_FN),
  614. PINMUX_DATA(GNT0_GNTIN_MARK, PQ3_FN),
  615. PINMUX_DATA(REQ0_REQOUT_MARK, PQ2_FN),
  616. PINMUX_DATA(PERR_MARK, PQ1_FN),
  617. PINMUX_DATA(SERR_MARK, PQ0_FN),
  618. /* PR FN */
  619. PINMUX_DATA(WE7_CBE3_MARK, PR3_FN),
  620. PINMUX_DATA(WE6_CBE2_MARK, PR2_FN),
  621. PINMUX_DATA(WE5_CBE1_MARK, PR1_FN),
  622. PINMUX_DATA(WE4_CBE0_MARK, PR0_FN),
  623. /* MISC FN */
  624. PINMUX_DATA(SCIF2_RXD_MARK, P1MSEL6_0, P1MSEL5_0),
  625. PINMUX_DATA(SIOF_RXD_MARK, P2MSEL1_1, P1MSEL6_1, P1MSEL5_0),
  626. PINMUX_DATA(MRESETOUT_MARK, P2MSEL2_0),
  627. PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
  628. };
  629. static const struct sh_pfc_pin pinmux_pins[] = {
  630. /* PA */
  631. PINMUX_GPIO(PA7),
  632. PINMUX_GPIO(PA6),
  633. PINMUX_GPIO(PA5),
  634. PINMUX_GPIO(PA4),
  635. PINMUX_GPIO(PA3),
  636. PINMUX_GPIO(PA2),
  637. PINMUX_GPIO(PA1),
  638. PINMUX_GPIO(PA0),
  639. /* PB */
  640. PINMUX_GPIO(PB7),
  641. PINMUX_GPIO(PB6),
  642. PINMUX_GPIO(PB5),
  643. PINMUX_GPIO(PB4),
  644. PINMUX_GPIO(PB3),
  645. PINMUX_GPIO(PB2),
  646. PINMUX_GPIO(PB1),
  647. PINMUX_GPIO(PB0),
  648. /* PC */
  649. PINMUX_GPIO(PC7),
  650. PINMUX_GPIO(PC6),
  651. PINMUX_GPIO(PC5),
  652. PINMUX_GPIO(PC4),
  653. PINMUX_GPIO(PC3),
  654. PINMUX_GPIO(PC2),
  655. PINMUX_GPIO(PC1),
  656. PINMUX_GPIO(PC0),
  657. /* PD */
  658. PINMUX_GPIO(PD7),
  659. PINMUX_GPIO(PD6),
  660. PINMUX_GPIO(PD5),
  661. PINMUX_GPIO(PD4),
  662. PINMUX_GPIO(PD3),
  663. PINMUX_GPIO(PD2),
  664. PINMUX_GPIO(PD1),
  665. PINMUX_GPIO(PD0),
  666. /* PE */
  667. PINMUX_GPIO(PE5),
  668. PINMUX_GPIO(PE4),
  669. PINMUX_GPIO(PE3),
  670. PINMUX_GPIO(PE2),
  671. PINMUX_GPIO(PE1),
  672. PINMUX_GPIO(PE0),
  673. /* PF */
  674. PINMUX_GPIO(PF7),
  675. PINMUX_GPIO(PF6),
  676. PINMUX_GPIO(PF5),
  677. PINMUX_GPIO(PF4),
  678. PINMUX_GPIO(PF3),
  679. PINMUX_GPIO(PF2),
  680. PINMUX_GPIO(PF1),
  681. PINMUX_GPIO(PF0),
  682. /* PG */
  683. PINMUX_GPIO(PG7),
  684. PINMUX_GPIO(PG6),
  685. PINMUX_GPIO(PG5),
  686. PINMUX_GPIO(PG4),
  687. PINMUX_GPIO(PG3),
  688. PINMUX_GPIO(PG2),
  689. PINMUX_GPIO(PG1),
  690. PINMUX_GPIO(PG0),
  691. /* PH */
  692. PINMUX_GPIO(PH7),
  693. PINMUX_GPIO(PH6),
  694. PINMUX_GPIO(PH5),
  695. PINMUX_GPIO(PH4),
  696. PINMUX_GPIO(PH3),
  697. PINMUX_GPIO(PH2),
  698. PINMUX_GPIO(PH1),
  699. PINMUX_GPIO(PH0),
  700. /* PJ */
  701. PINMUX_GPIO(PJ7),
  702. PINMUX_GPIO(PJ6),
  703. PINMUX_GPIO(PJ5),
  704. PINMUX_GPIO(PJ4),
  705. PINMUX_GPIO(PJ3),
  706. PINMUX_GPIO(PJ2),
  707. PINMUX_GPIO(PJ1),
  708. PINMUX_GPIO(PJ0),
  709. /* PK */
  710. PINMUX_GPIO(PK7),
  711. PINMUX_GPIO(PK6),
  712. PINMUX_GPIO(PK5),
  713. PINMUX_GPIO(PK4),
  714. PINMUX_GPIO(PK3),
  715. PINMUX_GPIO(PK2),
  716. PINMUX_GPIO(PK1),
  717. PINMUX_GPIO(PK0),
  718. /* PL */
  719. PINMUX_GPIO(PL7),
  720. PINMUX_GPIO(PL6),
  721. PINMUX_GPIO(PL5),
  722. PINMUX_GPIO(PL4),
  723. PINMUX_GPIO(PL3),
  724. PINMUX_GPIO(PL2),
  725. PINMUX_GPIO(PL1),
  726. PINMUX_GPIO(PL0),
  727. /* PM */
  728. PINMUX_GPIO(PM1),
  729. PINMUX_GPIO(PM0),
  730. /* PN */
  731. PINMUX_GPIO(PN7),
  732. PINMUX_GPIO(PN6),
  733. PINMUX_GPIO(PN5),
  734. PINMUX_GPIO(PN4),
  735. PINMUX_GPIO(PN3),
  736. PINMUX_GPIO(PN2),
  737. PINMUX_GPIO(PN1),
  738. PINMUX_GPIO(PN0),
  739. /* PP */
  740. PINMUX_GPIO(PP5),
  741. PINMUX_GPIO(PP4),
  742. PINMUX_GPIO(PP3),
  743. PINMUX_GPIO(PP2),
  744. PINMUX_GPIO(PP1),
  745. PINMUX_GPIO(PP0),
  746. /* PQ */
  747. PINMUX_GPIO(PQ4),
  748. PINMUX_GPIO(PQ3),
  749. PINMUX_GPIO(PQ2),
  750. PINMUX_GPIO(PQ1),
  751. PINMUX_GPIO(PQ0),
  752. /* PR */
  753. PINMUX_GPIO(PR3),
  754. PINMUX_GPIO(PR2),
  755. PINMUX_GPIO(PR1),
  756. PINMUX_GPIO(PR0),
  757. };
  758. #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
  759. static const struct pinmux_func pinmux_func_gpios[] = {
  760. /* FN */
  761. GPIO_FN(D63_AD31),
  762. GPIO_FN(D62_AD30),
  763. GPIO_FN(D61_AD29),
  764. GPIO_FN(D60_AD28),
  765. GPIO_FN(D59_AD27),
  766. GPIO_FN(D58_AD26),
  767. GPIO_FN(D57_AD25),
  768. GPIO_FN(D56_AD24),
  769. GPIO_FN(D55_AD23),
  770. GPIO_FN(D54_AD22),
  771. GPIO_FN(D53_AD21),
  772. GPIO_FN(D52_AD20),
  773. GPIO_FN(D51_AD19),
  774. GPIO_FN(D50_AD18),
  775. GPIO_FN(D49_AD17_DB5),
  776. GPIO_FN(D48_AD16_DB4),
  777. GPIO_FN(D47_AD15_DB3),
  778. GPIO_FN(D46_AD14_DB2),
  779. GPIO_FN(D45_AD13_DB1),
  780. GPIO_FN(D44_AD12_DB0),
  781. GPIO_FN(D43_AD11_DG5),
  782. GPIO_FN(D42_AD10_DG4),
  783. GPIO_FN(D41_AD9_DG3),
  784. GPIO_FN(D40_AD8_DG2),
  785. GPIO_FN(D39_AD7_DG1),
  786. GPIO_FN(D38_AD6_DG0),
  787. GPIO_FN(D37_AD5_DR5),
  788. GPIO_FN(D36_AD4_DR4),
  789. GPIO_FN(D35_AD3_DR3),
  790. GPIO_FN(D34_AD2_DR2),
  791. GPIO_FN(D33_AD1_DR1),
  792. GPIO_FN(D32_AD0_DR0),
  793. GPIO_FN(REQ1),
  794. GPIO_FN(REQ2),
  795. GPIO_FN(REQ3),
  796. GPIO_FN(GNT1),
  797. GPIO_FN(GNT2),
  798. GPIO_FN(GNT3),
  799. GPIO_FN(MMCCLK),
  800. GPIO_FN(D31),
  801. GPIO_FN(D30),
  802. GPIO_FN(D29),
  803. GPIO_FN(D28),
  804. GPIO_FN(D27),
  805. GPIO_FN(D26),
  806. GPIO_FN(D25),
  807. GPIO_FN(D24),
  808. GPIO_FN(D23),
  809. GPIO_FN(D22),
  810. GPIO_FN(D21),
  811. GPIO_FN(D20),
  812. GPIO_FN(D19),
  813. GPIO_FN(D18),
  814. GPIO_FN(D17),
  815. GPIO_FN(D16),
  816. GPIO_FN(SCIF1_SCK),
  817. GPIO_FN(SCIF1_RXD),
  818. GPIO_FN(SCIF1_TXD),
  819. GPIO_FN(SCIF0_CTS),
  820. GPIO_FN(INTD),
  821. GPIO_FN(FCE),
  822. GPIO_FN(SCIF0_RTS),
  823. GPIO_FN(HSPI_CS),
  824. GPIO_FN(FSE),
  825. GPIO_FN(SCIF0_SCK),
  826. GPIO_FN(HSPI_CLK),
  827. GPIO_FN(FRE),
  828. GPIO_FN(SCIF0_RXD),
  829. GPIO_FN(HSPI_RX),
  830. GPIO_FN(FRB),
  831. GPIO_FN(SCIF0_TXD),
  832. GPIO_FN(HSPI_TX),
  833. GPIO_FN(FWE),
  834. GPIO_FN(SCIF5_TXD),
  835. GPIO_FN(HAC1_SYNC),
  836. GPIO_FN(SSI1_WS),
  837. GPIO_FN(SIOF_TXD_PJ),
  838. GPIO_FN(HAC0_SDOUT),
  839. GPIO_FN(SSI0_SDATA),
  840. GPIO_FN(SIOF_RXD_PJ),
  841. GPIO_FN(HAC0_SDIN),
  842. GPIO_FN(SSI0_SCK),
  843. GPIO_FN(SIOF_SYNC_PJ),
  844. GPIO_FN(HAC0_SYNC),
  845. GPIO_FN(SSI0_WS),
  846. GPIO_FN(SIOF_MCLK_PJ),
  847. GPIO_FN(HAC_RES),
  848. GPIO_FN(SIOF_SCK_PJ),
  849. GPIO_FN(HAC0_BITCLK),
  850. GPIO_FN(SSI0_CLK),
  851. GPIO_FN(HAC1_BITCLK),
  852. GPIO_FN(SSI1_CLK),
  853. GPIO_FN(TCLK),
  854. GPIO_FN(IOIS16),
  855. GPIO_FN(STATUS0),
  856. GPIO_FN(DRAK0_PK3),
  857. GPIO_FN(STATUS1),
  858. GPIO_FN(DRAK1_PK2),
  859. GPIO_FN(DACK2),
  860. GPIO_FN(SCIF2_TXD),
  861. GPIO_FN(MMCCMD),
  862. GPIO_FN(SIOF_TXD_PK),
  863. GPIO_FN(DACK3),
  864. GPIO_FN(SCIF2_SCK),
  865. GPIO_FN(MMCDAT),
  866. GPIO_FN(SIOF_SCK_PK),
  867. GPIO_FN(DREQ0),
  868. GPIO_FN(DREQ1),
  869. GPIO_FN(DRAK0_PK1),
  870. GPIO_FN(DRAK1_PK0),
  871. GPIO_FN(DREQ2),
  872. GPIO_FN(INTB),
  873. GPIO_FN(DREQ3),
  874. GPIO_FN(INTC),
  875. GPIO_FN(DRAK2),
  876. GPIO_FN(CE2A),
  877. GPIO_FN(IRL4),
  878. GPIO_FN(FD4),
  879. GPIO_FN(IRL5),
  880. GPIO_FN(FD5),
  881. GPIO_FN(IRL6),
  882. GPIO_FN(FD6),
  883. GPIO_FN(IRL7),
  884. GPIO_FN(FD7),
  885. GPIO_FN(DRAK3),
  886. GPIO_FN(CE2B),
  887. GPIO_FN(BREQ_BSACK),
  888. GPIO_FN(BACK_BSREQ),
  889. GPIO_FN(SCIF5_RXD),
  890. GPIO_FN(HAC1_SDIN),
  891. GPIO_FN(SSI1_SCK),
  892. GPIO_FN(SCIF5_SCK),
  893. GPIO_FN(HAC1_SDOUT),
  894. GPIO_FN(SSI1_SDATA),
  895. GPIO_FN(SCIF3_TXD),
  896. GPIO_FN(FCLE),
  897. GPIO_FN(SCIF3_RXD),
  898. GPIO_FN(FALE),
  899. GPIO_FN(SCIF3_SCK),
  900. GPIO_FN(FD0),
  901. GPIO_FN(SCIF4_TXD),
  902. GPIO_FN(FD1),
  903. GPIO_FN(SCIF4_RXD),
  904. GPIO_FN(FD2),
  905. GPIO_FN(SCIF4_SCK),
  906. GPIO_FN(FD3),
  907. GPIO_FN(DEVSEL_DCLKOUT),
  908. GPIO_FN(STOP_CDE),
  909. GPIO_FN(LOCK_ODDF),
  910. GPIO_FN(TRDY_DISPL),
  911. GPIO_FN(IRDY_HSYNC),
  912. GPIO_FN(PCIFRAME_VSYNC),
  913. GPIO_FN(INTA),
  914. GPIO_FN(GNT0_GNTIN),
  915. GPIO_FN(REQ0_REQOUT),
  916. GPIO_FN(PERR),
  917. GPIO_FN(SERR),
  918. GPIO_FN(WE7_CBE3),
  919. GPIO_FN(WE6_CBE2),
  920. GPIO_FN(WE5_CBE1),
  921. GPIO_FN(WE4_CBE0),
  922. GPIO_FN(SCIF2_RXD),
  923. GPIO_FN(SIOF_RXD),
  924. GPIO_FN(MRESETOUT),
  925. GPIO_FN(IRQOUT),
  926. };
  927. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  928. { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2, GROUP(
  929. PA7_FN, PA7_OUT, PA7_IN, 0,
  930. PA6_FN, PA6_OUT, PA6_IN, 0,
  931. PA5_FN, PA5_OUT, PA5_IN, 0,
  932. PA4_FN, PA4_OUT, PA4_IN, 0,
  933. PA3_FN, PA3_OUT, PA3_IN, 0,
  934. PA2_FN, PA2_OUT, PA2_IN, 0,
  935. PA1_FN, PA1_OUT, PA1_IN, 0,
  936. PA0_FN, PA0_OUT, PA0_IN, 0 ))
  937. },
  938. { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2, GROUP(
  939. PB7_FN, PB7_OUT, PB7_IN, 0,
  940. PB6_FN, PB6_OUT, PB6_IN, 0,
  941. PB5_FN, PB5_OUT, PB5_IN, 0,
  942. PB4_FN, PB4_OUT, PB4_IN, 0,
  943. PB3_FN, PB3_OUT, PB3_IN, 0,
  944. PB2_FN, PB2_OUT, PB2_IN, 0,
  945. PB1_FN, PB1_OUT, PB1_IN, 0,
  946. PB0_FN, PB0_OUT, PB0_IN, 0 ))
  947. },
  948. { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2, GROUP(
  949. PC7_FN, PC7_OUT, PC7_IN, 0,
  950. PC6_FN, PC6_OUT, PC6_IN, 0,
  951. PC5_FN, PC5_OUT, PC5_IN, 0,
  952. PC4_FN, PC4_OUT, PC4_IN, 0,
  953. PC3_FN, PC3_OUT, PC3_IN, 0,
  954. PC2_FN, PC2_OUT, PC2_IN, 0,
  955. PC1_FN, PC1_OUT, PC1_IN, 0,
  956. PC0_FN, PC0_OUT, PC0_IN, 0 ))
  957. },
  958. { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2, GROUP(
  959. PD7_FN, PD7_OUT, PD7_IN, 0,
  960. PD6_FN, PD6_OUT, PD6_IN, 0,
  961. PD5_FN, PD5_OUT, PD5_IN, 0,
  962. PD4_FN, PD4_OUT, PD4_IN, 0,
  963. PD3_FN, PD3_OUT, PD3_IN, 0,
  964. PD2_FN, PD2_OUT, PD2_IN, 0,
  965. PD1_FN, PD1_OUT, PD1_IN, 0,
  966. PD0_FN, PD0_OUT, PD0_IN, 0 ))
  967. },
  968. { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2, GROUP(
  969. 0, 0, 0, 0,
  970. 0, 0, 0, 0,
  971. PE5_FN, PE5_OUT, PE5_IN, 0,
  972. PE4_FN, PE4_OUT, PE4_IN, 0,
  973. PE3_FN, PE3_OUT, PE3_IN, 0,
  974. PE2_FN, PE2_OUT, PE2_IN, 0,
  975. PE1_FN, PE1_OUT, PE1_IN, 0,
  976. PE0_FN, PE0_OUT, PE0_IN, 0 ))
  977. },
  978. { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2, GROUP(
  979. PF7_FN, PF7_OUT, PF7_IN, 0,
  980. PF6_FN, PF6_OUT, PF6_IN, 0,
  981. PF5_FN, PF5_OUT, PF5_IN, 0,
  982. PF4_FN, PF4_OUT, PF4_IN, 0,
  983. PF3_FN, PF3_OUT, PF3_IN, 0,
  984. PF2_FN, PF2_OUT, PF2_IN, 0,
  985. PF1_FN, PF1_OUT, PF1_IN, 0,
  986. PF0_FN, PF0_OUT, PF0_IN, 0 ))
  987. },
  988. { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2, GROUP(
  989. PG7_FN, PG7_OUT, PG7_IN, 0,
  990. PG6_FN, PG6_OUT, PG6_IN, 0,
  991. PG5_FN, PG5_OUT, PG5_IN, 0,
  992. PG4_FN, PG4_OUT, PG4_IN, 0,
  993. PG3_FN, PG3_OUT, PG3_IN, 0,
  994. PG2_FN, PG2_OUT, PG2_IN, 0,
  995. PG1_FN, PG1_OUT, PG1_IN, 0,
  996. PG0_FN, PG0_OUT, PG0_IN, 0 ))
  997. },
  998. { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2, GROUP(
  999. PH7_FN, PH7_OUT, PH7_IN, 0,
  1000. PH6_FN, PH6_OUT, PH6_IN, 0,
  1001. PH5_FN, PH5_OUT, PH5_IN, 0,
  1002. PH4_FN, PH4_OUT, PH4_IN, 0,
  1003. PH3_FN, PH3_OUT, PH3_IN, 0,
  1004. PH2_FN, PH2_OUT, PH2_IN, 0,
  1005. PH1_FN, PH1_OUT, PH1_IN, 0,
  1006. PH0_FN, PH0_OUT, PH0_IN, 0 ))
  1007. },
  1008. { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2, GROUP(
  1009. PJ7_FN, PJ7_OUT, PJ7_IN, 0,
  1010. PJ6_FN, PJ6_OUT, PJ6_IN, 0,
  1011. PJ5_FN, PJ5_OUT, PJ5_IN, 0,
  1012. PJ4_FN, PJ4_OUT, PJ4_IN, 0,
  1013. PJ3_FN, PJ3_OUT, PJ3_IN, 0,
  1014. PJ2_FN, PJ2_OUT, PJ2_IN, 0,
  1015. PJ1_FN, PJ1_OUT, PJ1_IN, 0,
  1016. PJ0_FN, PJ0_OUT, PJ0_IN, 0 ))
  1017. },
  1018. { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2, GROUP(
  1019. PK7_FN, PK7_OUT, PK7_IN, 0,
  1020. PK6_FN, PK6_OUT, PK6_IN, 0,
  1021. PK5_FN, PK5_OUT, PK5_IN, 0,
  1022. PK4_FN, PK4_OUT, PK4_IN, 0,
  1023. PK3_FN, PK3_OUT, PK3_IN, 0,
  1024. PK2_FN, PK2_OUT, PK2_IN, 0,
  1025. PK1_FN, PK1_OUT, PK1_IN, 0,
  1026. PK0_FN, PK0_OUT, PK0_IN, 0 ))
  1027. },
  1028. { PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2, GROUP(
  1029. PL7_FN, PL7_OUT, PL7_IN, 0,
  1030. PL6_FN, PL6_OUT, PL6_IN, 0,
  1031. PL5_FN, PL5_OUT, PL5_IN, 0,
  1032. PL4_FN, PL4_OUT, PL4_IN, 0,
  1033. PL3_FN, PL3_OUT, PL3_IN, 0,
  1034. PL2_FN, PL2_OUT, PL2_IN, 0,
  1035. PL1_FN, PL1_OUT, PL1_IN, 0,
  1036. PL0_FN, PL0_OUT, PL0_IN, 0 ))
  1037. },
  1038. { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2, GROUP(
  1039. 0, 0, 0, 0,
  1040. 0, 0, 0, 0,
  1041. 0, 0, 0, 0,
  1042. 0, 0, 0, 0,
  1043. 0, 0, 0, 0,
  1044. 0, 0, 0, 0,
  1045. PM1_FN, PM1_OUT, PM1_IN, 0,
  1046. PM0_FN, PM0_OUT, PM0_IN, 0 ))
  1047. },
  1048. { PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2, GROUP(
  1049. PN7_FN, PN7_OUT, PN7_IN, 0,
  1050. PN6_FN, PN6_OUT, PN6_IN, 0,
  1051. PN5_FN, PN5_OUT, PN5_IN, 0,
  1052. PN4_FN, PN4_OUT, PN4_IN, 0,
  1053. PN3_FN, PN3_OUT, PN3_IN, 0,
  1054. PN2_FN, PN2_OUT, PN2_IN, 0,
  1055. PN1_FN, PN1_OUT, PN1_IN, 0,
  1056. PN0_FN, PN0_OUT, PN0_IN, 0 ))
  1057. },
  1058. { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2, GROUP(
  1059. 0, 0, 0, 0,
  1060. 0, 0, 0, 0,
  1061. PP5_FN, PP5_OUT, PP5_IN, 0,
  1062. PP4_FN, PP4_OUT, PP4_IN, 0,
  1063. PP3_FN, PP3_OUT, PP3_IN, 0,
  1064. PP2_FN, PP2_OUT, PP2_IN, 0,
  1065. PP1_FN, PP1_OUT, PP1_IN, 0,
  1066. PP0_FN, PP0_OUT, PP0_IN, 0 ))
  1067. },
  1068. { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2, GROUP(
  1069. 0, 0, 0, 0,
  1070. 0, 0, 0, 0,
  1071. 0, 0, 0, 0,
  1072. PQ4_FN, PQ4_OUT, PQ4_IN, 0,
  1073. PQ3_FN, PQ3_OUT, PQ3_IN, 0,
  1074. PQ2_FN, PQ2_OUT, PQ2_IN, 0,
  1075. PQ1_FN, PQ1_OUT, PQ1_IN, 0,
  1076. PQ0_FN, PQ0_OUT, PQ0_IN, 0 ))
  1077. },
  1078. { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2, GROUP(
  1079. 0, 0, 0, 0,
  1080. 0, 0, 0, 0,
  1081. 0, 0, 0, 0,
  1082. 0, 0, 0, 0,
  1083. PR3_FN, PR3_OUT, PR3_IN, 0,
  1084. PR2_FN, PR2_OUT, PR2_IN, 0,
  1085. PR1_FN, PR1_OUT, PR1_IN, 0,
  1086. PR0_FN, PR0_OUT, PR0_IN, 0 ))
  1087. },
  1088. { PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1, GROUP(
  1089. P1MSEL15_0, P1MSEL15_1,
  1090. P1MSEL14_0, P1MSEL14_1,
  1091. P1MSEL13_0, P1MSEL13_1,
  1092. P1MSEL12_0, P1MSEL12_1,
  1093. P1MSEL11_0, P1MSEL11_1,
  1094. P1MSEL10_0, P1MSEL10_1,
  1095. P1MSEL9_0, P1MSEL9_1,
  1096. P1MSEL8_0, P1MSEL8_1,
  1097. P1MSEL7_0, P1MSEL7_1,
  1098. P1MSEL6_0, P1MSEL6_1,
  1099. P1MSEL5_0, 0,
  1100. P1MSEL4_0, P1MSEL4_1,
  1101. P1MSEL3_0, P1MSEL3_1,
  1102. P1MSEL2_0, P1MSEL2_1,
  1103. P1MSEL1_0, P1MSEL1_1,
  1104. P1MSEL0_0, P1MSEL0_1 ))
  1105. },
  1106. { PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1, GROUP(
  1107. 0, 0,
  1108. 0, 0,
  1109. 0, 0,
  1110. 0, 0,
  1111. 0, 0,
  1112. 0, 0,
  1113. 0, 0,
  1114. 0, 0,
  1115. 0, 0,
  1116. 0, 0,
  1117. 0, 0,
  1118. 0, 0,
  1119. 0, 0,
  1120. P2MSEL2_0, P2MSEL2_1,
  1121. P2MSEL1_0, P2MSEL1_1,
  1122. P2MSEL0_0, P2MSEL0_1 ))
  1123. },
  1124. {}
  1125. };
  1126. static const struct pinmux_data_reg pinmux_data_regs[] = {
  1127. { PINMUX_DATA_REG("PADR", 0xffe70020, 8, GROUP(
  1128. PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
  1129. PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
  1130. },
  1131. { PINMUX_DATA_REG("PBDR", 0xffe70022, 8, GROUP(
  1132. PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
  1133. PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
  1134. },
  1135. { PINMUX_DATA_REG("PCDR", 0xffe70024, 8, GROUP(
  1136. PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
  1137. PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
  1138. },
  1139. { PINMUX_DATA_REG("PDDR", 0xffe70026, 8, GROUP(
  1140. PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
  1141. PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
  1142. },
  1143. { PINMUX_DATA_REG("PEDR", 0xffe70028, 8, GROUP(
  1144. 0, 0, PE5_DATA, PE4_DATA,
  1145. PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
  1146. },
  1147. { PINMUX_DATA_REG("PFDR", 0xffe7002a, 8, GROUP(
  1148. PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
  1149. PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
  1150. },
  1151. { PINMUX_DATA_REG("PGDR", 0xffe7002c, 8, GROUP(
  1152. PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
  1153. PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
  1154. },
  1155. { PINMUX_DATA_REG("PHDR", 0xffe7002e, 8, GROUP(
  1156. PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
  1157. PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
  1158. },
  1159. { PINMUX_DATA_REG("PJDR", 0xffe70030, 8, GROUP(
  1160. PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
  1161. PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
  1162. },
  1163. { PINMUX_DATA_REG("PKDR", 0xffe70032, 8, GROUP(
  1164. PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
  1165. PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
  1166. },
  1167. { PINMUX_DATA_REG("PLDR", 0xffe70034, 8, GROUP(
  1168. PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA,
  1169. PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA ))
  1170. },
  1171. { PINMUX_DATA_REG("PMDR", 0xffe70036, 8, GROUP(
  1172. 0, 0, 0, 0,
  1173. 0, 0, PM1_DATA, PM0_DATA ))
  1174. },
  1175. { PINMUX_DATA_REG("PNDR", 0xffe70038, 8, GROUP(
  1176. PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA,
  1177. PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA ))
  1178. },
  1179. { PINMUX_DATA_REG("PPDR", 0xffe7003a, 8, GROUP(
  1180. 0, 0, PP5_DATA, PP4_DATA,
  1181. PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA ))
  1182. },
  1183. { PINMUX_DATA_REG("PQDR", 0xffe7003c, 8, GROUP(
  1184. 0, 0, 0, PQ4_DATA,
  1185. PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA ))
  1186. },
  1187. { PINMUX_DATA_REG("PRDR", 0xffe7003e, 8, GROUP(
  1188. 0, 0, 0, 0,
  1189. PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA ))
  1190. },
  1191. { },
  1192. };
  1193. const struct sh_pfc_soc_info sh7785_pinmux_info = {
  1194. .name = "sh7785_pfc",
  1195. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  1196. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  1197. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  1198. .pins = pinmux_pins,
  1199. .nr_pins = ARRAY_SIZE(pinmux_pins),
  1200. .func_gpios = pinmux_func_gpios,
  1201. .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
  1202. .cfg_regs = pinmux_config_regs,
  1203. .data_regs = pinmux_data_regs,
  1204. .pinmux_data = pinmux_data,
  1205. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  1206. };