pfc-sh7734.c 86 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SH7734 processor support - PFC hardware block
  4. *
  5. * Copyright (C) 2012 Renesas Solutions Corp.
  6. * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  7. */
  8. #include <linux/init.h>
  9. #include <linux/kernel.h>
  10. #include <cpu/sh7734.h>
  11. #include "sh_pfc.h"
  12. #define CPU_ALL_GP(fn, sfx) \
  13. PORT_GP_32(0, fn, sfx), \
  14. PORT_GP_32(1, fn, sfx), \
  15. PORT_GP_32(2, fn, sfx), \
  16. PORT_GP_32(3, fn, sfx), \
  17. PORT_GP_32(4, fn, sfx), \
  18. PORT_GP_12(5, fn, sfx)
  19. #undef _GP_DATA
  20. #define _GP_DATA(bank, pin, name, sfx, cfg) \
  21. PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
  22. #define _GP_INOUTSEL(bank, pin, name, sfx, cfg) name##_IN, name##_OUT
  23. #define _GP_INDT(bank, pin, name, sfx, cfg) name##_DATA
  24. #define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
  25. #define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
  26. enum {
  27. PINMUX_RESERVED = 0,
  28. PINMUX_DATA_BEGIN,
  29. GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
  30. PINMUX_DATA_END,
  31. PINMUX_INPUT_BEGIN,
  32. GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
  33. PINMUX_INPUT_END,
  34. PINMUX_OUTPUT_BEGIN,
  35. GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
  36. PINMUX_OUTPUT_END,
  37. PINMUX_FUNCTION_BEGIN,
  38. GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
  39. /* GPSR0 */
  40. FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
  41. FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
  42. FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
  43. FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
  44. FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
  45. FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
  46. FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
  47. FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
  48. /* GPSR1 */
  49. FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
  50. FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
  51. FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
  52. FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
  53. FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
  54. FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
  55. FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
  56. FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
  57. /* GPSR2 */
  58. FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
  59. FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
  60. FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
  61. FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
  62. FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  63. FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
  64. FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
  65. FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
  66. /* GPSR3 */
  67. FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
  68. FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
  69. FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
  70. FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
  71. FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
  72. FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  73. FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
  74. FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
  75. /* GPSR4 */
  76. FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
  77. FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
  78. FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
  79. FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
  80. FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
  81. FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
  82. FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
  83. FN_USB_OVC0, FN_IP11_18_16,
  84. FN_IP10_22, FN_IP10_24_23,
  85. /* GPSR5 */
  86. FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
  87. FN_IP10_27_26, /* 10 */
  88. FN_IP10_29_28, /* 11 */
  89. /* IPSR0 */
  90. FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
  91. FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
  92. FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
  93. FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
  94. FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
  95. FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
  96. FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
  97. FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
  98. FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
  99. FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
  100. FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
  101. FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
  102. FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
  103. FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
  104. FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
  105. FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
  106. /* IPSR1 */
  107. FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
  108. FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
  109. FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
  110. FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
  111. FN_A25, FN_TX2_D, FN_ST1_D2,
  112. FN_A24, FN_RX2_D, FN_ST1_D1,
  113. FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
  114. FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
  115. FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
  116. FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
  117. FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
  118. FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
  119. FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
  120. FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
  121. /* IPSR2 */
  122. FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
  123. FN_D13, FN_RX2_B, FN_FRB_A, FN_ET0_ETXD6_B,
  124. FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
  125. FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
  126. FN_ET0_ETXD3_B,
  127. FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
  128. FN_ET0_ETXD2_B,
  129. FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
  130. FN_ET0_ETXD1_B,
  131. FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
  132. FN_ET0_GTX_CLK_B,
  133. FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
  134. FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
  135. FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
  136. FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
  137. /* IPSR3 */
  138. FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
  139. FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
  140. FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
  141. FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
  142. FN_ET0_LINK_C, FN_ET0_ETXD5_A,
  143. FN_EX_WAIT0, FN_TCLK1_B,
  144. FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
  145. FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
  146. FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
  147. FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
  148. FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
  149. FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
  150. FN_CS1_A26, FN_QIO3_B,
  151. FN_D15, FN_SCK2_B,
  152. /* IPSR4 */
  153. FN_SCK2_A, FN_VI0_G3,
  154. FN_RTS1_B, FN_VI0_G2,
  155. FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
  156. FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
  157. FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
  158. FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
  159. FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
  160. FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
  161. FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
  162. FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
  163. FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
  164. FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
  165. FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
  166. /* IPSR5 */
  167. FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
  168. FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
  169. FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
  170. FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
  171. FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
  172. FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
  173. FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
  174. FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
  175. FN_REF125CK, FN_ADTRG, FN_RX5_C,
  176. FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
  177. /* IPSR6 */
  178. FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
  179. FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
  180. FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
  181. FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
  182. FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
  183. FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
  184. FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
  185. FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
  186. FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
  187. FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
  188. /* IPSR7 */
  189. FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
  190. FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
  191. FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
  192. FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
  193. FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
  194. FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
  195. FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
  196. FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
  197. FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
  198. FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
  199. FN_DU0_DB4, FN_HIFINT,
  200. /* IPSR8 */
  201. FN_DU0_DB5, FN_HIFDREQ,
  202. FN_DU0_DB6, FN_HIFRDY,
  203. FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
  204. FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
  205. FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
  206. FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
  207. FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
  208. FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
  209. FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
  210. FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
  211. FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
  212. FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
  213. FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
  214. FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
  215. /* IPSR9 */
  216. FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
  217. FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
  218. FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
  219. FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
  220. FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
  221. FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
  222. FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
  223. FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
  224. FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
  225. FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
  226. FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
  227. FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
  228. FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
  229. FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
  230. FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
  231. /* IPSR10 */
  232. FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
  233. FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
  234. FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
  235. FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
  236. FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
  237. FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
  238. FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
  239. FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
  240. FN_CAN_CLK_A, FN_RX4_D,
  241. FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
  242. FN_CAN1_RX_A, FN_IRQ1_B,
  243. FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
  244. FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
  245. /* IPSR11 */
  246. FN_SCL1, FN_SCIF_CLK_C,
  247. FN_SDA1, FN_RX1_E,
  248. FN_SDA0, FN_HIFEBL_A,
  249. FN_SDSELF, FN_RTS1_E,
  250. FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
  251. FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
  252. FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
  253. FN_TX0_A, FN_HSPI_TX_A,
  254. FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
  255. FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
  256. FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
  257. FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
  258. FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
  259. FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
  260. FN_PRESETOUT, FN_ST_CLKOUT,
  261. /* MOD_SEL1 */
  262. FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
  263. FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
  264. FN_SEL_VIN1_0, FN_SEL_VIN1_1,
  265. FN_SEL_HIF_0, FN_SEL_HIF_1,
  266. FN_SEL_RSPI_0, FN_SEL_RSPI_1,
  267. FN_SEL_LCDC_0, FN_SEL_LCDC_1,
  268. FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
  269. FN_SEL_ET0_0, FN_SEL_ET0_1,
  270. FN_SEL_RMII_0, FN_SEL_RMII_1,
  271. FN_SEL_TMU_0, FN_SEL_TMU_1,
  272. FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
  273. FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
  274. FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
  275. FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
  276. FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
  277. FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
  278. FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
  279. FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
  280. FN_SEL_SSI1_0, FN_SEL_SSI1_1,
  281. FN_SEL_SSI0_0, FN_SEL_SSI0_1,
  282. FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
  283. FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
  284. FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
  285. FN_SEL_MMC_0, FN_SEL_MMC_1,
  286. FN_SEL_INTC_0, FN_SEL_INTC_1,
  287. /* MOD_SEL2 */
  288. FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
  289. FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
  290. FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
  291. FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
  292. FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
  293. FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
  294. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
  295. FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
  296. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
  297. FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  298. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
  299. FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
  300. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
  301. FN_SEL_SCIF2_3,
  302. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
  303. FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
  304. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
  305. FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
  306. PINMUX_FUNCTION_END,
  307. PINMUX_MARK_BEGIN,
  308. CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
  309. WE0_MARK, WE1_MARK,
  310. SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
  311. IRQ2_B_MARK, IRQ3_B_MARK,
  312. /* IPSR0 */
  313. A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
  314. A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
  315. A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
  316. A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
  317. A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
  318. A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
  319. A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
  320. A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
  321. A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
  322. A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
  323. A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
  324. A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
  325. A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
  326. A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
  327. A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
  328. A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
  329. /* IPSR1 */
  330. D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
  331. D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
  332. D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
  333. D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
  334. A25_MARK, TX2_D_MARK, ST1_D2_MARK,
  335. A24_MARK, RX2_D_MARK, ST1_D1_MARK,
  336. A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
  337. A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
  338. A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
  339. A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
  340. A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK, TIOC4D_C_MARK,
  341. A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
  342. A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
  343. A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
  344. /* IPSR2 */
  345. D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
  346. D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
  347. D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
  348. D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
  349. ET0_ETXD3_B_MARK,
  350. D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
  351. ET0_ETXD2_B_MARK,
  352. D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
  353. FCLE_A_MARK, ET0_ETXD1_B_MARK,
  354. D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
  355. FCE_A_MARK, ET0_GTX_CLK_B_MARK,
  356. D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
  357. FD7_A_MARK,
  358. D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
  359. FD6_A_MARK,
  360. D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
  361. D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
  362. FD4_A_MARK,
  363. /* IPSR3 */
  364. DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
  365. EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
  366. ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
  367. EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
  368. ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
  369. EX_WAIT0_MARK, TCLK1_B_MARK,
  370. RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
  371. EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
  372. ET0_ETXD3_A_MARK,
  373. EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
  374. ET0_ETXD2_A_MARK,
  375. EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
  376. ET0_ETXD1_A_MARK,
  377. EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
  378. ET0_GTX_CLK_A_MARK,
  379. EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
  380. ET0_ETXD0_MARK,
  381. CS1_A26_MARK, QIO3_B_MARK,
  382. D15_MARK, SCK2_B_MARK,
  383. /* IPSR4 */
  384. SCK2_A_MARK, VI0_G3_MARK,
  385. RTS1_B_MARK, VI0_G2_MARK,
  386. CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
  387. TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
  388. RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
  389. SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
  390. RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
  391. CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
  392. ET0_MDC_MARK,
  393. HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
  394. RMII0_MDC_A_MARK, ET0_COL_MARK,
  395. HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
  396. RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
  397. HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
  398. RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
  399. HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
  400. RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
  401. HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
  402. RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
  403. /* IPSR5 */
  404. SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
  405. SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
  406. SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
  407. SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
  408. SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
  409. SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
  410. SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
  411. SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
  412. REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
  413. REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
  414. /* IPSR6 */
  415. DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
  416. TCLKA_A_MARK, HIFD00_MARK,
  417. DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
  418. TCLKB_A_MARK, HIFD01_MARK,
  419. DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
  420. DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
  421. DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
  422. DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
  423. DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
  424. DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
  425. DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
  426. TIOC1A_A_MARK, HIFD08_MARK,
  427. DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
  428. HIFD09_MARK,
  429. /* IPSR7 */
  430. DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
  431. HIFD10_MARK,
  432. DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
  433. HIFD11_MARK,
  434. DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
  435. HIFD12_MARK,
  436. DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
  437. HIFD13_MARK,
  438. DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
  439. HIFD14_MARK,
  440. DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
  441. HIFD15_MARK,
  442. DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
  443. HIFCS_MARK,
  444. DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
  445. HIFRS_MARK,
  446. DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
  447. HIFWR_MARK,
  448. DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
  449. DU0_DB4_MARK, HIFINT_MARK,
  450. /* IPSR8 */
  451. DU0_DB5_MARK, HIFDREQ_MARK,
  452. DU0_DB6_MARK, HIFRDY_MARK,
  453. DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
  454. DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
  455. DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
  456. DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
  457. DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
  458. DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
  459. SSI_SDATA1_B_MARK,
  460. DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
  461. DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
  462. IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
  463. IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
  464. IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
  465. IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
  466. /* IPSR9 */
  467. VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
  468. VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
  469. VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
  470. VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
  471. VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
  472. VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
  473. VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
  474. VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
  475. VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
  476. SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
  477. SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
  478. SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
  479. SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
  480. SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
  481. SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
  482. /* IPSR10 */
  483. SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
  484. LCD_DATA15_B_MARK,
  485. SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
  486. FALE_B_MARK, LCD_DON_B_MARK,
  487. SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
  488. LCD_CL1_B_MARK,
  489. SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
  490. LCD_CL2_B_MARK,
  491. AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
  492. LCD_FLM_B_MARK,
  493. AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
  494. AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
  495. LCD_VEPWC_B_MARK,
  496. AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
  497. LCD_M_DISP_B_MARK,
  498. CAN_CLK_A_MARK, RX4_D_MARK,
  499. CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
  500. CAN1_RX_A_MARK, IRQ1_B_MARK,
  501. CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
  502. CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
  503. /* IPSR11 */
  504. SCL1_MARK, SCIF_CLK_C_MARK,
  505. SDA1_MARK, RX1_E_MARK,
  506. SDA0_MARK, HIFEBL_A_MARK,
  507. SDSELF_MARK, RTS1_E_MARK,
  508. SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
  509. ET0_ERXD4_MARK,
  510. SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
  511. ET0_ERXD5_MARK,
  512. RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
  513. TX0_A_MARK, HSPI_TX_A_MARK,
  514. PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
  515. IETX_B_MARK,
  516. USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
  517. IERX_B_MARK,
  518. DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
  519. DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
  520. DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
  521. ET0_TX_CLK_A_MARK,
  522. DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
  523. PRESETOUT_MARK, ST_CLKOUT_MARK,
  524. PINMUX_MARK_END,
  525. };
  526. static const u16 pinmux_data[] = {
  527. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  528. PINMUX_SINGLE(CLKOUT),
  529. PINMUX_SINGLE(BS),
  530. PINMUX_SINGLE(CS0),
  531. PINMUX_SINGLE(EX_CS0),
  532. PINMUX_SINGLE(RD),
  533. PINMUX_SINGLE(WE0),
  534. PINMUX_SINGLE(WE1),
  535. PINMUX_SINGLE(SCL0),
  536. PINMUX_SINGLE(PENC0),
  537. PINMUX_SINGLE(USB_OVC0),
  538. PINMUX_SINGLE(IRQ2_B),
  539. PINMUX_SINGLE(IRQ3_B),
  540. /* IPSR0 */
  541. PINMUX_IPSR_GPSR(IP0_1_0, A0),
  542. PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
  543. PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
  544. PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
  545. PINMUX_IPSR_GPSR(IP0_3_2, A1),
  546. PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
  547. PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
  548. PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
  549. PINMUX_IPSR_GPSR(IP0_5_4, A2),
  550. PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
  551. PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
  552. PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
  553. PINMUX_IPSR_GPSR(IP0_7_6, A3),
  554. PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
  555. PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
  556. PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
  557. PINMUX_IPSR_GPSR(IP0_9_8, A4),
  558. PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
  559. PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
  560. PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
  561. PINMUX_IPSR_GPSR(IP0_11_10, A5),
  562. PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
  563. PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
  564. PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
  565. PINMUX_IPSR_GPSR(IP0_13_12, A6),
  566. PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
  567. PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
  568. PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
  569. PINMUX_IPSR_GPSR(IP0_15_14, A7),
  570. PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
  571. PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
  572. PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
  573. PINMUX_IPSR_GPSR(IP0_17_16, A8),
  574. PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
  575. PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
  576. PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
  577. PINMUX_IPSR_GPSR(IP0_19_18, A9),
  578. PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
  579. PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
  580. PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
  581. PINMUX_IPSR_GPSR(IP0_21_20, A10),
  582. PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
  583. PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
  584. PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
  585. PINMUX_IPSR_GPSR(IP0_23_22, A11),
  586. PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
  587. PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
  588. PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
  589. PINMUX_IPSR_GPSR(IP0_25_24, A12),
  590. PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
  591. PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
  592. PINMUX_IPSR_GPSR(IP0_27_26, A13),
  593. PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
  594. PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
  595. PINMUX_IPSR_GPSR(IP0_29_28, A14),
  596. PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
  597. PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
  598. PINMUX_IPSR_GPSR(IP0_31_30, A15),
  599. PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
  600. PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
  601. PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
  602. /* IPSR1 */
  603. PINMUX_IPSR_GPSR(IP1_1_0, A16),
  604. PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
  605. PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
  606. PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
  607. PINMUX_IPSR_GPSR(IP1_3_2, A17),
  608. PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
  609. PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
  610. PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
  611. PINMUX_IPSR_GPSR(IP1_5_4, A18),
  612. PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
  613. PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
  614. PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
  615. PINMUX_IPSR_GPSR(IP1_7_6, A19),
  616. PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
  617. PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
  618. PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
  619. PINMUX_IPSR_GPSR(IP1_9_8, A20),
  620. PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
  621. PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
  622. PINMUX_IPSR_GPSR(IP1_11_10, A21),
  623. PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
  624. PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
  625. PINMUX_IPSR_GPSR(IP1_13_12, A22),
  626. PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
  627. PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
  628. PINMUX_IPSR_GPSR(IP1_15_14, A23),
  629. PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
  630. PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
  631. PINMUX_IPSR_GPSR(IP1_17_16, A24),
  632. PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
  633. PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
  634. PINMUX_IPSR_GPSR(IP1_19_18, A25),
  635. PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
  636. PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
  637. PINMUX_IPSR_GPSR(IP1_22_20, D0),
  638. PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
  639. PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
  640. PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
  641. PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
  642. PINMUX_IPSR_GPSR(IP1_25_23, D1),
  643. PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
  644. PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
  645. PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
  646. PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
  647. PINMUX_IPSR_GPSR(IP1_28_26, D2),
  648. PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
  649. PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
  650. PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
  651. PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
  652. PINMUX_IPSR_GPSR(IP1_31_29, D3),
  653. PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
  654. PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
  655. PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
  656. PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
  657. /* IPSR2 */
  658. PINMUX_IPSR_GPSR(IP2_2_0, D4),
  659. PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
  660. PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
  661. PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
  662. PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
  663. PINMUX_IPSR_GPSR(IP2_4_3, D5),
  664. PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
  665. PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
  666. PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
  667. PINMUX_IPSR_GPSR(IP2_7_5, D6),
  668. PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
  669. PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
  670. PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
  671. PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
  672. PINMUX_IPSR_GPSR(IP2_10_8, D7),
  673. PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
  674. PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
  675. PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
  676. PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
  677. PINMUX_IPSR_GPSR(IP2_13_11, D8),
  678. PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
  679. PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
  680. PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
  681. PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
  682. PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
  683. PINMUX_IPSR_GPSR(IP2_16_14, D9),
  684. PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
  685. PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
  686. PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
  687. PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
  688. PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
  689. PINMUX_IPSR_GPSR(IP2_19_17, D10),
  690. PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
  691. PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
  692. PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
  693. PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
  694. PINMUX_IPSR_GPSR(IP2_22_20, D11),
  695. PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
  696. PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
  697. PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
  698. PINMUX_IPSR_GPSR(IP2_24_23, D12),
  699. PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
  700. PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
  701. PINMUX_IPSR_GPSR(IP2_27_25, D13),
  702. PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
  703. PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
  704. PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
  705. PINMUX_IPSR_GPSR(IP2_30_28, D14),
  706. PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
  707. PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
  708. PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
  709. /* IPSR3 */
  710. PINMUX_IPSR_GPSR(IP3_1_0, D15),
  711. PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
  712. PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
  713. PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
  714. PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
  715. PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
  716. PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
  717. PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
  718. PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
  719. PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
  720. PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
  721. PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
  722. PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
  723. PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
  724. PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
  725. PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
  726. PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
  727. PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
  728. PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
  729. PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
  730. PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
  731. PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
  732. PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
  733. PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
  734. PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
  735. PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
  736. PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
  737. PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
  738. PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
  739. PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
  740. PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
  741. PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
  742. PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
  743. PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
  744. PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
  745. PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
  746. PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
  747. PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
  748. PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
  749. PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
  750. PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
  751. PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
  752. PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
  753. PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
  754. PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
  755. PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
  756. PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
  757. PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
  758. PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
  759. PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
  760. PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
  761. PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
  762. /* IPSR4 */
  763. PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
  764. PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
  765. PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
  766. PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
  767. PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
  768. PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
  769. PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
  770. PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
  771. PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
  772. PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
  773. PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
  774. PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
  775. PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
  776. PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
  777. PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
  778. PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
  779. PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
  780. PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
  781. PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
  782. PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
  783. PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
  784. PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
  785. PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
  786. PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
  787. PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
  788. PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
  789. PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
  790. PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
  791. PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
  792. PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
  793. PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
  794. PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
  795. PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
  796. PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
  797. PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
  798. PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
  799. PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
  800. PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
  801. PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
  802. PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
  803. PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
  804. PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
  805. PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
  806. PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
  807. PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
  808. PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
  809. PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
  810. /* IPSR5 */
  811. PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
  812. PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
  813. PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
  814. PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
  815. PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
  816. PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
  817. PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
  818. PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
  819. PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
  820. PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
  821. PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
  822. PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
  823. PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
  824. PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
  825. PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
  826. PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
  827. PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
  828. PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
  829. PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
  830. PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
  831. PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
  832. PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
  833. PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
  834. PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
  835. PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
  836. PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
  837. PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
  838. PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
  839. PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
  840. PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
  841. PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
  842. PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
  843. PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
  844. PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
  845. PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
  846. PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
  847. PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
  848. /* IPSR6 */
  849. PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
  850. PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
  851. PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
  852. PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
  853. PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
  854. PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
  855. PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
  856. PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
  857. PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
  858. PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
  859. PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
  860. PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
  861. PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
  862. PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
  863. PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
  864. PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
  865. PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
  866. PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
  867. PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
  868. PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
  869. PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
  870. PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
  871. PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
  872. PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
  873. PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
  874. PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
  875. PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
  876. PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
  877. PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
  878. PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
  879. PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
  880. PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
  881. PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
  882. PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
  883. PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
  884. PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
  885. PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
  886. PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
  887. PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
  888. PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
  889. PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
  890. PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
  891. PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
  892. PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
  893. PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
  894. PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
  895. PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
  896. /* IPSR7 */
  897. PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
  898. PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
  899. PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
  900. PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
  901. PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
  902. PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
  903. PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
  904. PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
  905. PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
  906. PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
  907. PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
  908. PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
  909. PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
  910. PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
  911. PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
  912. PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
  913. PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
  914. PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
  915. PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
  916. PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
  917. PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
  918. PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
  919. PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
  920. PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
  921. PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
  922. PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
  923. PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
  924. PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
  925. PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
  926. PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
  927. PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
  928. PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
  929. PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
  930. PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
  931. PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
  932. PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
  933. PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
  934. PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
  935. PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
  936. PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
  937. PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
  938. PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
  939. PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
  940. PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
  941. PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
  942. PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
  943. PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
  944. PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
  945. PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
  946. PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
  947. /* IPSR8 */
  948. PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
  949. PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
  950. PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
  951. PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
  952. PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
  953. PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
  954. PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
  955. PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
  956. PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
  957. PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
  958. PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
  959. PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
  960. PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
  961. PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
  962. PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
  963. PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
  964. PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
  965. PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
  966. PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
  967. PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
  968. PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
  969. PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
  970. PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
  971. PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
  972. PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
  973. PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
  974. PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
  975. PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
  976. PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
  977. PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
  978. PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
  979. PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
  980. PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
  981. PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
  982. PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
  983. PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
  984. PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
  985. PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
  986. PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
  987. PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
  988. PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
  989. PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
  990. PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
  991. PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0),
  992. PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0),
  993. PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
  994. PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
  995. /* IPSR9 */
  996. PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
  997. PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1),
  998. PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
  999. PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0),
  1000. PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1),
  1001. PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
  1002. PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0),
  1003. PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1),
  1004. PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
  1005. PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0),
  1006. PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1),
  1007. PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
  1008. PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0),
  1009. PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1),
  1010. PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
  1011. PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0),
  1012. PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1),
  1013. PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
  1014. PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0),
  1015. PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1),
  1016. PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
  1017. PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0),
  1018. PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1),
  1019. PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
  1020. PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0),
  1021. PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1),
  1022. PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
  1023. PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
  1024. PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
  1025. PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
  1026. PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
  1027. PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
  1028. PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
  1029. PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
  1030. PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1),
  1031. PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
  1032. PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
  1033. PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
  1034. PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1),
  1035. PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
  1036. PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
  1037. PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
  1038. PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1),
  1039. PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
  1040. PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
  1041. PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1),
  1042. PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
  1043. /* IPSE10 */
  1044. PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
  1045. PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
  1046. PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
  1047. PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
  1048. PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
  1049. PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
  1050. PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
  1051. PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
  1052. PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
  1053. PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
  1054. PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
  1055. PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
  1056. PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
  1057. PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
  1058. PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
  1059. PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
  1060. PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
  1061. PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
  1062. PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
  1063. PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
  1064. PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
  1065. PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
  1066. PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
  1067. PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3),
  1068. PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1),
  1069. PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
  1070. PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
  1071. PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
  1072. PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
  1073. PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
  1074. PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
  1075. PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
  1076. PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
  1077. PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
  1078. PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
  1079. PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
  1080. PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
  1081. PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
  1082. PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
  1083. PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3),
  1084. PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
  1085. PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
  1086. PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
  1087. PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
  1088. PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
  1089. PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
  1090. PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
  1091. PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
  1092. PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
  1093. PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
  1094. PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
  1095. /* IPSR11 */
  1096. PINMUX_IPSR_GPSR(IP11_0, SCL1),
  1097. PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
  1098. PINMUX_IPSR_GPSR(IP11_1, SDA1),
  1099. PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
  1100. PINMUX_IPSR_GPSR(IP11_2, SDA0),
  1101. PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
  1102. PINMUX_IPSR_GPSR(IP11_3, SDSELF),
  1103. PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
  1104. PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
  1105. PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
  1106. PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
  1107. PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
  1108. PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
  1109. PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
  1110. PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
  1111. PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
  1112. PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
  1113. PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
  1114. PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
  1115. PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
  1116. PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
  1117. PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
  1118. PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
  1119. PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
  1120. PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
  1121. PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
  1122. PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
  1123. PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
  1124. PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
  1125. PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
  1126. PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
  1127. PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
  1128. PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
  1129. PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
  1130. PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
  1131. PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
  1132. PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
  1133. PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
  1134. PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
  1135. PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
  1136. PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
  1137. PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
  1138. PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
  1139. PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
  1140. PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
  1141. PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
  1142. PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
  1143. PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
  1144. PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
  1145. PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
  1146. PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
  1147. };
  1148. static const struct sh_pfc_pin pinmux_pins[] = {
  1149. PINMUX_GPIO_GP_ALL(),
  1150. };
  1151. #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
  1152. static const struct pinmux_func pinmux_func_gpios[] = {
  1153. GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
  1154. GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
  1155. GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
  1156. GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
  1157. /* IPSR0 */
  1158. GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
  1159. GPIO_FN(TCLKA_C),
  1160. GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
  1161. GPIO_FN(TCLKB_C),
  1162. GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
  1163. GPIO_FN(TCLKC_C),
  1164. GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
  1165. GPIO_FN(TCLKD_C),
  1166. GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
  1167. GPIO_FN(TIOC0A_C),
  1168. GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
  1169. GPIO_FN(TIOC0B_C),
  1170. GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
  1171. GPIO_FN(TIOC0C_C),
  1172. GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
  1173. GPIO_FN(TIOC0D_C),
  1174. GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
  1175. GPIO_FN(TIOC1A_C),
  1176. GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
  1177. GPIO_FN(TIOC1B_C),
  1178. GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
  1179. GPIO_FN(TIOC2A_C),
  1180. GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
  1181. GPIO_FN(TIOC2B_C),
  1182. GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
  1183. GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
  1184. GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
  1185. GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
  1186. GPIO_FN(TIOC3D_C),
  1187. /* IPSR1 */
  1188. GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
  1189. GPIO_FN(TIOC4A_C),
  1190. GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
  1191. GPIO_FN(TIOC4B_C),
  1192. GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
  1193. GPIO_FN(TIOC4C_C),
  1194. GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
  1195. GPIO_FN(TIOC4D_C),
  1196. GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
  1197. GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
  1198. GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
  1199. GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
  1200. GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
  1201. GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
  1202. GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
  1203. GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
  1204. GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
  1205. GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
  1206. GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
  1207. GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
  1208. GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
  1209. GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
  1210. /* IPSR2 */
  1211. GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
  1212. GPIO_FN(FD4_A),
  1213. GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
  1214. GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
  1215. GPIO_FN(QSPCLK_A),
  1216. GPIO_FN(FD6_A),
  1217. GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
  1218. GPIO_FN(FD7_A),
  1219. GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
  1220. GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
  1221. GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
  1222. GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
  1223. GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
  1224. GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
  1225. GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
  1226. GPIO_FN(ET0_ETXD3_B),
  1227. GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
  1228. GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
  1229. GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
  1230. /* IPSR3 */
  1231. GPIO_FN(D15), GPIO_FN(SCK2_B),
  1232. GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
  1233. GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
  1234. GPIO_FN(ET0_ETXD0),
  1235. GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
  1236. GPIO_FN(ET0_GTX_CLK_A),
  1237. GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
  1238. GPIO_FN(ET0_ETXD1_A),
  1239. GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
  1240. GPIO_FN(ET0_ETXD2_A),
  1241. GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
  1242. GPIO_FN(ET0_ETXD3_A),
  1243. GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
  1244. GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
  1245. GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
  1246. GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
  1247. GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
  1248. GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
  1249. GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
  1250. GPIO_FN(ET0_ETXD7),
  1251. /* IPSR4 */
  1252. GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
  1253. GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
  1254. GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
  1255. GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
  1256. GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
  1257. GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
  1258. GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
  1259. GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
  1260. GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
  1261. GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
  1262. GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
  1263. GPIO_FN(ET0_MDC),
  1264. GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
  1265. GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
  1266. GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
  1267. GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
  1268. GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
  1269. GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
  1270. GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
  1271. /* IPSR5 */
  1272. GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
  1273. GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
  1274. GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
  1275. GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
  1276. GPIO_FN(ET0_PHY_INT_B),
  1277. GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
  1278. GPIO_FN(ET0_MAGIC_B),
  1279. GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
  1280. GPIO_FN(ET0_LINK_B),
  1281. GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
  1282. GPIO_FN(ET0_MDIO_B),
  1283. GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
  1284. GPIO_FN(ET0_ERXD3_B),
  1285. GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
  1286. GPIO_FN(ET0_ERXD2_B),
  1287. GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
  1288. GPIO_FN(ET0_RX_CLK_B),
  1289. /* IPSR6 */
  1290. GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
  1291. GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
  1292. GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
  1293. GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
  1294. GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
  1295. GPIO_FN(HIFD07),
  1296. GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
  1297. GPIO_FN(HIFD06),
  1298. GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
  1299. GPIO_FN(HIFD05),
  1300. GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
  1301. GPIO_FN(HIFD04),
  1302. GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
  1303. GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
  1304. GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
  1305. GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
  1306. GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
  1307. GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
  1308. /* IPSR7 */
  1309. GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
  1310. GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
  1311. GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
  1312. GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
  1313. GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
  1314. GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
  1315. GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
  1316. GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
  1317. GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
  1318. GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
  1319. GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
  1320. GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
  1321. GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
  1322. GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
  1323. GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
  1324. GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
  1325. GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
  1326. GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
  1327. GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
  1328. GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
  1329. /* IPSR8 */
  1330. GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
  1331. GPIO_FN(ET0_ERXD3_A),
  1332. GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
  1333. GPIO_FN(ET0_ERXD2_A),
  1334. GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
  1335. GPIO_FN(ET0_ERXD1),
  1336. GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
  1337. GPIO_FN(ET0_ERXD0),
  1338. GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
  1339. GPIO_FN(LCD_VCPWC_B),
  1340. GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
  1341. GPIO_FN(AUDIO_CLKA_B),
  1342. GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
  1343. GPIO_FN(SSI_SDATA1_B),
  1344. GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
  1345. GPIO_FN(SSI_WS1_B),
  1346. GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
  1347. GPIO_FN(SSI_SCK1_B),
  1348. GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
  1349. GPIO_FN(SSI_SDATA0_B),
  1350. GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
  1351. GPIO_FN(SSI_WS0_B),
  1352. GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
  1353. GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
  1354. GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
  1355. /* IPSR9 */
  1356. GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
  1357. GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
  1358. GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
  1359. GPIO_FN(LCD_DATA12_B),
  1360. GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
  1361. GPIO_FN(LCD_DATA11_B),
  1362. GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
  1363. GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
  1364. GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
  1365. GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
  1366. GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
  1367. GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
  1368. GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
  1369. GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
  1370. GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
  1371. GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
  1372. GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
  1373. /* IPSR10 */
  1374. GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
  1375. GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
  1376. GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
  1377. GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
  1378. GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
  1379. GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
  1380. GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
  1381. GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
  1382. GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
  1383. GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
  1384. GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
  1385. GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
  1386. GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
  1387. GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
  1388. GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
  1389. GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
  1390. GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
  1391. GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
  1392. GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
  1393. GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
  1394. /* IPSR11 */
  1395. GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
  1396. GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
  1397. GPIO_FN(ET0_RX_CLK_A),
  1398. GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
  1399. GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
  1400. GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
  1401. GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
  1402. GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
  1403. GPIO_FN(RX5_D), GPIO_FN(IERX_B),
  1404. GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
  1405. GPIO_FN(TX5_D), GPIO_FN(IETX_B),
  1406. GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
  1407. GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
  1408. GPIO_FN(ET0_ERXD6),
  1409. GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
  1410. GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
  1411. GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
  1412. GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
  1413. GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
  1414. GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
  1415. GPIO_FN(SDA1), GPIO_FN(RX1_E),
  1416. GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
  1417. };
  1418. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  1419. { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1, GROUP(
  1420. GP_0_31_FN, FN_IP2_2_0,
  1421. GP_0_30_FN, FN_IP1_31_29,
  1422. GP_0_29_FN, FN_IP1_28_26,
  1423. GP_0_28_FN, FN_IP1_25_23,
  1424. GP_0_27_FN, FN_IP1_22_20,
  1425. GP_0_26_FN, FN_IP1_19_18,
  1426. GP_0_25_FN, FN_IP1_17_16,
  1427. GP_0_24_FN, FN_IP0_5_4,
  1428. GP_0_23_FN, FN_IP0_3_2,
  1429. GP_0_22_FN, FN_IP0_1_0,
  1430. GP_0_21_FN, FN_IP11_28,
  1431. GP_0_20_FN, FN_IP1_7_6,
  1432. GP_0_19_FN, FN_IP1_5_4,
  1433. GP_0_18_FN, FN_IP1_3_2,
  1434. GP_0_17_FN, FN_IP1_1_0,
  1435. GP_0_16_FN, FN_IP0_31_30,
  1436. GP_0_15_FN, FN_IP0_29_28,
  1437. GP_0_14_FN, FN_IP0_27_26,
  1438. GP_0_13_FN, FN_IP0_25_24,
  1439. GP_0_12_FN, FN_IP0_23_22,
  1440. GP_0_11_FN, FN_IP0_21_20,
  1441. GP_0_10_FN, FN_IP0_19_18,
  1442. GP_0_9_FN, FN_IP0_17_16,
  1443. GP_0_8_FN, FN_IP0_15_14,
  1444. GP_0_7_FN, FN_IP0_13_12,
  1445. GP_0_6_FN, FN_IP0_11_10,
  1446. GP_0_5_FN, FN_IP0_9_8,
  1447. GP_0_4_FN, FN_IP0_7_6,
  1448. GP_0_3_FN, FN_IP1_15_14,
  1449. GP_0_2_FN, FN_IP1_13_12,
  1450. GP_0_1_FN, FN_IP1_11_10,
  1451. GP_0_0_FN, FN_IP1_9_8 ))
  1452. },
  1453. { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1, GROUP(
  1454. GP_1_31_FN, FN_IP11_25_23,
  1455. GP_1_30_FN, FN_IP2_13_11,
  1456. GP_1_29_FN, FN_IP2_10_8,
  1457. GP_1_28_FN, FN_IP2_7_5,
  1458. GP_1_27_FN, FN_IP3_26_24,
  1459. GP_1_26_FN, FN_IP3_23_21,
  1460. GP_1_25_FN, FN_IP2_4_3,
  1461. GP_1_24_FN, FN_WE1,
  1462. GP_1_23_FN, FN_WE0,
  1463. GP_1_22_FN, FN_IP3_19_18,
  1464. GP_1_21_FN, FN_RD,
  1465. GP_1_20_FN, FN_IP3_17_15,
  1466. GP_1_19_FN, FN_IP3_14_12,
  1467. GP_1_18_FN, FN_IP3_11_9,
  1468. GP_1_17_FN, FN_IP3_8_6,
  1469. GP_1_16_FN, FN_IP3_5_3,
  1470. GP_1_15_FN, FN_EX_CS0,
  1471. GP_1_14_FN, FN_IP3_2,
  1472. GP_1_13_FN, FN_CS0,
  1473. GP_1_12_FN, FN_BS,
  1474. GP_1_11_FN, FN_CLKOUT,
  1475. GP_1_10_FN, FN_IP3_1_0,
  1476. GP_1_9_FN, FN_IP2_30_28,
  1477. GP_1_8_FN, FN_IP2_27_25,
  1478. GP_1_7_FN, FN_IP2_24_23,
  1479. GP_1_6_FN, FN_IP2_22_20,
  1480. GP_1_5_FN, FN_IP2_19_17,
  1481. GP_1_4_FN, FN_IP2_16_14,
  1482. GP_1_3_FN, FN_IP11_22_21,
  1483. GP_1_2_FN, FN_IP11_20_19,
  1484. GP_1_1_FN, FN_IP3_29_27,
  1485. GP_1_0_FN, FN_IP3_20 ))
  1486. },
  1487. { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1, GROUP(
  1488. GP_2_31_FN, FN_IP4_31_30,
  1489. GP_2_30_FN, FN_IP5_2_0,
  1490. GP_2_29_FN, FN_IP5_5_3,
  1491. GP_2_28_FN, FN_IP5_8_6,
  1492. GP_2_27_FN, FN_IP5_11_9,
  1493. GP_2_26_FN, FN_IP5_14_12,
  1494. GP_2_25_FN, FN_IP5_17_15,
  1495. GP_2_24_FN, FN_IP5_20_18,
  1496. GP_2_23_FN, FN_IP5_22_21,
  1497. GP_2_22_FN, FN_IP5_24_23,
  1498. GP_2_21_FN, FN_IP5_26_25,
  1499. GP_2_20_FN, FN_IP4_29_28,
  1500. GP_2_19_FN, FN_IP4_27_26,
  1501. GP_2_18_FN, FN_IP4_25_24,
  1502. GP_2_17_FN, FN_IP4_23_22,
  1503. GP_2_16_FN, FN_IP4_21_20,
  1504. GP_2_15_FN, FN_IP4_19_18,
  1505. GP_2_14_FN, FN_IP4_17_15,
  1506. GP_2_13_FN, FN_IP4_14_12,
  1507. GP_2_12_FN, FN_IP4_11_9,
  1508. GP_2_11_FN, FN_IP4_8_6,
  1509. GP_2_10_FN, FN_IP4_5_3,
  1510. GP_2_9_FN, FN_IP8_27_26,
  1511. GP_2_8_FN, FN_IP11_12,
  1512. GP_2_7_FN, FN_IP8_25_23,
  1513. GP_2_6_FN, FN_IP8_22_20,
  1514. GP_2_5_FN, FN_IP11_27_26,
  1515. GP_2_4_FN, FN_IP8_29_28,
  1516. GP_2_3_FN, FN_IP4_2_0,
  1517. GP_2_2_FN, FN_IP11_11_10,
  1518. GP_2_1_FN, FN_IP11_9_7,
  1519. GP_2_0_FN, FN_IP11_6_4 ))
  1520. },
  1521. { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1, GROUP(
  1522. GP_3_31_FN, FN_IP9_1_0,
  1523. GP_3_30_FN, FN_IP8_19_18,
  1524. GP_3_29_FN, FN_IP8_17_16,
  1525. GP_3_28_FN, FN_IP8_15_14,
  1526. GP_3_27_FN, FN_IP8_13_12,
  1527. GP_3_26_FN, FN_IP8_11_10,
  1528. GP_3_25_FN, FN_IP8_9_8,
  1529. GP_3_24_FN, FN_IP8_7_6,
  1530. GP_3_23_FN, FN_IP8_5_4,
  1531. GP_3_22_FN, FN_IP8_3_2,
  1532. GP_3_21_FN, FN_IP8_1_0,
  1533. GP_3_20_FN, FN_IP7_30_29,
  1534. GP_3_19_FN, FN_IP7_28_27,
  1535. GP_3_18_FN, FN_IP7_26_24,
  1536. GP_3_17_FN, FN_IP7_23_21,
  1537. GP_3_16_FN, FN_IP7_20_18,
  1538. GP_3_15_FN, FN_IP7_17_15,
  1539. GP_3_14_FN, FN_IP7_14_12,
  1540. GP_3_13_FN, FN_IP7_11_9,
  1541. GP_3_12_FN, FN_IP7_8_6,
  1542. GP_3_11_FN, FN_IP7_5_3,
  1543. GP_3_10_FN, FN_IP7_2_0,
  1544. GP_3_9_FN, FN_IP6_23_21,
  1545. GP_3_8_FN, FN_IP6_20_18,
  1546. GP_3_7_FN, FN_IP6_17_16,
  1547. GP_3_6_FN, FN_IP6_15_14,
  1548. GP_3_5_FN, FN_IP6_13_12,
  1549. GP_3_4_FN, FN_IP6_11_10,
  1550. GP_3_3_FN, FN_IP6_9_8,
  1551. GP_3_2_FN, FN_IP6_7_6,
  1552. GP_3_1_FN, FN_IP6_5_3,
  1553. GP_3_0_FN, FN_IP6_2_0 ))
  1554. },
  1555. { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1, GROUP(
  1556. GP_4_31_FN, FN_IP10_24_23,
  1557. GP_4_30_FN, FN_IP10_22,
  1558. GP_4_29_FN, FN_IP11_18_16,
  1559. GP_4_28_FN, FN_USB_OVC0,
  1560. GP_4_27_FN, FN_IP11_15_13,
  1561. GP_4_26_FN, FN_PENC0,
  1562. GP_4_25_FN, FN_IP11_2,
  1563. GP_4_24_FN, FN_SCL0,
  1564. GP_4_23_FN, FN_IP11_1,
  1565. GP_4_22_FN, FN_IP11_0,
  1566. GP_4_21_FN, FN_IP10_21_19,
  1567. GP_4_20_FN, FN_IP10_18_16,
  1568. GP_4_19_FN, FN_IP10_15,
  1569. GP_4_18_FN, FN_IP10_14_12,
  1570. GP_4_17_FN, FN_IP10_11_9,
  1571. GP_4_16_FN, FN_IP10_8_6,
  1572. GP_4_15_FN, FN_IP10_5_3,
  1573. GP_4_14_FN, FN_IP10_2_0,
  1574. GP_4_13_FN, FN_IP9_29_28,
  1575. GP_4_12_FN, FN_IP9_27_26,
  1576. GP_4_11_FN, FN_IP9_9_8,
  1577. GP_4_10_FN, FN_IP9_7_6,
  1578. GP_4_9_FN, FN_IP9_5_4,
  1579. GP_4_8_FN, FN_IP9_3_2,
  1580. GP_4_7_FN, FN_IP9_17_16,
  1581. GP_4_6_FN, FN_IP9_15_14,
  1582. GP_4_5_FN, FN_IP9_13_12,
  1583. GP_4_4_FN, FN_IP9_11_10,
  1584. GP_4_3_FN, FN_IP9_25_24,
  1585. GP_4_2_FN, FN_IP9_23_22,
  1586. GP_4_1_FN, FN_IP9_21_20,
  1587. GP_4_0_FN, FN_IP9_19_18 ))
  1588. },
  1589. { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
  1590. 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
  1591. 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
  1592. 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
  1593. 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
  1594. 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
  1595. GP_5_11_FN, FN_IP10_29_28,
  1596. GP_5_10_FN, FN_IP10_27_26,
  1597. 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
  1598. 0, 0, 0, 0, /* 5, 4 */
  1599. GP_5_3_FN, FN_IRQ3_B,
  1600. GP_5_2_FN, FN_IRQ2_B,
  1601. GP_5_1_FN, FN_IP11_3,
  1602. GP_5_0_FN, FN_IP10_25 ))
  1603. },
  1604. { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
  1605. GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
  1606. GROUP(
  1607. /* IP0_31_30 [2] */
  1608. FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
  1609. FN_TIOC3D_C,
  1610. /* IP0_29_28 [2] */
  1611. FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
  1612. /* IP0_27_26 [2] */
  1613. FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
  1614. /* IP0_25_24 [2] */
  1615. FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
  1616. /* IP0_23_22 [2] */
  1617. FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
  1618. /* IP0_21_20 [2] */
  1619. FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
  1620. /* IP0_19_18 [2] */
  1621. FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
  1622. /* IP0_17_16 [2] */
  1623. FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
  1624. /* IP0_15_14 [2] */
  1625. FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
  1626. /* IP0_13_12 [2] */
  1627. FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
  1628. /* IP0_11_10 [2] */
  1629. FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
  1630. /* IP0_9_8 [2] */
  1631. FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
  1632. /* IP0_7_6 [2] */
  1633. FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
  1634. /* IP0_5_4 [2] */
  1635. FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
  1636. /* IP0_3_2 [2] */
  1637. FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
  1638. /* IP0_1_0 [2] */
  1639. FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C ))
  1640. },
  1641. { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
  1642. GROUP(3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
  1643. GROUP(
  1644. /* IP1_31_29 [3] */
  1645. FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
  1646. FN_FD3_A, 0, 0, 0,
  1647. /* IP1_28_26 [3] */
  1648. FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
  1649. FN_FD2_A, 0, 0, 0,
  1650. /* IP1_25_23 [3] */
  1651. FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
  1652. FN_FD1_A, 0, 0, 0,
  1653. /* IP1_22_20 [3] */
  1654. FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
  1655. FN_FD0_A, 0, 0, 0,
  1656. /* IP1_19_18 [2] */
  1657. FN_A25, FN_TX2_D, FN_ST1_D2, 0,
  1658. /* IP1_17_16 [2] */
  1659. FN_A24, FN_RX2_D, FN_ST1_D1, 0,
  1660. /* IP1_15_14 [2] */
  1661. FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
  1662. /* IP1_13_12 [2] */
  1663. FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
  1664. /* IP1_11_10 [2] */
  1665. FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
  1666. /* IP1_9_8 [2] */
  1667. FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
  1668. /* IP1_7_6 [2] */
  1669. FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
  1670. /* IP1_5_4 [2] */
  1671. FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
  1672. /* IP1_3_2 [2] */
  1673. FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
  1674. /* IP1_1_0 [2] */
  1675. FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
  1676. },
  1677. { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
  1678. GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
  1679. GROUP(
  1680. /* IP2_31 [1] */
  1681. 0, 0,
  1682. /* IP2_30_28 [3] */
  1683. FN_D14, FN_TX2_B, 0, FN_FSE_A,
  1684. FN_ET0_TX_CLK_B, 0, 0, 0,
  1685. /* IP2_27_25 [3] */
  1686. FN_D13, FN_RX2_B, 0, FN_FRB_A,
  1687. FN_ET0_ETXD6_B, 0, 0, 0,
  1688. /* IP2_24_23 [2] */
  1689. FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
  1690. /* IP2_22_20 [3] */
  1691. FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
  1692. FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
  1693. /* IP2_19_17 [3] */
  1694. FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
  1695. FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
  1696. /* IP2_16_14 [3] */
  1697. FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
  1698. FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
  1699. /* IP2_13_11 [3] */
  1700. FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
  1701. FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
  1702. /* IP2_10_8 [3] */
  1703. FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
  1704. FN_FD7_A, 0, 0, 0,
  1705. /* IP2_7_5 [3] */
  1706. FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
  1707. FN_FD6_A, 0, 0, 0,
  1708. /* IP2_4_3 [2] */
  1709. FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
  1710. /* IP2_2_0 [3] */
  1711. FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
  1712. FN_FD4_A, 0, 0, 0 ))
  1713. },
  1714. { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
  1715. GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
  1716. GROUP(
  1717. /* IP3_31_30 [2] */
  1718. 0, 0, 0, 0,
  1719. /* IP3_29_27 [3] */
  1720. FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
  1721. FN_ET0_ETXD7, 0, 0, 0,
  1722. /* IP3_26_24 [3] */
  1723. FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
  1724. FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
  1725. /* IP3_23_21 [3] */
  1726. FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
  1727. FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
  1728. /* IP3_20 [1] */
  1729. FN_EX_WAIT0, FN_TCLK1_B,
  1730. /* IP3_19_18 [2] */
  1731. FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
  1732. /* IP3_17_15 [3] */
  1733. FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
  1734. FN_ET0_ETXD3_A, 0, 0, 0,
  1735. /* IP3_14_12 [3] */
  1736. FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
  1737. FN_ET0_ETXD2_A, 0, 0, 0,
  1738. /* IP3_11_9 [3] */
  1739. FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
  1740. FN_ET0_ETXD1_A, 0, 0, 0,
  1741. /* IP3_8_6 [3] */
  1742. FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
  1743. FN_ET0_GTX_CLK_A, 0, 0, 0,
  1744. /* IP3_5_3 [3] */
  1745. FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
  1746. FN_ET0_ETXD0, 0, 0, 0,
  1747. /* IP3_2 [1] */
  1748. FN_CS1_A26, FN_QIO3_B,
  1749. /* IP3_1_0 [2] */
  1750. FN_D15, FN_SCK2_B, 0, 0 ))
  1751. },
  1752. { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
  1753. GROUP(2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3),
  1754. GROUP(
  1755. /* IP4_31_30 [2] */
  1756. 0, FN_SCK2_A, FN_VI0_G3, 0,
  1757. /* IP4_29_28 [2] */
  1758. 0, FN_RTS1_B, FN_VI0_G2, 0,
  1759. /* IP4_27_26 [2] */
  1760. 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
  1761. /* IP4_25_24 [2] */
  1762. 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
  1763. /* IP4_23_22 [2] */
  1764. 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
  1765. /* IP4_21_20 [2] */
  1766. 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
  1767. /* IP4_19_18 [2] */
  1768. 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
  1769. /* IP4_17_15 [3] */
  1770. 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
  1771. FN_ET0_MDC, 0, 0, 0,
  1772. /* IP4_14_12 [3] */
  1773. FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
  1774. FN_ET0_COL, 0, 0, 0,
  1775. /* IP4_11_9 [3] */
  1776. FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
  1777. FN_ET0_CRS, 0, 0, 0,
  1778. /* IP4_8_6 [3] */
  1779. FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
  1780. FN_ET0_RX_ER, 0, 0, 0,
  1781. /* IP4_5_3 [3] */
  1782. FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
  1783. FN_ET0_RX_DV, 0, 0, 0,
  1784. /* IP4_2_0 [3] */
  1785. FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
  1786. FN_ET0_ERXD7, 0, 0, 0 ))
  1787. },
  1788. { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
  1789. GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
  1790. 3, 3, 3),
  1791. GROUP(
  1792. /* IP5_31 [1] */
  1793. 0, 0,
  1794. /* IP5_30 [1] */
  1795. 0, 0,
  1796. /* IP5_29 [1] */
  1797. 0, 0,
  1798. /* IP5_28 [1] */
  1799. 0, 0,
  1800. /* IP5_27 [1] */
  1801. 0, 0,
  1802. /* IP5_26_25 [2] */
  1803. FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
  1804. /* IP5_24_23 [2] */
  1805. FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
  1806. /* IP5_22_21 [2] */
  1807. FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
  1808. /* IP5_20_18 [3] */
  1809. FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
  1810. 0, 0, 0, FN_ET0_PHY_INT_B,
  1811. /* IP5_17_15 [3] */
  1812. FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
  1813. 0, 0, 0, FN_ET0_MAGIC_B,
  1814. /* IP5_14_12 [3] */
  1815. FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
  1816. 0, 0, 0, FN_ET0_LINK_B,
  1817. /* IP5_11_9 [3] */
  1818. FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
  1819. 0, 0, 0, FN_ET0_MDIO_B,
  1820. /* IP5_8_6 [3] */
  1821. FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
  1822. 0, 0, 0, FN_ET0_ERXD3_B,
  1823. /* IP5_5_3 [3] */
  1824. FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
  1825. 0, 0, 0, FN_ET0_ERXD2_B,
  1826. /* IP5_2_0 [3] */
  1827. FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
  1828. FN_ET0_RX_CLK_B, 0, 0, 0 ))
  1829. },
  1830. { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
  1831. GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
  1832. 2, 2, 2, 2, 3, 3),
  1833. GROUP(
  1834. /* IP5_31 [1] */
  1835. 0, 0,
  1836. /* IP6_30 [1] */
  1837. 0, 0,
  1838. /* IP6_29 [1] */
  1839. 0, 0,
  1840. /* IP6_28 [1] */
  1841. 0, 0,
  1842. /* IP6_27 [1] */
  1843. 0, 0,
  1844. /* IP6_26 [1] */
  1845. 0, 0,
  1846. /* IP6_25 [1] */
  1847. 0, 0,
  1848. /* IP6_24 [1] */
  1849. 0, 0,
  1850. /* IP6_23_21 [3] */
  1851. FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
  1852. FN_HIFD09, 0, 0, 0,
  1853. /* IP6_20_18 [3] */
  1854. FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
  1855. FN_TIOC1A_A, FN_HIFD08, 0, 0,
  1856. /* IP6_17_16 [2] */
  1857. FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
  1858. /* IP6_15_14 [2] */
  1859. FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
  1860. /* IP6_13_12 [2] */
  1861. FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
  1862. /* IP6_11_10 [2] */
  1863. FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
  1864. /* IP6_9_8 [2] */
  1865. FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
  1866. /* IP6_7_6 [2] */
  1867. FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
  1868. /* IP6_5_3 [3] */
  1869. FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
  1870. FN_TCLKB_A, FN_HIFD01, 0, 0,
  1871. /* IP6_2_0 [3] */
  1872. FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
  1873. FN_TCLKA_A, FN_HIFD00, 0, 0 ))
  1874. },
  1875. { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
  1876. GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  1877. GROUP(
  1878. /* IP7_31 [1] */
  1879. 0, 0,
  1880. /* IP7_30_29 [2] */
  1881. FN_DU0_DB4, 0, FN_HIFINT, 0,
  1882. /* IP7_28_27 [2] */
  1883. FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
  1884. /* IP7_26_24 [3] */
  1885. FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
  1886. FN_HIFWR, 0, 0, 0,
  1887. /* IP7_23_21 [3] */
  1888. FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
  1889. FN_HIFRS, 0, 0, 0,
  1890. /* IP7_20_18 [3] */
  1891. FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
  1892. FN_HIFCS, 0, 0, 0,
  1893. /* IP7_17_15 [3] */
  1894. FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
  1895. FN_HIFD15, 0, 0, 0,
  1896. /* IP7_14_12 [3] */
  1897. FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
  1898. FN_HIFD14, 0, 0, 0,
  1899. /* IP7_11_9 [3] */
  1900. FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
  1901. FN_HIFD13, 0, 0, 0,
  1902. /* IP7_8_6 [3] */
  1903. FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
  1904. FN_HIFD12, 0, 0, 0,
  1905. /* IP7_5_3 [3] */
  1906. FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
  1907. FN_HIFD11, 0, 0, 0,
  1908. /* IP7_2_0 [3] */
  1909. FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
  1910. FN_HIFD10, 0, 0, 0 ))
  1911. },
  1912. { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
  1913. GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
  1914. 2, 2, 2),
  1915. GROUP(
  1916. /* IP9_31_30 [2] */
  1917. 0, 0, 0, 0,
  1918. /* IP8_29_28 [2] */
  1919. FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
  1920. /* IP8_27_26 [2] */
  1921. FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
  1922. /* IP8_25_23 [3] */
  1923. FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
  1924. FN_ET0_ERXD1, 0, 0, 0,
  1925. /* IP8_22_20 [3] */
  1926. FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
  1927. FN_ET0_ERXD0, 0, 0, 0,
  1928. /* IP8_19_18 [2] */
  1929. FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
  1930. /* IP8_17_16 [2] */
  1931. FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
  1932. /* IP8_15_14 [2] */
  1933. FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
  1934. FN_SSI_SDATA1_B,
  1935. /* IP8_13_12 [2] */
  1936. FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
  1937. /* IP8_11_10 [2] */
  1938. FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
  1939. /* IP8_9_8 [2] */
  1940. FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
  1941. /* IP8_7_6 [2] */
  1942. FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
  1943. /* IP8_5_4 [2] */
  1944. FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
  1945. /* IP8_3_2 [2] */
  1946. FN_DU0_DB6, 0, FN_HIFRDY, 0,
  1947. /* IP8_1_0 [2] */
  1948. FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
  1949. },
  1950. { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
  1951. GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  1952. 2, 2, 2, 2),
  1953. GROUP(
  1954. /* IP9_31_30 [2] */
  1955. 0, 0, 0, 0,
  1956. /* IP9_29_28 [2] */
  1957. FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
  1958. /* IP9_27_26 [2] */
  1959. FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
  1960. /* IP9_25_24 [2] */
  1961. FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
  1962. /* IP9_23_22 [2] */
  1963. FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
  1964. /* IP9_21_20 [2] */
  1965. FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
  1966. /* IP9_19_18 [2] */
  1967. FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
  1968. /* IP9_17_16 [2] */
  1969. FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
  1970. /* IP9_15_14 [2] */
  1971. FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
  1972. /* IP9_13_12 [2] */
  1973. FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
  1974. /* IP9_11_10 [2] */
  1975. FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
  1976. /* IP9_9_8 [2] */
  1977. FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
  1978. /* IP9_7_6 [2] */
  1979. FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
  1980. /* IP9_5_4 [2] */
  1981. FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
  1982. /* IP9_3_2 [2] */
  1983. FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
  1984. /* IP9_1_0 [2] */
  1985. FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
  1986. },
  1987. { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
  1988. GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
  1989. GROUP(
  1990. /* IP9_31_30 [2] */
  1991. 0, 0, 0, 0,
  1992. /* IP10_29_28 [2] */
  1993. FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
  1994. /* IP10_27_26 [2] */
  1995. FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
  1996. /* IP10_25 [1] */
  1997. FN_CAN1_RX_A, FN_IRQ1_B,
  1998. /* IP10_24_23 [2] */
  1999. FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
  2000. /* IP10_22 [1] */
  2001. FN_CAN_CLK_A, FN_RX4_D,
  2002. /* IP10_21_19 [3] */
  2003. FN_AUDIO_CLKOUT, FN_TX1_E, 0, FN_HRTS0_C, FN_FSE_B,
  2004. FN_LCD_M_DISP_B, 0, 0,
  2005. /* IP10_18_16 [3] */
  2006. FN_AUDIO_CLKC, FN_SCK1_E, 0, FN_HCTS0_C, FN_FRB_B,
  2007. FN_LCD_VEPWC_B, 0, 0,
  2008. /* IP10_15 [1] */
  2009. FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
  2010. /* IP10_14_12 [3] */
  2011. FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
  2012. FN_LCD_FLM_B, 0, 0, 0,
  2013. /* IP10_11_9 [3] */
  2014. FN_SSI_SDATA3, FN_VI1_7_B, 0, FN_HTX0_C, FN_FWE_B,
  2015. FN_LCD_CL2_B, 0, 0,
  2016. /* IP10_8_6 [3] */
  2017. FN_SSI_SDATA2, FN_VI1_6_B, 0, FN_HRX0_C, FN_FRE_B,
  2018. FN_LCD_CL1_B, 0, 0,
  2019. /* IP10_5_3 [3] */
  2020. FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
  2021. FN_LCD_DON_B, 0, 0,
  2022. /* IP10_2_0 [3] */
  2023. FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
  2024. FN_LCD_DATA15_B, 0, 0, 0 ))
  2025. },
  2026. { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
  2027. GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
  2028. 1, 1, 1, 1),
  2029. GROUP(
  2030. /* IP11_31_29 [3] */
  2031. 0, 0, 0, 0, 0, 0, 0, 0,
  2032. /* IP11_28 [1] */
  2033. FN_PRESETOUT, FN_ST_CLKOUT,
  2034. /* IP11_27_26 [2] */
  2035. FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
  2036. /* IP11_25_23 [3] */
  2037. FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
  2038. FN_ET0_TX_CLK_A, 0, 0, 0,
  2039. /* IP11_22_21 [2] */
  2040. FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
  2041. /* IP11_20_19 [2] */
  2042. FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
  2043. /* IP11_18_16 [3] */
  2044. FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
  2045. FN_IERX_B, 0, 0, 0,
  2046. /* IP11_15_13 [3] */
  2047. FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
  2048. FN_IETX_B, 0, 0, 0,
  2049. /* IP11_12 [1] */
  2050. FN_TX0_A, FN_HSPI_TX_A,
  2051. /* IP11_11_10 [2] */
  2052. FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
  2053. /* IP11_9_7 [3] */
  2054. FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
  2055. FN_ET0_ERXD5, 0, 0, 0,
  2056. /* IP11_6_4 [3] */
  2057. FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
  2058. FN_ET0_ERXD4, 0, 0, 0,
  2059. /* IP11_3 [1] */
  2060. FN_SDSELF, FN_RTS1_E,
  2061. /* IP11_2 [1] */
  2062. FN_SDA0, FN_HIFEBL_A,
  2063. /* IP11_1 [1] */
  2064. FN_SDA1, FN_RX1_E,
  2065. /* IP11_0 [1] */
  2066. FN_SCL1, FN_SCIF_CLK_C ))
  2067. },
  2068. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
  2069. GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
  2070. 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
  2071. GROUP(
  2072. /* SEL1_31_29 [3] */
  2073. 0, 0, 0, 0, 0, 0, 0, 0,
  2074. /* SEL1_28 [1] */
  2075. FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
  2076. /* SEL1_27 [1] */
  2077. FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
  2078. /* SEL1_26 [1] */
  2079. FN_SEL_VIN1_0, FN_SEL_VIN1_1,
  2080. /* SEL1_25 [1] */
  2081. FN_SEL_HIF_0, FN_SEL_HIF_1,
  2082. /* SEL1_24 [1] */
  2083. FN_SEL_RSPI_0, FN_SEL_RSPI_1,
  2084. /* SEL1_23 [1] */
  2085. FN_SEL_LCDC_0, FN_SEL_LCDC_1,
  2086. /* SEL1_22_21 [2] */
  2087. FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
  2088. /* SEL1_20 [1] */
  2089. FN_SEL_ET0_0, FN_SEL_ET0_1,
  2090. /* SEL1_19 [1] */
  2091. FN_SEL_RMII_0, FN_SEL_RMII_1,
  2092. /* SEL1_18 [1] */
  2093. FN_SEL_TMU_0, FN_SEL_TMU_1,
  2094. /* SEL1_17_16 [2] */
  2095. FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
  2096. /* SEL1_15_14 [2] */
  2097. FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
  2098. /* SEL1_13 [1] */
  2099. FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
  2100. /* SEL1_12_11 [2] */
  2101. FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
  2102. /* SEL1_10 [1] */
  2103. FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
  2104. /* SEL1_9 [1] */
  2105. FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
  2106. /* SEL1_8 [1] */
  2107. FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
  2108. /* SEL1_7 [1] */
  2109. FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
  2110. /* SEL1_6 [1] */
  2111. FN_SEL_SSI1_0, FN_SEL_SSI1_1,
  2112. /* SEL1_5 [1] */
  2113. FN_SEL_SSI0_0, FN_SEL_SSI0_1,
  2114. /* SEL1_4 [1] */
  2115. FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
  2116. /* SEL1_3 [1] */
  2117. FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
  2118. /* SEL1_2 [1] */
  2119. FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
  2120. /* SEL1_1 [1] */
  2121. FN_SEL_MMC_0, FN_SEL_MMC_1,
  2122. /* SEL1_0 [1] */
  2123. FN_SEL_INTC_0, FN_SEL_INTC_1 ))
  2124. },
  2125. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
  2126. GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
  2127. 2, 1, 2, 2, 3, 2, 3, 2, 2),
  2128. GROUP(
  2129. /* SEL2_31 [1] */
  2130. 0, 0,
  2131. /* SEL2_30 [1] */
  2132. 0, 0,
  2133. /* SEL2_29 [1] */
  2134. 0, 0,
  2135. /* SEL2_28 [1] */
  2136. 0, 0,
  2137. /* SEL2_27 [1] */
  2138. 0, 0,
  2139. /* SEL2_26 [1] */
  2140. 0, 0,
  2141. /* SEL2_25 [1] */
  2142. 0, 0,
  2143. /* SEL2_24 [1] */
  2144. 0, 0,
  2145. /* SEL2_23 [1] */
  2146. FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
  2147. /* SEL2_22 [1] */
  2148. FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
  2149. /* SEL2_21 [1] */
  2150. FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
  2151. /* SEL2_20_19 [2] */
  2152. FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
  2153. /* SEL2_18_17 [2] */
  2154. FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
  2155. /* SEL2_16 [1] */
  2156. FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
  2157. /* SEL2_15_14 [2] */
  2158. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
  2159. /* SEL2_13_12 [2] */
  2160. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  2161. /* SEL2_11_9 [3] */
  2162. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
  2163. FN_SEL_SCIF3_4, 0, 0, 0,
  2164. /* SEL2_8_7 [2] */
  2165. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
  2166. /* SEL2_6_4 [3] */
  2167. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
  2168. FN_SEL_SCIF1_4, 0, 0, 0,
  2169. /* SEL2_3_2 [2] */
  2170. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
  2171. /* SEL2_1_0 [2] */
  2172. FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 ))
  2173. },
  2174. /* GPIO 0 - 5*/
  2175. { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1, GROUP(GP_INOUTSEL(0)))
  2176. },
  2177. { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1, GROUP(GP_INOUTSEL(1)))
  2178. },
  2179. { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1, GROUP(GP_INOUTSEL(2)))
  2180. },
  2181. { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1, GROUP(GP_INOUTSEL(3)))
  2182. },
  2183. { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
  2184. },
  2185. { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
  2186. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
  2187. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
  2188. 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
  2189. GP_5_11_IN, GP_5_11_OUT,
  2190. GP_5_10_IN, GP_5_10_OUT,
  2191. GP_5_9_IN, GP_5_9_OUT,
  2192. GP_5_8_IN, GP_5_8_OUT,
  2193. GP_5_7_IN, GP_5_7_OUT,
  2194. GP_5_6_IN, GP_5_6_OUT,
  2195. GP_5_5_IN, GP_5_5_OUT,
  2196. GP_5_4_IN, GP_5_4_OUT,
  2197. GP_5_3_IN, GP_5_3_OUT,
  2198. GP_5_2_IN, GP_5_2_OUT,
  2199. GP_5_1_IN, GP_5_1_OUT,
  2200. GP_5_0_IN, GP_5_0_OUT ))
  2201. },
  2202. { },
  2203. };
  2204. static const struct pinmux_data_reg pinmux_data_regs[] = {
  2205. /* GPIO 0 - 5*/
  2206. { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
  2207. { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
  2208. { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
  2209. { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
  2210. { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
  2211. { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
  2212. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2213. 0, 0, 0, 0,
  2214. GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
  2215. GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
  2216. GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
  2217. },
  2218. { },
  2219. };
  2220. const struct sh_pfc_soc_info sh7734_pinmux_info = {
  2221. .name = "sh7734_pfc",
  2222. .unlock_reg = 0xFFFC0000,
  2223. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  2224. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  2225. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  2226. .pins = pinmux_pins,
  2227. .nr_pins = ARRAY_SIZE(pinmux_pins),
  2228. .func_gpios = pinmux_func_gpios,
  2229. .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
  2230. .cfg_regs = pinmux_config_regs,
  2231. .data_regs = pinmux_data_regs,
  2232. .pinmux_data = pinmux_data,
  2233. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  2234. };