pfc-sh73a0.c 128 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sh73a0 processor support - PFC hardware block
  4. *
  5. * Copyright (C) 2010 Renesas Solutions Corp.
  6. * Copyright (C) 2010 NISHIMOTO Hiroki
  7. */
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/pinctrl/pinconf-generic.h>
  12. #include <linux/regulator/driver.h>
  13. #include <linux/regulator/machine.h>
  14. #include <linux/slab.h>
  15. #include "core.h"
  16. #include "sh_pfc.h"
  17. #define CPU_ALL_PORT(fn, pfx, sfx) \
  18. PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
  19. PORT_10(100, fn, pfx##10, sfx), \
  20. PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
  21. PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
  22. PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
  23. PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
  24. PORT_1(118, fn, pfx##118, sfx), \
  25. PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  26. PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
  27. PORT_10(150, fn, pfx##15, sfx), \
  28. PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
  29. PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
  30. PORT_1(164, fn, pfx##164, sfx), \
  31. PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  32. PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  33. PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  34. PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  35. PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
  36. PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
  37. PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
  38. PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
  39. PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  40. PORT_1(282, fn, pfx##282, sfx), \
  41. PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  42. PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
  43. #define CPU_ALL_NOGP(fn) \
  44. PIN_NOGP(A11, "F26", fn)
  45. enum {
  46. PINMUX_RESERVED = 0,
  47. PINMUX_DATA_BEGIN,
  48. PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
  49. PINMUX_DATA_END,
  50. PINMUX_INPUT_BEGIN,
  51. PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
  52. PINMUX_INPUT_END,
  53. PINMUX_OUTPUT_BEGIN,
  54. PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
  55. PINMUX_OUTPUT_END,
  56. PINMUX_FUNCTION_BEGIN,
  57. PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
  58. PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
  59. PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
  60. PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
  61. PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
  62. PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
  63. PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
  64. PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
  65. PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
  66. PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
  67. MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
  68. MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
  69. MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
  70. MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
  71. MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
  72. MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
  73. MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
  74. MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
  75. MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
  76. MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
  77. MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
  78. MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
  79. MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
  80. MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
  81. MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
  82. MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
  83. MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
  84. MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
  85. MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
  86. MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
  87. MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
  88. MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
  89. MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
  90. MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
  91. MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
  92. MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
  93. MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
  94. MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
  95. MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
  96. MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
  97. MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
  98. MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
  99. MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
  100. MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
  101. MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
  102. MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
  103. MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
  104. MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
  105. MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
  106. MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
  107. MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
  108. MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
  109. PINMUX_FUNCTION_END,
  110. PINMUX_MARK_BEGIN,
  111. /* Hardware manual Table 25-1 (Function 0-7) */
  112. VBUS_0_MARK,
  113. GPI0_MARK,
  114. GPI1_MARK,
  115. GPI2_MARK,
  116. GPI3_MARK,
  117. GPI4_MARK,
  118. GPI5_MARK,
  119. GPI6_MARK,
  120. GPI7_MARK,
  121. SCIFA7_RXD_MARK,
  122. SCIFA7_CTS__MARK,
  123. GPO7_MARK, MFG0_OUT2_MARK,
  124. GPO6_MARK, MFG1_OUT2_MARK,
  125. GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
  126. SCIFA0_TXD_MARK,
  127. SCIFA7_TXD_MARK,
  128. SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
  129. GPO0_MARK,
  130. GPO1_MARK,
  131. GPO2_MARK, STATUS0_MARK,
  132. GPO3_MARK, STATUS1_MARK,
  133. GPO4_MARK, STATUS2_MARK,
  134. VINT_MARK,
  135. TCKON_MARK,
  136. XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
  137. MFG0_OUT1_MARK, PORT27_IROUT_MARK,
  138. XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
  139. PORT28_TPU1TO1_MARK,
  140. SIM_RST_MARK, PORT29_TPU1TO1_MARK,
  141. SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
  142. SIM_D_MARK, PORT31_IROUT_MARK,
  143. SCIFA4_TXD_MARK,
  144. SCIFA4_RXD_MARK, XWUP_MARK,
  145. SCIFA4_RTS__MARK,
  146. SCIFA4_CTS__MARK,
  147. FSIBOBT_MARK, FSIBIBT_MARK,
  148. FSIBOLR_MARK, FSIBILR_MARK,
  149. FSIBOSLD_MARK,
  150. FSIBISLD_MARK,
  151. VACK_MARK,
  152. XTAL1L_MARK,
  153. SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
  154. SCIFA0_RXD_MARK,
  155. SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
  156. FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
  157. FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
  158. FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
  159. FSICISLD_MARK, FSIDISLD_MARK,
  160. FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
  161. FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
  162. FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
  163. FSIAOSLD_MARK, BBIF2_TXD2_MARK,
  164. FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
  165. PORT53_FSICSPDIF_MARK,
  166. FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
  167. FSICCK_MARK, FSICOMC_MARK,
  168. FSIAISLD_MARK, TPU0TO0_MARK,
  169. A0_MARK, BS__MARK,
  170. A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
  171. A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
  172. A14_MARK, KEYOUT5_MARK,
  173. A15_MARK, KEYOUT4_MARK,
  174. A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
  175. A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
  176. A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
  177. A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
  178. A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
  179. A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
  180. A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
  181. A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
  182. A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
  183. A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
  184. A26_MARK, KEYIN6_MARK,
  185. KEYIN7_MARK,
  186. D0_NAF0_MARK,
  187. D1_NAF1_MARK,
  188. D2_NAF2_MARK,
  189. D3_NAF3_MARK,
  190. D4_NAF4_MARK,
  191. D5_NAF5_MARK,
  192. D6_NAF6_MARK,
  193. D7_NAF7_MARK,
  194. D8_NAF8_MARK,
  195. D9_NAF9_MARK,
  196. D10_NAF10_MARK,
  197. D11_NAF11_MARK,
  198. D12_NAF12_MARK,
  199. D13_NAF13_MARK,
  200. D14_NAF14_MARK,
  201. D15_NAF15_MARK,
  202. CS4__MARK,
  203. CS5A__MARK, PORT91_RDWR_MARK,
  204. CS5B__MARK, FCE1__MARK,
  205. CS6B__MARK, DACK0_MARK,
  206. FCE0__MARK, CS6A__MARK,
  207. WAIT__MARK, DREQ0_MARK,
  208. RD__FSC_MARK,
  209. WE0__FWE_MARK, RDWR_FWE_MARK,
  210. WE1__MARK,
  211. FRB_MARK,
  212. CKO_MARK,
  213. NBRSTOUT__MARK,
  214. NBRST__MARK,
  215. BBIF2_TXD_MARK,
  216. BBIF2_RXD_MARK,
  217. BBIF2_SYNC_MARK,
  218. BBIF2_SCK_MARK,
  219. SCIFA3_CTS__MARK, MFG3_IN2_MARK,
  220. SCIFA3_RXD_MARK, MFG3_IN1_MARK,
  221. BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
  222. SCIFA3_TXD_MARK,
  223. HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
  224. HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
  225. HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
  226. HSI_TX_READY_MARK, BBIF1_TXD_MARK,
  227. HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
  228. PORT115_I2C_SCL3_MARK,
  229. HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
  230. PORT116_I2C_SDA3_MARK,
  231. HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
  232. HSI_TX_FLAG_MARK,
  233. VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
  234. VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
  235. VIO2_HD_MARK, LCD2D1_MARK,
  236. VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
  237. VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
  238. PORT131_KEYOUT11_MARK, LCD2D11_MARK,
  239. VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
  240. PORT132_KEYOUT10_MARK, LCD2D12_MARK,
  241. VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
  242. VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
  243. VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
  244. VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
  245. VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
  246. VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
  247. VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
  248. VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
  249. VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
  250. VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
  251. VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
  252. VIO2_D5_MARK, LCD2D3_MARK,
  253. VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
  254. VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
  255. PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
  256. VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
  257. LCD2D18_MARK,
  258. VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
  259. VIO_CKO_MARK,
  260. A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
  261. MFG0_IN2_MARK,
  262. TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
  263. TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
  264. TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
  265. SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
  266. SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
  267. SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
  268. SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
  269. DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
  270. PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
  271. PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
  272. PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
  273. PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
  274. PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
  275. LCDD0_MARK,
  276. LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
  277. LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
  278. LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
  279. LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
  280. LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
  281. LCDD6_MARK,
  282. LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
  283. LCDD8_MARK, D16_MARK,
  284. LCDD9_MARK, D17_MARK,
  285. LCDD10_MARK, D18_MARK,
  286. LCDD11_MARK, D19_MARK,
  287. LCDD12_MARK, D20_MARK,
  288. LCDD13_MARK, D21_MARK,
  289. LCDD14_MARK, D22_MARK,
  290. LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
  291. LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
  292. LCDD17_MARK, D25_MARK,
  293. LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
  294. LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
  295. LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
  296. LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
  297. LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
  298. LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
  299. LCDDCK_MARK, LCDWR__MARK,
  300. LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
  301. VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
  302. LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
  303. PORT218_VIO_CKOR_MARK,
  304. LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
  305. MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
  306. LCDVSYN_MARK, LCDVSYN2_MARK,
  307. LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
  308. MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
  309. LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
  310. VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
  311. SCIFA1_TXD_MARK, OVCN2_MARK,
  312. EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
  313. SCIFA1_RTS__MARK, IDIN_MARK,
  314. SCIFA1_RXD_MARK,
  315. SCIFA1_CTS__MARK, MFG1_IN1_MARK,
  316. MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
  317. MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
  318. MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
  319. MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
  320. MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
  321. MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
  322. MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
  323. MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
  324. MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
  325. MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
  326. SCIFA6_TXD_MARK,
  327. PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
  328. PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
  329. PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
  330. PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
  331. MSIOF2R_RXD_MARK,
  332. PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
  333. MSIOF2R_TXD_MARK,
  334. PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
  335. TPU1TO0_MARK,
  336. PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
  337. TPU3TO1_MARK,
  338. PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
  339. TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
  340. PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
  341. MSIOF2R_TSYNC_MARK,
  342. SDHICLK0_MARK,
  343. SDHICD0_MARK,
  344. SDHID0_0_MARK,
  345. SDHID0_1_MARK,
  346. SDHID0_2_MARK,
  347. SDHID0_3_MARK,
  348. SDHICMD0_MARK,
  349. SDHIWP0_MARK,
  350. SDHICLK1_MARK,
  351. SDHID1_0_MARK, TS_SPSYNC2_MARK,
  352. SDHID1_1_MARK, TS_SDAT2_MARK,
  353. SDHID1_2_MARK, TS_SDEN2_MARK,
  354. SDHID1_3_MARK, TS_SCK2_MARK,
  355. SDHICMD1_MARK,
  356. SDHICLK2_MARK,
  357. SDHID2_0_MARK, TS_SPSYNC4_MARK,
  358. SDHID2_1_MARK, TS_SDAT4_MARK,
  359. SDHID2_2_MARK, TS_SDEN4_MARK,
  360. SDHID2_3_MARK, TS_SCK4_MARK,
  361. SDHICMD2_MARK,
  362. MMCCLK0_MARK,
  363. MMCD0_0_MARK,
  364. MMCD0_1_MARK,
  365. MMCD0_2_MARK,
  366. MMCD0_3_MARK,
  367. MMCD0_4_MARK, TS_SPSYNC5_MARK,
  368. MMCD0_5_MARK, TS_SDAT5_MARK,
  369. MMCD0_6_MARK, TS_SDEN5_MARK,
  370. MMCD0_7_MARK, TS_SCK5_MARK,
  371. MMCCMD0_MARK,
  372. RESETOUTS__MARK, EXTAL2OUT_MARK,
  373. MCP_WAIT__MCP_FRB_MARK,
  374. MCP_CKO_MARK, MMCCLK1_MARK,
  375. MCP_D15_MCP_NAF15_MARK,
  376. MCP_D14_MCP_NAF14_MARK,
  377. MCP_D13_MCP_NAF13_MARK,
  378. MCP_D12_MCP_NAF12_MARK,
  379. MCP_D11_MCP_NAF11_MARK,
  380. MCP_D10_MCP_NAF10_MARK,
  381. MCP_D9_MCP_NAF9_MARK,
  382. MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
  383. MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
  384. MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
  385. MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
  386. MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
  387. MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
  388. MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
  389. MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
  390. MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
  391. MCP_NBRSTOUT__MARK,
  392. MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
  393. /* MSEL2 special cases */
  394. TSIF2_TS_XX1_MARK,
  395. TSIF2_TS_XX2_MARK,
  396. TSIF2_TS_XX3_MARK,
  397. TSIF2_TS_XX4_MARK,
  398. TSIF2_TS_XX5_MARK,
  399. TSIF1_TS_XX1_MARK,
  400. TSIF1_TS_XX2_MARK,
  401. TSIF1_TS_XX3_MARK,
  402. TSIF1_TS_XX4_MARK,
  403. TSIF1_TS_XX5_MARK,
  404. TSIF0_TS_XX1_MARK,
  405. TSIF0_TS_XX2_MARK,
  406. TSIF0_TS_XX3_MARK,
  407. TSIF0_TS_XX4_MARK,
  408. TSIF0_TS_XX5_MARK,
  409. MST1_TS_XX1_MARK,
  410. MST1_TS_XX2_MARK,
  411. MST1_TS_XX3_MARK,
  412. MST1_TS_XX4_MARK,
  413. MST1_TS_XX5_MARK,
  414. MST0_TS_XX1_MARK,
  415. MST0_TS_XX2_MARK,
  416. MST0_TS_XX3_MARK,
  417. MST0_TS_XX4_MARK,
  418. MST0_TS_XX5_MARK,
  419. /* MSEL3 special cases */
  420. SDHI0_VCCQ_MC0_ON_MARK,
  421. SDHI0_VCCQ_MC0_OFF_MARK,
  422. DEBUG_MON_VIO_MARK,
  423. DEBUG_MON_LCDD_MARK,
  424. LCDC_LCDC0_MARK,
  425. LCDC_LCDC1_MARK,
  426. /* MSEL4 special cases */
  427. IRQ9_MEM_INT_MARK,
  428. IRQ9_MCP_INT_MARK,
  429. A11_MARK,
  430. KEYOUT8_MARK,
  431. TPU4TO3_MARK,
  432. RESETA_N_PU_ON_MARK,
  433. RESETA_N_PU_OFF_MARK,
  434. EDBGREQ_PD_MARK,
  435. EDBGREQ_PU_MARK,
  436. PINMUX_MARK_END,
  437. };
  438. static const u16 pinmux_data[] = {
  439. /* specify valid pin states for each pin in GPIO mode */
  440. PINMUX_DATA_ALL(),
  441. /* Table 25-1 (Function 0-7) */
  442. PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
  443. PINMUX_DATA(GPI0_MARK, PORT1_FN1),
  444. PINMUX_DATA(GPI1_MARK, PORT2_FN1),
  445. PINMUX_DATA(GPI2_MARK, PORT3_FN1),
  446. PINMUX_DATA(GPI3_MARK, PORT4_FN1),
  447. PINMUX_DATA(GPI4_MARK, PORT5_FN1),
  448. PINMUX_DATA(GPI5_MARK, PORT6_FN1),
  449. PINMUX_DATA(GPI6_MARK, PORT7_FN1),
  450. PINMUX_DATA(GPI7_MARK, PORT8_FN1),
  451. PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
  452. PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
  453. PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
  454. PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
  455. PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
  456. PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
  457. PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
  458. PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
  459. PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
  460. PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
  461. PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
  462. PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
  463. PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
  464. PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
  465. PINMUX_DATA(GPO0_MARK, PORT20_FN1),
  466. PINMUX_DATA(GPO1_MARK, PORT21_FN1),
  467. PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
  468. PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
  469. PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
  470. PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
  471. PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
  472. PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
  473. PINMUX_DATA(VINT_MARK, PORT25_FN1),
  474. PINMUX_DATA(TCKON_MARK, PORT26_FN1),
  475. PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
  476. PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
  477. MSEL2CR_MSEL16_1), \
  478. PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
  479. MSEL2CR_MSEL18_1), \
  480. PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
  481. PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
  482. PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
  483. PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
  484. MSEL2CR_MSEL16_1), \
  485. PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
  486. MSEL2CR_MSEL18_1), \
  487. PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
  488. PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
  489. PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
  490. PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
  491. PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
  492. PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
  493. PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
  494. PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
  495. PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
  496. PINMUX_DATA(XWUP_MARK, PORT33_FN3),
  497. PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
  498. PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
  499. PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
  500. PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
  501. PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
  502. PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
  503. PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
  504. PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
  505. PINMUX_DATA(VACK_MARK, PORT40_FN1),
  506. PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
  507. PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
  508. PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
  509. PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
  510. PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
  511. PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
  512. PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
  513. PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
  514. PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
  515. PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
  516. PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
  517. PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
  518. PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
  519. PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
  520. PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
  521. PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
  522. PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
  523. PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
  524. PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
  525. PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
  526. PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
  527. PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
  528. PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
  529. PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
  530. PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
  531. PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
  532. PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
  533. PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
  534. PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
  535. PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
  536. PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
  537. PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
  538. PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
  539. PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
  540. PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
  541. PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
  542. PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
  543. PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
  544. PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
  545. PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
  546. PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
  547. PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
  548. PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
  549. PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
  550. PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
  551. PINMUX_DATA(A0_MARK, PORT57_FN1), \
  552. PINMUX_DATA(BS__MARK, PORT57_FN2),
  553. PINMUX_DATA(A12_MARK, PORT58_FN1), \
  554. PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
  555. PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
  556. PINMUX_DATA(A13_MARK, PORT59_FN1), \
  557. PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
  558. PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
  559. PINMUX_DATA(A14_MARK, PORT60_FN1), \
  560. PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
  561. PINMUX_DATA(A15_MARK, PORT61_FN1), \
  562. PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
  563. PINMUX_DATA(A16_MARK, PORT62_FN1), \
  564. PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
  565. PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
  566. PINMUX_DATA(A17_MARK, PORT63_FN1), \
  567. PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
  568. PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
  569. PINMUX_DATA(A18_MARK, PORT64_FN1), \
  570. PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
  571. PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
  572. PINMUX_DATA(A19_MARK, PORT65_FN1), \
  573. PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
  574. PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
  575. PINMUX_DATA(A20_MARK, PORT66_FN1), \
  576. PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
  577. PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
  578. PINMUX_DATA(A21_MARK, PORT67_FN1), \
  579. PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
  580. PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
  581. PINMUX_DATA(A22_MARK, PORT68_FN1), \
  582. PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
  583. PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
  584. PINMUX_DATA(A23_MARK, PORT69_FN1), \
  585. PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
  586. PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
  587. PINMUX_DATA(A24_MARK, PORT70_FN1), \
  588. PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
  589. PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
  590. PINMUX_DATA(A25_MARK, PORT71_FN1), \
  591. PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
  592. PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
  593. PINMUX_DATA(A26_MARK, PORT72_FN1), \
  594. PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
  595. PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
  596. PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
  597. PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
  598. PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
  599. PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
  600. PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
  601. PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
  602. PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
  603. PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
  604. PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
  605. PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
  606. PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
  607. PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
  608. PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
  609. PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
  610. PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
  611. PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
  612. PINMUX_DATA(CS4__MARK, PORT90_FN1),
  613. PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
  614. PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
  615. PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
  616. PINMUX_DATA(FCE1__MARK, PORT92_FN2),
  617. PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
  618. PINMUX_DATA(DACK0_MARK, PORT93_FN4),
  619. PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
  620. PINMUX_DATA(CS6A__MARK, PORT94_FN2),
  621. PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
  622. PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
  623. PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
  624. PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
  625. PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
  626. PINMUX_DATA(WE1__MARK, PORT98_FN1),
  627. PINMUX_DATA(FRB_MARK, PORT99_FN1),
  628. PINMUX_DATA(CKO_MARK, PORT100_FN1),
  629. PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
  630. PINMUX_DATA(NBRST__MARK, PORT102_FN1),
  631. PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
  632. PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
  633. PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
  634. PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
  635. PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
  636. PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
  637. PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
  638. PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
  639. PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
  640. PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
  641. PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
  642. PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
  643. PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
  644. PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
  645. PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
  646. PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
  647. PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
  648. PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
  649. PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
  650. PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
  651. PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
  652. PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
  653. PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
  654. PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
  655. PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
  656. PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
  657. PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
  658. PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
  659. PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
  660. PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
  661. PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
  662. PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
  663. PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
  664. PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
  665. PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
  666. PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
  667. PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
  668. PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
  669. PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
  670. PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
  671. PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
  672. PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
  673. PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
  674. MSEL4CR_MSEL10_1), \
  675. PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
  676. PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
  677. PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
  678. PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
  679. PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
  680. PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
  681. PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
  682. PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
  683. PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
  684. PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
  685. PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
  686. PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
  687. PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
  688. PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
  689. PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
  690. PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
  691. PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
  692. PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
  693. PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
  694. PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
  695. PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
  696. PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
  697. PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
  698. PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
  699. PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
  700. PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
  701. PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
  702. PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
  703. PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
  704. PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
  705. PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
  706. PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
  707. PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
  708. PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
  709. PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
  710. PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
  711. PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
  712. PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
  713. PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
  714. PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
  715. PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
  716. PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
  717. PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
  718. PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
  719. PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
  720. PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
  721. PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
  722. PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
  723. PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
  724. PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
  725. PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
  726. PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
  727. PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
  728. PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
  729. PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
  730. PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
  731. PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
  732. PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
  733. PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
  734. PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
  735. PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
  736. PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
  737. PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
  738. PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
  739. PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
  740. PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
  741. PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
  742. PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
  743. PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
  744. PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
  745. PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
  746. PINMUX_DATA(A27_MARK, PORT149_FN1), \
  747. PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
  748. PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
  749. PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
  750. PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
  751. PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
  752. PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
  753. PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
  754. PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
  755. PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
  756. PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
  757. PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
  758. PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
  759. PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
  760. PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
  761. PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
  762. PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
  763. PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
  764. PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
  765. PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
  766. MSEL4CR_MSEL10_0),
  767. PINMUX_DATA(DINT__MARK, PORT158_FN1), \
  768. PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
  769. PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
  770. PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
  771. PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
  772. PINMUX_DATA(NMI_MARK, PORT159_FN3),
  773. PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
  774. PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
  775. PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
  776. PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
  777. PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
  778. PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
  779. PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
  780. PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
  781. PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
  782. PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
  783. PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
  784. PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
  785. MSEL4CR_MSEL20_1), \
  786. PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
  787. PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
  788. PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
  789. MSEL4CR_MSEL20_1), \
  790. PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
  791. PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
  792. PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
  793. MSEL4CR_MSEL20_1), \
  794. PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
  795. PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
  796. PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
  797. MSEL4CR_MSEL20_1),
  798. PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
  799. PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
  800. MSEL4CR_MSEL20_1), \
  801. PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
  802. PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
  803. PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
  804. PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
  805. PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
  806. PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
  807. PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
  808. PINMUX_DATA(D16_MARK, PORT200_FN6),
  809. PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
  810. PINMUX_DATA(D17_MARK, PORT201_FN6),
  811. PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
  812. PINMUX_DATA(D18_MARK, PORT202_FN6),
  813. PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
  814. PINMUX_DATA(D19_MARK, PORT203_FN6),
  815. PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
  816. PINMUX_DATA(D20_MARK, PORT204_FN6),
  817. PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
  818. PINMUX_DATA(D21_MARK, PORT205_FN6),
  819. PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
  820. PINMUX_DATA(D22_MARK, PORT206_FN6),
  821. PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
  822. PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
  823. PINMUX_DATA(D23_MARK, PORT207_FN6),
  824. PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
  825. PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
  826. PINMUX_DATA(D24_MARK, PORT208_FN6),
  827. PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
  828. PINMUX_DATA(D25_MARK, PORT209_FN6),
  829. PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
  830. PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
  831. PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
  832. PINMUX_DATA(D26_MARK, PORT210_FN6),
  833. PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
  834. PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
  835. PINMUX_DATA(D27_MARK, PORT211_FN6),
  836. PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
  837. PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
  838. PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
  839. PINMUX_DATA(D28_MARK, PORT212_FN6),
  840. PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
  841. PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
  842. PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
  843. PINMUX_DATA(D29_MARK, PORT213_FN6),
  844. PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
  845. PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
  846. PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
  847. PINMUX_DATA(D30_MARK, PORT214_FN6),
  848. PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
  849. PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
  850. PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
  851. PINMUX_DATA(D31_MARK, PORT215_FN6),
  852. PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
  853. PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
  854. PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
  855. PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
  856. PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
  857. PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
  858. PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
  859. MSEL4CR_MSEL26_1), \
  860. PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
  861. PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
  862. PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
  863. PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
  864. PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
  865. PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
  866. PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
  867. PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
  868. PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
  869. PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
  870. PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
  871. PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
  872. MSEL4CR_MSEL26_1), \
  873. PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
  874. PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
  875. PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
  876. PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
  877. PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
  878. PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
  879. PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
  880. PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
  881. PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
  882. MSEL4CR_MSEL26_1), \
  883. PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
  884. PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
  885. PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
  886. PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
  887. PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
  888. PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
  889. PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
  890. MSEL4CR_MSEL26_1), \
  891. PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
  892. PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
  893. PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
  894. PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
  895. PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
  896. PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
  897. PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
  898. PINMUX_DATA(IDIN_MARK, PORT227_FN4),
  899. PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
  900. PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
  901. PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
  902. PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
  903. PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
  904. PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
  905. PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
  906. PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
  907. PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
  908. PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
  909. PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
  910. PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
  911. PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
  912. PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
  913. MSEL4CR_MSEL26_0), \
  914. PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
  915. PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
  916. PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
  917. PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
  918. MSEL4CR_MSEL26_0), \
  919. PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
  920. PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
  921. PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
  922. MSEL2CR_MSEL16_0),
  923. PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
  924. PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
  925. MSEL2CR_MSEL16_0),
  926. PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
  927. PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
  928. MSEL4CR_MSEL26_0), \
  929. PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
  930. PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
  931. PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
  932. MSEL4CR_MSEL26_0), \
  933. PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
  934. PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
  935. PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
  936. PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
  937. PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
  938. PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
  939. PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
  940. PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
  941. PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
  942. PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
  943. PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
  944. MSEL4CR_MSEL20_0), \
  945. PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
  946. PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
  947. PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
  948. PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
  949. MSEL4CR_MSEL20_0), \
  950. PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
  951. PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
  952. PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
  953. PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
  954. MSEL4CR_MSEL20_0), \
  955. PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
  956. PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
  957. PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
  958. PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
  959. MSEL4CR_MSEL20_0), \
  960. PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
  961. PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
  962. PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
  963. PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
  964. MSEL4CR_MSEL20_0), \
  965. PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
  966. PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
  967. PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
  968. PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
  969. MSEL2CR_MSEL18_0), \
  970. PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
  971. PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
  972. PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
  973. PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
  974. MSEL2CR_MSEL18_0), \
  975. PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
  976. PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
  977. PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
  978. PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
  979. PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
  980. PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
  981. PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
  982. PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
  983. PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
  984. PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
  985. PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
  986. PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
  987. PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
  988. PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
  989. PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
  990. PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
  991. PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
  992. PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
  993. PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
  994. PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
  995. PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
  996. PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
  997. PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
  998. PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
  999. PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
  1000. PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
  1001. PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
  1002. PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
  1003. PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
  1004. PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
  1005. PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
  1006. PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
  1007. PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
  1008. PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
  1009. PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
  1010. PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
  1011. PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
  1012. PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
  1013. PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
  1014. PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
  1015. PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
  1016. PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
  1017. PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
  1018. PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
  1019. PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
  1020. PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
  1021. PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
  1022. PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
  1023. PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
  1024. PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
  1025. PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
  1026. PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
  1027. PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
  1028. PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
  1029. PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
  1030. PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
  1031. PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
  1032. PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
  1033. PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
  1034. PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
  1035. PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
  1036. PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
  1037. PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
  1038. PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
  1039. PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
  1040. PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
  1041. PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
  1042. PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
  1043. PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
  1044. PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
  1045. PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
  1046. PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
  1047. PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
  1048. PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
  1049. PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
  1050. PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
  1051. /* MSEL2 special cases */
  1052. PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
  1053. MSEL2CR_MSEL12_0),
  1054. PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
  1055. MSEL2CR_MSEL12_1),
  1056. PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
  1057. MSEL2CR_MSEL12_0),
  1058. PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
  1059. MSEL2CR_MSEL12_1),
  1060. PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
  1061. MSEL2CR_MSEL12_0),
  1062. PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
  1063. MSEL2CR_MSEL9_0),
  1064. PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
  1065. MSEL2CR_MSEL9_1),
  1066. PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
  1067. MSEL2CR_MSEL9_0),
  1068. PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
  1069. MSEL2CR_MSEL9_1),
  1070. PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
  1071. MSEL2CR_MSEL9_0),
  1072. PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
  1073. MSEL2CR_MSEL6_0),
  1074. PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
  1075. MSEL2CR_MSEL6_1),
  1076. PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
  1077. MSEL2CR_MSEL6_0),
  1078. PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
  1079. MSEL2CR_MSEL6_1),
  1080. PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
  1081. MSEL2CR_MSEL6_0),
  1082. PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
  1083. MSEL2CR_MSEL3_0),
  1084. PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
  1085. MSEL2CR_MSEL3_1),
  1086. PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
  1087. MSEL2CR_MSEL3_0),
  1088. PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
  1089. MSEL2CR_MSEL3_1),
  1090. PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
  1091. MSEL2CR_MSEL3_0),
  1092. PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
  1093. MSEL2CR_MSEL0_0),
  1094. PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
  1095. MSEL2CR_MSEL0_1),
  1096. PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
  1097. MSEL2CR_MSEL0_0),
  1098. PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
  1099. MSEL2CR_MSEL0_1),
  1100. PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
  1101. MSEL2CR_MSEL0_0),
  1102. /* MSEL3 special cases */
  1103. PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
  1104. PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
  1105. PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
  1106. PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
  1107. PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
  1108. PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
  1109. /* MSEL4 special cases */
  1110. PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
  1111. PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
  1112. PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
  1113. PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
  1114. PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
  1115. PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
  1116. PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
  1117. PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
  1118. PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
  1119. };
  1120. #define __I (SH_PFC_PIN_CFG_INPUT)
  1121. #define __O (SH_PFC_PIN_CFG_OUTPUT)
  1122. #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
  1123. #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
  1124. #define __PU (SH_PFC_PIN_CFG_PULL_UP)
  1125. #define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
  1126. #define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
  1127. #define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
  1128. #define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
  1129. #define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
  1130. #define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
  1131. #define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
  1132. #define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
  1133. #define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
  1134. /*
  1135. * Pins not associated with a GPIO port.
  1136. */
  1137. enum {
  1138. PORT_ASSIGN_LAST(),
  1139. NOGP_ALL(),
  1140. };
  1141. static const struct sh_pfc_pin pinmux_pins[] = {
  1142. /* Table 25-1 (I/O and Pull U/D) */
  1143. SH73A0_PIN_I_PD(0),
  1144. SH73A0_PIN_I_PU(1),
  1145. SH73A0_PIN_I_PU(2),
  1146. SH73A0_PIN_I_PU(3),
  1147. SH73A0_PIN_I_PU(4),
  1148. SH73A0_PIN_I_PU(5),
  1149. SH73A0_PIN_I_PU(6),
  1150. SH73A0_PIN_I_PU(7),
  1151. SH73A0_PIN_I_PU(8),
  1152. SH73A0_PIN_I_PD(9),
  1153. SH73A0_PIN_I_PD(10),
  1154. SH73A0_PIN_I_PU_PD(11),
  1155. SH73A0_PIN_IO_PU_PD(12),
  1156. SH73A0_PIN_IO_PU_PD(13),
  1157. SH73A0_PIN_IO_PU_PD(14),
  1158. SH73A0_PIN_IO_PU_PD(15),
  1159. SH73A0_PIN_IO_PD(16),
  1160. SH73A0_PIN_IO_PD(17),
  1161. SH73A0_PIN_IO_PU(18),
  1162. SH73A0_PIN_IO_PU(19),
  1163. SH73A0_PIN_O(20),
  1164. SH73A0_PIN_O(21),
  1165. SH73A0_PIN_O(22),
  1166. SH73A0_PIN_O(23),
  1167. SH73A0_PIN_O(24),
  1168. SH73A0_PIN_I_PD(25),
  1169. SH73A0_PIN_I_PD(26),
  1170. SH73A0_PIN_IO_PU(27),
  1171. SH73A0_PIN_IO_PU(28),
  1172. SH73A0_PIN_IO_PD(29),
  1173. SH73A0_PIN_IO_PD(30),
  1174. SH73A0_PIN_IO_PU(31),
  1175. SH73A0_PIN_IO_PD(32),
  1176. SH73A0_PIN_I_PU_PD(33),
  1177. SH73A0_PIN_IO_PD(34),
  1178. SH73A0_PIN_I_PU_PD(35),
  1179. SH73A0_PIN_IO_PD(36),
  1180. SH73A0_PIN_IO(37),
  1181. SH73A0_PIN_O(38),
  1182. SH73A0_PIN_I_PU(39),
  1183. SH73A0_PIN_I_PU_PD(40),
  1184. SH73A0_PIN_O(41),
  1185. SH73A0_PIN_IO_PD(42),
  1186. SH73A0_PIN_IO_PU_PD(43),
  1187. SH73A0_PIN_IO_PU_PD(44),
  1188. SH73A0_PIN_IO_PD(45),
  1189. SH73A0_PIN_IO_PD(46),
  1190. SH73A0_PIN_IO_PD(47),
  1191. SH73A0_PIN_I_PD(48),
  1192. SH73A0_PIN_IO_PU_PD(49),
  1193. SH73A0_PIN_IO_PD(50),
  1194. SH73A0_PIN_IO_PD(51),
  1195. SH73A0_PIN_O(52),
  1196. SH73A0_PIN_IO_PU_PD(53),
  1197. SH73A0_PIN_IO_PU_PD(54),
  1198. SH73A0_PIN_IO_PD(55),
  1199. SH73A0_PIN_I_PU_PD(56),
  1200. SH73A0_PIN_IO(57),
  1201. SH73A0_PIN_IO(58),
  1202. SH73A0_PIN_IO(59),
  1203. SH73A0_PIN_IO(60),
  1204. SH73A0_PIN_IO(61),
  1205. SH73A0_PIN_IO_PD(62),
  1206. SH73A0_PIN_IO_PD(63),
  1207. SH73A0_PIN_IO_PU_PD(64),
  1208. SH73A0_PIN_IO_PD(65),
  1209. SH73A0_PIN_IO_PU_PD(66),
  1210. SH73A0_PIN_IO_PU_PD(67),
  1211. SH73A0_PIN_IO_PU_PD(68),
  1212. SH73A0_PIN_IO_PU_PD(69),
  1213. SH73A0_PIN_IO_PU_PD(70),
  1214. SH73A0_PIN_IO_PU_PD(71),
  1215. SH73A0_PIN_IO_PU_PD(72),
  1216. SH73A0_PIN_I_PU_PD(73),
  1217. SH73A0_PIN_IO_PU(74),
  1218. SH73A0_PIN_IO_PU(75),
  1219. SH73A0_PIN_IO_PU(76),
  1220. SH73A0_PIN_IO_PU(77),
  1221. SH73A0_PIN_IO_PU(78),
  1222. SH73A0_PIN_IO_PU(79),
  1223. SH73A0_PIN_IO_PU(80),
  1224. SH73A0_PIN_IO_PU(81),
  1225. SH73A0_PIN_IO_PU(82),
  1226. SH73A0_PIN_IO_PU(83),
  1227. SH73A0_PIN_IO_PU(84),
  1228. SH73A0_PIN_IO_PU(85),
  1229. SH73A0_PIN_IO_PU(86),
  1230. SH73A0_PIN_IO_PU(87),
  1231. SH73A0_PIN_IO_PU(88),
  1232. SH73A0_PIN_IO_PU(89),
  1233. SH73A0_PIN_O(90),
  1234. SH73A0_PIN_IO_PU(91),
  1235. SH73A0_PIN_O(92),
  1236. SH73A0_PIN_IO_PU(93),
  1237. SH73A0_PIN_O(94),
  1238. SH73A0_PIN_I_PU_PD(95),
  1239. SH73A0_PIN_IO(96),
  1240. SH73A0_PIN_IO(97),
  1241. SH73A0_PIN_IO(98),
  1242. SH73A0_PIN_I_PU(99),
  1243. SH73A0_PIN_O(100),
  1244. SH73A0_PIN_O(101),
  1245. SH73A0_PIN_I_PU(102),
  1246. SH73A0_PIN_IO_PD(103),
  1247. SH73A0_PIN_I_PU_PD(104),
  1248. SH73A0_PIN_I_PD(105),
  1249. SH73A0_PIN_I_PD(106),
  1250. SH73A0_PIN_I_PU_PD(107),
  1251. SH73A0_PIN_I_PU_PD(108),
  1252. SH73A0_PIN_IO_PD(109),
  1253. SH73A0_PIN_IO_PD(110),
  1254. SH73A0_PIN_IO_PU_PD(111),
  1255. SH73A0_PIN_IO_PU_PD(112),
  1256. SH73A0_PIN_IO_PU_PD(113),
  1257. SH73A0_PIN_IO_PD(114),
  1258. SH73A0_PIN_IO_PU(115),
  1259. SH73A0_PIN_IO_PU(116),
  1260. SH73A0_PIN_IO_PU_PD(117),
  1261. SH73A0_PIN_IO_PU_PD(118),
  1262. SH73A0_PIN_IO_PD(128),
  1263. SH73A0_PIN_IO_PD(129),
  1264. SH73A0_PIN_IO_PU_PD(130),
  1265. SH73A0_PIN_IO_PD(131),
  1266. SH73A0_PIN_IO_PD(132),
  1267. SH73A0_PIN_IO_PD(133),
  1268. SH73A0_PIN_IO_PU_PD(134),
  1269. SH73A0_PIN_IO_PU_PD(135),
  1270. SH73A0_PIN_IO_PU_PD(136),
  1271. SH73A0_PIN_IO_PU_PD(137),
  1272. SH73A0_PIN_IO_PD(138),
  1273. SH73A0_PIN_IO_PD(139),
  1274. SH73A0_PIN_IO_PD(140),
  1275. SH73A0_PIN_IO_PD(141),
  1276. SH73A0_PIN_IO_PD(142),
  1277. SH73A0_PIN_IO_PD(143),
  1278. SH73A0_PIN_IO_PU_PD(144),
  1279. SH73A0_PIN_IO_PD(145),
  1280. SH73A0_PIN_IO_PU_PD(146),
  1281. SH73A0_PIN_IO_PU_PD(147),
  1282. SH73A0_PIN_IO_PU_PD(148),
  1283. SH73A0_PIN_IO_PU_PD(149),
  1284. SH73A0_PIN_I_PU_PD(150),
  1285. SH73A0_PIN_IO_PU_PD(151),
  1286. SH73A0_PIN_IO_PU_PD(152),
  1287. SH73A0_PIN_IO_PD(153),
  1288. SH73A0_PIN_IO_PD(154),
  1289. SH73A0_PIN_I_PU_PD(155),
  1290. SH73A0_PIN_IO_PU_PD(156),
  1291. SH73A0_PIN_I_PD(157),
  1292. SH73A0_PIN_IO_PD(158),
  1293. SH73A0_PIN_IO_PU_PD(159),
  1294. SH73A0_PIN_IO_PU_PD(160),
  1295. SH73A0_PIN_I_PU_PD(161),
  1296. SH73A0_PIN_I_PU_PD(162),
  1297. SH73A0_PIN_IO_PU_PD(163),
  1298. SH73A0_PIN_I_PU_PD(164),
  1299. SH73A0_PIN_IO_PD(192),
  1300. SH73A0_PIN_IO_PU_PD(193),
  1301. SH73A0_PIN_IO_PD(194),
  1302. SH73A0_PIN_IO_PU_PD(195),
  1303. SH73A0_PIN_IO_PD(196),
  1304. SH73A0_PIN_IO_PD(197),
  1305. SH73A0_PIN_IO_PD(198),
  1306. SH73A0_PIN_IO_PD(199),
  1307. SH73A0_PIN_IO_PU_PD(200),
  1308. SH73A0_PIN_IO_PU_PD(201),
  1309. SH73A0_PIN_IO_PU_PD(202),
  1310. SH73A0_PIN_IO_PU_PD(203),
  1311. SH73A0_PIN_IO_PU_PD(204),
  1312. SH73A0_PIN_IO_PU_PD(205),
  1313. SH73A0_PIN_IO_PU_PD(206),
  1314. SH73A0_PIN_IO_PD(207),
  1315. SH73A0_PIN_IO_PD(208),
  1316. SH73A0_PIN_IO_PD(209),
  1317. SH73A0_PIN_IO_PD(210),
  1318. SH73A0_PIN_IO_PD(211),
  1319. SH73A0_PIN_IO_PD(212),
  1320. SH73A0_PIN_IO_PD(213),
  1321. SH73A0_PIN_IO_PU_PD(214),
  1322. SH73A0_PIN_IO_PU_PD(215),
  1323. SH73A0_PIN_IO_PD(216),
  1324. SH73A0_PIN_IO_PD(217),
  1325. SH73A0_PIN_O(218),
  1326. SH73A0_PIN_IO_PD(219),
  1327. SH73A0_PIN_IO_PD(220),
  1328. SH73A0_PIN_IO_PU_PD(221),
  1329. SH73A0_PIN_IO_PU_PD(222),
  1330. SH73A0_PIN_I_PU_PD(223),
  1331. SH73A0_PIN_I_PU_PD(224),
  1332. SH73A0_PIN_IO_PU_PD(225),
  1333. SH73A0_PIN_O(226),
  1334. SH73A0_PIN_IO_PU_PD(227),
  1335. SH73A0_PIN_I_PU_PD(228),
  1336. SH73A0_PIN_I_PD(229),
  1337. SH73A0_PIN_IO(230),
  1338. SH73A0_PIN_IO_PU_PD(231),
  1339. SH73A0_PIN_IO_PU_PD(232),
  1340. SH73A0_PIN_I_PU_PD(233),
  1341. SH73A0_PIN_IO_PU_PD(234),
  1342. SH73A0_PIN_IO_PU_PD(235),
  1343. SH73A0_PIN_IO_PU_PD(236),
  1344. SH73A0_PIN_IO_PD(237),
  1345. SH73A0_PIN_IO_PU_PD(238),
  1346. SH73A0_PIN_IO_PU_PD(239),
  1347. SH73A0_PIN_IO_PU_PD(240),
  1348. SH73A0_PIN_O(241),
  1349. SH73A0_PIN_I_PD(242),
  1350. SH73A0_PIN_IO_PU_PD(243),
  1351. SH73A0_PIN_IO_PU_PD(244),
  1352. SH73A0_PIN_IO_PU_PD(245),
  1353. SH73A0_PIN_IO_PU_PD(246),
  1354. SH73A0_PIN_IO_PU_PD(247),
  1355. SH73A0_PIN_IO_PU_PD(248),
  1356. SH73A0_PIN_IO_PU_PD(249),
  1357. SH73A0_PIN_IO_PU_PD(250),
  1358. SH73A0_PIN_IO_PU_PD(251),
  1359. SH73A0_PIN_IO_PU_PD(252),
  1360. SH73A0_PIN_IO_PU_PD(253),
  1361. SH73A0_PIN_IO_PU_PD(254),
  1362. SH73A0_PIN_IO_PU_PD(255),
  1363. SH73A0_PIN_IO_PU_PD(256),
  1364. SH73A0_PIN_IO_PU_PD(257),
  1365. SH73A0_PIN_IO_PU_PD(258),
  1366. SH73A0_PIN_IO_PU_PD(259),
  1367. SH73A0_PIN_IO_PU_PD(260),
  1368. SH73A0_PIN_IO_PU_PD(261),
  1369. SH73A0_PIN_IO_PU_PD(262),
  1370. SH73A0_PIN_IO_PU_PD(263),
  1371. SH73A0_PIN_IO_PU_PD(264),
  1372. SH73A0_PIN_IO_PU_PD(265),
  1373. SH73A0_PIN_IO_PU_PD(266),
  1374. SH73A0_PIN_IO_PU_PD(267),
  1375. SH73A0_PIN_IO_PU_PD(268),
  1376. SH73A0_PIN_IO_PU_PD(269),
  1377. SH73A0_PIN_IO_PU_PD(270),
  1378. SH73A0_PIN_IO_PU_PD(271),
  1379. SH73A0_PIN_IO_PU_PD(272),
  1380. SH73A0_PIN_IO_PU_PD(273),
  1381. SH73A0_PIN_IO_PU_PD(274),
  1382. SH73A0_PIN_IO_PU_PD(275),
  1383. SH73A0_PIN_IO_PU_PD(276),
  1384. SH73A0_PIN_IO_PU_PD(277),
  1385. SH73A0_PIN_IO_PU_PD(278),
  1386. SH73A0_PIN_IO_PU_PD(279),
  1387. SH73A0_PIN_IO_PU_PD(280),
  1388. SH73A0_PIN_O(281),
  1389. SH73A0_PIN_O(282),
  1390. SH73A0_PIN_I_PU(288),
  1391. SH73A0_PIN_IO_PU_PD(289),
  1392. SH73A0_PIN_IO_PU_PD(290),
  1393. SH73A0_PIN_IO_PU_PD(291),
  1394. SH73A0_PIN_IO_PU_PD(292),
  1395. SH73A0_PIN_IO_PU_PD(293),
  1396. SH73A0_PIN_IO_PU_PD(294),
  1397. SH73A0_PIN_IO_PU_PD(295),
  1398. SH73A0_PIN_IO_PU_PD(296),
  1399. SH73A0_PIN_IO_PU_PD(297),
  1400. SH73A0_PIN_IO_PU_PD(298),
  1401. SH73A0_PIN_IO_PU_PD(299),
  1402. SH73A0_PIN_IO_PU_PD(300),
  1403. SH73A0_PIN_IO_PU_PD(301),
  1404. SH73A0_PIN_IO_PU_PD(302),
  1405. SH73A0_PIN_IO_PU_PD(303),
  1406. SH73A0_PIN_IO_PU_PD(304),
  1407. SH73A0_PIN_IO_PU_PD(305),
  1408. SH73A0_PIN_O(306),
  1409. SH73A0_PIN_O(307),
  1410. SH73A0_PIN_I_PU(308),
  1411. SH73A0_PIN_O(309),
  1412. /* Pins not associated with a GPIO port */
  1413. PINMUX_NOGP_ALL(),
  1414. };
  1415. /* - BSC -------------------------------------------------------------------- */
  1416. static const unsigned int bsc_data_0_7_pins[] = {
  1417. /* D[0:7] */
  1418. 74, 75, 76, 77, 78, 79, 80, 81,
  1419. };
  1420. static const unsigned int bsc_data_0_7_mux[] = {
  1421. D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
  1422. D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
  1423. };
  1424. static const unsigned int bsc_data_8_15_pins[] = {
  1425. /* D[8:15] */
  1426. 82, 83, 84, 85, 86, 87, 88, 89,
  1427. };
  1428. static const unsigned int bsc_data_8_15_mux[] = {
  1429. D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
  1430. D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
  1431. };
  1432. static const unsigned int bsc_cs4_pins[] = {
  1433. /* CS */
  1434. 90,
  1435. };
  1436. static const unsigned int bsc_cs4_mux[] = {
  1437. CS4__MARK,
  1438. };
  1439. static const unsigned int bsc_cs5_a_pins[] = {
  1440. /* CS */
  1441. 91,
  1442. };
  1443. static const unsigned int bsc_cs5_a_mux[] = {
  1444. CS5A__MARK,
  1445. };
  1446. static const unsigned int bsc_cs5_b_pins[] = {
  1447. /* CS */
  1448. 92,
  1449. };
  1450. static const unsigned int bsc_cs5_b_mux[] = {
  1451. CS5B__MARK,
  1452. };
  1453. static const unsigned int bsc_cs6_a_pins[] = {
  1454. /* CS */
  1455. 94,
  1456. };
  1457. static const unsigned int bsc_cs6_a_mux[] = {
  1458. CS6A__MARK,
  1459. };
  1460. static const unsigned int bsc_cs6_b_pins[] = {
  1461. /* CS */
  1462. 93,
  1463. };
  1464. static const unsigned int bsc_cs6_b_mux[] = {
  1465. CS6B__MARK,
  1466. };
  1467. static const unsigned int bsc_rd_pins[] = {
  1468. /* RD */
  1469. 96,
  1470. };
  1471. static const unsigned int bsc_rd_mux[] = {
  1472. RD__FSC_MARK,
  1473. };
  1474. static const unsigned int bsc_rdwr_0_pins[] = {
  1475. /* RDWR */
  1476. 91,
  1477. };
  1478. static const unsigned int bsc_rdwr_0_mux[] = {
  1479. PORT91_RDWR_MARK,
  1480. };
  1481. static const unsigned int bsc_rdwr_1_pins[] = {
  1482. /* RDWR */
  1483. 97,
  1484. };
  1485. static const unsigned int bsc_rdwr_1_mux[] = {
  1486. RDWR_FWE_MARK,
  1487. };
  1488. static const unsigned int bsc_rdwr_2_pins[] = {
  1489. /* RDWR */
  1490. 149,
  1491. };
  1492. static const unsigned int bsc_rdwr_2_mux[] = {
  1493. PORT149_RDWR_MARK,
  1494. };
  1495. static const unsigned int bsc_we0_pins[] = {
  1496. /* WE0 */
  1497. 97,
  1498. };
  1499. static const unsigned int bsc_we0_mux[] = {
  1500. WE0__FWE_MARK,
  1501. };
  1502. static const unsigned int bsc_we1_pins[] = {
  1503. /* WE1 */
  1504. 98,
  1505. };
  1506. static const unsigned int bsc_we1_mux[] = {
  1507. WE1__MARK,
  1508. };
  1509. /* - FSIA ------------------------------------------------------------------- */
  1510. static const unsigned int fsia_mclk_in_pins[] = {
  1511. /* CK */
  1512. 49,
  1513. };
  1514. static const unsigned int fsia_mclk_in_mux[] = {
  1515. FSIACK_MARK,
  1516. };
  1517. static const unsigned int fsia_mclk_out_pins[] = {
  1518. /* OMC */
  1519. 49,
  1520. };
  1521. static const unsigned int fsia_mclk_out_mux[] = {
  1522. FSIAOMC_MARK,
  1523. };
  1524. static const unsigned int fsia_sclk_in_pins[] = {
  1525. /* ILR, IBT */
  1526. 50, 51,
  1527. };
  1528. static const unsigned int fsia_sclk_in_mux[] = {
  1529. FSIAILR_MARK, FSIAIBT_MARK,
  1530. };
  1531. static const unsigned int fsia_sclk_out_pins[] = {
  1532. /* OLR, OBT */
  1533. 50, 51,
  1534. };
  1535. static const unsigned int fsia_sclk_out_mux[] = {
  1536. FSIAOLR_MARK, FSIAOBT_MARK,
  1537. };
  1538. static const unsigned int fsia_data_in_pins[] = {
  1539. /* ISLD */
  1540. 55,
  1541. };
  1542. static const unsigned int fsia_data_in_mux[] = {
  1543. FSIAISLD_MARK,
  1544. };
  1545. static const unsigned int fsia_data_out_pins[] = {
  1546. /* OSLD */
  1547. 52,
  1548. };
  1549. static const unsigned int fsia_data_out_mux[] = {
  1550. FSIAOSLD_MARK,
  1551. };
  1552. static const unsigned int fsia_spdif_pins[] = {
  1553. /* SPDIF */
  1554. 53,
  1555. };
  1556. static const unsigned int fsia_spdif_mux[] = {
  1557. FSIASPDIF_MARK,
  1558. };
  1559. /* - FSIB ------------------------------------------------------------------- */
  1560. static const unsigned int fsib_mclk_in_pins[] = {
  1561. /* CK */
  1562. 54,
  1563. };
  1564. static const unsigned int fsib_mclk_in_mux[] = {
  1565. FSIBCK_MARK,
  1566. };
  1567. static const unsigned int fsib_mclk_out_pins[] = {
  1568. /* OMC */
  1569. 54,
  1570. };
  1571. static const unsigned int fsib_mclk_out_mux[] = {
  1572. FSIBOMC_MARK,
  1573. };
  1574. static const unsigned int fsib_sclk_in_pins[] = {
  1575. /* ILR, IBT */
  1576. 37, 36,
  1577. };
  1578. static const unsigned int fsib_sclk_in_mux[] = {
  1579. FSIBILR_MARK, FSIBIBT_MARK,
  1580. };
  1581. static const unsigned int fsib_sclk_out_pins[] = {
  1582. /* OLR, OBT */
  1583. 37, 36,
  1584. };
  1585. static const unsigned int fsib_sclk_out_mux[] = {
  1586. FSIBOLR_MARK, FSIBOBT_MARK,
  1587. };
  1588. static const unsigned int fsib_data_in_pins[] = {
  1589. /* ISLD */
  1590. 39,
  1591. };
  1592. static const unsigned int fsib_data_in_mux[] = {
  1593. FSIBISLD_MARK,
  1594. };
  1595. static const unsigned int fsib_data_out_pins[] = {
  1596. /* OSLD */
  1597. 38,
  1598. };
  1599. static const unsigned int fsib_data_out_mux[] = {
  1600. FSIBOSLD_MARK,
  1601. };
  1602. static const unsigned int fsib_spdif_pins[] = {
  1603. /* SPDIF */
  1604. 53,
  1605. };
  1606. static const unsigned int fsib_spdif_mux[] = {
  1607. FSIBSPDIF_MARK,
  1608. };
  1609. /* - FSIC ------------------------------------------------------------------- */
  1610. static const unsigned int fsic_mclk_in_pins[] = {
  1611. /* CK */
  1612. 54,
  1613. };
  1614. static const unsigned int fsic_mclk_in_mux[] = {
  1615. FSICCK_MARK,
  1616. };
  1617. static const unsigned int fsic_mclk_out_pins[] = {
  1618. /* OMC */
  1619. 54,
  1620. };
  1621. static const unsigned int fsic_mclk_out_mux[] = {
  1622. FSICOMC_MARK,
  1623. };
  1624. static const unsigned int fsic_sclk_in_pins[] = {
  1625. /* ILR, IBT */
  1626. 46, 45,
  1627. };
  1628. static const unsigned int fsic_sclk_in_mux[] = {
  1629. FSICILR_MARK, FSICIBT_MARK,
  1630. };
  1631. static const unsigned int fsic_sclk_out_pins[] = {
  1632. /* OLR, OBT */
  1633. 46, 45,
  1634. };
  1635. static const unsigned int fsic_sclk_out_mux[] = {
  1636. FSICOLR_MARK, FSICOBT_MARK,
  1637. };
  1638. static const unsigned int fsic_data_in_pins[] = {
  1639. /* ISLD */
  1640. 48,
  1641. };
  1642. static const unsigned int fsic_data_in_mux[] = {
  1643. FSICISLD_MARK,
  1644. };
  1645. static const unsigned int fsic_data_out_pins[] = {
  1646. /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
  1647. 47, 44, 42, 16,
  1648. };
  1649. static const unsigned int fsic_data_out_mux[] = {
  1650. FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
  1651. };
  1652. static const unsigned int fsic_spdif_0_pins[] = {
  1653. /* SPDIF */
  1654. 53,
  1655. };
  1656. static const unsigned int fsic_spdif_0_mux[] = {
  1657. PORT53_FSICSPDIF_MARK,
  1658. };
  1659. static const unsigned int fsic_spdif_1_pins[] = {
  1660. /* SPDIF */
  1661. 47,
  1662. };
  1663. static const unsigned int fsic_spdif_1_mux[] = {
  1664. PORT47_FSICSPDIF_MARK,
  1665. };
  1666. /* - FSID ------------------------------------------------------------------- */
  1667. static const unsigned int fsid_sclk_in_pins[] = {
  1668. /* ILR, IBT */
  1669. 46, 45,
  1670. };
  1671. static const unsigned int fsid_sclk_in_mux[] = {
  1672. FSIDILR_MARK, FSIDIBT_MARK,
  1673. };
  1674. static const unsigned int fsid_sclk_out_pins[] = {
  1675. /* OLR, OBT */
  1676. 46, 45,
  1677. };
  1678. static const unsigned int fsid_sclk_out_mux[] = {
  1679. FSIDOLR_MARK, FSIDOBT_MARK,
  1680. };
  1681. static const unsigned int fsid_data_in_pins[] = {
  1682. /* ISLD */
  1683. 48,
  1684. };
  1685. static const unsigned int fsid_data_in_mux[] = {
  1686. FSIDISLD_MARK,
  1687. };
  1688. /* - I2C2 ------------------------------------------------------------------- */
  1689. static const unsigned int i2c2_0_pins[] = {
  1690. /* SCL, SDA */
  1691. 237, 236,
  1692. };
  1693. static const unsigned int i2c2_0_mux[] = {
  1694. PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
  1695. };
  1696. static const unsigned int i2c2_1_pins[] = {
  1697. /* SCL, SDA */
  1698. 27, 28,
  1699. };
  1700. static const unsigned int i2c2_1_mux[] = {
  1701. PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
  1702. };
  1703. static const unsigned int i2c2_2_pins[] = {
  1704. /* SCL, SDA */
  1705. 115, 116,
  1706. };
  1707. static const unsigned int i2c2_2_mux[] = {
  1708. PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
  1709. };
  1710. /* - I2C3 ------------------------------------------------------------------- */
  1711. static const unsigned int i2c3_0_pins[] = {
  1712. /* SCL, SDA */
  1713. 248, 249,
  1714. };
  1715. static const unsigned int i2c3_0_mux[] = {
  1716. PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
  1717. };
  1718. static const unsigned int i2c3_1_pins[] = {
  1719. /* SCL, SDA */
  1720. 27, 28,
  1721. };
  1722. static const unsigned int i2c3_1_mux[] = {
  1723. PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
  1724. };
  1725. static const unsigned int i2c3_2_pins[] = {
  1726. /* SCL, SDA */
  1727. 115, 116,
  1728. };
  1729. static const unsigned int i2c3_2_mux[] = {
  1730. PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
  1731. };
  1732. /* - IrDA ------------------------------------------------------------------- */
  1733. static const unsigned int irda_0_pins[] = {
  1734. /* OUT, IN, FIRSEL */
  1735. 241, 242, 243,
  1736. };
  1737. static const unsigned int irda_0_mux[] = {
  1738. PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
  1739. };
  1740. static const unsigned int irda_1_pins[] = {
  1741. /* OUT, IN, FIRSEL */
  1742. 49, 53, 54,
  1743. };
  1744. static const unsigned int irda_1_mux[] = {
  1745. PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
  1746. };
  1747. /* - KEYSC ------------------------------------------------------------------ */
  1748. static const unsigned int keysc_in5_pins[] = {
  1749. /* KEYIN[0:4] */
  1750. 66, 67, 68, 69, 70,
  1751. };
  1752. static const unsigned int keysc_in5_mux[] = {
  1753. KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
  1754. KEYIN4_MARK,
  1755. };
  1756. static const unsigned int keysc_in6_pins[] = {
  1757. /* KEYIN[0:5] */
  1758. 66, 67, 68, 69, 70, 71,
  1759. };
  1760. static const unsigned int keysc_in6_mux[] = {
  1761. KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
  1762. KEYIN4_MARK, KEYIN5_MARK,
  1763. };
  1764. static const unsigned int keysc_in7_pins[] = {
  1765. /* KEYIN[0:6] */
  1766. 66, 67, 68, 69, 70, 71, 72,
  1767. };
  1768. static const unsigned int keysc_in7_mux[] = {
  1769. KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
  1770. KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
  1771. };
  1772. static const unsigned int keysc_in8_pins[] = {
  1773. /* KEYIN[0:7] */
  1774. 66, 67, 68, 69, 70, 71, 72, 73,
  1775. };
  1776. static const unsigned int keysc_in8_mux[] = {
  1777. KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
  1778. KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
  1779. };
  1780. static const unsigned int keysc_out04_pins[] = {
  1781. /* KEYOUT[0:4] */
  1782. 65, 64, 63, 62, 61,
  1783. };
  1784. static const unsigned int keysc_out04_mux[] = {
  1785. KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
  1786. };
  1787. static const unsigned int keysc_out5_pins[] = {
  1788. /* KEYOUT5 */
  1789. 60,
  1790. };
  1791. static const unsigned int keysc_out5_mux[] = {
  1792. KEYOUT5_MARK,
  1793. };
  1794. static const unsigned int keysc_out6_0_pins[] = {
  1795. /* KEYOUT6 */
  1796. 59,
  1797. };
  1798. static const unsigned int keysc_out6_0_mux[] = {
  1799. PORT59_KEYOUT6_MARK,
  1800. };
  1801. static const unsigned int keysc_out6_1_pins[] = {
  1802. /* KEYOUT6 */
  1803. 131,
  1804. };
  1805. static const unsigned int keysc_out6_1_mux[] = {
  1806. PORT131_KEYOUT6_MARK,
  1807. };
  1808. static const unsigned int keysc_out6_2_pins[] = {
  1809. /* KEYOUT6 */
  1810. 143,
  1811. };
  1812. static const unsigned int keysc_out6_2_mux[] = {
  1813. PORT143_KEYOUT6_MARK,
  1814. };
  1815. static const unsigned int keysc_out7_0_pins[] = {
  1816. /* KEYOUT7 */
  1817. 58,
  1818. };
  1819. static const unsigned int keysc_out7_0_mux[] = {
  1820. PORT58_KEYOUT7_MARK,
  1821. };
  1822. static const unsigned int keysc_out7_1_pins[] = {
  1823. /* KEYOUT7 */
  1824. 132,
  1825. };
  1826. static const unsigned int keysc_out7_1_mux[] = {
  1827. PORT132_KEYOUT7_MARK,
  1828. };
  1829. static const unsigned int keysc_out7_2_pins[] = {
  1830. /* KEYOUT7 */
  1831. 144,
  1832. };
  1833. static const unsigned int keysc_out7_2_mux[] = {
  1834. PORT144_KEYOUT7_MARK,
  1835. };
  1836. static const unsigned int keysc_out8_0_pins[] = {
  1837. /* KEYOUT8 */
  1838. PIN_A11,
  1839. };
  1840. static const unsigned int keysc_out8_0_mux[] = {
  1841. KEYOUT8_MARK,
  1842. };
  1843. static const unsigned int keysc_out8_1_pins[] = {
  1844. /* KEYOUT8 */
  1845. 136,
  1846. };
  1847. static const unsigned int keysc_out8_1_mux[] = {
  1848. PORT136_KEYOUT8_MARK,
  1849. };
  1850. static const unsigned int keysc_out8_2_pins[] = {
  1851. /* KEYOUT8 */
  1852. 138,
  1853. };
  1854. static const unsigned int keysc_out8_2_mux[] = {
  1855. PORT138_KEYOUT8_MARK,
  1856. };
  1857. static const unsigned int keysc_out9_0_pins[] = {
  1858. /* KEYOUT9 */
  1859. 137,
  1860. };
  1861. static const unsigned int keysc_out9_0_mux[] = {
  1862. PORT137_KEYOUT9_MARK,
  1863. };
  1864. static const unsigned int keysc_out9_1_pins[] = {
  1865. /* KEYOUT9 */
  1866. 139,
  1867. };
  1868. static const unsigned int keysc_out9_1_mux[] = {
  1869. PORT139_KEYOUT9_MARK,
  1870. };
  1871. static const unsigned int keysc_out9_2_pins[] = {
  1872. /* KEYOUT9 */
  1873. 149,
  1874. };
  1875. static const unsigned int keysc_out9_2_mux[] = {
  1876. PORT149_KEYOUT9_MARK,
  1877. };
  1878. static const unsigned int keysc_out10_0_pins[] = {
  1879. /* KEYOUT10 */
  1880. 132,
  1881. };
  1882. static const unsigned int keysc_out10_0_mux[] = {
  1883. PORT132_KEYOUT10_MARK,
  1884. };
  1885. static const unsigned int keysc_out10_1_pins[] = {
  1886. /* KEYOUT10 */
  1887. 142,
  1888. };
  1889. static const unsigned int keysc_out10_1_mux[] = {
  1890. PORT142_KEYOUT10_MARK,
  1891. };
  1892. static const unsigned int keysc_out11_0_pins[] = {
  1893. /* KEYOUT11 */
  1894. 131,
  1895. };
  1896. static const unsigned int keysc_out11_0_mux[] = {
  1897. PORT131_KEYOUT11_MARK,
  1898. };
  1899. static const unsigned int keysc_out11_1_pins[] = {
  1900. /* KEYOUT11 */
  1901. 143,
  1902. };
  1903. static const unsigned int keysc_out11_1_mux[] = {
  1904. PORT143_KEYOUT11_MARK,
  1905. };
  1906. /* - LCD -------------------------------------------------------------------- */
  1907. static const unsigned int lcd_data8_pins[] = {
  1908. /* D[0:7] */
  1909. 192, 193, 194, 195, 196, 197, 198, 199,
  1910. };
  1911. static const unsigned int lcd_data8_mux[] = {
  1912. LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
  1913. LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
  1914. };
  1915. static const unsigned int lcd_data9_pins[] = {
  1916. /* D[0:8] */
  1917. 192, 193, 194, 195, 196, 197, 198, 199,
  1918. 200,
  1919. };
  1920. static const unsigned int lcd_data9_mux[] = {
  1921. LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
  1922. LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
  1923. LCDD8_MARK,
  1924. };
  1925. static const unsigned int lcd_data12_pins[] = {
  1926. /* D[0:11] */
  1927. 192, 193, 194, 195, 196, 197, 198, 199,
  1928. 200, 201, 202, 203,
  1929. };
  1930. static const unsigned int lcd_data12_mux[] = {
  1931. LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
  1932. LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
  1933. LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
  1934. };
  1935. static const unsigned int lcd_data16_pins[] = {
  1936. /* D[0:15] */
  1937. 192, 193, 194, 195, 196, 197, 198, 199,
  1938. 200, 201, 202, 203, 204, 205, 206, 207,
  1939. };
  1940. static const unsigned int lcd_data16_mux[] = {
  1941. LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
  1942. LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
  1943. LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
  1944. LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
  1945. };
  1946. static const unsigned int lcd_data18_pins[] = {
  1947. /* D[0:17] */
  1948. 192, 193, 194, 195, 196, 197, 198, 199,
  1949. 200, 201, 202, 203, 204, 205, 206, 207,
  1950. 208, 209,
  1951. };
  1952. static const unsigned int lcd_data18_mux[] = {
  1953. LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
  1954. LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
  1955. LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
  1956. LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
  1957. LCDD16_MARK, LCDD17_MARK,
  1958. };
  1959. static const unsigned int lcd_data24_pins[] = {
  1960. /* D[0:23] */
  1961. 192, 193, 194, 195, 196, 197, 198, 199,
  1962. 200, 201, 202, 203, 204, 205, 206, 207,
  1963. 208, 209, 210, 211, 212, 213, 214, 215
  1964. };
  1965. static const unsigned int lcd_data24_mux[] = {
  1966. LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
  1967. LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
  1968. LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
  1969. LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
  1970. LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
  1971. LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
  1972. };
  1973. static const unsigned int lcd_display_pins[] = {
  1974. /* DON */
  1975. 222,
  1976. };
  1977. static const unsigned int lcd_display_mux[] = {
  1978. LCDDON_MARK,
  1979. };
  1980. static const unsigned int lcd_lclk_pins[] = {
  1981. /* LCLK */
  1982. 221,
  1983. };
  1984. static const unsigned int lcd_lclk_mux[] = {
  1985. LCDLCLK_MARK,
  1986. };
  1987. static const unsigned int lcd_sync_pins[] = {
  1988. /* VSYN, HSYN, DCK, DISP */
  1989. 220, 218, 216, 219,
  1990. };
  1991. static const unsigned int lcd_sync_mux[] = {
  1992. LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
  1993. };
  1994. static const unsigned int lcd_sys_pins[] = {
  1995. /* CS, WR, RD, RS */
  1996. 218, 216, 217, 219,
  1997. };
  1998. static const unsigned int lcd_sys_mux[] = {
  1999. LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
  2000. };
  2001. /* - LCD2 ------------------------------------------------------------------- */
  2002. static const unsigned int lcd2_data8_pins[] = {
  2003. /* D[0:7] */
  2004. 128, 129, 142, 143, 144, 145, 138, 139,
  2005. };
  2006. static const unsigned int lcd2_data8_mux[] = {
  2007. LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
  2008. LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
  2009. };
  2010. static const unsigned int lcd2_data9_pins[] = {
  2011. /* D[0:8] */
  2012. 128, 129, 142, 143, 144, 145, 138, 139,
  2013. 140,
  2014. };
  2015. static const unsigned int lcd2_data9_mux[] = {
  2016. LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
  2017. LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
  2018. LCD2D8_MARK,
  2019. };
  2020. static const unsigned int lcd2_data12_pins[] = {
  2021. /* D[0:11] */
  2022. 128, 129, 142, 143, 144, 145, 138, 139,
  2023. 140, 141, 130, 131,
  2024. };
  2025. static const unsigned int lcd2_data12_mux[] = {
  2026. LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
  2027. LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
  2028. LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
  2029. };
  2030. static const unsigned int lcd2_data16_pins[] = {
  2031. /* D[0:15] */
  2032. 128, 129, 142, 143, 144, 145, 138, 139,
  2033. 140, 141, 130, 131, 132, 133, 134, 135,
  2034. };
  2035. static const unsigned int lcd2_data16_mux[] = {
  2036. LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
  2037. LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
  2038. LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
  2039. LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
  2040. };
  2041. static const unsigned int lcd2_data18_pins[] = {
  2042. /* D[0:17] */
  2043. 128, 129, 142, 143, 144, 145, 138, 139,
  2044. 140, 141, 130, 131, 132, 133, 134, 135,
  2045. 136, 137,
  2046. };
  2047. static const unsigned int lcd2_data18_mux[] = {
  2048. LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
  2049. LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
  2050. LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
  2051. LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
  2052. LCD2D16_MARK, LCD2D17_MARK,
  2053. };
  2054. static const unsigned int lcd2_data24_pins[] = {
  2055. /* D[0:23] */
  2056. 128, 129, 142, 143, 144, 145, 138, 139,
  2057. 140, 141, 130, 131, 132, 133, 134, 135,
  2058. 136, 137, 146, 147, 234, 235, 238, 239
  2059. };
  2060. static const unsigned int lcd2_data24_mux[] = {
  2061. LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
  2062. LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
  2063. LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
  2064. LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
  2065. LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
  2066. LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
  2067. };
  2068. static const unsigned int lcd2_sync_0_pins[] = {
  2069. /* VSYN, HSYN, DCK, DISP */
  2070. 128, 129, 146, 145,
  2071. };
  2072. static const unsigned int lcd2_sync_0_mux[] = {
  2073. PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
  2074. LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
  2075. };
  2076. static const unsigned int lcd2_sync_1_pins[] = {
  2077. /* VSYN, HSYN, DCK, DISP */
  2078. 222, 221, 219, 217,
  2079. };
  2080. static const unsigned int lcd2_sync_1_mux[] = {
  2081. PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
  2082. LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
  2083. };
  2084. static const unsigned int lcd2_sys_0_pins[] = {
  2085. /* CS, WR, RD, RS */
  2086. 129, 146, 147, 145,
  2087. };
  2088. static const unsigned int lcd2_sys_0_mux[] = {
  2089. PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
  2090. LCD2RD__MARK, PORT145_LCD2RS_MARK,
  2091. };
  2092. static const unsigned int lcd2_sys_1_pins[] = {
  2093. /* CS, WR, RD, RS */
  2094. 221, 219, 147, 217,
  2095. };
  2096. static const unsigned int lcd2_sys_1_mux[] = {
  2097. PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
  2098. LCD2RD__MARK, PORT217_LCD2RS_MARK,
  2099. };
  2100. /* - MMCIF ------------------------------------------------------------------ */
  2101. static const unsigned int mmc0_data1_0_pins[] = {
  2102. /* D[0] */
  2103. 271,
  2104. };
  2105. static const unsigned int mmc0_data1_0_mux[] = {
  2106. MMCD0_0_MARK,
  2107. };
  2108. static const unsigned int mmc0_data4_0_pins[] = {
  2109. /* D[0:3] */
  2110. 271, 272, 273, 274,
  2111. };
  2112. static const unsigned int mmc0_data4_0_mux[] = {
  2113. MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
  2114. };
  2115. static const unsigned int mmc0_data8_0_pins[] = {
  2116. /* D[0:7] */
  2117. 271, 272, 273, 274, 275, 276, 277, 278,
  2118. };
  2119. static const unsigned int mmc0_data8_0_mux[] = {
  2120. MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
  2121. MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
  2122. };
  2123. static const unsigned int mmc0_ctrl_0_pins[] = {
  2124. /* CMD, CLK */
  2125. 279, 270,
  2126. };
  2127. static const unsigned int mmc0_ctrl_0_mux[] = {
  2128. MMCCMD0_MARK, MMCCLK0_MARK,
  2129. };
  2130. static const unsigned int mmc0_data1_1_pins[] = {
  2131. /* D[0] */
  2132. 305,
  2133. };
  2134. static const unsigned int mmc0_data1_1_mux[] = {
  2135. MMCD1_0_MARK,
  2136. };
  2137. static const unsigned int mmc0_data4_1_pins[] = {
  2138. /* D[0:3] */
  2139. 305, 304, 303, 302,
  2140. };
  2141. static const unsigned int mmc0_data4_1_mux[] = {
  2142. MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
  2143. };
  2144. static const unsigned int mmc0_data8_1_pins[] = {
  2145. /* D[0:7] */
  2146. 305, 304, 303, 302, 301, 300, 299, 298,
  2147. };
  2148. static const unsigned int mmc0_data8_1_mux[] = {
  2149. MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
  2150. MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
  2151. };
  2152. static const unsigned int mmc0_ctrl_1_pins[] = {
  2153. /* CMD, CLK */
  2154. 297, 289,
  2155. };
  2156. static const unsigned int mmc0_ctrl_1_mux[] = {
  2157. MMCCMD1_MARK, MMCCLK1_MARK,
  2158. };
  2159. /* - MSIOF0 ----------------------------------------------------------------- */
  2160. static const unsigned int msiof0_rsck_pins[] = {
  2161. /* RSCK */
  2162. 66,
  2163. };
  2164. static const unsigned int msiof0_rsck_mux[] = {
  2165. MSIOF0_RSCK_MARK,
  2166. };
  2167. static const unsigned int msiof0_tsck_pins[] = {
  2168. /* TSCK */
  2169. 64,
  2170. };
  2171. static const unsigned int msiof0_tsck_mux[] = {
  2172. MSIOF0_TSCK_MARK,
  2173. };
  2174. static const unsigned int msiof0_rsync_pins[] = {
  2175. /* RSYNC */
  2176. 67,
  2177. };
  2178. static const unsigned int msiof0_rsync_mux[] = {
  2179. MSIOF0_RSYNC_MARK,
  2180. };
  2181. static const unsigned int msiof0_tsync_pins[] = {
  2182. /* TSYNC */
  2183. 63,
  2184. };
  2185. static const unsigned int msiof0_tsync_mux[] = {
  2186. MSIOF0_TSYNC_MARK,
  2187. };
  2188. static const unsigned int msiof0_ss1_pins[] = {
  2189. /* SS1 */
  2190. 62,
  2191. };
  2192. static const unsigned int msiof0_ss1_mux[] = {
  2193. MSIOF0_SS1_MARK,
  2194. };
  2195. static const unsigned int msiof0_ss2_pins[] = {
  2196. /* SS2 */
  2197. 71,
  2198. };
  2199. static const unsigned int msiof0_ss2_mux[] = {
  2200. MSIOF0_SS2_MARK,
  2201. };
  2202. static const unsigned int msiof0_rxd_pins[] = {
  2203. /* RXD */
  2204. 70,
  2205. };
  2206. static const unsigned int msiof0_rxd_mux[] = {
  2207. MSIOF0_RXD_MARK,
  2208. };
  2209. static const unsigned int msiof0_txd_pins[] = {
  2210. /* TXD */
  2211. 65,
  2212. };
  2213. static const unsigned int msiof0_txd_mux[] = {
  2214. MSIOF0_TXD_MARK,
  2215. };
  2216. static const unsigned int msiof0_mck0_pins[] = {
  2217. /* MSCK0 */
  2218. 68,
  2219. };
  2220. static const unsigned int msiof0_mck0_mux[] = {
  2221. MSIOF0_MCK0_MARK,
  2222. };
  2223. static const unsigned int msiof0_mck1_pins[] = {
  2224. /* MSCK1 */
  2225. 69,
  2226. };
  2227. static const unsigned int msiof0_mck1_mux[] = {
  2228. MSIOF0_MCK1_MARK,
  2229. };
  2230. static const unsigned int msiof0l_rsck_pins[] = {
  2231. /* RSCK */
  2232. 214,
  2233. };
  2234. static const unsigned int msiof0l_rsck_mux[] = {
  2235. MSIOF0L_RSCK_MARK,
  2236. };
  2237. static const unsigned int msiof0l_tsck_pins[] = {
  2238. /* TSCK */
  2239. 219,
  2240. };
  2241. static const unsigned int msiof0l_tsck_mux[] = {
  2242. MSIOF0L_TSCK_MARK,
  2243. };
  2244. static const unsigned int msiof0l_rsync_pins[] = {
  2245. /* RSYNC */
  2246. 215,
  2247. };
  2248. static const unsigned int msiof0l_rsync_mux[] = {
  2249. MSIOF0L_RSYNC_MARK,
  2250. };
  2251. static const unsigned int msiof0l_tsync_pins[] = {
  2252. /* TSYNC */
  2253. 217,
  2254. };
  2255. static const unsigned int msiof0l_tsync_mux[] = {
  2256. MSIOF0L_TSYNC_MARK,
  2257. };
  2258. static const unsigned int msiof0l_ss1_a_pins[] = {
  2259. /* SS1 */
  2260. 207,
  2261. };
  2262. static const unsigned int msiof0l_ss1_a_mux[] = {
  2263. PORT207_MSIOF0L_SS1_MARK,
  2264. };
  2265. static const unsigned int msiof0l_ss1_b_pins[] = {
  2266. /* SS1 */
  2267. 210,
  2268. };
  2269. static const unsigned int msiof0l_ss1_b_mux[] = {
  2270. PORT210_MSIOF0L_SS1_MARK,
  2271. };
  2272. static const unsigned int msiof0l_ss2_a_pins[] = {
  2273. /* SS2 */
  2274. 208,
  2275. };
  2276. static const unsigned int msiof0l_ss2_a_mux[] = {
  2277. PORT208_MSIOF0L_SS2_MARK,
  2278. };
  2279. static const unsigned int msiof0l_ss2_b_pins[] = {
  2280. /* SS2 */
  2281. 211,
  2282. };
  2283. static const unsigned int msiof0l_ss2_b_mux[] = {
  2284. PORT211_MSIOF0L_SS2_MARK,
  2285. };
  2286. static const unsigned int msiof0l_rxd_pins[] = {
  2287. /* RXD */
  2288. 221,
  2289. };
  2290. static const unsigned int msiof0l_rxd_mux[] = {
  2291. MSIOF0L_RXD_MARK,
  2292. };
  2293. static const unsigned int msiof0l_txd_pins[] = {
  2294. /* TXD */
  2295. 222,
  2296. };
  2297. static const unsigned int msiof0l_txd_mux[] = {
  2298. MSIOF0L_TXD_MARK,
  2299. };
  2300. static const unsigned int msiof0l_mck0_pins[] = {
  2301. /* MSCK0 */
  2302. 212,
  2303. };
  2304. static const unsigned int msiof0l_mck0_mux[] = {
  2305. MSIOF0L_MCK0_MARK,
  2306. };
  2307. static const unsigned int msiof0l_mck1_pins[] = {
  2308. /* MSCK1 */
  2309. 213,
  2310. };
  2311. static const unsigned int msiof0l_mck1_mux[] = {
  2312. MSIOF0L_MCK1_MARK,
  2313. };
  2314. /* - MSIOF1 ----------------------------------------------------------------- */
  2315. static const unsigned int msiof1_rsck_pins[] = {
  2316. /* RSCK */
  2317. 234,
  2318. };
  2319. static const unsigned int msiof1_rsck_mux[] = {
  2320. MSIOF1_RSCK_MARK,
  2321. };
  2322. static const unsigned int msiof1_tsck_pins[] = {
  2323. /* TSCK */
  2324. 232,
  2325. };
  2326. static const unsigned int msiof1_tsck_mux[] = {
  2327. MSIOF1_TSCK_MARK,
  2328. };
  2329. static const unsigned int msiof1_rsync_pins[] = {
  2330. /* RSYNC */
  2331. 235,
  2332. };
  2333. static const unsigned int msiof1_rsync_mux[] = {
  2334. MSIOF1_RSYNC_MARK,
  2335. };
  2336. static const unsigned int msiof1_tsync_pins[] = {
  2337. /* TSYNC */
  2338. 231,
  2339. };
  2340. static const unsigned int msiof1_tsync_mux[] = {
  2341. MSIOF1_TSYNC_MARK,
  2342. };
  2343. static const unsigned int msiof1_ss1_pins[] = {
  2344. /* SS1 */
  2345. 238,
  2346. };
  2347. static const unsigned int msiof1_ss1_mux[] = {
  2348. MSIOF1_SS1_MARK,
  2349. };
  2350. static const unsigned int msiof1_ss2_pins[] = {
  2351. /* SS2 */
  2352. 239,
  2353. };
  2354. static const unsigned int msiof1_ss2_mux[] = {
  2355. MSIOF1_SS2_MARK,
  2356. };
  2357. static const unsigned int msiof1_rxd_pins[] = {
  2358. /* RXD */
  2359. 233,
  2360. };
  2361. static const unsigned int msiof1_rxd_mux[] = {
  2362. MSIOF1_RXD_MARK,
  2363. };
  2364. static const unsigned int msiof1_txd_pins[] = {
  2365. /* TXD */
  2366. 230,
  2367. };
  2368. static const unsigned int msiof1_txd_mux[] = {
  2369. MSIOF1_TXD_MARK,
  2370. };
  2371. static const unsigned int msiof1_mck0_pins[] = {
  2372. /* MSCK0 */
  2373. 236,
  2374. };
  2375. static const unsigned int msiof1_mck0_mux[] = {
  2376. MSIOF1_MCK0_MARK,
  2377. };
  2378. static const unsigned int msiof1_mck1_pins[] = {
  2379. /* MSCK1 */
  2380. 237,
  2381. };
  2382. static const unsigned int msiof1_mck1_mux[] = {
  2383. MSIOF1_MCK1_MARK,
  2384. };
  2385. /* - MSIOF2 ----------------------------------------------------------------- */
  2386. static const unsigned int msiof2_rsck_pins[] = {
  2387. /* RSCK */
  2388. 151,
  2389. };
  2390. static const unsigned int msiof2_rsck_mux[] = {
  2391. MSIOF2_RSCK_MARK,
  2392. };
  2393. static const unsigned int msiof2_tsck_pins[] = {
  2394. /* TSCK */
  2395. 135,
  2396. };
  2397. static const unsigned int msiof2_tsck_mux[] = {
  2398. MSIOF2_TSCK_MARK,
  2399. };
  2400. static const unsigned int msiof2_rsync_pins[] = {
  2401. /* RSYNC */
  2402. 152,
  2403. };
  2404. static const unsigned int msiof2_rsync_mux[] = {
  2405. MSIOF2_RSYNC_MARK,
  2406. };
  2407. static const unsigned int msiof2_tsync_pins[] = {
  2408. /* TSYNC */
  2409. 133,
  2410. };
  2411. static const unsigned int msiof2_tsync_mux[] = {
  2412. MSIOF2_TSYNC_MARK,
  2413. };
  2414. static const unsigned int msiof2_ss1_a_pins[] = {
  2415. /* SS1 */
  2416. 131,
  2417. };
  2418. static const unsigned int msiof2_ss1_a_mux[] = {
  2419. PORT131_MSIOF2_SS1_MARK,
  2420. };
  2421. static const unsigned int msiof2_ss1_b_pins[] = {
  2422. /* SS1 */
  2423. 153,
  2424. };
  2425. static const unsigned int msiof2_ss1_b_mux[] = {
  2426. PORT153_MSIOF2_SS1_MARK,
  2427. };
  2428. static const unsigned int msiof2_ss2_a_pins[] = {
  2429. /* SS2 */
  2430. 132,
  2431. };
  2432. static const unsigned int msiof2_ss2_a_mux[] = {
  2433. PORT132_MSIOF2_SS2_MARK,
  2434. };
  2435. static const unsigned int msiof2_ss2_b_pins[] = {
  2436. /* SS2 */
  2437. 156,
  2438. };
  2439. static const unsigned int msiof2_ss2_b_mux[] = {
  2440. PORT156_MSIOF2_SS2_MARK,
  2441. };
  2442. static const unsigned int msiof2_rxd_a_pins[] = {
  2443. /* RXD */
  2444. 130,
  2445. };
  2446. static const unsigned int msiof2_rxd_a_mux[] = {
  2447. PORT130_MSIOF2_RXD_MARK,
  2448. };
  2449. static const unsigned int msiof2_rxd_b_pins[] = {
  2450. /* RXD */
  2451. 157,
  2452. };
  2453. static const unsigned int msiof2_rxd_b_mux[] = {
  2454. PORT157_MSIOF2_RXD_MARK,
  2455. };
  2456. static const unsigned int msiof2_txd_pins[] = {
  2457. /* TXD */
  2458. 134,
  2459. };
  2460. static const unsigned int msiof2_txd_mux[] = {
  2461. MSIOF2_TXD_MARK,
  2462. };
  2463. static const unsigned int msiof2_mck0_pins[] = {
  2464. /* MSCK0 */
  2465. 154,
  2466. };
  2467. static const unsigned int msiof2_mck0_mux[] = {
  2468. MSIOF2_MCK0_MARK,
  2469. };
  2470. static const unsigned int msiof2_mck1_pins[] = {
  2471. /* MSCK1 */
  2472. 155,
  2473. };
  2474. static const unsigned int msiof2_mck1_mux[] = {
  2475. MSIOF2_MCK1_MARK,
  2476. };
  2477. static const unsigned int msiof2r_tsck_pins[] = {
  2478. /* TSCK */
  2479. 248,
  2480. };
  2481. static const unsigned int msiof2r_tsck_mux[] = {
  2482. MSIOF2R_TSCK_MARK,
  2483. };
  2484. static const unsigned int msiof2r_tsync_pins[] = {
  2485. /* TSYNC */
  2486. 249,
  2487. };
  2488. static const unsigned int msiof2r_tsync_mux[] = {
  2489. MSIOF2R_TSYNC_MARK,
  2490. };
  2491. static const unsigned int msiof2r_rxd_pins[] = {
  2492. /* RXD */
  2493. 244,
  2494. };
  2495. static const unsigned int msiof2r_rxd_mux[] = {
  2496. MSIOF2R_RXD_MARK,
  2497. };
  2498. static const unsigned int msiof2r_txd_pins[] = {
  2499. /* TXD */
  2500. 245,
  2501. };
  2502. static const unsigned int msiof2r_txd_mux[] = {
  2503. MSIOF2R_TXD_MARK,
  2504. };
  2505. /* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
  2506. static const unsigned int msiof3_rsck_pins[] = {
  2507. /* RSCK */
  2508. 115,
  2509. };
  2510. static const unsigned int msiof3_rsck_mux[] = {
  2511. BBIF1_RSCK_MARK,
  2512. };
  2513. static const unsigned int msiof3_tsck_pins[] = {
  2514. /* TSCK */
  2515. 112,
  2516. };
  2517. static const unsigned int msiof3_tsck_mux[] = {
  2518. BBIF1_TSCK_MARK,
  2519. };
  2520. static const unsigned int msiof3_rsync_pins[] = {
  2521. /* RSYNC */
  2522. 116,
  2523. };
  2524. static const unsigned int msiof3_rsync_mux[] = {
  2525. BBIF1_RSYNC_MARK,
  2526. };
  2527. static const unsigned int msiof3_tsync_pins[] = {
  2528. /* TSYNC */
  2529. 113,
  2530. };
  2531. static const unsigned int msiof3_tsync_mux[] = {
  2532. BBIF1_TSYNC_MARK,
  2533. };
  2534. static const unsigned int msiof3_ss1_pins[] = {
  2535. /* SS1 */
  2536. 117,
  2537. };
  2538. static const unsigned int msiof3_ss1_mux[] = {
  2539. BBIF1_SS1_MARK,
  2540. };
  2541. static const unsigned int msiof3_ss2_pins[] = {
  2542. /* SS2 */
  2543. 109,
  2544. };
  2545. static const unsigned int msiof3_ss2_mux[] = {
  2546. BBIF1_SS2_MARK,
  2547. };
  2548. static const unsigned int msiof3_rxd_pins[] = {
  2549. /* RXD */
  2550. 111,
  2551. };
  2552. static const unsigned int msiof3_rxd_mux[] = {
  2553. BBIF1_RXD_MARK,
  2554. };
  2555. static const unsigned int msiof3_txd_pins[] = {
  2556. /* TXD */
  2557. 114,
  2558. };
  2559. static const unsigned int msiof3_txd_mux[] = {
  2560. BBIF1_TXD_MARK,
  2561. };
  2562. static const unsigned int msiof3_flow_pins[] = {
  2563. /* FLOW */
  2564. 117,
  2565. };
  2566. static const unsigned int msiof3_flow_mux[] = {
  2567. BBIF1_FLOW_MARK,
  2568. };
  2569. /* - SCIFA0 ----------------------------------------------------------------- */
  2570. static const unsigned int scifa0_data_pins[] = {
  2571. /* RXD, TXD */
  2572. 43, 17,
  2573. };
  2574. static const unsigned int scifa0_data_mux[] = {
  2575. SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
  2576. };
  2577. static const unsigned int scifa0_clk_pins[] = {
  2578. /* SCK */
  2579. 16,
  2580. };
  2581. static const unsigned int scifa0_clk_mux[] = {
  2582. SCIFA0_SCK_MARK,
  2583. };
  2584. static const unsigned int scifa0_ctrl_pins[] = {
  2585. /* RTS, CTS */
  2586. 42, 44,
  2587. };
  2588. static const unsigned int scifa0_ctrl_mux[] = {
  2589. SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
  2590. };
  2591. /* - SCIFA1 ----------------------------------------------------------------- */
  2592. static const unsigned int scifa1_data_pins[] = {
  2593. /* RXD, TXD */
  2594. 228, 225,
  2595. };
  2596. static const unsigned int scifa1_data_mux[] = {
  2597. SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
  2598. };
  2599. static const unsigned int scifa1_clk_pins[] = {
  2600. /* SCK */
  2601. 226,
  2602. };
  2603. static const unsigned int scifa1_clk_mux[] = {
  2604. SCIFA1_SCK_MARK,
  2605. };
  2606. static const unsigned int scifa1_ctrl_pins[] = {
  2607. /* RTS, CTS */
  2608. 227, 229,
  2609. };
  2610. static const unsigned int scifa1_ctrl_mux[] = {
  2611. SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
  2612. };
  2613. /* - SCIFA2 ----------------------------------------------------------------- */
  2614. static const unsigned int scifa2_data_0_pins[] = {
  2615. /* RXD, TXD */
  2616. 155, 154,
  2617. };
  2618. static const unsigned int scifa2_data_0_mux[] = {
  2619. SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
  2620. };
  2621. static const unsigned int scifa2_clk_0_pins[] = {
  2622. /* SCK */
  2623. 158,
  2624. };
  2625. static const unsigned int scifa2_clk_0_mux[] = {
  2626. SCIFA2_SCK1_MARK,
  2627. };
  2628. static const unsigned int scifa2_ctrl_0_pins[] = {
  2629. /* RTS, CTS */
  2630. 156, 157,
  2631. };
  2632. static const unsigned int scifa2_ctrl_0_mux[] = {
  2633. SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
  2634. };
  2635. static const unsigned int scifa2_data_1_pins[] = {
  2636. /* RXD, TXD */
  2637. 233, 230,
  2638. };
  2639. static const unsigned int scifa2_data_1_mux[] = {
  2640. SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
  2641. };
  2642. static const unsigned int scifa2_clk_1_pins[] = {
  2643. /* SCK */
  2644. 232,
  2645. };
  2646. static const unsigned int scifa2_clk_1_mux[] = {
  2647. SCIFA2_SCK2_MARK,
  2648. };
  2649. static const unsigned int scifa2_ctrl_1_pins[] = {
  2650. /* RTS, CTS */
  2651. 234, 231,
  2652. };
  2653. static const unsigned int scifa2_ctrl_1_mux[] = {
  2654. SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
  2655. };
  2656. /* - SCIFA3 ----------------------------------------------------------------- */
  2657. static const unsigned int scifa3_data_pins[] = {
  2658. /* RXD, TXD */
  2659. 108, 110,
  2660. };
  2661. static const unsigned int scifa3_data_mux[] = {
  2662. SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
  2663. };
  2664. static const unsigned int scifa3_ctrl_pins[] = {
  2665. /* RTS, CTS */
  2666. 109, 107,
  2667. };
  2668. static const unsigned int scifa3_ctrl_mux[] = {
  2669. SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
  2670. };
  2671. /* - SCIFA4 ----------------------------------------------------------------- */
  2672. static const unsigned int scifa4_data_pins[] = {
  2673. /* RXD, TXD */
  2674. 33, 32,
  2675. };
  2676. static const unsigned int scifa4_data_mux[] = {
  2677. SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
  2678. };
  2679. static const unsigned int scifa4_ctrl_pins[] = {
  2680. /* RTS, CTS */
  2681. 34, 35,
  2682. };
  2683. static const unsigned int scifa4_ctrl_mux[] = {
  2684. SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
  2685. };
  2686. /* - SCIFA5 ----------------------------------------------------------------- */
  2687. static const unsigned int scifa5_data_0_pins[] = {
  2688. /* RXD, TXD */
  2689. 246, 247,
  2690. };
  2691. static const unsigned int scifa5_data_0_mux[] = {
  2692. PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
  2693. };
  2694. static const unsigned int scifa5_clk_0_pins[] = {
  2695. /* SCK */
  2696. 248,
  2697. };
  2698. static const unsigned int scifa5_clk_0_mux[] = {
  2699. PORT248_SCIFA5_SCK_MARK,
  2700. };
  2701. static const unsigned int scifa5_ctrl_0_pins[] = {
  2702. /* RTS, CTS */
  2703. 245, 244,
  2704. };
  2705. static const unsigned int scifa5_ctrl_0_mux[] = {
  2706. PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
  2707. };
  2708. static const unsigned int scifa5_data_1_pins[] = {
  2709. /* RXD, TXD */
  2710. 195, 196,
  2711. };
  2712. static const unsigned int scifa5_data_1_mux[] = {
  2713. PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
  2714. };
  2715. static const unsigned int scifa5_clk_1_pins[] = {
  2716. /* SCK */
  2717. 197,
  2718. };
  2719. static const unsigned int scifa5_clk_1_mux[] = {
  2720. PORT197_SCIFA5_SCK_MARK,
  2721. };
  2722. static const unsigned int scifa5_ctrl_1_pins[] = {
  2723. /* RTS, CTS */
  2724. 194, 193,
  2725. };
  2726. static const unsigned int scifa5_ctrl_1_mux[] = {
  2727. PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
  2728. };
  2729. static const unsigned int scifa5_data_2_pins[] = {
  2730. /* RXD, TXD */
  2731. 162, 160,
  2732. };
  2733. static const unsigned int scifa5_data_2_mux[] = {
  2734. PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
  2735. };
  2736. static const unsigned int scifa5_clk_2_pins[] = {
  2737. /* SCK */
  2738. 159,
  2739. };
  2740. static const unsigned int scifa5_clk_2_mux[] = {
  2741. PORT159_SCIFA5_SCK_MARK,
  2742. };
  2743. static const unsigned int scifa5_ctrl_2_pins[] = {
  2744. /* RTS, CTS */
  2745. 163, 161,
  2746. };
  2747. static const unsigned int scifa5_ctrl_2_mux[] = {
  2748. PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
  2749. };
  2750. /* - SCIFA6 ----------------------------------------------------------------- */
  2751. static const unsigned int scifa6_pins[] = {
  2752. /* TXD */
  2753. 240,
  2754. };
  2755. static const unsigned int scifa6_mux[] = {
  2756. SCIFA6_TXD_MARK,
  2757. };
  2758. /* - SCIFA7 ----------------------------------------------------------------- */
  2759. static const unsigned int scifa7_data_pins[] = {
  2760. /* RXD, TXD */
  2761. 12, 18,
  2762. };
  2763. static const unsigned int scifa7_data_mux[] = {
  2764. SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
  2765. };
  2766. static const unsigned int scifa7_ctrl_pins[] = {
  2767. /* RTS, CTS */
  2768. 19, 13,
  2769. };
  2770. static const unsigned int scifa7_ctrl_mux[] = {
  2771. SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
  2772. };
  2773. /* - SCIFB ------------------------------------------------------------------ */
  2774. static const unsigned int scifb_data_0_pins[] = {
  2775. /* RXD, TXD */
  2776. 162, 160,
  2777. };
  2778. static const unsigned int scifb_data_0_mux[] = {
  2779. PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
  2780. };
  2781. static const unsigned int scifb_clk_0_pins[] = {
  2782. /* SCK */
  2783. 159,
  2784. };
  2785. static const unsigned int scifb_clk_0_mux[] = {
  2786. PORT159_SCIFB_SCK_MARK,
  2787. };
  2788. static const unsigned int scifb_ctrl_0_pins[] = {
  2789. /* RTS, CTS */
  2790. 163, 161,
  2791. };
  2792. static const unsigned int scifb_ctrl_0_mux[] = {
  2793. PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
  2794. };
  2795. static const unsigned int scifb_data_1_pins[] = {
  2796. /* RXD, TXD */
  2797. 246, 247,
  2798. };
  2799. static const unsigned int scifb_data_1_mux[] = {
  2800. PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
  2801. };
  2802. static const unsigned int scifb_clk_1_pins[] = {
  2803. /* SCK */
  2804. 248,
  2805. };
  2806. static const unsigned int scifb_clk_1_mux[] = {
  2807. PORT248_SCIFB_SCK_MARK,
  2808. };
  2809. static const unsigned int scifb_ctrl_1_pins[] = {
  2810. /* RTS, CTS */
  2811. 245, 244,
  2812. };
  2813. static const unsigned int scifb_ctrl_1_mux[] = {
  2814. PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
  2815. };
  2816. /* - SDHI0 ------------------------------------------------------------------ */
  2817. static const unsigned int sdhi0_data1_pins[] = {
  2818. /* D0 */
  2819. 252,
  2820. };
  2821. static const unsigned int sdhi0_data1_mux[] = {
  2822. SDHID0_0_MARK,
  2823. };
  2824. static const unsigned int sdhi0_data4_pins[] = {
  2825. /* D[0:3] */
  2826. 252, 253, 254, 255,
  2827. };
  2828. static const unsigned int sdhi0_data4_mux[] = {
  2829. SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
  2830. };
  2831. static const unsigned int sdhi0_ctrl_pins[] = {
  2832. /* CMD, CLK */
  2833. 256, 250,
  2834. };
  2835. static const unsigned int sdhi0_ctrl_mux[] = {
  2836. SDHICMD0_MARK, SDHICLK0_MARK,
  2837. };
  2838. static const unsigned int sdhi0_cd_pins[] = {
  2839. /* CD */
  2840. 251,
  2841. };
  2842. static const unsigned int sdhi0_cd_mux[] = {
  2843. SDHICD0_MARK,
  2844. };
  2845. static const unsigned int sdhi0_wp_pins[] = {
  2846. /* WP */
  2847. 257,
  2848. };
  2849. static const unsigned int sdhi0_wp_mux[] = {
  2850. SDHIWP0_MARK,
  2851. };
  2852. /* - SDHI1 ------------------------------------------------------------------ */
  2853. static const unsigned int sdhi1_data1_pins[] = {
  2854. /* D0 */
  2855. 259,
  2856. };
  2857. static const unsigned int sdhi1_data1_mux[] = {
  2858. SDHID1_0_MARK,
  2859. };
  2860. static const unsigned int sdhi1_data4_pins[] = {
  2861. /* D[0:3] */
  2862. 259, 260, 261, 262,
  2863. };
  2864. static const unsigned int sdhi1_data4_mux[] = {
  2865. SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
  2866. };
  2867. static const unsigned int sdhi1_ctrl_pins[] = {
  2868. /* CMD, CLK */
  2869. 263, 258,
  2870. };
  2871. static const unsigned int sdhi1_ctrl_mux[] = {
  2872. SDHICMD1_MARK, SDHICLK1_MARK,
  2873. };
  2874. /* - SDHI2 ------------------------------------------------------------------ */
  2875. static const unsigned int sdhi2_data1_pins[] = {
  2876. /* D0 */
  2877. 265,
  2878. };
  2879. static const unsigned int sdhi2_data1_mux[] = {
  2880. SDHID2_0_MARK,
  2881. };
  2882. static const unsigned int sdhi2_data4_pins[] = {
  2883. /* D[0:3] */
  2884. 265, 266, 267, 268,
  2885. };
  2886. static const unsigned int sdhi2_data4_mux[] = {
  2887. SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
  2888. };
  2889. static const unsigned int sdhi2_ctrl_pins[] = {
  2890. /* CMD, CLK */
  2891. 269, 264,
  2892. };
  2893. static const unsigned int sdhi2_ctrl_mux[] = {
  2894. SDHICMD2_MARK, SDHICLK2_MARK,
  2895. };
  2896. /* - TPU0 ------------------------------------------------------------------- */
  2897. static const unsigned int tpu0_to0_pins[] = {
  2898. /* TO */
  2899. 55,
  2900. };
  2901. static const unsigned int tpu0_to0_mux[] = {
  2902. TPU0TO0_MARK,
  2903. };
  2904. static const unsigned int tpu0_to1_pins[] = {
  2905. /* TO */
  2906. 59,
  2907. };
  2908. static const unsigned int tpu0_to1_mux[] = {
  2909. TPU0TO1_MARK,
  2910. };
  2911. static const unsigned int tpu0_to2_pins[] = {
  2912. /* TO */
  2913. 140,
  2914. };
  2915. static const unsigned int tpu0_to2_mux[] = {
  2916. TPU0TO2_MARK,
  2917. };
  2918. static const unsigned int tpu0_to3_pins[] = {
  2919. /* TO */
  2920. 141,
  2921. };
  2922. static const unsigned int tpu0_to3_mux[] = {
  2923. TPU0TO3_MARK,
  2924. };
  2925. /* - TPU1 ------------------------------------------------------------------- */
  2926. static const unsigned int tpu1_to0_pins[] = {
  2927. /* TO */
  2928. 246,
  2929. };
  2930. static const unsigned int tpu1_to0_mux[] = {
  2931. TPU1TO0_MARK,
  2932. };
  2933. static const unsigned int tpu1_to1_0_pins[] = {
  2934. /* TO */
  2935. 28,
  2936. };
  2937. static const unsigned int tpu1_to1_0_mux[] = {
  2938. PORT28_TPU1TO1_MARK,
  2939. };
  2940. static const unsigned int tpu1_to1_1_pins[] = {
  2941. /* TO */
  2942. 29,
  2943. };
  2944. static const unsigned int tpu1_to1_1_mux[] = {
  2945. PORT29_TPU1TO1_MARK,
  2946. };
  2947. static const unsigned int tpu1_to2_pins[] = {
  2948. /* TO */
  2949. 153,
  2950. };
  2951. static const unsigned int tpu1_to2_mux[] = {
  2952. TPU1TO2_MARK,
  2953. };
  2954. static const unsigned int tpu1_to3_pins[] = {
  2955. /* TO */
  2956. 145,
  2957. };
  2958. static const unsigned int tpu1_to3_mux[] = {
  2959. TPU1TO3_MARK,
  2960. };
  2961. /* - TPU2 ------------------------------------------------------------------- */
  2962. static const unsigned int tpu2_to0_pins[] = {
  2963. /* TO */
  2964. 248,
  2965. };
  2966. static const unsigned int tpu2_to0_mux[] = {
  2967. TPU2TO0_MARK,
  2968. };
  2969. static const unsigned int tpu2_to1_pins[] = {
  2970. /* TO */
  2971. 197,
  2972. };
  2973. static const unsigned int tpu2_to1_mux[] = {
  2974. TPU2TO1_MARK,
  2975. };
  2976. static const unsigned int tpu2_to2_pins[] = {
  2977. /* TO */
  2978. 50,
  2979. };
  2980. static const unsigned int tpu2_to2_mux[] = {
  2981. TPU2TO2_MARK,
  2982. };
  2983. static const unsigned int tpu2_to3_pins[] = {
  2984. /* TO */
  2985. 51,
  2986. };
  2987. static const unsigned int tpu2_to3_mux[] = {
  2988. TPU2TO3_MARK,
  2989. };
  2990. /* - TPU3 ------------------------------------------------------------------- */
  2991. static const unsigned int tpu3_to0_pins[] = {
  2992. /* TO */
  2993. 163,
  2994. };
  2995. static const unsigned int tpu3_to0_mux[] = {
  2996. TPU3TO0_MARK,
  2997. };
  2998. static const unsigned int tpu3_to1_pins[] = {
  2999. /* TO */
  3000. 247,
  3001. };
  3002. static const unsigned int tpu3_to1_mux[] = {
  3003. TPU3TO1_MARK,
  3004. };
  3005. static const unsigned int tpu3_to2_pins[] = {
  3006. /* TO */
  3007. 54,
  3008. };
  3009. static const unsigned int tpu3_to2_mux[] = {
  3010. TPU3TO2_MARK,
  3011. };
  3012. static const unsigned int tpu3_to3_pins[] = {
  3013. /* TO */
  3014. 53,
  3015. };
  3016. static const unsigned int tpu3_to3_mux[] = {
  3017. TPU3TO3_MARK,
  3018. };
  3019. /* - TPU4 ------------------------------------------------------------------- */
  3020. static const unsigned int tpu4_to0_pins[] = {
  3021. /* TO */
  3022. 241,
  3023. };
  3024. static const unsigned int tpu4_to0_mux[] = {
  3025. TPU4TO0_MARK,
  3026. };
  3027. static const unsigned int tpu4_to1_pins[] = {
  3028. /* TO */
  3029. 199,
  3030. };
  3031. static const unsigned int tpu4_to1_mux[] = {
  3032. TPU4TO1_MARK,
  3033. };
  3034. static const unsigned int tpu4_to2_pins[] = {
  3035. /* TO */
  3036. 58,
  3037. };
  3038. static const unsigned int tpu4_to2_mux[] = {
  3039. TPU4TO2_MARK,
  3040. };
  3041. static const unsigned int tpu4_to3_pins[] = {
  3042. /* TO */
  3043. PIN_A11,
  3044. };
  3045. static const unsigned int tpu4_to3_mux[] = {
  3046. TPU4TO3_MARK,
  3047. };
  3048. /* - USB -------------------------------------------------------------------- */
  3049. static const unsigned int usb_vbus_pins[] = {
  3050. /* VBUS */
  3051. 0,
  3052. };
  3053. static const unsigned int usb_vbus_mux[] = {
  3054. VBUS_0_MARK,
  3055. };
  3056. static const struct sh_pfc_pin_group pinmux_groups[] = {
  3057. SH_PFC_PIN_GROUP(bsc_data_0_7),
  3058. SH_PFC_PIN_GROUP(bsc_data_8_15),
  3059. SH_PFC_PIN_GROUP(bsc_cs4),
  3060. SH_PFC_PIN_GROUP(bsc_cs5_a),
  3061. SH_PFC_PIN_GROUP(bsc_cs5_b),
  3062. SH_PFC_PIN_GROUP(bsc_cs6_a),
  3063. SH_PFC_PIN_GROUP(bsc_cs6_b),
  3064. SH_PFC_PIN_GROUP(bsc_rd),
  3065. SH_PFC_PIN_GROUP(bsc_rdwr_0),
  3066. SH_PFC_PIN_GROUP(bsc_rdwr_1),
  3067. SH_PFC_PIN_GROUP(bsc_rdwr_2),
  3068. SH_PFC_PIN_GROUP(bsc_we0),
  3069. SH_PFC_PIN_GROUP(bsc_we1),
  3070. SH_PFC_PIN_GROUP(fsia_mclk_in),
  3071. SH_PFC_PIN_GROUP(fsia_mclk_out),
  3072. SH_PFC_PIN_GROUP(fsia_sclk_in),
  3073. SH_PFC_PIN_GROUP(fsia_sclk_out),
  3074. SH_PFC_PIN_GROUP(fsia_data_in),
  3075. SH_PFC_PIN_GROUP(fsia_data_out),
  3076. SH_PFC_PIN_GROUP(fsia_spdif),
  3077. SH_PFC_PIN_GROUP(fsib_mclk_in),
  3078. SH_PFC_PIN_GROUP(fsib_mclk_out),
  3079. SH_PFC_PIN_GROUP(fsib_sclk_in),
  3080. SH_PFC_PIN_GROUP(fsib_sclk_out),
  3081. SH_PFC_PIN_GROUP(fsib_data_in),
  3082. SH_PFC_PIN_GROUP(fsib_data_out),
  3083. SH_PFC_PIN_GROUP(fsib_spdif),
  3084. SH_PFC_PIN_GROUP(fsic_mclk_in),
  3085. SH_PFC_PIN_GROUP(fsic_mclk_out),
  3086. SH_PFC_PIN_GROUP(fsic_sclk_in),
  3087. SH_PFC_PIN_GROUP(fsic_sclk_out),
  3088. SH_PFC_PIN_GROUP(fsic_data_in),
  3089. SH_PFC_PIN_GROUP(fsic_data_out),
  3090. SH_PFC_PIN_GROUP(fsic_spdif_0),
  3091. SH_PFC_PIN_GROUP(fsic_spdif_1),
  3092. SH_PFC_PIN_GROUP(fsid_sclk_in),
  3093. SH_PFC_PIN_GROUP(fsid_sclk_out),
  3094. SH_PFC_PIN_GROUP(fsid_data_in),
  3095. SH_PFC_PIN_GROUP(i2c2_0),
  3096. SH_PFC_PIN_GROUP(i2c2_1),
  3097. SH_PFC_PIN_GROUP(i2c2_2),
  3098. SH_PFC_PIN_GROUP(i2c3_0),
  3099. SH_PFC_PIN_GROUP(i2c3_1),
  3100. SH_PFC_PIN_GROUP(i2c3_2),
  3101. SH_PFC_PIN_GROUP(irda_0),
  3102. SH_PFC_PIN_GROUP(irda_1),
  3103. SH_PFC_PIN_GROUP(keysc_in5),
  3104. SH_PFC_PIN_GROUP(keysc_in6),
  3105. SH_PFC_PIN_GROUP(keysc_in7),
  3106. SH_PFC_PIN_GROUP(keysc_in8),
  3107. SH_PFC_PIN_GROUP(keysc_out04),
  3108. SH_PFC_PIN_GROUP(keysc_out5),
  3109. SH_PFC_PIN_GROUP(keysc_out6_0),
  3110. SH_PFC_PIN_GROUP(keysc_out6_1),
  3111. SH_PFC_PIN_GROUP(keysc_out6_2),
  3112. SH_PFC_PIN_GROUP(keysc_out7_0),
  3113. SH_PFC_PIN_GROUP(keysc_out7_1),
  3114. SH_PFC_PIN_GROUP(keysc_out7_2),
  3115. SH_PFC_PIN_GROUP(keysc_out8_0),
  3116. SH_PFC_PIN_GROUP(keysc_out8_1),
  3117. SH_PFC_PIN_GROUP(keysc_out8_2),
  3118. SH_PFC_PIN_GROUP(keysc_out9_0),
  3119. SH_PFC_PIN_GROUP(keysc_out9_1),
  3120. SH_PFC_PIN_GROUP(keysc_out9_2),
  3121. SH_PFC_PIN_GROUP(keysc_out10_0),
  3122. SH_PFC_PIN_GROUP(keysc_out10_1),
  3123. SH_PFC_PIN_GROUP(keysc_out11_0),
  3124. SH_PFC_PIN_GROUP(keysc_out11_1),
  3125. SH_PFC_PIN_GROUP(lcd_data8),
  3126. SH_PFC_PIN_GROUP(lcd_data9),
  3127. SH_PFC_PIN_GROUP(lcd_data12),
  3128. SH_PFC_PIN_GROUP(lcd_data16),
  3129. SH_PFC_PIN_GROUP(lcd_data18),
  3130. SH_PFC_PIN_GROUP(lcd_data24),
  3131. SH_PFC_PIN_GROUP(lcd_display),
  3132. SH_PFC_PIN_GROUP(lcd_lclk),
  3133. SH_PFC_PIN_GROUP(lcd_sync),
  3134. SH_PFC_PIN_GROUP(lcd_sys),
  3135. SH_PFC_PIN_GROUP(lcd2_data8),
  3136. SH_PFC_PIN_GROUP(lcd2_data9),
  3137. SH_PFC_PIN_GROUP(lcd2_data12),
  3138. SH_PFC_PIN_GROUP(lcd2_data16),
  3139. SH_PFC_PIN_GROUP(lcd2_data18),
  3140. SH_PFC_PIN_GROUP(lcd2_data24),
  3141. SH_PFC_PIN_GROUP(lcd2_sync_0),
  3142. SH_PFC_PIN_GROUP(lcd2_sync_1),
  3143. SH_PFC_PIN_GROUP(lcd2_sys_0),
  3144. SH_PFC_PIN_GROUP(lcd2_sys_1),
  3145. SH_PFC_PIN_GROUP(mmc0_data1_0),
  3146. SH_PFC_PIN_GROUP(mmc0_data4_0),
  3147. SH_PFC_PIN_GROUP(mmc0_data8_0),
  3148. SH_PFC_PIN_GROUP(mmc0_ctrl_0),
  3149. SH_PFC_PIN_GROUP(mmc0_data1_1),
  3150. SH_PFC_PIN_GROUP(mmc0_data4_1),
  3151. SH_PFC_PIN_GROUP(mmc0_data8_1),
  3152. SH_PFC_PIN_GROUP(mmc0_ctrl_1),
  3153. SH_PFC_PIN_GROUP(msiof0_rsck),
  3154. SH_PFC_PIN_GROUP(msiof0_tsck),
  3155. SH_PFC_PIN_GROUP(msiof0_rsync),
  3156. SH_PFC_PIN_GROUP(msiof0_tsync),
  3157. SH_PFC_PIN_GROUP(msiof0_ss1),
  3158. SH_PFC_PIN_GROUP(msiof0_ss2),
  3159. SH_PFC_PIN_GROUP(msiof0_rxd),
  3160. SH_PFC_PIN_GROUP(msiof0_txd),
  3161. SH_PFC_PIN_GROUP(msiof0_mck0),
  3162. SH_PFC_PIN_GROUP(msiof0_mck1),
  3163. SH_PFC_PIN_GROUP(msiof0l_rsck),
  3164. SH_PFC_PIN_GROUP(msiof0l_tsck),
  3165. SH_PFC_PIN_GROUP(msiof0l_rsync),
  3166. SH_PFC_PIN_GROUP(msiof0l_tsync),
  3167. SH_PFC_PIN_GROUP(msiof0l_ss1_a),
  3168. SH_PFC_PIN_GROUP(msiof0l_ss1_b),
  3169. SH_PFC_PIN_GROUP(msiof0l_ss2_a),
  3170. SH_PFC_PIN_GROUP(msiof0l_ss2_b),
  3171. SH_PFC_PIN_GROUP(msiof0l_rxd),
  3172. SH_PFC_PIN_GROUP(msiof0l_txd),
  3173. SH_PFC_PIN_GROUP(msiof0l_mck0),
  3174. SH_PFC_PIN_GROUP(msiof0l_mck1),
  3175. SH_PFC_PIN_GROUP(msiof1_rsck),
  3176. SH_PFC_PIN_GROUP(msiof1_tsck),
  3177. SH_PFC_PIN_GROUP(msiof1_rsync),
  3178. SH_PFC_PIN_GROUP(msiof1_tsync),
  3179. SH_PFC_PIN_GROUP(msiof1_ss1),
  3180. SH_PFC_PIN_GROUP(msiof1_ss2),
  3181. SH_PFC_PIN_GROUP(msiof1_rxd),
  3182. SH_PFC_PIN_GROUP(msiof1_txd),
  3183. SH_PFC_PIN_GROUP(msiof1_mck0),
  3184. SH_PFC_PIN_GROUP(msiof1_mck1),
  3185. SH_PFC_PIN_GROUP(msiof2_rsck),
  3186. SH_PFC_PIN_GROUP(msiof2_tsck),
  3187. SH_PFC_PIN_GROUP(msiof2_rsync),
  3188. SH_PFC_PIN_GROUP(msiof2_tsync),
  3189. SH_PFC_PIN_GROUP(msiof2_ss1_a),
  3190. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  3191. SH_PFC_PIN_GROUP(msiof2_ss2_a),
  3192. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  3193. SH_PFC_PIN_GROUP(msiof2_rxd_a),
  3194. SH_PFC_PIN_GROUP(msiof2_rxd_b),
  3195. SH_PFC_PIN_GROUP(msiof2_txd),
  3196. SH_PFC_PIN_GROUP(msiof2_mck0),
  3197. SH_PFC_PIN_GROUP(msiof2_mck1),
  3198. SH_PFC_PIN_GROUP(msiof2r_tsck),
  3199. SH_PFC_PIN_GROUP(msiof2r_tsync),
  3200. SH_PFC_PIN_GROUP(msiof2r_rxd),
  3201. SH_PFC_PIN_GROUP(msiof2r_txd),
  3202. SH_PFC_PIN_GROUP(msiof3_rsck),
  3203. SH_PFC_PIN_GROUP(msiof3_tsck),
  3204. SH_PFC_PIN_GROUP(msiof3_rsync),
  3205. SH_PFC_PIN_GROUP(msiof3_tsync),
  3206. SH_PFC_PIN_GROUP(msiof3_ss1),
  3207. SH_PFC_PIN_GROUP(msiof3_ss2),
  3208. SH_PFC_PIN_GROUP(msiof3_rxd),
  3209. SH_PFC_PIN_GROUP(msiof3_txd),
  3210. SH_PFC_PIN_GROUP(msiof3_flow),
  3211. SH_PFC_PIN_GROUP(scifa0_data),
  3212. SH_PFC_PIN_GROUP(scifa0_clk),
  3213. SH_PFC_PIN_GROUP(scifa0_ctrl),
  3214. SH_PFC_PIN_GROUP(scifa1_data),
  3215. SH_PFC_PIN_GROUP(scifa1_clk),
  3216. SH_PFC_PIN_GROUP(scifa1_ctrl),
  3217. SH_PFC_PIN_GROUP(scifa2_data_0),
  3218. SH_PFC_PIN_GROUP(scifa2_clk_0),
  3219. SH_PFC_PIN_GROUP(scifa2_ctrl_0),
  3220. SH_PFC_PIN_GROUP(scifa2_data_1),
  3221. SH_PFC_PIN_GROUP(scifa2_clk_1),
  3222. SH_PFC_PIN_GROUP(scifa2_ctrl_1),
  3223. SH_PFC_PIN_GROUP(scifa3_data),
  3224. SH_PFC_PIN_GROUP(scifa3_ctrl),
  3225. SH_PFC_PIN_GROUP(scifa4_data),
  3226. SH_PFC_PIN_GROUP(scifa4_ctrl),
  3227. SH_PFC_PIN_GROUP(scifa5_data_0),
  3228. SH_PFC_PIN_GROUP(scifa5_clk_0),
  3229. SH_PFC_PIN_GROUP(scifa5_ctrl_0),
  3230. SH_PFC_PIN_GROUP(scifa5_data_1),
  3231. SH_PFC_PIN_GROUP(scifa5_clk_1),
  3232. SH_PFC_PIN_GROUP(scifa5_ctrl_1),
  3233. SH_PFC_PIN_GROUP(scifa5_data_2),
  3234. SH_PFC_PIN_GROUP(scifa5_clk_2),
  3235. SH_PFC_PIN_GROUP(scifa5_ctrl_2),
  3236. SH_PFC_PIN_GROUP(scifa6),
  3237. SH_PFC_PIN_GROUP(scifa7_data),
  3238. SH_PFC_PIN_GROUP(scifa7_ctrl),
  3239. SH_PFC_PIN_GROUP(scifb_data_0),
  3240. SH_PFC_PIN_GROUP(scifb_clk_0),
  3241. SH_PFC_PIN_GROUP(scifb_ctrl_0),
  3242. SH_PFC_PIN_GROUP(scifb_data_1),
  3243. SH_PFC_PIN_GROUP(scifb_clk_1),
  3244. SH_PFC_PIN_GROUP(scifb_ctrl_1),
  3245. SH_PFC_PIN_GROUP(sdhi0_data1),
  3246. SH_PFC_PIN_GROUP(sdhi0_data4),
  3247. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  3248. SH_PFC_PIN_GROUP(sdhi0_cd),
  3249. SH_PFC_PIN_GROUP(sdhi0_wp),
  3250. SH_PFC_PIN_GROUP(sdhi1_data1),
  3251. SH_PFC_PIN_GROUP(sdhi1_data4),
  3252. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  3253. SH_PFC_PIN_GROUP(sdhi2_data1),
  3254. SH_PFC_PIN_GROUP(sdhi2_data4),
  3255. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  3256. SH_PFC_PIN_GROUP(tpu0_to0),
  3257. SH_PFC_PIN_GROUP(tpu0_to1),
  3258. SH_PFC_PIN_GROUP(tpu0_to2),
  3259. SH_PFC_PIN_GROUP(tpu0_to3),
  3260. SH_PFC_PIN_GROUP(tpu1_to0),
  3261. SH_PFC_PIN_GROUP(tpu1_to1_0),
  3262. SH_PFC_PIN_GROUP(tpu1_to1_1),
  3263. SH_PFC_PIN_GROUP(tpu1_to2),
  3264. SH_PFC_PIN_GROUP(tpu1_to3),
  3265. SH_PFC_PIN_GROUP(tpu2_to0),
  3266. SH_PFC_PIN_GROUP(tpu2_to1),
  3267. SH_PFC_PIN_GROUP(tpu2_to2),
  3268. SH_PFC_PIN_GROUP(tpu2_to3),
  3269. SH_PFC_PIN_GROUP(tpu3_to0),
  3270. SH_PFC_PIN_GROUP(tpu3_to1),
  3271. SH_PFC_PIN_GROUP(tpu3_to2),
  3272. SH_PFC_PIN_GROUP(tpu3_to3),
  3273. SH_PFC_PIN_GROUP(tpu4_to0),
  3274. SH_PFC_PIN_GROUP(tpu4_to1),
  3275. SH_PFC_PIN_GROUP(tpu4_to2),
  3276. SH_PFC_PIN_GROUP(tpu4_to3),
  3277. SH_PFC_PIN_GROUP(usb_vbus),
  3278. };
  3279. static const char * const bsc_groups[] = {
  3280. "bsc_data_0_7",
  3281. "bsc_data_8_15",
  3282. "bsc_cs4",
  3283. "bsc_cs5_a",
  3284. "bsc_cs5_b",
  3285. "bsc_cs6_a",
  3286. "bsc_cs6_b",
  3287. "bsc_rd",
  3288. "bsc_rdwr_0",
  3289. "bsc_rdwr_1",
  3290. "bsc_rdwr_2",
  3291. "bsc_we0",
  3292. "bsc_we1",
  3293. };
  3294. static const char * const fsia_groups[] = {
  3295. "fsia_mclk_in",
  3296. "fsia_mclk_out",
  3297. "fsia_sclk_in",
  3298. "fsia_sclk_out",
  3299. "fsia_data_in",
  3300. "fsia_data_out",
  3301. "fsia_spdif",
  3302. };
  3303. static const char * const fsib_groups[] = {
  3304. "fsib_mclk_in",
  3305. "fsib_mclk_out",
  3306. "fsib_sclk_in",
  3307. "fsib_sclk_out",
  3308. "fsib_data_in",
  3309. "fsib_data_out",
  3310. "fsib_spdif",
  3311. };
  3312. static const char * const fsic_groups[] = {
  3313. "fsic_mclk_in",
  3314. "fsic_mclk_out",
  3315. "fsic_sclk_in",
  3316. "fsic_sclk_out",
  3317. "fsic_data_in",
  3318. "fsic_data_out",
  3319. "fsic_spdif_0",
  3320. "fsic_spdif_1",
  3321. };
  3322. static const char * const fsid_groups[] = {
  3323. "fsid_sclk_in",
  3324. "fsid_sclk_out",
  3325. "fsid_data_in",
  3326. };
  3327. static const char * const i2c2_groups[] = {
  3328. "i2c2_0",
  3329. "i2c2_1",
  3330. "i2c2_2",
  3331. };
  3332. static const char * const i2c3_groups[] = {
  3333. "i2c3_0",
  3334. "i2c3_1",
  3335. "i2c3_2",
  3336. };
  3337. static const char * const irda_groups[] = {
  3338. "irda_0",
  3339. "irda_1",
  3340. };
  3341. static const char * const keysc_groups[] = {
  3342. "keysc_in5",
  3343. "keysc_in6",
  3344. "keysc_in7",
  3345. "keysc_in8",
  3346. "keysc_out04",
  3347. "keysc_out5",
  3348. "keysc_out6_0",
  3349. "keysc_out6_1",
  3350. "keysc_out6_2",
  3351. "keysc_out7_0",
  3352. "keysc_out7_1",
  3353. "keysc_out7_2",
  3354. "keysc_out8_0",
  3355. "keysc_out8_1",
  3356. "keysc_out8_2",
  3357. "keysc_out9_0",
  3358. "keysc_out9_1",
  3359. "keysc_out9_2",
  3360. "keysc_out10_0",
  3361. "keysc_out10_1",
  3362. "keysc_out11_0",
  3363. "keysc_out11_1",
  3364. };
  3365. static const char * const lcd_groups[] = {
  3366. "lcd_data8",
  3367. "lcd_data9",
  3368. "lcd_data12",
  3369. "lcd_data16",
  3370. "lcd_data18",
  3371. "lcd_data24",
  3372. "lcd_display",
  3373. "lcd_lclk",
  3374. "lcd_sync",
  3375. "lcd_sys",
  3376. };
  3377. static const char * const lcd2_groups[] = {
  3378. "lcd2_data8",
  3379. "lcd2_data9",
  3380. "lcd2_data12",
  3381. "lcd2_data16",
  3382. "lcd2_data18",
  3383. "lcd2_data24",
  3384. "lcd2_sync_0",
  3385. "lcd2_sync_1",
  3386. "lcd2_sys_0",
  3387. "lcd2_sys_1",
  3388. };
  3389. static const char * const mmc0_groups[] = {
  3390. "mmc0_data1_0",
  3391. "mmc0_data4_0",
  3392. "mmc0_data8_0",
  3393. "mmc0_ctrl_0",
  3394. "mmc0_data1_1",
  3395. "mmc0_data4_1",
  3396. "mmc0_data8_1",
  3397. "mmc0_ctrl_1",
  3398. };
  3399. static const char * const msiof0_groups[] = {
  3400. "msiof0_rsck",
  3401. "msiof0_tsck",
  3402. "msiof0_rsync",
  3403. "msiof0_tsync",
  3404. "msiof0_ss1",
  3405. "msiof0_ss2",
  3406. "msiof0_rxd",
  3407. "msiof0_txd",
  3408. "msiof0_mck0",
  3409. "msiof0_mck1",
  3410. "msiof0l_rsck",
  3411. "msiof0l_tsck",
  3412. "msiof0l_rsync",
  3413. "msiof0l_tsync",
  3414. "msiof0l_ss1_a",
  3415. "msiof0l_ss1_b",
  3416. "msiof0l_ss2_a",
  3417. "msiof0l_ss2_b",
  3418. "msiof0l_rxd",
  3419. "msiof0l_txd",
  3420. "msiof0l_mck0",
  3421. "msiof0l_mck1",
  3422. };
  3423. static const char * const msiof1_groups[] = {
  3424. "msiof1_rsck",
  3425. "msiof1_tsck",
  3426. "msiof1_rsync",
  3427. "msiof1_tsync",
  3428. "msiof1_ss1",
  3429. "msiof1_ss2",
  3430. "msiof1_rxd",
  3431. "msiof1_txd",
  3432. "msiof1_mck0",
  3433. "msiof1_mck1",
  3434. };
  3435. static const char * const msiof2_groups[] = {
  3436. "msiof2_rsck",
  3437. "msiof2_tsck",
  3438. "msiof2_rsync",
  3439. "msiof2_tsync",
  3440. "msiof2_ss1_a",
  3441. "msiof2_ss1_b",
  3442. "msiof2_ss2_a",
  3443. "msiof2_ss2_b",
  3444. "msiof2_rxd_a",
  3445. "msiof2_rxd_b",
  3446. "msiof2_txd",
  3447. "msiof2_mck0",
  3448. "msiof2_mck1",
  3449. "msiof2r_tsck",
  3450. "msiof2r_tsync",
  3451. "msiof2r_rxd",
  3452. "msiof2r_txd",
  3453. };
  3454. static const char * const msiof3_groups[] = {
  3455. "msiof3_rsck",
  3456. "msiof3_tsck",
  3457. "msiof3_rsync",
  3458. "msiof3_tsync",
  3459. "msiof3_ss1",
  3460. "msiof3_ss2",
  3461. "msiof3_rxd",
  3462. "msiof3_txd",
  3463. "msiof3_flow",
  3464. };
  3465. static const char * const scifa0_groups[] = {
  3466. "scifa0_data",
  3467. "scifa0_clk",
  3468. "scifa0_ctrl",
  3469. };
  3470. static const char * const scifa1_groups[] = {
  3471. "scifa1_data",
  3472. "scifa1_clk",
  3473. "scifa1_ctrl",
  3474. };
  3475. static const char * const scifa2_groups[] = {
  3476. "scifa2_data_0",
  3477. "scifa2_clk_0",
  3478. "scifa2_ctrl_0",
  3479. "scifa2_data_1",
  3480. "scifa2_clk_1",
  3481. "scifa2_ctrl_1",
  3482. };
  3483. static const char * const scifa3_groups[] = {
  3484. "scifa3_data",
  3485. "scifa3_ctrl",
  3486. };
  3487. static const char * const scifa4_groups[] = {
  3488. "scifa4_data",
  3489. "scifa4_ctrl",
  3490. };
  3491. static const char * const scifa5_groups[] = {
  3492. "scifa5_data_0",
  3493. "scifa5_clk_0",
  3494. "scifa5_ctrl_0",
  3495. "scifa5_data_1",
  3496. "scifa5_clk_1",
  3497. "scifa5_ctrl_1",
  3498. "scifa5_data_2",
  3499. "scifa5_clk_2",
  3500. "scifa5_ctrl_2",
  3501. };
  3502. static const char * const scifa6_groups[] = {
  3503. "scifa6",
  3504. };
  3505. static const char * const scifa7_groups[] = {
  3506. "scifa7_data",
  3507. "scifa7_ctrl",
  3508. };
  3509. static const char * const scifb_groups[] = {
  3510. "scifb_data_0",
  3511. "scifb_clk_0",
  3512. "scifb_ctrl_0",
  3513. "scifb_data_1",
  3514. "scifb_clk_1",
  3515. "scifb_ctrl_1",
  3516. };
  3517. static const char * const sdhi0_groups[] = {
  3518. "sdhi0_data1",
  3519. "sdhi0_data4",
  3520. "sdhi0_ctrl",
  3521. "sdhi0_cd",
  3522. "sdhi0_wp",
  3523. };
  3524. static const char * const sdhi1_groups[] = {
  3525. "sdhi1_data1",
  3526. "sdhi1_data4",
  3527. "sdhi1_ctrl",
  3528. };
  3529. static const char * const sdhi2_groups[] = {
  3530. "sdhi2_data1",
  3531. "sdhi2_data4",
  3532. "sdhi2_ctrl",
  3533. };
  3534. static const char * const usb_groups[] = {
  3535. "usb_vbus",
  3536. };
  3537. static const char * const tpu0_groups[] = {
  3538. "tpu0_to0",
  3539. "tpu0_to1",
  3540. "tpu0_to2",
  3541. "tpu0_to3",
  3542. };
  3543. static const char * const tpu1_groups[] = {
  3544. "tpu1_to0",
  3545. "tpu1_to1_0",
  3546. "tpu1_to1_1",
  3547. "tpu1_to2",
  3548. "tpu1_to3",
  3549. };
  3550. static const char * const tpu2_groups[] = {
  3551. "tpu2_to0",
  3552. "tpu2_to1",
  3553. "tpu2_to2",
  3554. "tpu2_to3",
  3555. };
  3556. static const char * const tpu3_groups[] = {
  3557. "tpu3_to0",
  3558. "tpu3_to1",
  3559. "tpu3_to2",
  3560. "tpu3_to3",
  3561. };
  3562. static const char * const tpu4_groups[] = {
  3563. "tpu4_to0",
  3564. "tpu4_to1",
  3565. "tpu4_to2",
  3566. "tpu4_to3",
  3567. };
  3568. static const struct sh_pfc_function pinmux_functions[] = {
  3569. SH_PFC_FUNCTION(bsc),
  3570. SH_PFC_FUNCTION(fsia),
  3571. SH_PFC_FUNCTION(fsib),
  3572. SH_PFC_FUNCTION(fsic),
  3573. SH_PFC_FUNCTION(fsid),
  3574. SH_PFC_FUNCTION(i2c2),
  3575. SH_PFC_FUNCTION(i2c3),
  3576. SH_PFC_FUNCTION(irda),
  3577. SH_PFC_FUNCTION(keysc),
  3578. SH_PFC_FUNCTION(lcd),
  3579. SH_PFC_FUNCTION(lcd2),
  3580. SH_PFC_FUNCTION(mmc0),
  3581. SH_PFC_FUNCTION(msiof0),
  3582. SH_PFC_FUNCTION(msiof1),
  3583. SH_PFC_FUNCTION(msiof2),
  3584. SH_PFC_FUNCTION(msiof3),
  3585. SH_PFC_FUNCTION(scifa0),
  3586. SH_PFC_FUNCTION(scifa1),
  3587. SH_PFC_FUNCTION(scifa2),
  3588. SH_PFC_FUNCTION(scifa3),
  3589. SH_PFC_FUNCTION(scifa4),
  3590. SH_PFC_FUNCTION(scifa5),
  3591. SH_PFC_FUNCTION(scifa6),
  3592. SH_PFC_FUNCTION(scifa7),
  3593. SH_PFC_FUNCTION(scifb),
  3594. SH_PFC_FUNCTION(sdhi0),
  3595. SH_PFC_FUNCTION(sdhi1),
  3596. SH_PFC_FUNCTION(sdhi2),
  3597. SH_PFC_FUNCTION(tpu0),
  3598. SH_PFC_FUNCTION(tpu1),
  3599. SH_PFC_FUNCTION(tpu2),
  3600. SH_PFC_FUNCTION(tpu3),
  3601. SH_PFC_FUNCTION(tpu4),
  3602. SH_PFC_FUNCTION(usb),
  3603. };
  3604. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  3605. PORTCR(0, 0xe6050000), /* PORT0CR */
  3606. PORTCR(1, 0xe6050001), /* PORT1CR */
  3607. PORTCR(2, 0xe6050002), /* PORT2CR */
  3608. PORTCR(3, 0xe6050003), /* PORT3CR */
  3609. PORTCR(4, 0xe6050004), /* PORT4CR */
  3610. PORTCR(5, 0xe6050005), /* PORT5CR */
  3611. PORTCR(6, 0xe6050006), /* PORT6CR */
  3612. PORTCR(7, 0xe6050007), /* PORT7CR */
  3613. PORTCR(8, 0xe6050008), /* PORT8CR */
  3614. PORTCR(9, 0xe6050009), /* PORT9CR */
  3615. PORTCR(10, 0xe605000a), /* PORT10CR */
  3616. PORTCR(11, 0xe605000b), /* PORT11CR */
  3617. PORTCR(12, 0xe605000c), /* PORT12CR */
  3618. PORTCR(13, 0xe605000d), /* PORT13CR */
  3619. PORTCR(14, 0xe605000e), /* PORT14CR */
  3620. PORTCR(15, 0xe605000f), /* PORT15CR */
  3621. PORTCR(16, 0xe6050010), /* PORT16CR */
  3622. PORTCR(17, 0xe6050011), /* PORT17CR */
  3623. PORTCR(18, 0xe6050012), /* PORT18CR */
  3624. PORTCR(19, 0xe6050013), /* PORT19CR */
  3625. PORTCR(20, 0xe6050014), /* PORT20CR */
  3626. PORTCR(21, 0xe6050015), /* PORT21CR */
  3627. PORTCR(22, 0xe6050016), /* PORT22CR */
  3628. PORTCR(23, 0xe6050017), /* PORT23CR */
  3629. PORTCR(24, 0xe6050018), /* PORT24CR */
  3630. PORTCR(25, 0xe6050019), /* PORT25CR */
  3631. PORTCR(26, 0xe605001a), /* PORT26CR */
  3632. PORTCR(27, 0xe605001b), /* PORT27CR */
  3633. PORTCR(28, 0xe605001c), /* PORT28CR */
  3634. PORTCR(29, 0xe605001d), /* PORT29CR */
  3635. PORTCR(30, 0xe605001e), /* PORT30CR */
  3636. PORTCR(31, 0xe605001f), /* PORT31CR */
  3637. PORTCR(32, 0xe6051020), /* PORT32CR */
  3638. PORTCR(33, 0xe6051021), /* PORT33CR */
  3639. PORTCR(34, 0xe6051022), /* PORT34CR */
  3640. PORTCR(35, 0xe6051023), /* PORT35CR */
  3641. PORTCR(36, 0xe6051024), /* PORT36CR */
  3642. PORTCR(37, 0xe6051025), /* PORT37CR */
  3643. PORTCR(38, 0xe6051026), /* PORT38CR */
  3644. PORTCR(39, 0xe6051027), /* PORT39CR */
  3645. PORTCR(40, 0xe6051028), /* PORT40CR */
  3646. PORTCR(41, 0xe6051029), /* PORT41CR */
  3647. PORTCR(42, 0xe605102a), /* PORT42CR */
  3648. PORTCR(43, 0xe605102b), /* PORT43CR */
  3649. PORTCR(44, 0xe605102c), /* PORT44CR */
  3650. PORTCR(45, 0xe605102d), /* PORT45CR */
  3651. PORTCR(46, 0xe605102e), /* PORT46CR */
  3652. PORTCR(47, 0xe605102f), /* PORT47CR */
  3653. PORTCR(48, 0xe6051030), /* PORT48CR */
  3654. PORTCR(49, 0xe6051031), /* PORT49CR */
  3655. PORTCR(50, 0xe6051032), /* PORT50CR */
  3656. PORTCR(51, 0xe6051033), /* PORT51CR */
  3657. PORTCR(52, 0xe6051034), /* PORT52CR */
  3658. PORTCR(53, 0xe6051035), /* PORT53CR */
  3659. PORTCR(54, 0xe6051036), /* PORT54CR */
  3660. PORTCR(55, 0xe6051037), /* PORT55CR */
  3661. PORTCR(56, 0xe6051038), /* PORT56CR */
  3662. PORTCR(57, 0xe6051039), /* PORT57CR */
  3663. PORTCR(58, 0xe605103a), /* PORT58CR */
  3664. PORTCR(59, 0xe605103b), /* PORT59CR */
  3665. PORTCR(60, 0xe605103c), /* PORT60CR */
  3666. PORTCR(61, 0xe605103d), /* PORT61CR */
  3667. PORTCR(62, 0xe605103e), /* PORT62CR */
  3668. PORTCR(63, 0xe605103f), /* PORT63CR */
  3669. PORTCR(64, 0xe6051040), /* PORT64CR */
  3670. PORTCR(65, 0xe6051041), /* PORT65CR */
  3671. PORTCR(66, 0xe6051042), /* PORT66CR */
  3672. PORTCR(67, 0xe6051043), /* PORT67CR */
  3673. PORTCR(68, 0xe6051044), /* PORT68CR */
  3674. PORTCR(69, 0xe6051045), /* PORT69CR */
  3675. PORTCR(70, 0xe6051046), /* PORT70CR */
  3676. PORTCR(71, 0xe6051047), /* PORT71CR */
  3677. PORTCR(72, 0xe6051048), /* PORT72CR */
  3678. PORTCR(73, 0xe6051049), /* PORT73CR */
  3679. PORTCR(74, 0xe605104a), /* PORT74CR */
  3680. PORTCR(75, 0xe605104b), /* PORT75CR */
  3681. PORTCR(76, 0xe605104c), /* PORT76CR */
  3682. PORTCR(77, 0xe605104d), /* PORT77CR */
  3683. PORTCR(78, 0xe605104e), /* PORT78CR */
  3684. PORTCR(79, 0xe605104f), /* PORT79CR */
  3685. PORTCR(80, 0xe6051050), /* PORT80CR */
  3686. PORTCR(81, 0xe6051051), /* PORT81CR */
  3687. PORTCR(82, 0xe6051052), /* PORT82CR */
  3688. PORTCR(83, 0xe6051053), /* PORT83CR */
  3689. PORTCR(84, 0xe6051054), /* PORT84CR */
  3690. PORTCR(85, 0xe6051055), /* PORT85CR */
  3691. PORTCR(86, 0xe6051056), /* PORT86CR */
  3692. PORTCR(87, 0xe6051057), /* PORT87CR */
  3693. PORTCR(88, 0xe6051058), /* PORT88CR */
  3694. PORTCR(89, 0xe6051059), /* PORT89CR */
  3695. PORTCR(90, 0xe605105a), /* PORT90CR */
  3696. PORTCR(91, 0xe605105b), /* PORT91CR */
  3697. PORTCR(92, 0xe605105c), /* PORT92CR */
  3698. PORTCR(93, 0xe605105d), /* PORT93CR */
  3699. PORTCR(94, 0xe605105e), /* PORT94CR */
  3700. PORTCR(95, 0xe605105f), /* PORT95CR */
  3701. PORTCR(96, 0xe6052060), /* PORT96CR */
  3702. PORTCR(97, 0xe6052061), /* PORT97CR */
  3703. PORTCR(98, 0xe6052062), /* PORT98CR */
  3704. PORTCR(99, 0xe6052063), /* PORT99CR */
  3705. PORTCR(100, 0xe6052064), /* PORT100CR */
  3706. PORTCR(101, 0xe6052065), /* PORT101CR */
  3707. PORTCR(102, 0xe6052066), /* PORT102CR */
  3708. PORTCR(103, 0xe6052067), /* PORT103CR */
  3709. PORTCR(104, 0xe6052068), /* PORT104CR */
  3710. PORTCR(105, 0xe6052069), /* PORT105CR */
  3711. PORTCR(106, 0xe605206a), /* PORT106CR */
  3712. PORTCR(107, 0xe605206b), /* PORT107CR */
  3713. PORTCR(108, 0xe605206c), /* PORT108CR */
  3714. PORTCR(109, 0xe605206d), /* PORT109CR */
  3715. PORTCR(110, 0xe605206e), /* PORT110CR */
  3716. PORTCR(111, 0xe605206f), /* PORT111CR */
  3717. PORTCR(112, 0xe6052070), /* PORT112CR */
  3718. PORTCR(113, 0xe6052071), /* PORT113CR */
  3719. PORTCR(114, 0xe6052072), /* PORT114CR */
  3720. PORTCR(115, 0xe6052073), /* PORT115CR */
  3721. PORTCR(116, 0xe6052074), /* PORT116CR */
  3722. PORTCR(117, 0xe6052075), /* PORT117CR */
  3723. PORTCR(118, 0xe6052076), /* PORT118CR */
  3724. PORTCR(128, 0xe6052080), /* PORT128CR */
  3725. PORTCR(129, 0xe6052081), /* PORT129CR */
  3726. PORTCR(130, 0xe6052082), /* PORT130CR */
  3727. PORTCR(131, 0xe6052083), /* PORT131CR */
  3728. PORTCR(132, 0xe6052084), /* PORT132CR */
  3729. PORTCR(133, 0xe6052085), /* PORT133CR */
  3730. PORTCR(134, 0xe6052086), /* PORT134CR */
  3731. PORTCR(135, 0xe6052087), /* PORT135CR */
  3732. PORTCR(136, 0xe6052088), /* PORT136CR */
  3733. PORTCR(137, 0xe6052089), /* PORT137CR */
  3734. PORTCR(138, 0xe605208a), /* PORT138CR */
  3735. PORTCR(139, 0xe605208b), /* PORT139CR */
  3736. PORTCR(140, 0xe605208c), /* PORT140CR */
  3737. PORTCR(141, 0xe605208d), /* PORT141CR */
  3738. PORTCR(142, 0xe605208e), /* PORT142CR */
  3739. PORTCR(143, 0xe605208f), /* PORT143CR */
  3740. PORTCR(144, 0xe6052090), /* PORT144CR */
  3741. PORTCR(145, 0xe6052091), /* PORT145CR */
  3742. PORTCR(146, 0xe6052092), /* PORT146CR */
  3743. PORTCR(147, 0xe6052093), /* PORT147CR */
  3744. PORTCR(148, 0xe6052094), /* PORT148CR */
  3745. PORTCR(149, 0xe6052095), /* PORT149CR */
  3746. PORTCR(150, 0xe6052096), /* PORT150CR */
  3747. PORTCR(151, 0xe6052097), /* PORT151CR */
  3748. PORTCR(152, 0xe6052098), /* PORT152CR */
  3749. PORTCR(153, 0xe6052099), /* PORT153CR */
  3750. PORTCR(154, 0xe605209a), /* PORT154CR */
  3751. PORTCR(155, 0xe605209b), /* PORT155CR */
  3752. PORTCR(156, 0xe605209c), /* PORT156CR */
  3753. PORTCR(157, 0xe605209d), /* PORT157CR */
  3754. PORTCR(158, 0xe605209e), /* PORT158CR */
  3755. PORTCR(159, 0xe605209f), /* PORT159CR */
  3756. PORTCR(160, 0xe60520a0), /* PORT160CR */
  3757. PORTCR(161, 0xe60520a1), /* PORT161CR */
  3758. PORTCR(162, 0xe60520a2), /* PORT162CR */
  3759. PORTCR(163, 0xe60520a3), /* PORT163CR */
  3760. PORTCR(164, 0xe60520a4), /* PORT164CR */
  3761. PORTCR(192, 0xe60520c0), /* PORT192CR */
  3762. PORTCR(193, 0xe60520c1), /* PORT193CR */
  3763. PORTCR(194, 0xe60520c2), /* PORT194CR */
  3764. PORTCR(195, 0xe60520c3), /* PORT195CR */
  3765. PORTCR(196, 0xe60520c4), /* PORT196CR */
  3766. PORTCR(197, 0xe60520c5), /* PORT197CR */
  3767. PORTCR(198, 0xe60520c6), /* PORT198CR */
  3768. PORTCR(199, 0xe60520c7), /* PORT199CR */
  3769. PORTCR(200, 0xe60520c8), /* PORT200CR */
  3770. PORTCR(201, 0xe60520c9), /* PORT201CR */
  3771. PORTCR(202, 0xe60520ca), /* PORT202CR */
  3772. PORTCR(203, 0xe60520cb), /* PORT203CR */
  3773. PORTCR(204, 0xe60520cc), /* PORT204CR */
  3774. PORTCR(205, 0xe60520cd), /* PORT205CR */
  3775. PORTCR(206, 0xe60520ce), /* PORT206CR */
  3776. PORTCR(207, 0xe60520cf), /* PORT207CR */
  3777. PORTCR(208, 0xe60520d0), /* PORT208CR */
  3778. PORTCR(209, 0xe60520d1), /* PORT209CR */
  3779. PORTCR(210, 0xe60520d2), /* PORT210CR */
  3780. PORTCR(211, 0xe60520d3), /* PORT211CR */
  3781. PORTCR(212, 0xe60520d4), /* PORT212CR */
  3782. PORTCR(213, 0xe60520d5), /* PORT213CR */
  3783. PORTCR(214, 0xe60520d6), /* PORT214CR */
  3784. PORTCR(215, 0xe60520d7), /* PORT215CR */
  3785. PORTCR(216, 0xe60520d8), /* PORT216CR */
  3786. PORTCR(217, 0xe60520d9), /* PORT217CR */
  3787. PORTCR(218, 0xe60520da), /* PORT218CR */
  3788. PORTCR(219, 0xe60520db), /* PORT219CR */
  3789. PORTCR(220, 0xe60520dc), /* PORT220CR */
  3790. PORTCR(221, 0xe60520dd), /* PORT221CR */
  3791. PORTCR(222, 0xe60520de), /* PORT222CR */
  3792. PORTCR(223, 0xe60520df), /* PORT223CR */
  3793. PORTCR(224, 0xe60530e0), /* PORT224CR */
  3794. PORTCR(225, 0xe60530e1), /* PORT225CR */
  3795. PORTCR(226, 0xe60530e2), /* PORT226CR */
  3796. PORTCR(227, 0xe60530e3), /* PORT227CR */
  3797. PORTCR(228, 0xe60530e4), /* PORT228CR */
  3798. PORTCR(229, 0xe60530e5), /* PORT229CR */
  3799. PORTCR(230, 0xe60530e6), /* PORT230CR */
  3800. PORTCR(231, 0xe60530e7), /* PORT231CR */
  3801. PORTCR(232, 0xe60530e8), /* PORT232CR */
  3802. PORTCR(233, 0xe60530e9), /* PORT233CR */
  3803. PORTCR(234, 0xe60530ea), /* PORT234CR */
  3804. PORTCR(235, 0xe60530eb), /* PORT235CR */
  3805. PORTCR(236, 0xe60530ec), /* PORT236CR */
  3806. PORTCR(237, 0xe60530ed), /* PORT237CR */
  3807. PORTCR(238, 0xe60530ee), /* PORT238CR */
  3808. PORTCR(239, 0xe60530ef), /* PORT239CR */
  3809. PORTCR(240, 0xe60530f0), /* PORT240CR */
  3810. PORTCR(241, 0xe60530f1), /* PORT241CR */
  3811. PORTCR(242, 0xe60530f2), /* PORT242CR */
  3812. PORTCR(243, 0xe60530f3), /* PORT243CR */
  3813. PORTCR(244, 0xe60530f4), /* PORT244CR */
  3814. PORTCR(245, 0xe60530f5), /* PORT245CR */
  3815. PORTCR(246, 0xe60530f6), /* PORT246CR */
  3816. PORTCR(247, 0xe60530f7), /* PORT247CR */
  3817. PORTCR(248, 0xe60530f8), /* PORT248CR */
  3818. PORTCR(249, 0xe60530f9), /* PORT249CR */
  3819. PORTCR(250, 0xe60530fa), /* PORT250CR */
  3820. PORTCR(251, 0xe60530fb), /* PORT251CR */
  3821. PORTCR(252, 0xe60530fc), /* PORT252CR */
  3822. PORTCR(253, 0xe60530fd), /* PORT253CR */
  3823. PORTCR(254, 0xe60530fe), /* PORT254CR */
  3824. PORTCR(255, 0xe60530ff), /* PORT255CR */
  3825. PORTCR(256, 0xe6053100), /* PORT256CR */
  3826. PORTCR(257, 0xe6053101), /* PORT257CR */
  3827. PORTCR(258, 0xe6053102), /* PORT258CR */
  3828. PORTCR(259, 0xe6053103), /* PORT259CR */
  3829. PORTCR(260, 0xe6053104), /* PORT260CR */
  3830. PORTCR(261, 0xe6053105), /* PORT261CR */
  3831. PORTCR(262, 0xe6053106), /* PORT262CR */
  3832. PORTCR(263, 0xe6053107), /* PORT263CR */
  3833. PORTCR(264, 0xe6053108), /* PORT264CR */
  3834. PORTCR(265, 0xe6053109), /* PORT265CR */
  3835. PORTCR(266, 0xe605310a), /* PORT266CR */
  3836. PORTCR(267, 0xe605310b), /* PORT267CR */
  3837. PORTCR(268, 0xe605310c), /* PORT268CR */
  3838. PORTCR(269, 0xe605310d), /* PORT269CR */
  3839. PORTCR(270, 0xe605310e), /* PORT270CR */
  3840. PORTCR(271, 0xe605310f), /* PORT271CR */
  3841. PORTCR(272, 0xe6053110), /* PORT272CR */
  3842. PORTCR(273, 0xe6053111), /* PORT273CR */
  3843. PORTCR(274, 0xe6053112), /* PORT274CR */
  3844. PORTCR(275, 0xe6053113), /* PORT275CR */
  3845. PORTCR(276, 0xe6053114), /* PORT276CR */
  3846. PORTCR(277, 0xe6053115), /* PORT277CR */
  3847. PORTCR(278, 0xe6053116), /* PORT278CR */
  3848. PORTCR(279, 0xe6053117), /* PORT279CR */
  3849. PORTCR(280, 0xe6053118), /* PORT280CR */
  3850. PORTCR(281, 0xe6053119), /* PORT281CR */
  3851. PORTCR(282, 0xe605311a), /* PORT282CR */
  3852. PORTCR(288, 0xe6052120), /* PORT288CR */
  3853. PORTCR(289, 0xe6052121), /* PORT289CR */
  3854. PORTCR(290, 0xe6052122), /* PORT290CR */
  3855. PORTCR(291, 0xe6052123), /* PORT291CR */
  3856. PORTCR(292, 0xe6052124), /* PORT292CR */
  3857. PORTCR(293, 0xe6052125), /* PORT293CR */
  3858. PORTCR(294, 0xe6052126), /* PORT294CR */
  3859. PORTCR(295, 0xe6052127), /* PORT295CR */
  3860. PORTCR(296, 0xe6052128), /* PORT296CR */
  3861. PORTCR(297, 0xe6052129), /* PORT297CR */
  3862. PORTCR(298, 0xe605212a), /* PORT298CR */
  3863. PORTCR(299, 0xe605212b), /* PORT299CR */
  3864. PORTCR(300, 0xe605212c), /* PORT300CR */
  3865. PORTCR(301, 0xe605212d), /* PORT301CR */
  3866. PORTCR(302, 0xe605212e), /* PORT302CR */
  3867. PORTCR(303, 0xe605212f), /* PORT303CR */
  3868. PORTCR(304, 0xe6052130), /* PORT304CR */
  3869. PORTCR(305, 0xe6052131), /* PORT305CR */
  3870. PORTCR(306, 0xe6052132), /* PORT306CR */
  3871. PORTCR(307, 0xe6052133), /* PORT307CR */
  3872. PORTCR(308, 0xe6052134), /* PORT308CR */
  3873. PORTCR(309, 0xe6052135), /* PORT309CR */
  3874. { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
  3875. 0, 0,
  3876. 0, 0,
  3877. 0, 0,
  3878. 0, 0,
  3879. 0, 0,
  3880. 0, 0,
  3881. 0, 0,
  3882. 0, 0,
  3883. 0, 0,
  3884. 0, 0,
  3885. 0, 0,
  3886. 0, 0,
  3887. MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
  3888. MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
  3889. MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
  3890. MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
  3891. 0, 0,
  3892. MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
  3893. MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
  3894. MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
  3895. MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
  3896. MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
  3897. MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
  3898. MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
  3899. MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
  3900. MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
  3901. MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
  3902. MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
  3903. MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
  3904. MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
  3905. MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
  3906. MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
  3907. ))
  3908. },
  3909. { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
  3910. 0, 0,
  3911. 0, 0,
  3912. 0, 0,
  3913. MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
  3914. 0, 0,
  3915. 0, 0,
  3916. 0, 0,
  3917. 0, 0,
  3918. 0, 0,
  3919. 0, 0,
  3920. 0, 0,
  3921. 0, 0,
  3922. 0, 0,
  3923. 0, 0,
  3924. 0, 0,
  3925. 0, 0,
  3926. MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
  3927. 0, 0,
  3928. 0, 0,
  3929. 0, 0,
  3930. MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
  3931. 0, 0,
  3932. MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
  3933. 0, 0,
  3934. 0, 0,
  3935. MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
  3936. 0, 0,
  3937. 0, 0,
  3938. 0, 0,
  3939. MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
  3940. 0, 0,
  3941. 0, 0,
  3942. ))
  3943. },
  3944. { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
  3945. 0, 0,
  3946. 0, 0,
  3947. MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
  3948. 0, 0,
  3949. MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
  3950. MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
  3951. 0, 0,
  3952. 0, 0,
  3953. 0, 0,
  3954. MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
  3955. MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
  3956. MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
  3957. MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
  3958. 0, 0,
  3959. 0, 0,
  3960. 0, 0,
  3961. MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
  3962. 0, 0,
  3963. MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
  3964. MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
  3965. MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
  3966. MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
  3967. MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
  3968. MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
  3969. MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
  3970. 0, 0,
  3971. 0, 0,
  3972. MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
  3973. 0, 0,
  3974. 0, 0,
  3975. MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
  3976. 0, 0,
  3977. ))
  3978. },
  3979. { },
  3980. };
  3981. static const struct pinmux_data_reg pinmux_data_regs[] = {
  3982. { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
  3983. PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
  3984. PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
  3985. PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
  3986. PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
  3987. PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
  3988. PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
  3989. PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
  3990. PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
  3991. },
  3992. { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
  3993. PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
  3994. PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
  3995. PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
  3996. PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
  3997. PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
  3998. PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
  3999. PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
  4000. PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
  4001. },
  4002. { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
  4003. PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
  4004. PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
  4005. PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
  4006. PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
  4007. PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
  4008. PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
  4009. PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
  4010. PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
  4011. },
  4012. { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
  4013. 0, 0, 0, 0,
  4014. 0, 0, 0, 0,
  4015. 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
  4016. PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
  4017. PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
  4018. PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
  4019. PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
  4020. PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
  4021. },
  4022. { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
  4023. PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
  4024. PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
  4025. PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
  4026. PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
  4027. PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
  4028. PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
  4029. PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
  4030. PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
  4031. },
  4032. { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
  4033. 0, 0, 0, 0,
  4034. 0, 0, 0, 0,
  4035. 0, 0, 0, 0,
  4036. 0, 0, 0, 0,
  4037. 0, 0, 0, 0,
  4038. 0, 0, 0, 0,
  4039. 0, 0, 0, PORT164_DATA,
  4040. PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
  4041. },
  4042. { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
  4043. PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
  4044. PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
  4045. PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
  4046. PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
  4047. PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
  4048. PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
  4049. PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
  4050. PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
  4051. },
  4052. { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
  4053. PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
  4054. PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
  4055. PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
  4056. PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
  4057. PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
  4058. PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
  4059. PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
  4060. PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
  4061. },
  4062. { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
  4063. 0, 0, 0, 0,
  4064. 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
  4065. PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
  4066. PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
  4067. PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
  4068. PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
  4069. PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
  4070. PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
  4071. },
  4072. { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
  4073. 0, 0, 0, 0,
  4074. 0, 0, 0, 0,
  4075. 0, 0, PORT309_DATA, PORT308_DATA,
  4076. PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
  4077. PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
  4078. PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
  4079. PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
  4080. PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
  4081. },
  4082. { },
  4083. };
  4084. static const struct pinmux_irq pinmux_irqs[] = {
  4085. PINMUX_IRQ(11), /* IRQ0 */
  4086. PINMUX_IRQ(10), /* IRQ1 */
  4087. PINMUX_IRQ(149), /* IRQ2 */
  4088. PINMUX_IRQ(224), /* IRQ3 */
  4089. PINMUX_IRQ(159), /* IRQ4 */
  4090. PINMUX_IRQ(227), /* IRQ5 */
  4091. PINMUX_IRQ(147), /* IRQ6 */
  4092. PINMUX_IRQ(150), /* IRQ7 */
  4093. PINMUX_IRQ(223), /* IRQ8 */
  4094. PINMUX_IRQ(56, 308), /* IRQ9 */
  4095. PINMUX_IRQ(54), /* IRQ10 */
  4096. PINMUX_IRQ(238), /* IRQ11 */
  4097. PINMUX_IRQ(156), /* IRQ12 */
  4098. PINMUX_IRQ(239), /* IRQ13 */
  4099. PINMUX_IRQ(251), /* IRQ14 */
  4100. PINMUX_IRQ(0), /* IRQ15 */
  4101. PINMUX_IRQ(249), /* IRQ16 */
  4102. PINMUX_IRQ(234), /* IRQ17 */
  4103. PINMUX_IRQ(13), /* IRQ18 */
  4104. PINMUX_IRQ(9), /* IRQ19 */
  4105. PINMUX_IRQ(14), /* IRQ20 */
  4106. PINMUX_IRQ(15), /* IRQ21 */
  4107. PINMUX_IRQ(40), /* IRQ22 */
  4108. PINMUX_IRQ(53), /* IRQ23 */
  4109. PINMUX_IRQ(118), /* IRQ24 */
  4110. PINMUX_IRQ(164), /* IRQ25 */
  4111. PINMUX_IRQ(115), /* IRQ26 */
  4112. PINMUX_IRQ(116), /* IRQ27 */
  4113. PINMUX_IRQ(117), /* IRQ28 */
  4114. PINMUX_IRQ(28), /* IRQ29 */
  4115. PINMUX_IRQ(27), /* IRQ30 */
  4116. PINMUX_IRQ(26), /* IRQ31 */
  4117. };
  4118. /* -----------------------------------------------------------------------------
  4119. * VCCQ MC0 regulator
  4120. */
  4121. static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
  4122. {
  4123. struct sh_pfc *pfc = reg->reg_data;
  4124. void __iomem *addr = pfc->windows[1].virt + 4;
  4125. unsigned long flags;
  4126. u32 value;
  4127. spin_lock_irqsave(&pfc->lock, flags);
  4128. value = ioread32(addr);
  4129. if (enable)
  4130. value |= BIT(28);
  4131. else
  4132. value &= ~BIT(28);
  4133. iowrite32(value, addr);
  4134. spin_unlock_irqrestore(&pfc->lock, flags);
  4135. }
  4136. static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
  4137. {
  4138. sh73a0_vccq_mc0_endisable(reg, true);
  4139. return 0;
  4140. }
  4141. static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
  4142. {
  4143. sh73a0_vccq_mc0_endisable(reg, false);
  4144. return 0;
  4145. }
  4146. static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
  4147. {
  4148. struct sh_pfc *pfc = reg->reg_data;
  4149. void __iomem *addr = pfc->windows[1].virt + 4;
  4150. unsigned long flags;
  4151. u32 value;
  4152. spin_lock_irqsave(&pfc->lock, flags);
  4153. value = ioread32(addr);
  4154. spin_unlock_irqrestore(&pfc->lock, flags);
  4155. return !!(value & BIT(28));
  4156. }
  4157. static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
  4158. {
  4159. return 3300000;
  4160. }
  4161. static struct regulator_ops sh73a0_vccq_mc0_ops = {
  4162. .enable = sh73a0_vccq_mc0_enable,
  4163. .disable = sh73a0_vccq_mc0_disable,
  4164. .is_enabled = sh73a0_vccq_mc0_is_enabled,
  4165. .get_voltage = sh73a0_vccq_mc0_get_voltage,
  4166. };
  4167. static const struct regulator_desc sh73a0_vccq_mc0_desc = {
  4168. .owner = THIS_MODULE,
  4169. .name = "vccq_mc0",
  4170. .type = REGULATOR_VOLTAGE,
  4171. .ops = &sh73a0_vccq_mc0_ops,
  4172. };
  4173. static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
  4174. REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
  4175. REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
  4176. };
  4177. static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
  4178. .constraints = {
  4179. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  4180. },
  4181. .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
  4182. .consumer_supplies = sh73a0_vccq_mc0_consumers,
  4183. };
  4184. /* -----------------------------------------------------------------------------
  4185. * Pin bias
  4186. */
  4187. #define PORTnCR_PULMD_OFF (0 << 6)
  4188. #define PORTnCR_PULMD_DOWN (2 << 6)
  4189. #define PORTnCR_PULMD_UP (3 << 6)
  4190. #define PORTnCR_PULMD_MASK (3 << 6)
  4191. static const unsigned int sh73a0_portcr_offsets[] = {
  4192. 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
  4193. 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
  4194. };
  4195. static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
  4196. {
  4197. void __iomem *addr = pfc->windows->virt
  4198. + sh73a0_portcr_offsets[pin >> 5] + pin;
  4199. u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
  4200. switch (value) {
  4201. case PORTnCR_PULMD_UP:
  4202. return PIN_CONFIG_BIAS_PULL_UP;
  4203. case PORTnCR_PULMD_DOWN:
  4204. return PIN_CONFIG_BIAS_PULL_DOWN;
  4205. case PORTnCR_PULMD_OFF:
  4206. default:
  4207. return PIN_CONFIG_BIAS_DISABLE;
  4208. }
  4209. }
  4210. static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  4211. unsigned int bias)
  4212. {
  4213. void __iomem *addr = pfc->windows->virt
  4214. + sh73a0_portcr_offsets[pin >> 5] + pin;
  4215. u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
  4216. switch (bias) {
  4217. case PIN_CONFIG_BIAS_PULL_UP:
  4218. value |= PORTnCR_PULMD_UP;
  4219. break;
  4220. case PIN_CONFIG_BIAS_PULL_DOWN:
  4221. value |= PORTnCR_PULMD_DOWN;
  4222. break;
  4223. }
  4224. iowrite8(value, addr);
  4225. }
  4226. /* -----------------------------------------------------------------------------
  4227. * SoC information
  4228. */
  4229. static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
  4230. {
  4231. struct regulator_config cfg = { };
  4232. struct regulator_dev *vccq;
  4233. int ret;
  4234. cfg.dev = pfc->dev;
  4235. cfg.init_data = &sh73a0_vccq_mc0_init_data;
  4236. cfg.driver_data = pfc;
  4237. vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
  4238. if (IS_ERR(vccq)) {
  4239. ret = PTR_ERR(vccq);
  4240. dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
  4241. ret);
  4242. return ret;
  4243. }
  4244. return 0;
  4245. }
  4246. static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
  4247. .init = sh73a0_pinmux_soc_init,
  4248. .get_bias = sh73a0_pinmux_get_bias,
  4249. .set_bias = sh73a0_pinmux_set_bias,
  4250. };
  4251. const struct sh_pfc_soc_info sh73a0_pinmux_info = {
  4252. .name = "sh73a0_pfc",
  4253. .ops = &sh73a0_pfc_ops,
  4254. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  4255. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  4256. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  4257. .pins = pinmux_pins,
  4258. .nr_pins = ARRAY_SIZE(pinmux_pins),
  4259. .groups = pinmux_groups,
  4260. .nr_groups = ARRAY_SIZE(pinmux_groups),
  4261. .functions = pinmux_functions,
  4262. .nr_functions = ARRAY_SIZE(pinmux_functions),
  4263. .cfg_regs = pinmux_config_regs,
  4264. .data_regs = pinmux_data_regs,
  4265. .pinmux_data = pinmux_data,
  4266. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  4267. .gpio_irq = pinmux_irqs,
  4268. .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
  4269. };