pfc-r8a77980.c 89 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A77980 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Corp.
  6. * Copyright (C) 2018 Cogent Embedded, Inc.
  7. *
  8. * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  9. *
  10. * R-Car Gen3 processor support - PFC hardware block.
  11. *
  12. * Copyright (C) 2015 Renesas Electronics Corporation
  13. */
  14. #include <linux/errno.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include "core.h"
  18. #include "sh_pfc.h"
  19. #define CPU_ALL_GP(fn, sfx) \
  20. PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  21. PORT_GP_28(1, fn, sfx), \
  22. PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  23. PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  24. PORT_GP_25(4, fn, sfx), \
  25. PORT_GP_15(5, fn, sfx)
  26. /*
  27. * F_() : just information
  28. * FM() : macro for FN_xxx / xxx_MARK
  29. */
  30. /* GPSR0 */
  31. #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
  32. #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
  33. #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
  34. #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
  35. #define GPSR0_17 F_(DU_DB7, IP2_7_4)
  36. #define GPSR0_16 F_(DU_DB6, IP2_3_0)
  37. #define GPSR0_15 F_(DU_DB5, IP1_31_28)
  38. #define GPSR0_14 F_(DU_DB4, IP1_27_24)
  39. #define GPSR0_13 F_(DU_DB3, IP1_23_20)
  40. #define GPSR0_12 F_(DU_DB2, IP1_19_16)
  41. #define GPSR0_11 F_(DU_DG7, IP1_15_12)
  42. #define GPSR0_10 F_(DU_DG6, IP1_11_8)
  43. #define GPSR0_9 F_(DU_DG5, IP1_7_4)
  44. #define GPSR0_8 F_(DU_DG4, IP1_3_0)
  45. #define GPSR0_7 F_(DU_DG3, IP0_31_28)
  46. #define GPSR0_6 F_(DU_DG2, IP0_27_24)
  47. #define GPSR0_5 F_(DU_DR7, IP0_23_20)
  48. #define GPSR0_4 F_(DU_DR6, IP0_19_16)
  49. #define GPSR0_3 F_(DU_DR5, IP0_15_12)
  50. #define GPSR0_2 F_(DU_DR4, IP0_11_8)
  51. #define GPSR0_1 F_(DU_DR3, IP0_7_4)
  52. #define GPSR0_0 F_(DU_DR2, IP0_3_0)
  53. /* GPSR1 */
  54. #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
  55. #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
  56. #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
  57. #define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
  58. #define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
  59. #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
  60. #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
  61. #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
  62. #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
  63. #define GPSR1_18 FM(AVB_LINK)
  64. #define GPSR1_17 FM(AVB_PHY_INT)
  65. #define GPSR1_16 FM(AVB_MAGIC)
  66. #define GPSR1_15 FM(AVB_MDC)
  67. #define GPSR1_14 FM(AVB_MDIO)
  68. #define GPSR1_13 FM(AVB_TXCREFCLK)
  69. #define GPSR1_12 FM(AVB_TD3)
  70. #define GPSR1_11 FM(AVB_TD2)
  71. #define GPSR1_10 FM(AVB_TD1)
  72. #define GPSR1_9 FM(AVB_TD0)
  73. #define GPSR1_8 FM(AVB_TXC)
  74. #define GPSR1_7 FM(AVB_TX_CTL)
  75. #define GPSR1_6 FM(AVB_RD3)
  76. #define GPSR1_5 FM(AVB_RD2)
  77. #define GPSR1_4 FM(AVB_RD1)
  78. #define GPSR1_3 FM(AVB_RD0)
  79. #define GPSR1_2 FM(AVB_RXC)
  80. #define GPSR1_1 FM(AVB_RX_CTL)
  81. #define GPSR1_0 F_(IRQ0, IP2_27_24)
  82. /* GPSR2 */
  83. #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
  84. #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
  85. #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
  86. #define GPSR2_26 F_(SDA3, IP10_7_4)
  87. #define GPSR2_25 F_(SCL3, IP10_3_0)
  88. #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
  89. #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
  90. #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
  91. #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
  92. #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
  93. #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
  94. #define GPSR2_18 F_(IRQ5, IP9_7_4)
  95. #define GPSR2_17 F_(IRQ4, IP9_3_0)
  96. #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
  97. #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
  98. #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
  99. #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
  100. #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
  101. #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
  102. #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
  103. #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
  104. #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
  105. #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
  106. #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
  107. #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
  108. #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
  109. #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
  110. #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
  111. #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
  112. #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
  113. /* GPSR3 */
  114. #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
  115. #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
  116. #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
  117. #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
  118. #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
  119. #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
  120. #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
  121. #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
  122. #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
  123. #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
  124. #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
  125. #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
  126. #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
  127. #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
  128. #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
  129. #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
  130. #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
  131. /* GPSR4 */
  132. #define GPSR4_24 FM(GETHER_LINK_A)
  133. #define GPSR4_23 FM(GETHER_PHY_INT_A)
  134. #define GPSR4_22 FM(GETHER_MAGIC)
  135. #define GPSR4_21 FM(GETHER_MDC_A)
  136. #define GPSR4_20 FM(GETHER_MDIO_A)
  137. #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
  138. #define GPSR4_18 FM(GETHER_TXCREFCLK)
  139. #define GPSR4_17 FM(GETHER_TD3)
  140. #define GPSR4_16 FM(GETHER_TD2)
  141. #define GPSR4_15 FM(GETHER_TD1)
  142. #define GPSR4_14 FM(GETHER_TD0)
  143. #define GPSR4_13 FM(GETHER_TXC)
  144. #define GPSR4_12 FM(GETHER_TX_CTL)
  145. #define GPSR4_11 FM(GETHER_RD3)
  146. #define GPSR4_10 FM(GETHER_RD2)
  147. #define GPSR4_9 FM(GETHER_RD1)
  148. #define GPSR4_8 FM(GETHER_RD0)
  149. #define GPSR4_7 FM(GETHER_RXC)
  150. #define GPSR4_6 FM(GETHER_RX_CTL)
  151. #define GPSR4_5 F_(SDA2, IP7_27_24)
  152. #define GPSR4_4 F_(SCL2, IP7_23_20)
  153. #define GPSR4_3 F_(SDA1, IP7_19_16)
  154. #define GPSR4_2 F_(SCL1, IP7_15_12)
  155. #define GPSR4_1 F_(SDA0, IP7_11_8)
  156. #define GPSR4_0 F_(SCL0, IP7_7_4)
  157. /* GPSR5 */
  158. #define GPSR5_14 FM(RPC_INT_N)
  159. #define GPSR5_13 FM(RPC_WP_N)
  160. #define GPSR5_12 FM(RPC_RESET_N)
  161. #define GPSR5_11 FM(QSPI1_SSL)
  162. #define GPSR5_10 FM(QSPI1_IO3)
  163. #define GPSR5_9 FM(QSPI1_IO2)
  164. #define GPSR5_8 FM(QSPI1_MISO_IO1)
  165. #define GPSR5_7 FM(QSPI1_MOSI_IO0)
  166. #define GPSR5_6 FM(QSPI1_SPCLK)
  167. #define GPSR5_5 FM(QSPI0_SSL)
  168. #define GPSR5_4 FM(QSPI0_IO3)
  169. #define GPSR5_3 FM(QSPI0_IO2)
  170. #define GPSR5_2 FM(QSPI0_MISO_IO1)
  171. #define GPSR5_1 FM(QSPI0_MOSI_IO0)
  172. #define GPSR5_0 FM(QSPI0_SPCLK)
  173. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
  174. #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  175. #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  176. #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  177. #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  178. #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  179. #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  180. #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  181. #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  182. #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  183. #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  184. #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  185. #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  186. #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  187. #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  188. #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  189. #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  190. #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  191. #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  192. #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  193. #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  194. #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  195. #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  196. #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  197. #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  198. #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  199. #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  200. #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  201. #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  202. #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  203. #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  204. #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  205. #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  206. #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  207. #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  208. #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  209. #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  210. #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  211. #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  212. #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  213. #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  214. #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  215. #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  216. #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  217. #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  218. #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  219. #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  220. #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  221. #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  222. #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  223. #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  224. #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  225. #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  226. #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  227. #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  228. #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  229. #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  230. #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  231. #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  232. #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  233. #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  234. #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  235. #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  236. #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  237. #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  238. #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  239. #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  240. #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  241. #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  242. #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  243. #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  244. #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  245. #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  246. #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  247. #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  248. #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  249. #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  250. #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  251. #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  252. #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  253. #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  254. #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  255. #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  256. #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  257. #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  258. #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  259. #define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  260. #define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  261. #define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  262. #define PINMUX_GPSR \
  263. \
  264. GPSR2_29 \
  265. GPSR2_28 \
  266. GPSR1_27 GPSR2_27 \
  267. GPSR1_26 GPSR2_26 \
  268. GPSR1_25 GPSR2_25 \
  269. GPSR1_24 GPSR2_24 GPSR4_24 \
  270. GPSR1_23 GPSR2_23 GPSR4_23 \
  271. GPSR1_22 GPSR2_22 GPSR4_22 \
  272. GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
  273. GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
  274. GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
  275. GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
  276. GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
  277. GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
  278. GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
  279. GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
  280. GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
  281. GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
  282. GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
  283. GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
  284. GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
  285. GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
  286. GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
  287. GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
  288. GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
  289. GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
  290. GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
  291. GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
  292. GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
  293. GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
  294. #define PINMUX_IPSR \
  295. \
  296. FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
  297. FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
  298. FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
  299. FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
  300. FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
  301. FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
  302. FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
  303. FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
  304. \
  305. FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
  306. FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
  307. FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
  308. FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
  309. FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
  310. FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
  311. FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
  312. FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
  313. \
  314. FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
  315. FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
  316. FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
  317. FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
  318. FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
  319. FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
  320. FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
  321. FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
  322. /* MOD_SEL0 */ /* 0 */ /* 1 */
  323. #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
  324. #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
  325. #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
  326. #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
  327. #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
  328. #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
  329. #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
  330. #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
  331. #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
  332. #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
  333. #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
  334. #define PINMUX_MOD_SELS \
  335. \
  336. MOD_SEL0_11 \
  337. MOD_SEL0_10 \
  338. MOD_SEL0_9 \
  339. MOD_SEL0_8 \
  340. MOD_SEL0_7 \
  341. MOD_SEL0_6 \
  342. MOD_SEL0_5 \
  343. MOD_SEL0_4 \
  344. MOD_SEL0_2 \
  345. MOD_SEL0_1 \
  346. MOD_SEL0_0
  347. enum {
  348. PINMUX_RESERVED = 0,
  349. PINMUX_DATA_BEGIN,
  350. GP_ALL(DATA),
  351. PINMUX_DATA_END,
  352. #define F_(x, y)
  353. #define FM(x) FN_##x,
  354. PINMUX_FUNCTION_BEGIN,
  355. GP_ALL(FN),
  356. PINMUX_GPSR
  357. PINMUX_IPSR
  358. PINMUX_MOD_SELS
  359. PINMUX_FUNCTION_END,
  360. #undef F_
  361. #undef FM
  362. #define F_(x, y)
  363. #define FM(x) x##_MARK,
  364. PINMUX_MARK_BEGIN,
  365. PINMUX_GPSR
  366. PINMUX_IPSR
  367. PINMUX_MOD_SELS
  368. PINMUX_MARK_END,
  369. #undef F_
  370. #undef FM
  371. };
  372. static const u16 pinmux_data[] = {
  373. PINMUX_DATA_GP_ALL(),
  374. PINMUX_SINGLE(AVB_RX_CTL),
  375. PINMUX_SINGLE(AVB_RXC),
  376. PINMUX_SINGLE(AVB_RD0),
  377. PINMUX_SINGLE(AVB_RD1),
  378. PINMUX_SINGLE(AVB_RD2),
  379. PINMUX_SINGLE(AVB_RD3),
  380. PINMUX_SINGLE(AVB_TX_CTL),
  381. PINMUX_SINGLE(AVB_TXC),
  382. PINMUX_SINGLE(AVB_TD0),
  383. PINMUX_SINGLE(AVB_TD1),
  384. PINMUX_SINGLE(AVB_TD2),
  385. PINMUX_SINGLE(AVB_TD3),
  386. PINMUX_SINGLE(AVB_TXCREFCLK),
  387. PINMUX_SINGLE(AVB_MDIO),
  388. PINMUX_SINGLE(AVB_MDC),
  389. PINMUX_SINGLE(AVB_MAGIC),
  390. PINMUX_SINGLE(AVB_PHY_INT),
  391. PINMUX_SINGLE(AVB_LINK),
  392. PINMUX_SINGLE(GETHER_RX_CTL),
  393. PINMUX_SINGLE(GETHER_RXC),
  394. PINMUX_SINGLE(GETHER_RD0),
  395. PINMUX_SINGLE(GETHER_RD1),
  396. PINMUX_SINGLE(GETHER_RD2),
  397. PINMUX_SINGLE(GETHER_RD3),
  398. PINMUX_SINGLE(GETHER_TX_CTL),
  399. PINMUX_SINGLE(GETHER_TXC),
  400. PINMUX_SINGLE(GETHER_TD0),
  401. PINMUX_SINGLE(GETHER_TD1),
  402. PINMUX_SINGLE(GETHER_TD2),
  403. PINMUX_SINGLE(GETHER_TD3),
  404. PINMUX_SINGLE(GETHER_TXCREFCLK),
  405. PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
  406. PINMUX_SINGLE(GETHER_MDIO_A),
  407. PINMUX_SINGLE(GETHER_MDC_A),
  408. PINMUX_SINGLE(GETHER_MAGIC),
  409. PINMUX_SINGLE(GETHER_PHY_INT_A),
  410. PINMUX_SINGLE(GETHER_LINK_A),
  411. PINMUX_SINGLE(QSPI0_SPCLK),
  412. PINMUX_SINGLE(QSPI0_MOSI_IO0),
  413. PINMUX_SINGLE(QSPI0_MISO_IO1),
  414. PINMUX_SINGLE(QSPI0_IO2),
  415. PINMUX_SINGLE(QSPI0_IO3),
  416. PINMUX_SINGLE(QSPI0_SSL),
  417. PINMUX_SINGLE(QSPI1_SPCLK),
  418. PINMUX_SINGLE(QSPI1_MOSI_IO0),
  419. PINMUX_SINGLE(QSPI1_MISO_IO1),
  420. PINMUX_SINGLE(QSPI1_IO2),
  421. PINMUX_SINGLE(QSPI1_IO3),
  422. PINMUX_SINGLE(QSPI1_SSL),
  423. PINMUX_SINGLE(RPC_RESET_N),
  424. PINMUX_SINGLE(RPC_WP_N),
  425. PINMUX_SINGLE(RPC_INT_N),
  426. /* IPSR0 */
  427. PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
  428. PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
  429. PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
  430. PINMUX_IPSR_GPSR(IP0_3_0, A0),
  431. PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
  432. PINMUX_IPSR_GPSR(IP0_7_4, RX4),
  433. PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
  434. PINMUX_IPSR_GPSR(IP0_7_4, A1),
  435. PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
  436. PINMUX_IPSR_GPSR(IP0_11_8, TX4),
  437. PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
  438. PINMUX_IPSR_GPSR(IP0_11_8, A2),
  439. PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
  440. PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
  441. PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
  442. PINMUX_IPSR_GPSR(IP0_15_12, A3),
  443. PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
  444. PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
  445. PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
  446. PINMUX_IPSR_GPSR(IP0_19_16, A4),
  447. PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
  448. PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
  449. PINMUX_IPSR_GPSR(IP0_23_20, A5),
  450. PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
  451. PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
  452. PINMUX_IPSR_GPSR(IP0_27_24, A6),
  453. PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
  454. PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
  455. PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
  456. PINMUX_IPSR_GPSR(IP0_31_28, A7),
  457. PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
  458. /* IPSR1 */
  459. PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
  460. PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
  461. PINMUX_IPSR_GPSR(IP1_3_0, A8),
  462. PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
  463. PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
  464. PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
  465. PINMUX_IPSR_GPSR(IP1_7_4, A9),
  466. PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
  467. PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
  468. PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
  469. PINMUX_IPSR_GPSR(IP1_11_8, A10),
  470. PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
  471. PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
  472. PINMUX_IPSR_GPSR(IP1_15_12, A11),
  473. PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
  474. PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
  475. PINMUX_IPSR_GPSR(IP1_19_16, A12),
  476. PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
  477. PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
  478. PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
  479. PINMUX_IPSR_GPSR(IP1_23_20, A13),
  480. PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
  481. PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
  482. PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
  483. PINMUX_IPSR_GPSR(IP1_27_24, A14),
  484. PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
  485. PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
  486. PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
  487. PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
  488. PINMUX_IPSR_GPSR(IP1_31_28, A15),
  489. /* IPSR2 */
  490. PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
  491. PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
  492. PINMUX_IPSR_GPSR(IP2_3_0, A16),
  493. PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
  494. PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
  495. PINMUX_IPSR_GPSR(IP2_7_4, A17),
  496. PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
  497. PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
  498. PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
  499. PINMUX_IPSR_GPSR(IP2_11_8, A18),
  500. PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
  501. PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
  502. PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
  503. PINMUX_IPSR_GPSR(IP2_15_12, A19),
  504. PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
  505. PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
  506. PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
  507. PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
  508. PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
  509. PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
  510. PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
  511. PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
  512. PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
  513. PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
  514. PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
  515. /* IPSR3 */
  516. PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
  517. PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
  518. PINMUX_IPSR_GPSR(IP3_3_0, RX3),
  519. PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
  520. PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
  521. PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
  522. PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
  523. PINMUX_IPSR_GPSR(IP3_7_4, TX3),
  524. PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
  525. PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
  526. PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
  527. PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
  528. PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
  529. PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
  530. PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
  531. PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
  532. PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
  533. PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
  534. PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
  535. PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
  536. PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
  537. PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
  538. PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
  539. PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
  540. PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
  541. PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
  542. PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
  543. PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
  544. /* IPSR4 */
  545. PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
  546. PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
  547. PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
  548. PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
  549. PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
  550. PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
  551. PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
  552. PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
  553. PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
  554. PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
  555. PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
  556. PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
  557. PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
  558. PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
  559. PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
  560. PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
  561. PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
  562. PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
  563. PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
  564. PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
  565. PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
  566. PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
  567. PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
  568. PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
  569. /* IPSR5 */
  570. PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
  571. PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
  572. PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
  573. PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
  574. PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
  575. PINMUX_IPSR_GPSR(IP5_7_4, D0),
  576. PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
  577. PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
  578. PINMUX_IPSR_GPSR(IP5_11_8, D1),
  579. PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
  580. PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
  581. PINMUX_IPSR_GPSR(IP5_15_12, D2),
  582. PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
  583. PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
  584. PINMUX_IPSR_GPSR(IP5_19_16, D3),
  585. PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
  586. PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
  587. PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
  588. PINMUX_IPSR_GPSR(IP5_23_20, D4),
  589. PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
  590. PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
  591. PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
  592. PINMUX_IPSR_GPSR(IP5_27_24, D5),
  593. PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
  594. PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
  595. PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
  596. PINMUX_IPSR_GPSR(IP5_31_28, D6),
  597. PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
  598. /* IPSR6 */
  599. PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
  600. PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
  601. PINMUX_IPSR_GPSR(IP6_3_0, D7),
  602. PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
  603. PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
  604. PINMUX_IPSR_GPSR(IP6_7_4, D8),
  605. PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
  606. PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
  607. PINMUX_IPSR_GPSR(IP6_11_8, D9),
  608. PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
  609. PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
  610. PINMUX_IPSR_GPSR(IP6_15_12, D10),
  611. PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
  612. PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
  613. PINMUX_IPSR_GPSR(IP6_19_16, D11),
  614. PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
  615. PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
  616. PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
  617. PINMUX_IPSR_GPSR(IP6_23_20, D12),
  618. PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
  619. PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
  620. PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
  621. PINMUX_IPSR_GPSR(IP6_27_24, D13),
  622. PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
  623. PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
  624. PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
  625. PINMUX_IPSR_GPSR(IP6_31_28, D14),
  626. PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
  627. /* IPSR7 */
  628. PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
  629. PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
  630. PINMUX_IPSR_GPSR(IP7_3_0, D15),
  631. PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
  632. PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
  633. PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
  634. PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
  635. PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
  636. PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
  637. PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
  638. PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
  639. PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
  640. PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
  641. PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
  642. PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
  643. PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
  644. PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
  645. PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
  646. PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
  647. PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
  648. PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
  649. PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
  650. PINMUX_IPSR_GPSR(IP7_23_20, RX0),
  651. PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
  652. PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
  653. PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
  654. PINMUX_IPSR_GPSR(IP7_27_24, TX0),
  655. PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
  656. PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
  657. PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
  658. /* IPSR8 */
  659. PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
  660. PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
  661. PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
  662. PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
  663. PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
  664. PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
  665. PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
  666. PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
  667. PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
  668. PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
  669. PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
  670. PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
  671. PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
  672. PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
  673. PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
  674. PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
  675. PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
  676. PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
  677. PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
  678. PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
  679. PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
  680. PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
  681. PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
  682. PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
  683. PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
  684. PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
  685. PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
  686. PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
  687. PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
  688. /* IPSR9 */
  689. PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
  690. PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
  691. PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
  692. PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
  693. PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
  694. PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
  695. PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
  696. PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
  697. PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
  698. PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
  699. PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
  700. PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
  701. PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
  702. PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
  703. PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
  704. PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
  705. PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
  706. PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
  707. PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
  708. PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
  709. PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
  710. PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
  711. PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
  712. PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
  713. /* IPSR10 */
  714. PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
  715. PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
  716. PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
  717. PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
  718. PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
  719. PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
  720. PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
  721. PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
  722. PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
  723. };
  724. static const struct sh_pfc_pin pinmux_pins[] = {
  725. PINMUX_GPIO_GP_ALL(),
  726. };
  727. /* - AVB -------------------------------------------------------------------- */
  728. static const unsigned int avb_link_pins[] = {
  729. /* AVB_LINK */
  730. RCAR_GP_PIN(1, 18),
  731. };
  732. static const unsigned int avb_link_mux[] = {
  733. AVB_LINK_MARK,
  734. };
  735. static const unsigned int avb_magic_pins[] = {
  736. /* AVB_MAGIC */
  737. RCAR_GP_PIN(1, 16),
  738. };
  739. static const unsigned int avb_magic_mux[] = {
  740. AVB_MAGIC_MARK,
  741. };
  742. static const unsigned int avb_phy_int_pins[] = {
  743. /* AVB_PHY_INT */
  744. RCAR_GP_PIN(1, 17),
  745. };
  746. static const unsigned int avb_phy_int_mux[] = {
  747. AVB_PHY_INT_MARK,
  748. };
  749. static const unsigned int avb_mdio_pins[] = {
  750. /* AVB_MDC, AVB_MDIO */
  751. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
  752. };
  753. static const unsigned int avb_mdio_mux[] = {
  754. AVB_MDC_MARK, AVB_MDIO_MARK,
  755. };
  756. static const unsigned int avb_rgmii_pins[] = {
  757. /*
  758. * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
  759. * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
  760. */
  761. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
  762. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
  763. RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
  764. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
  765. RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
  766. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  767. };
  768. static const unsigned int avb_rgmii_mux[] = {
  769. AVB_TX_CTL_MARK, AVB_TXC_MARK,
  770. AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
  771. AVB_RX_CTL_MARK, AVB_RXC_MARK,
  772. AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
  773. };
  774. static const unsigned int avb_txcrefclk_pins[] = {
  775. /* AVB_TXCREFCLK */
  776. RCAR_GP_PIN(1, 13),
  777. };
  778. static const unsigned int avb_txcrefclk_mux[] = {
  779. AVB_TXCREFCLK_MARK,
  780. };
  781. static const unsigned int avb_avtp_pps_pins[] = {
  782. /* AVB_AVTP_PPS */
  783. RCAR_GP_PIN(2, 6),
  784. };
  785. static const unsigned int avb_avtp_pps_mux[] = {
  786. AVB_AVTP_PPS_MARK,
  787. };
  788. static const unsigned int avb_avtp_capture_pins[] = {
  789. /* AVB_AVTP_CAPTURE */
  790. RCAR_GP_PIN(1, 20),
  791. };
  792. static const unsigned int avb_avtp_capture_mux[] = {
  793. AVB_AVTP_CAPTURE_MARK,
  794. };
  795. static const unsigned int avb_avtp_match_pins[] = {
  796. /* AVB_AVTP_MATCH */
  797. RCAR_GP_PIN(1, 19),
  798. };
  799. static const unsigned int avb_avtp_match_mux[] = {
  800. AVB_AVTP_MATCH_MARK,
  801. };
  802. /* - CANFD0 ----------------------------------------------------------------- */
  803. static const unsigned int canfd0_data_a_pins[] = {
  804. /* CANFD0_TX, CANFD0_RX */
  805. RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
  806. };
  807. static const unsigned int canfd0_data_a_mux[] = {
  808. CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
  809. };
  810. static const unsigned int canfd0_data_b_pins[] = {
  811. /* CANFD0_TX, CANFD0_RX */
  812. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  813. };
  814. static const unsigned int canfd0_data_b_mux[] = {
  815. CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
  816. };
  817. /* - CANFD1 ----------------------------------------------------------------- */
  818. static const unsigned int canfd1_data_pins[] = {
  819. /* CANFD1_TX, CANFD1_RX */
  820. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  821. };
  822. static const unsigned int canfd1_data_mux[] = {
  823. CANFD1_TX_MARK, CANFD1_RX_MARK,
  824. };
  825. /* - CANFD Clock ------------------------------------------------------------ */
  826. static const unsigned int canfd_clk_a_pins[] = {
  827. /* CANFD_CLK */
  828. RCAR_GP_PIN(1, 25),
  829. };
  830. static const unsigned int canfd_clk_a_mux[] = {
  831. CANFD_CLK_A_MARK,
  832. };
  833. static const unsigned int canfd_clk_b_pins[] = {
  834. /* CANFD_CLK */
  835. RCAR_GP_PIN(3, 8),
  836. };
  837. static const unsigned int canfd_clk_b_mux[] = {
  838. CANFD_CLK_B_MARK,
  839. };
  840. /* - DU --------------------------------------------------------------------- */
  841. static const unsigned int du_rgb666_pins[] = {
  842. /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
  843. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
  844. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
  845. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
  846. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
  847. RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
  848. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
  849. };
  850. static const unsigned int du_rgb666_mux[] = {
  851. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
  852. DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
  853. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
  854. DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
  855. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
  856. DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
  857. };
  858. static const unsigned int du_rgb888_pins[] = {
  859. /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
  860. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
  861. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
  862. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
  863. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
  864. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
  865. RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
  866. RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
  867. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
  868. RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
  869. };
  870. static const unsigned int du_rgb888_mux[] = {
  871. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
  872. DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
  873. DU_DR1_MARK, DU_DR0_MARK,
  874. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
  875. DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
  876. DU_DG1_MARK, DU_DG0_MARK,
  877. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
  878. DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
  879. DU_DB1_MARK, DU_DB0_MARK,
  880. };
  881. static const unsigned int du_clk_out_pins[] = {
  882. /* DU_DOTCLKOUT */
  883. RCAR_GP_PIN(0, 18),
  884. };
  885. static const unsigned int du_clk_out_mux[] = {
  886. DU_DOTCLKOUT_MARK,
  887. };
  888. static const unsigned int du_sync_pins[] = {
  889. /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
  890. RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
  891. };
  892. static const unsigned int du_sync_mux[] = {
  893. DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
  894. };
  895. static const unsigned int du_oddf_pins[] = {
  896. /* DU_EXODDF/DU_ODDF/DISP/CDE */
  897. RCAR_GP_PIN(0, 21),
  898. };
  899. static const unsigned int du_oddf_mux[] = {
  900. DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
  901. };
  902. static const unsigned int du_cde_pins[] = {
  903. /* DU_CDE */
  904. RCAR_GP_PIN(1, 22),
  905. };
  906. static const unsigned int du_cde_mux[] = {
  907. DU_CDE_MARK,
  908. };
  909. static const unsigned int du_disp_pins[] = {
  910. /* DU_DISP */
  911. RCAR_GP_PIN(1, 21),
  912. };
  913. static const unsigned int du_disp_mux[] = {
  914. DU_DISP_MARK,
  915. };
  916. /* - GETHER ----------------------------------------------------------------- */
  917. static const unsigned int gether_link_a_pins[] = {
  918. /* GETHER_LINK */
  919. RCAR_GP_PIN(4, 24),
  920. };
  921. static const unsigned int gether_link_a_mux[] = {
  922. GETHER_LINK_A_MARK,
  923. };
  924. static const unsigned int gether_phy_int_a_pins[] = {
  925. /* GETHER_PHY_INT */
  926. RCAR_GP_PIN(4, 23),
  927. };
  928. static const unsigned int gether_phy_int_a_mux[] = {
  929. GETHER_PHY_INT_A_MARK,
  930. };
  931. static const unsigned int gether_mdio_a_pins[] = {
  932. /* GETHER_MDC, GETHER_MDIO */
  933. RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
  934. };
  935. static const unsigned int gether_mdio_a_mux[] = {
  936. GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
  937. };
  938. static const unsigned int gether_link_b_pins[] = {
  939. /* GETHER_LINK */
  940. RCAR_GP_PIN(0, 18),
  941. };
  942. static const unsigned int gether_link_b_mux[] = {
  943. GETHER_LINK_B_MARK,
  944. };
  945. static const unsigned int gether_phy_int_b_pins[] = {
  946. /* GETHER_PHY_INT */
  947. RCAR_GP_PIN(0, 19),
  948. };
  949. static const unsigned int gether_phy_int_b_mux[] = {
  950. GETHER_PHY_INT_B_MARK,
  951. };
  952. static const unsigned int gether_mdio_b_mux[] = {
  953. GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
  954. };
  955. static const unsigned int gether_mdio_b_pins[] = {
  956. /* GETHER_MDC, GETHER_MDIO */
  957. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
  958. };
  959. static const unsigned int gether_magic_pins[] = {
  960. /* GETHER_MAGIC */
  961. RCAR_GP_PIN(4, 22),
  962. };
  963. static const unsigned int gether_magic_mux[] = {
  964. GETHER_MAGIC_MARK,
  965. };
  966. static const unsigned int gether_rgmii_pins[] = {
  967. /*
  968. * GETHER_TX_CTL, GETHER_TXC,
  969. * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
  970. * GETHER_RX_CTL, GETHER_RXC,
  971. * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
  972. */
  973. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
  974. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  975. RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
  976. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
  977. RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
  978. RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
  979. };
  980. static const unsigned int gether_rgmii_mux[] = {
  981. GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
  982. GETHER_TD0_MARK, GETHER_TD1_MARK,
  983. GETHER_TD2_MARK, GETHER_TD3_MARK,
  984. GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
  985. GETHER_RD0_MARK, AVB_RD1_MARK,
  986. GETHER_RD2_MARK, AVB_RD3_MARK,
  987. };
  988. static const unsigned int gether_txcrefclk_pins[] = {
  989. /* GETHER_TXCREFCLK */
  990. RCAR_GP_PIN(4, 18),
  991. };
  992. static const unsigned int gether_txcrefclk_mux[] = {
  993. GETHER_TXCREFCLK_MARK,
  994. };
  995. static const unsigned int gether_txcrefclk_mega_pins[] = {
  996. /* GETHER_TXCREFCLK_MEGA */
  997. RCAR_GP_PIN(4, 19),
  998. };
  999. static const unsigned int gether_txcrefclk_mega_mux[] = {
  1000. GETHER_TXCREFCLK_MEGA_MARK,
  1001. };
  1002. static const unsigned int gether_rmii_pins[] = {
  1003. /*
  1004. * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
  1005. * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
  1006. * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
  1007. * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
  1008. */
  1009. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  1010. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  1011. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  1012. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  1013. };
  1014. static const unsigned int gether_rmii_mux[] = {
  1015. GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
  1016. GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
  1017. GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
  1018. GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
  1019. };
  1020. /* - HSCIF0 ----------------------------------------------------------------- */
  1021. static const unsigned int hscif0_data_a_pins[] = {
  1022. /* HRX0, HTX0 */
  1023. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
  1024. };
  1025. static const unsigned int hscif0_data_a_mux[] = {
  1026. HRX0_A_MARK, HTX0_A_MARK,
  1027. };
  1028. static const unsigned int hscif0_clk_a_pins[] = {
  1029. /* HSCK0 */
  1030. RCAR_GP_PIN(0, 12),
  1031. };
  1032. static const unsigned int hscif0_clk_a_mux[] = {
  1033. HSCK0_A_MARK,
  1034. };
  1035. static const unsigned int hscif0_ctrl_a_pins[] = {
  1036. /* HRTS0#, HCTS0# */
  1037. RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
  1038. };
  1039. static const unsigned int hscif0_ctrl_a_mux[] = {
  1040. HRTS0_N_A_MARK, HCTS0_N_A_MARK,
  1041. };
  1042. static const unsigned int hscif0_data_b_pins[] = {
  1043. /* HRX0, HTX0 */
  1044. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1045. };
  1046. static const unsigned int hscif0_data_b_mux[] = {
  1047. HRX0_B_MARK, HTX0_B_MARK,
  1048. };
  1049. static const unsigned int hscif0_clk_b_pins[] = {
  1050. /* HSCK0 */
  1051. RCAR_GP_PIN(4, 1),
  1052. };
  1053. static const unsigned int hscif0_clk_b_mux[] = {
  1054. HSCK0_B_MARK,
  1055. };
  1056. static const unsigned int hscif0_ctrl_b_pins[] = {
  1057. /* HRTS0#, HCTS0# */
  1058. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1059. };
  1060. static const unsigned int hscif0_ctrl_b_mux[] = {
  1061. HRTS0_N_B_MARK, HCTS0_N_B_MARK,
  1062. };
  1063. /* - HSCIF1 ----------------------------------------------------------------- */
  1064. static const unsigned int hscif1_data_pins[] = {
  1065. /* HRX1, HTX1 */
  1066. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1067. };
  1068. static const unsigned int hscif1_data_mux[] = {
  1069. HRX1_MARK, HTX1_MARK,
  1070. };
  1071. static const unsigned int hscif1_clk_pins[] = {
  1072. /* HSCK1 */
  1073. RCAR_GP_PIN(2, 7),
  1074. };
  1075. static const unsigned int hscif1_clk_mux[] = {
  1076. HSCK1_MARK,
  1077. };
  1078. static const unsigned int hscif1_ctrl_pins[] = {
  1079. /* HRTS1#, HCTS1# */
  1080. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1081. };
  1082. static const unsigned int hscif1_ctrl_mux[] = {
  1083. HRTS1_N_MARK, HCTS1_N_MARK,
  1084. };
  1085. /* - HSCIF2 ----------------------------------------------------------------- */
  1086. static const unsigned int hscif2_data_pins[] = {
  1087. /* HRX2, HTX2 */
  1088. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
  1089. };
  1090. static const unsigned int hscif2_data_mux[] = {
  1091. HRX2_MARK, HTX2_MARK,
  1092. };
  1093. static const unsigned int hscif2_clk_pins[] = {
  1094. /* HSCK2 */
  1095. RCAR_GP_PIN(2, 12),
  1096. };
  1097. static const unsigned int hscif2_clk_mux[] = {
  1098. HSCK2_MARK,
  1099. };
  1100. static const unsigned int hscif2_ctrl_pins[] = {
  1101. /* HRTS2#, HCTS2# */
  1102. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  1103. };
  1104. static const unsigned int hscif2_ctrl_mux[] = {
  1105. HRTS2_N_MARK, HCTS2_N_MARK,
  1106. };
  1107. /* - HSCIF3 ----------------------------------------------------------------- */
  1108. static const unsigned int hscif3_data_pins[] = {
  1109. /* HRX3, HTX3 */
  1110. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
  1111. };
  1112. static const unsigned int hscif3_data_mux[] = {
  1113. HRX3_MARK, HTX3_MARK,
  1114. };
  1115. static const unsigned int hscif3_clk_pins[] = {
  1116. /* HSCK3 */
  1117. RCAR_GP_PIN(2, 0),
  1118. };
  1119. static const unsigned int hscif3_clk_mux[] = {
  1120. HSCK3_MARK,
  1121. };
  1122. static const unsigned int hscif3_ctrl_pins[] = {
  1123. /* HRTS3#, HCTS3# */
  1124. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
  1125. };
  1126. static const unsigned int hscif3_ctrl_mux[] = {
  1127. HRTS3_N_MARK, HCTS3_N_MARK,
  1128. };
  1129. /* - I2C0 ------------------------------------------------------------------- */
  1130. static const unsigned int i2c0_pins[] = {
  1131. /* SDA0, SCL0 */
  1132. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
  1133. };
  1134. static const unsigned int i2c0_mux[] = {
  1135. SDA0_MARK, SCL0_MARK,
  1136. };
  1137. /* - I2C1 ------------------------------------------------------------------- */
  1138. static const unsigned int i2c1_pins[] = {
  1139. /* SDA1, SCL1 */
  1140. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1141. };
  1142. static const unsigned int i2c1_mux[] = {
  1143. SDA1_MARK, SCL1_MARK,
  1144. };
  1145. /* - I2C2 ------------------------------------------------------------------- */
  1146. static const unsigned int i2c2_pins[] = {
  1147. /* SDA2, SCL2 */
  1148. RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
  1149. };
  1150. static const unsigned int i2c2_mux[] = {
  1151. SDA2_MARK, SCL2_MARK,
  1152. };
  1153. /* - I2C3 ------------------------------------------------------------------- */
  1154. static const unsigned int i2c3_pins[] = {
  1155. /* SDA3, SCL3 */
  1156. RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
  1157. };
  1158. static const unsigned int i2c3_mux[] = {
  1159. SDA3_MARK, SCL3_MARK,
  1160. };
  1161. /* - I2C4 ------------------------------------------------------------------- */
  1162. static const unsigned int i2c4_pins[] = {
  1163. /* SDA4, SCL4 */
  1164. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
  1165. };
  1166. static const unsigned int i2c4_mux[] = {
  1167. SDA4_MARK, SCL4_MARK,
  1168. };
  1169. /* - I2C5 ------------------------------------------------------------------- */
  1170. static const unsigned int i2c5_pins[] = {
  1171. /* SDA5, SCL5 */
  1172. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
  1173. };
  1174. static const unsigned int i2c5_mux[] = {
  1175. SDA5_MARK, SCL5_MARK,
  1176. };
  1177. /* - INTC-EX ---------------------------------------------------------------- */
  1178. static const unsigned int intc_ex_irq0_pins[] = {
  1179. /* IRQ0 */
  1180. RCAR_GP_PIN(1, 0),
  1181. };
  1182. static const unsigned int intc_ex_irq0_mux[] = {
  1183. IRQ0_MARK,
  1184. };
  1185. static const unsigned int intc_ex_irq1_pins[] = {
  1186. /* IRQ1 */
  1187. RCAR_GP_PIN(0, 12),
  1188. };
  1189. static const unsigned int intc_ex_irq1_mux[] = {
  1190. IRQ1_MARK,
  1191. };
  1192. static const unsigned int intc_ex_irq2_pins[] = {
  1193. /* IRQ2 */
  1194. RCAR_GP_PIN(0, 13),
  1195. };
  1196. static const unsigned int intc_ex_irq2_mux[] = {
  1197. IRQ2_MARK,
  1198. };
  1199. static const unsigned int intc_ex_irq3_pins[] = {
  1200. /* IRQ3 */
  1201. RCAR_GP_PIN(0, 14),
  1202. };
  1203. static const unsigned int intc_ex_irq3_mux[] = {
  1204. IRQ3_MARK,
  1205. };
  1206. static const unsigned int intc_ex_irq4_pins[] = {
  1207. /* IRQ4 */
  1208. RCAR_GP_PIN(2, 17),
  1209. };
  1210. static const unsigned int intc_ex_irq4_mux[] = {
  1211. IRQ4_MARK,
  1212. };
  1213. static const unsigned int intc_ex_irq5_pins[] = {
  1214. /* IRQ5 */
  1215. RCAR_GP_PIN(2, 18),
  1216. };
  1217. static const unsigned int intc_ex_irq5_mux[] = {
  1218. IRQ5_MARK,
  1219. };
  1220. /* - MMC -------------------------------------------------------------------- */
  1221. static const unsigned int mmc_data1_pins[] = {
  1222. /* MMC_D0 */
  1223. RCAR_GP_PIN(3, 8),
  1224. };
  1225. static const unsigned int mmc_data1_mux[] = {
  1226. MMC_D0_MARK,
  1227. };
  1228. static const unsigned int mmc_data4_pins[] = {
  1229. /* MMC_D[0:3] */
  1230. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1231. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  1232. };
  1233. static const unsigned int mmc_data4_mux[] = {
  1234. MMC_D0_MARK, MMC_D1_MARK,
  1235. MMC_D2_MARK, MMC_D3_MARK,
  1236. };
  1237. static const unsigned int mmc_data8_pins[] = {
  1238. /* MMC_D[0:7] */
  1239. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1240. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  1241. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  1242. RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  1243. };
  1244. static const unsigned int mmc_data8_mux[] = {
  1245. MMC_D0_MARK, MMC_D1_MARK,
  1246. MMC_D2_MARK, MMC_D3_MARK,
  1247. MMC_D4_MARK, MMC_D5_MARK,
  1248. MMC_D6_MARK, MMC_D7_MARK,
  1249. };
  1250. static const unsigned int mmc_ctrl_pins[] = {
  1251. /* MMC_CLK, MMC_CMD */
  1252. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
  1253. };
  1254. static const unsigned int mmc_ctrl_mux[] = {
  1255. MMC_CLK_MARK, MMC_CMD_MARK,
  1256. };
  1257. static const unsigned int mmc_cd_pins[] = {
  1258. /* MMC_CD */
  1259. RCAR_GP_PIN(3, 5),
  1260. };
  1261. static const unsigned int mmc_cd_mux[] = {
  1262. MMC_CD_MARK,
  1263. };
  1264. static const unsigned int mmc_wp_pins[] = {
  1265. /* MMC_WP */
  1266. RCAR_GP_PIN(3, 4),
  1267. };
  1268. static const unsigned int mmc_wp_mux[] = {
  1269. MMC_WP_MARK,
  1270. };
  1271. static const unsigned int mmc_ds_pins[] = {
  1272. /* MMC_DS */
  1273. RCAR_GP_PIN(3, 6),
  1274. };
  1275. static const unsigned int mmc_ds_mux[] = {
  1276. MMC_DS_MARK,
  1277. };
  1278. /* - MSIOF0 ----------------------------------------------------------------- */
  1279. static const unsigned int msiof0_clk_pins[] = {
  1280. /* MSIOF0_SCK */
  1281. RCAR_GP_PIN(2, 21),
  1282. };
  1283. static const unsigned int msiof0_clk_mux[] = {
  1284. MSIOF0_SCK_MARK,
  1285. };
  1286. static const unsigned int msiof0_sync_pins[] = {
  1287. /* MSIOF0_SYNC */
  1288. RCAR_GP_PIN(2, 22),
  1289. };
  1290. static const unsigned int msiof0_sync_mux[] = {
  1291. MSIOF0_SYNC_MARK,
  1292. };
  1293. static const unsigned int msiof0_ss1_pins[] = {
  1294. /* MSIOF0_SS1 */
  1295. RCAR_GP_PIN(2, 23),
  1296. };
  1297. static const unsigned int msiof0_ss1_mux[] = {
  1298. MSIOF0_SS1_MARK,
  1299. };
  1300. static const unsigned int msiof0_ss2_pins[] = {
  1301. /* MSIOF0_SS2 */
  1302. RCAR_GP_PIN(2, 24),
  1303. };
  1304. static const unsigned int msiof0_ss2_mux[] = {
  1305. MSIOF0_SS2_MARK,
  1306. };
  1307. static const unsigned int msiof0_txd_pins[] = {
  1308. /* MSIOF0_TXD */
  1309. RCAR_GP_PIN(2, 20),
  1310. };
  1311. static const unsigned int msiof0_txd_mux[] = {
  1312. MSIOF0_TXD_MARK,
  1313. };
  1314. static const unsigned int msiof0_rxd_pins[] = {
  1315. /* MSIOF0_RXD */
  1316. RCAR_GP_PIN(2, 19),
  1317. };
  1318. static const unsigned int msiof0_rxd_mux[] = {
  1319. MSIOF0_RXD_MARK,
  1320. };
  1321. /* - MSIOF1 ----------------------------------------------------------------- */
  1322. static const unsigned int msiof1_clk_pins[] = {
  1323. /* MSIOF1_SCK */
  1324. RCAR_GP_PIN(3, 2),
  1325. };
  1326. static const unsigned int msiof1_clk_mux[] = {
  1327. MSIOF1_SCK_MARK,
  1328. };
  1329. static const unsigned int msiof1_sync_pins[] = {
  1330. /* MSIOF1_SYNC */
  1331. RCAR_GP_PIN(3, 3),
  1332. };
  1333. static const unsigned int msiof1_sync_mux[] = {
  1334. MSIOF1_SYNC_MARK,
  1335. };
  1336. static const unsigned int msiof1_ss1_pins[] = {
  1337. /* MSIOF1_SS1 */
  1338. RCAR_GP_PIN(3, 4),
  1339. };
  1340. static const unsigned int msiof1_ss1_mux[] = {
  1341. MSIOF1_SS1_MARK,
  1342. };
  1343. static const unsigned int msiof1_ss2_pins[] = {
  1344. /* MSIOF1_SS2 */
  1345. RCAR_GP_PIN(3, 5),
  1346. };
  1347. static const unsigned int msiof1_ss2_mux[] = {
  1348. MSIOF1_SS2_MARK,
  1349. };
  1350. static const unsigned int msiof1_txd_pins[] = {
  1351. /* MSIOF1_TXD */
  1352. RCAR_GP_PIN(3, 1),
  1353. };
  1354. static const unsigned int msiof1_txd_mux[] = {
  1355. MSIOF1_TXD_MARK,
  1356. };
  1357. static const unsigned int msiof1_rxd_pins[] = {
  1358. /* MSIOF1_RXD */
  1359. RCAR_GP_PIN(3, 0),
  1360. };
  1361. static const unsigned int msiof1_rxd_mux[] = {
  1362. MSIOF1_RXD_MARK,
  1363. };
  1364. /* - MSIOF2 ----------------------------------------------------------------- */
  1365. static const unsigned int msiof2_clk_pins[] = {
  1366. /* MSIOF2_SCK */
  1367. RCAR_GP_PIN(2, 0),
  1368. };
  1369. static const unsigned int msiof2_clk_mux[] = {
  1370. MSIOF2_SCK_MARK,
  1371. };
  1372. static const unsigned int msiof2_sync_pins[] = {
  1373. /* MSIOF2_SYNC */
  1374. RCAR_GP_PIN(2, 3),
  1375. };
  1376. static const unsigned int msiof2_sync_mux[] = {
  1377. MSIOF2_SYNC_MARK,
  1378. };
  1379. static const unsigned int msiof2_ss1_pins[] = {
  1380. /* MSIOF2_SS1 */
  1381. RCAR_GP_PIN(2, 4),
  1382. };
  1383. static const unsigned int msiof2_ss1_mux[] = {
  1384. MSIOF2_SS1_MARK,
  1385. };
  1386. static const unsigned int msiof2_ss2_pins[] = {
  1387. /* MSIOF2_SS2 */
  1388. RCAR_GP_PIN(2, 5),
  1389. };
  1390. static const unsigned int msiof2_ss2_mux[] = {
  1391. MSIOF2_SS2_MARK,
  1392. };
  1393. static const unsigned int msiof2_txd_pins[] = {
  1394. /* MSIOF2_TXD */
  1395. RCAR_GP_PIN(2, 2),
  1396. };
  1397. static const unsigned int msiof2_txd_mux[] = {
  1398. MSIOF2_TXD_MARK,
  1399. };
  1400. static const unsigned int msiof2_rxd_pins[] = {
  1401. /* MSIOF2_RXD */
  1402. RCAR_GP_PIN(2, 1),
  1403. };
  1404. static const unsigned int msiof2_rxd_mux[] = {
  1405. MSIOF2_RXD_MARK,
  1406. };
  1407. /* - MSIOF3 ----------------------------------------------------------------- */
  1408. static const unsigned int msiof3_clk_pins[] = {
  1409. /* MSIOF3_SCK */
  1410. RCAR_GP_PIN(0, 20),
  1411. };
  1412. static const unsigned int msiof3_clk_mux[] = {
  1413. MSIOF3_SCK_MARK,
  1414. };
  1415. static const unsigned int msiof3_sync_pins[] = {
  1416. /* MSIOF3_SYNC */
  1417. RCAR_GP_PIN(0, 21),
  1418. };
  1419. static const unsigned int msiof3_sync_mux[] = {
  1420. MSIOF3_SYNC_MARK,
  1421. };
  1422. static const unsigned int msiof3_ss1_pins[] = {
  1423. /* MSIOF3_SS1 */
  1424. RCAR_GP_PIN(0, 18),
  1425. };
  1426. static const unsigned int msiof3_ss1_mux[] = {
  1427. MSIOF3_SS1_MARK,
  1428. };
  1429. static const unsigned int msiof3_ss2_pins[] = {
  1430. /* MSIOF3_SS2 */
  1431. RCAR_GP_PIN(0, 19),
  1432. };
  1433. static const unsigned int msiof3_ss2_mux[] = {
  1434. MSIOF3_SS2_MARK,
  1435. };
  1436. static const unsigned int msiof3_txd_pins[] = {
  1437. /* MSIOF3_TXD */
  1438. RCAR_GP_PIN(0, 17),
  1439. };
  1440. static const unsigned int msiof3_txd_mux[] = {
  1441. MSIOF3_TXD_MARK,
  1442. };
  1443. static const unsigned int msiof3_rxd_pins[] = {
  1444. /* MSIOF3_RXD */
  1445. RCAR_GP_PIN(0, 16),
  1446. };
  1447. static const unsigned int msiof3_rxd_mux[] = {
  1448. MSIOF3_RXD_MARK,
  1449. };
  1450. /* - PWM0 ------------------------------------------------------------------- */
  1451. static const unsigned int pwm0_a_pins[] = {
  1452. /* PWM0 */
  1453. RCAR_GP_PIN(0, 15),
  1454. };
  1455. static const unsigned int pwm0_a_mux[] = {
  1456. PWM0_A_MARK,
  1457. };
  1458. static const unsigned int pwm0_b_pins[] = {
  1459. /* PWM0 */
  1460. RCAR_GP_PIN(1, 21),
  1461. };
  1462. static const unsigned int pwm0_b_mux[] = {
  1463. PWM0_B_MARK,
  1464. };
  1465. /* - PWM1 ------------------------------------------------------------------- */
  1466. static const unsigned int pwm1_a_pins[] = {
  1467. /* PWM1 */
  1468. RCAR_GP_PIN(2, 13),
  1469. };
  1470. static const unsigned int pwm1_a_mux[] = {
  1471. PWM1_A_MARK,
  1472. };
  1473. static const unsigned int pwm1_b_pins[] = {
  1474. /* PWM1 */
  1475. RCAR_GP_PIN(1, 22),
  1476. };
  1477. static const unsigned int pwm1_b_mux[] = {
  1478. PWM1_B_MARK,
  1479. };
  1480. /* - PWM2 ------------------------------------------------------------------- */
  1481. static const unsigned int pwm2_a_pins[] = {
  1482. /* PWM2 */
  1483. RCAR_GP_PIN(2, 14),
  1484. };
  1485. static const unsigned int pwm2_a_mux[] = {
  1486. PWM2_A_MARK,
  1487. };
  1488. static const unsigned int pwm2_b_pins[] = {
  1489. /* PWM2 */
  1490. RCAR_GP_PIN(1, 23),
  1491. };
  1492. static const unsigned int pwm2_b_mux[] = {
  1493. PWM2_B_MARK,
  1494. };
  1495. /* - PWM3 ------------------------------------------------------------------- */
  1496. static const unsigned int pwm3_a_pins[] = {
  1497. /* PWM3 */
  1498. RCAR_GP_PIN(2, 15),
  1499. };
  1500. static const unsigned int pwm3_a_mux[] = {
  1501. PWM3_A_MARK,
  1502. };
  1503. static const unsigned int pwm3_b_pins[] = {
  1504. /* PWM3 */
  1505. RCAR_GP_PIN(1, 24),
  1506. };
  1507. static const unsigned int pwm3_b_mux[] = {
  1508. PWM3_B_MARK,
  1509. };
  1510. /* - PWM4 ------------------------------------------------------------------- */
  1511. static const unsigned int pwm4_a_pins[] = {
  1512. /* PWM4 */
  1513. RCAR_GP_PIN(2, 16),
  1514. };
  1515. static const unsigned int pwm4_a_mux[] = {
  1516. PWM4_A_MARK,
  1517. };
  1518. static const unsigned int pwm4_b_pins[] = {
  1519. /* PWM4 */
  1520. RCAR_GP_PIN(1, 25),
  1521. };
  1522. static const unsigned int pwm4_b_mux[] = {
  1523. PWM4_B_MARK,
  1524. };
  1525. /* - QSPI0 ------------------------------------------------------------------ */
  1526. static const unsigned int qspi0_ctrl_pins[] = {
  1527. /* SPCLK, SSL */
  1528. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
  1529. };
  1530. static const unsigned int qspi0_ctrl_mux[] = {
  1531. QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
  1532. };
  1533. static const unsigned int qspi0_data2_pins[] = {
  1534. /* MOSI_IO0, MISO_IO1 */
  1535. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1536. };
  1537. static const unsigned int qspi0_data2_mux[] = {
  1538. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  1539. };
  1540. static const unsigned int qspi0_data4_pins[] = {
  1541. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  1542. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1543. RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
  1544. };
  1545. static const unsigned int qspi0_data4_mux[] = {
  1546. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  1547. QSPI0_IO2_MARK, QSPI0_IO3_MARK
  1548. };
  1549. /* - QSPI1 ------------------------------------------------------------------ */
  1550. static const unsigned int qspi1_ctrl_pins[] = {
  1551. /* SPCLK, SSL */
  1552. RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
  1553. };
  1554. static const unsigned int qspi1_ctrl_mux[] = {
  1555. QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
  1556. };
  1557. static const unsigned int qspi1_data2_pins[] = {
  1558. /* MOSI_IO0, MISO_IO1 */
  1559. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  1560. };
  1561. static const unsigned int qspi1_data2_mux[] = {
  1562. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  1563. };
  1564. static const unsigned int qspi1_data4_pins[] = {
  1565. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  1566. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  1567. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
  1568. };
  1569. static const unsigned int qspi1_data4_mux[] = {
  1570. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  1571. QSPI1_IO2_MARK, QSPI1_IO3_MARK
  1572. };
  1573. /* - RPC -------------------------------------------------------------------- */
  1574. static const unsigned int rpc_clk1_pins[] = {
  1575. /* Octal-SPI flash: C/SCLK */
  1576. RCAR_GP_PIN(5, 0),
  1577. };
  1578. static const unsigned int rpc_clk1_mux[] = {
  1579. QSPI0_SPCLK_MARK,
  1580. };
  1581. static const unsigned int rpc_clk2_pins[] = {
  1582. /* HyperFlash: CK, CK# */
  1583. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
  1584. };
  1585. static const unsigned int rpc_clk2_mux[] = {
  1586. QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
  1587. };
  1588. static const unsigned int rpc_ctrl_pins[] = {
  1589. /* Octal-SPI flash: S#/CS, DQS */
  1590. /* HyperFlash: CS#, RDS */
  1591. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
  1592. };
  1593. static const unsigned int rpc_ctrl_mux[] = {
  1594. QSPI0_SSL_MARK, QSPI1_SSL_MARK,
  1595. };
  1596. static const unsigned int rpc_data_pins[] = {
  1597. /* DQ[0:7] */
  1598. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1599. RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
  1600. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  1601. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
  1602. };
  1603. static const unsigned int rpc_data_mux[] = {
  1604. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  1605. QSPI0_IO2_MARK, QSPI0_IO3_MARK,
  1606. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  1607. QSPI1_IO2_MARK, QSPI1_IO3_MARK,
  1608. };
  1609. static const unsigned int rpc_reset_pins[] = {
  1610. /* RPC_RESET# */
  1611. RCAR_GP_PIN(5, 12),
  1612. };
  1613. static const unsigned int rpc_reset_mux[] = {
  1614. RPC_RESET_N_MARK,
  1615. };
  1616. static const unsigned int rpc_int_pins[] = {
  1617. /* RPC_INT# */
  1618. RCAR_GP_PIN(5, 14),
  1619. };
  1620. static const unsigned int rpc_int_mux[] = {
  1621. RPC_INT_N_MARK,
  1622. };
  1623. static const unsigned int rpc_wp_pins[] = {
  1624. /* RPC_WP# */
  1625. RCAR_GP_PIN(5, 13),
  1626. };
  1627. static const unsigned int rpc_wp_mux[] = {
  1628. RPC_WP_N_MARK,
  1629. };
  1630. /* - SCIF0 ------------------------------------------------------------------ */
  1631. static const unsigned int scif0_data_pins[] = {
  1632. /* RX0, TX0 */
  1633. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1634. };
  1635. static const unsigned int scif0_data_mux[] = {
  1636. RX0_MARK, TX0_MARK,
  1637. };
  1638. static const unsigned int scif0_clk_pins[] = {
  1639. /* SCK0 */
  1640. RCAR_GP_PIN(4, 1),
  1641. };
  1642. static const unsigned int scif0_clk_mux[] = {
  1643. SCK0_MARK,
  1644. };
  1645. static const unsigned int scif0_ctrl_pins[] = {
  1646. /* RTS0#, CTS0# */
  1647. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1648. };
  1649. static const unsigned int scif0_ctrl_mux[] = {
  1650. RTS0_N_MARK, CTS0_N_MARK,
  1651. };
  1652. /* - SCIF1 ------------------------------------------------------------------ */
  1653. static const unsigned int scif1_data_a_pins[] = {
  1654. /* RX1, TX1 */
  1655. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1656. };
  1657. static const unsigned int scif1_data_a_mux[] = {
  1658. RX1_A_MARK, TX1_A_MARK,
  1659. };
  1660. static const unsigned int scif1_clk_pins[] = {
  1661. /* SCK1 */
  1662. RCAR_GP_PIN(2, 5),
  1663. };
  1664. static const unsigned int scif1_clk_mux[] = {
  1665. SCK1_MARK,
  1666. };
  1667. static const unsigned int scif1_ctrl_pins[] = {
  1668. /* RTS1#, CTS1# */
  1669. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1670. };
  1671. static const unsigned int scif1_ctrl_mux[] = {
  1672. RTS1_N_MARK, CTS1_N_MARK,
  1673. };
  1674. static const unsigned int scif1_data_b_pins[] = {
  1675. /* RX1, TX1 */
  1676. RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
  1677. };
  1678. static const unsigned int scif1_data_b_mux[] = {
  1679. RX1_B_MARK, TX1_B_MARK,
  1680. };
  1681. /* - SCIF3 ------------------------------------------------------------------ */
  1682. static const unsigned int scif3_data_pins[] = {
  1683. /* RX3, TX3 */
  1684. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
  1685. };
  1686. static const unsigned int scif3_data_mux[] = {
  1687. RX3_MARK, TX3_MARK,
  1688. };
  1689. static const unsigned int scif3_clk_pins[] = {
  1690. /* SCK3 */
  1691. RCAR_GP_PIN(2, 0),
  1692. };
  1693. static const unsigned int scif3_clk_mux[] = {
  1694. SCK3_MARK,
  1695. };
  1696. static const unsigned int scif3_ctrl_pins[] = {
  1697. /* RTS3#, CTS3# */
  1698. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
  1699. };
  1700. static const unsigned int scif3_ctrl_mux[] = {
  1701. RTS3_N_MARK, CTS3_N_MARK,
  1702. };
  1703. /* - SCIF4 ------------------------------------------------------------------ */
  1704. static const unsigned int scif4_data_pins[] = {
  1705. /* RX4, TX4 */
  1706. RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
  1707. };
  1708. static const unsigned int scif4_data_mux[] = {
  1709. RX4_MARK, TX4_MARK,
  1710. };
  1711. static const unsigned int scif4_clk_pins[] = {
  1712. /* SCK4 */
  1713. RCAR_GP_PIN(0, 0),
  1714. };
  1715. static const unsigned int scif4_clk_mux[] = {
  1716. SCK4_MARK,
  1717. };
  1718. static const unsigned int scif4_ctrl_pins[] = {
  1719. /* RTS4#, CTS4# */
  1720. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
  1721. };
  1722. static const unsigned int scif4_ctrl_mux[] = {
  1723. RTS4_N_MARK, CTS4_N_MARK,
  1724. };
  1725. /* - SCIF Clock ------------------------------------------------------------- */
  1726. static const unsigned int scif_clk_a_pins[] = {
  1727. /* SCIF_CLK */
  1728. RCAR_GP_PIN(0, 10),
  1729. };
  1730. static const unsigned int scif_clk_a_mux[] = {
  1731. SCIF_CLK_A_MARK,
  1732. };
  1733. static const unsigned int scif_clk_b_pins[] = {
  1734. /* SCIF_CLK */
  1735. RCAR_GP_PIN(1, 25),
  1736. };
  1737. static const unsigned int scif_clk_b_mux[] = {
  1738. SCIF_CLK_B_MARK,
  1739. };
  1740. /* - TMU -------------------------------------------------------------------- */
  1741. static const unsigned int tmu_tclk1_a_pins[] = {
  1742. /* TCLK1 */
  1743. RCAR_GP_PIN(3, 13),
  1744. };
  1745. static const unsigned int tmu_tclk1_a_mux[] = {
  1746. TCLK1_A_MARK,
  1747. };
  1748. static const unsigned int tmu_tclk1_b_pins[] = {
  1749. /* TCLK1 */
  1750. RCAR_GP_PIN(1, 23),
  1751. };
  1752. static const unsigned int tmu_tclk1_b_mux[] = {
  1753. TCLK1_B_MARK,
  1754. };
  1755. static const unsigned int tmu_tclk2_a_pins[] = {
  1756. /* TCLK2 */
  1757. RCAR_GP_PIN(3, 14),
  1758. };
  1759. static const unsigned int tmu_tclk2_a_mux[] = {
  1760. TCLK2_A_MARK,
  1761. };
  1762. static const unsigned int tmu_tclk2_b_pins[] = {
  1763. /* TCLK2 */
  1764. RCAR_GP_PIN(1, 24),
  1765. };
  1766. static const unsigned int tmu_tclk2_b_mux[] = {
  1767. TCLK2_B_MARK,
  1768. };
  1769. /* - TPU ------------------------------------------------------------------- */
  1770. static const unsigned int tpu_to0_pins[] = {
  1771. /* TPU0TO0 */
  1772. RCAR_GP_PIN(1, 19),
  1773. };
  1774. static const unsigned int tpu_to0_mux[] = {
  1775. TPU0TO0_MARK,
  1776. };
  1777. static const unsigned int tpu_to1_pins[] = {
  1778. /* TPU0TO1 */
  1779. RCAR_GP_PIN(1, 20),
  1780. };
  1781. static const unsigned int tpu_to1_mux[] = {
  1782. TPU0TO1_MARK,
  1783. };
  1784. static const unsigned int tpu_to2_pins[] = {
  1785. /* TPU0TO2 */
  1786. RCAR_GP_PIN(4, 2),
  1787. };
  1788. static const unsigned int tpu_to2_mux[] = {
  1789. TPU0TO2_MARK,
  1790. };
  1791. static const unsigned int tpu_to3_pins[] = {
  1792. /* TPU0TO3 */
  1793. RCAR_GP_PIN(4, 3),
  1794. };
  1795. static const unsigned int tpu_to3_mux[] = {
  1796. TPU0TO3_MARK,
  1797. };
  1798. /* - VIN0 ------------------------------------------------------------------- */
  1799. static const union vin_data vin0_data_pins = {
  1800. .data24 = {
  1801. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
  1802. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  1803. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1804. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  1805. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
  1806. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
  1807. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
  1808. RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
  1809. RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
  1810. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
  1811. RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
  1812. RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
  1813. },
  1814. };
  1815. static const union vin_data vin0_data_mux = {
  1816. .data24 = {
  1817. VI0_DATA0_MARK, VI0_DATA1_MARK,
  1818. VI0_DATA2_MARK, VI0_DATA3_MARK,
  1819. VI0_DATA4_MARK, VI0_DATA5_MARK,
  1820. VI0_DATA6_MARK, VI0_DATA7_MARK,
  1821. VI0_DATA8_MARK, VI0_DATA9_MARK,
  1822. VI0_DATA10_MARK, VI0_DATA11_MARK,
  1823. VI0_DATA12_MARK, VI0_DATA13_MARK,
  1824. VI0_DATA14_MARK, VI0_DATA15_MARK,
  1825. VI0_DATA16_MARK, VI0_DATA17_MARK,
  1826. VI0_DATA18_MARK, VI0_DATA19_MARK,
  1827. VI0_DATA20_MARK, VI0_DATA21_MARK,
  1828. VI0_DATA22_MARK, VI0_DATA23_MARK,
  1829. },
  1830. };
  1831. static const unsigned int vin0_data18_pins[] = {
  1832. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  1833. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1834. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  1835. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
  1836. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
  1837. RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
  1838. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
  1839. RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
  1840. RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
  1841. };
  1842. static const unsigned int vin0_data18_mux[] = {
  1843. VI0_DATA2_MARK, VI0_DATA3_MARK,
  1844. VI0_DATA4_MARK, VI0_DATA5_MARK,
  1845. VI0_DATA6_MARK, VI0_DATA7_MARK,
  1846. VI0_DATA10_MARK, VI0_DATA11_MARK,
  1847. VI0_DATA12_MARK, VI0_DATA13_MARK,
  1848. VI0_DATA14_MARK, VI0_DATA15_MARK,
  1849. VI0_DATA18_MARK, VI0_DATA19_MARK,
  1850. VI0_DATA20_MARK, VI0_DATA21_MARK,
  1851. VI0_DATA22_MARK, VI0_DATA23_MARK,
  1852. };
  1853. static const unsigned int vin0_sync_pins[] = {
  1854. /* VI0_VSYNC#, VI0_HSYNC# */
  1855. RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
  1856. };
  1857. static const unsigned int vin0_sync_mux[] = {
  1858. VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
  1859. };
  1860. static const unsigned int vin0_field_pins[] = {
  1861. /* VI0_FIELD */
  1862. RCAR_GP_PIN(2, 16),
  1863. };
  1864. static const unsigned int vin0_field_mux[] = {
  1865. VI0_FIELD_MARK,
  1866. };
  1867. static const unsigned int vin0_clkenb_pins[] = {
  1868. /* VI0_CLKENB */
  1869. RCAR_GP_PIN(2, 1),
  1870. };
  1871. static const unsigned int vin0_clkenb_mux[] = {
  1872. VI0_CLKENB_MARK,
  1873. };
  1874. static const unsigned int vin0_clk_pins[] = {
  1875. /* VI0_CLK */
  1876. RCAR_GP_PIN(2, 0),
  1877. };
  1878. static const unsigned int vin0_clk_mux[] = {
  1879. VI0_CLK_MARK,
  1880. };
  1881. /* - VIN1 ------------------------------------------------------------------- */
  1882. static const union vin_data12 vin1_data_pins = {
  1883. .data12 = {
  1884. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  1885. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  1886. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1887. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  1888. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
  1889. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  1890. },
  1891. };
  1892. static const union vin_data12 vin1_data_mux = {
  1893. .data12 = {
  1894. VI1_DATA0_MARK, VI1_DATA1_MARK,
  1895. VI1_DATA2_MARK, VI1_DATA3_MARK,
  1896. VI1_DATA4_MARK, VI1_DATA5_MARK,
  1897. VI1_DATA6_MARK, VI1_DATA7_MARK,
  1898. VI1_DATA8_MARK, VI1_DATA9_MARK,
  1899. VI1_DATA10_MARK, VI1_DATA11_MARK,
  1900. },
  1901. };
  1902. static const unsigned int vin1_sync_pins[] = {
  1903. /* VI1_VSYNC#, VI1_HSYNC# */
  1904. RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
  1905. };
  1906. static const unsigned int vin1_sync_mux[] = {
  1907. VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
  1908. };
  1909. static const unsigned int vin1_field_pins[] = {
  1910. /* VI1_FIELD */
  1911. RCAR_GP_PIN(3, 16),
  1912. };
  1913. static const unsigned int vin1_field_mux[] = {
  1914. VI1_FIELD_MARK,
  1915. };
  1916. static const unsigned int vin1_clkenb_pins[] = {
  1917. /* VI1_CLKENB */
  1918. RCAR_GP_PIN(3, 1),
  1919. };
  1920. static const unsigned int vin1_clkenb_mux[] = {
  1921. VI1_CLKENB_MARK,
  1922. };
  1923. static const unsigned int vin1_clk_pins[] = {
  1924. /* VI1_CLK */
  1925. RCAR_GP_PIN(3, 0),
  1926. };
  1927. static const unsigned int vin1_clk_mux[] = {
  1928. VI1_CLK_MARK,
  1929. };
  1930. static const struct sh_pfc_pin_group pinmux_groups[] = {
  1931. SH_PFC_PIN_GROUP(avb_link),
  1932. SH_PFC_PIN_GROUP(avb_magic),
  1933. SH_PFC_PIN_GROUP(avb_phy_int),
  1934. SH_PFC_PIN_GROUP(avb_mdio),
  1935. SH_PFC_PIN_GROUP(avb_rgmii),
  1936. SH_PFC_PIN_GROUP(avb_txcrefclk),
  1937. SH_PFC_PIN_GROUP(avb_avtp_pps),
  1938. SH_PFC_PIN_GROUP(avb_avtp_capture),
  1939. SH_PFC_PIN_GROUP(avb_avtp_match),
  1940. SH_PFC_PIN_GROUP(canfd0_data_a),
  1941. SH_PFC_PIN_GROUP(canfd0_data_b),
  1942. SH_PFC_PIN_GROUP(canfd1_data),
  1943. SH_PFC_PIN_GROUP(canfd_clk_a),
  1944. SH_PFC_PIN_GROUP(canfd_clk_b),
  1945. SH_PFC_PIN_GROUP(du_rgb666),
  1946. SH_PFC_PIN_GROUP(du_rgb888),
  1947. SH_PFC_PIN_GROUP(du_clk_out),
  1948. SH_PFC_PIN_GROUP(du_sync),
  1949. SH_PFC_PIN_GROUP(du_oddf),
  1950. SH_PFC_PIN_GROUP(du_cde),
  1951. SH_PFC_PIN_GROUP(du_disp),
  1952. SH_PFC_PIN_GROUP(gether_link_a),
  1953. SH_PFC_PIN_GROUP(gether_phy_int_a),
  1954. SH_PFC_PIN_GROUP(gether_mdio_a),
  1955. SH_PFC_PIN_GROUP(gether_link_b),
  1956. SH_PFC_PIN_GROUP(gether_phy_int_b),
  1957. SH_PFC_PIN_GROUP(gether_mdio_b),
  1958. SH_PFC_PIN_GROUP(gether_magic),
  1959. SH_PFC_PIN_GROUP(gether_rgmii),
  1960. SH_PFC_PIN_GROUP(gether_txcrefclk),
  1961. SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
  1962. SH_PFC_PIN_GROUP(gether_rmii),
  1963. SH_PFC_PIN_GROUP(hscif0_data_a),
  1964. SH_PFC_PIN_GROUP(hscif0_clk_a),
  1965. SH_PFC_PIN_GROUP(hscif0_ctrl_a),
  1966. SH_PFC_PIN_GROUP(hscif0_data_b),
  1967. SH_PFC_PIN_GROUP(hscif0_clk_b),
  1968. SH_PFC_PIN_GROUP(hscif0_ctrl_b),
  1969. SH_PFC_PIN_GROUP(hscif1_data),
  1970. SH_PFC_PIN_GROUP(hscif1_clk),
  1971. SH_PFC_PIN_GROUP(hscif1_ctrl),
  1972. SH_PFC_PIN_GROUP(hscif2_data),
  1973. SH_PFC_PIN_GROUP(hscif2_clk),
  1974. SH_PFC_PIN_GROUP(hscif2_ctrl),
  1975. SH_PFC_PIN_GROUP(hscif3_data),
  1976. SH_PFC_PIN_GROUP(hscif3_clk),
  1977. SH_PFC_PIN_GROUP(hscif3_ctrl),
  1978. SH_PFC_PIN_GROUP(i2c0),
  1979. SH_PFC_PIN_GROUP(i2c1),
  1980. SH_PFC_PIN_GROUP(i2c2),
  1981. SH_PFC_PIN_GROUP(i2c3),
  1982. SH_PFC_PIN_GROUP(i2c4),
  1983. SH_PFC_PIN_GROUP(i2c5),
  1984. SH_PFC_PIN_GROUP(intc_ex_irq0),
  1985. SH_PFC_PIN_GROUP(intc_ex_irq1),
  1986. SH_PFC_PIN_GROUP(intc_ex_irq2),
  1987. SH_PFC_PIN_GROUP(intc_ex_irq3),
  1988. SH_PFC_PIN_GROUP(intc_ex_irq4),
  1989. SH_PFC_PIN_GROUP(intc_ex_irq5),
  1990. SH_PFC_PIN_GROUP(mmc_data1),
  1991. SH_PFC_PIN_GROUP(mmc_data4),
  1992. SH_PFC_PIN_GROUP(mmc_data8),
  1993. SH_PFC_PIN_GROUP(mmc_ctrl),
  1994. SH_PFC_PIN_GROUP(mmc_cd),
  1995. SH_PFC_PIN_GROUP(mmc_wp),
  1996. SH_PFC_PIN_GROUP(mmc_ds),
  1997. SH_PFC_PIN_GROUP(msiof0_clk),
  1998. SH_PFC_PIN_GROUP(msiof0_sync),
  1999. SH_PFC_PIN_GROUP(msiof0_ss1),
  2000. SH_PFC_PIN_GROUP(msiof0_ss2),
  2001. SH_PFC_PIN_GROUP(msiof0_txd),
  2002. SH_PFC_PIN_GROUP(msiof0_rxd),
  2003. SH_PFC_PIN_GROUP(msiof1_clk),
  2004. SH_PFC_PIN_GROUP(msiof1_sync),
  2005. SH_PFC_PIN_GROUP(msiof1_ss1),
  2006. SH_PFC_PIN_GROUP(msiof1_ss2),
  2007. SH_PFC_PIN_GROUP(msiof1_txd),
  2008. SH_PFC_PIN_GROUP(msiof1_rxd),
  2009. SH_PFC_PIN_GROUP(msiof2_clk),
  2010. SH_PFC_PIN_GROUP(msiof2_sync),
  2011. SH_PFC_PIN_GROUP(msiof2_ss1),
  2012. SH_PFC_PIN_GROUP(msiof2_ss2),
  2013. SH_PFC_PIN_GROUP(msiof2_txd),
  2014. SH_PFC_PIN_GROUP(msiof2_rxd),
  2015. SH_PFC_PIN_GROUP(msiof3_clk),
  2016. SH_PFC_PIN_GROUP(msiof3_sync),
  2017. SH_PFC_PIN_GROUP(msiof3_ss1),
  2018. SH_PFC_PIN_GROUP(msiof3_ss2),
  2019. SH_PFC_PIN_GROUP(msiof3_txd),
  2020. SH_PFC_PIN_GROUP(msiof3_rxd),
  2021. SH_PFC_PIN_GROUP(pwm0_a),
  2022. SH_PFC_PIN_GROUP(pwm0_b),
  2023. SH_PFC_PIN_GROUP(pwm1_a),
  2024. SH_PFC_PIN_GROUP(pwm1_b),
  2025. SH_PFC_PIN_GROUP(pwm2_a),
  2026. SH_PFC_PIN_GROUP(pwm2_b),
  2027. SH_PFC_PIN_GROUP(pwm3_a),
  2028. SH_PFC_PIN_GROUP(pwm3_b),
  2029. SH_PFC_PIN_GROUP(pwm4_a),
  2030. SH_PFC_PIN_GROUP(pwm4_b),
  2031. SH_PFC_PIN_GROUP(qspi0_ctrl),
  2032. SH_PFC_PIN_GROUP(qspi0_data2),
  2033. SH_PFC_PIN_GROUP(qspi0_data4),
  2034. SH_PFC_PIN_GROUP(qspi1_ctrl),
  2035. SH_PFC_PIN_GROUP(qspi1_data2),
  2036. SH_PFC_PIN_GROUP(qspi1_data4),
  2037. SH_PFC_PIN_GROUP(rpc_clk1),
  2038. SH_PFC_PIN_GROUP(rpc_clk2),
  2039. SH_PFC_PIN_GROUP(rpc_ctrl),
  2040. SH_PFC_PIN_GROUP(rpc_data),
  2041. SH_PFC_PIN_GROUP(rpc_reset),
  2042. SH_PFC_PIN_GROUP(rpc_int),
  2043. SH_PFC_PIN_GROUP(rpc_wp),
  2044. SH_PFC_PIN_GROUP(scif0_data),
  2045. SH_PFC_PIN_GROUP(scif0_clk),
  2046. SH_PFC_PIN_GROUP(scif0_ctrl),
  2047. SH_PFC_PIN_GROUP(scif1_data_a),
  2048. SH_PFC_PIN_GROUP(scif1_clk),
  2049. SH_PFC_PIN_GROUP(scif1_ctrl),
  2050. SH_PFC_PIN_GROUP(scif1_data_b),
  2051. SH_PFC_PIN_GROUP(scif3_data),
  2052. SH_PFC_PIN_GROUP(scif3_clk),
  2053. SH_PFC_PIN_GROUP(scif3_ctrl),
  2054. SH_PFC_PIN_GROUP(scif4_data),
  2055. SH_PFC_PIN_GROUP(scif4_clk),
  2056. SH_PFC_PIN_GROUP(scif4_ctrl),
  2057. SH_PFC_PIN_GROUP(scif_clk_a),
  2058. SH_PFC_PIN_GROUP(scif_clk_b),
  2059. SH_PFC_PIN_GROUP(tmu_tclk1_a),
  2060. SH_PFC_PIN_GROUP(tmu_tclk1_b),
  2061. SH_PFC_PIN_GROUP(tmu_tclk2_a),
  2062. SH_PFC_PIN_GROUP(tmu_tclk2_b),
  2063. SH_PFC_PIN_GROUP(tpu_to0),
  2064. SH_PFC_PIN_GROUP(tpu_to1),
  2065. SH_PFC_PIN_GROUP(tpu_to2),
  2066. SH_PFC_PIN_GROUP(tpu_to3),
  2067. VIN_DATA_PIN_GROUP(vin0_data, 8),
  2068. VIN_DATA_PIN_GROUP(vin0_data, 10),
  2069. VIN_DATA_PIN_GROUP(vin0_data, 12),
  2070. VIN_DATA_PIN_GROUP(vin0_data, 16),
  2071. SH_PFC_PIN_GROUP(vin0_data18),
  2072. VIN_DATA_PIN_GROUP(vin0_data, 20),
  2073. VIN_DATA_PIN_GROUP(vin0_data, 24),
  2074. SH_PFC_PIN_GROUP(vin0_sync),
  2075. SH_PFC_PIN_GROUP(vin0_field),
  2076. SH_PFC_PIN_GROUP(vin0_clkenb),
  2077. SH_PFC_PIN_GROUP(vin0_clk),
  2078. VIN_DATA_PIN_GROUP(vin1_data, 8),
  2079. VIN_DATA_PIN_GROUP(vin1_data, 10),
  2080. VIN_DATA_PIN_GROUP(vin1_data, 12),
  2081. SH_PFC_PIN_GROUP(vin1_sync),
  2082. SH_PFC_PIN_GROUP(vin1_field),
  2083. SH_PFC_PIN_GROUP(vin1_clkenb),
  2084. SH_PFC_PIN_GROUP(vin1_clk),
  2085. };
  2086. static const char * const avb_groups[] = {
  2087. "avb_link",
  2088. "avb_magic",
  2089. "avb_phy_int",
  2090. "avb_mdio",
  2091. "avb_rgmii",
  2092. "avb_txcrefclk",
  2093. "avb_avtp_pps",
  2094. "avb_avtp_capture",
  2095. "avb_avtp_match",
  2096. };
  2097. static const char * const canfd0_groups[] = {
  2098. "canfd0_data_a",
  2099. "canfd0_data_b",
  2100. };
  2101. static const char * const canfd1_groups[] = {
  2102. "canfd1_data",
  2103. };
  2104. static const char * const canfd_clk_groups[] = {
  2105. "canfd_clk_a",
  2106. "canfd_clk_b",
  2107. };
  2108. static const char * const du_groups[] = {
  2109. "du_rgb666",
  2110. "du_rgb888",
  2111. "du_clk_out",
  2112. "du_sync",
  2113. "du_oddf",
  2114. "du_cde",
  2115. "du_disp",
  2116. };
  2117. static const char * const gether_groups[] = {
  2118. "gether_link_a",
  2119. "gether_phy_int_a",
  2120. "gether_mdio_a",
  2121. "gether_link_b",
  2122. "gether_phy_int_b",
  2123. "gether_mdio_b",
  2124. "gether_magic",
  2125. "gether_rgmii",
  2126. "gether_txcrefclk",
  2127. "gether_txcrefclk_mega",
  2128. "gether_rmii",
  2129. };
  2130. static const char * const hscif0_groups[] = {
  2131. "hscif0_data_a",
  2132. "hscif0_clk_a",
  2133. "hscif0_ctrl_a",
  2134. "hscif0_data_b",
  2135. "hscif0_clk_b",
  2136. "hscif0_ctrl_b",
  2137. };
  2138. static const char * const hscif1_groups[] = {
  2139. "hscif1_data",
  2140. "hscif1_clk",
  2141. "hscif1_ctrl",
  2142. };
  2143. static const char * const hscif2_groups[] = {
  2144. "hscif2_data",
  2145. "hscif2_clk",
  2146. "hscif2_ctrl",
  2147. };
  2148. static const char * const hscif3_groups[] = {
  2149. "hscif3_data",
  2150. "hscif3_clk",
  2151. "hscif3_ctrl",
  2152. };
  2153. static const char * const i2c0_groups[] = {
  2154. "i2c0",
  2155. };
  2156. static const char * const i2c1_groups[] = {
  2157. "i2c1",
  2158. };
  2159. static const char * const i2c2_groups[] = {
  2160. "i2c2",
  2161. };
  2162. static const char * const i2c3_groups[] = {
  2163. "i2c3",
  2164. };
  2165. static const char * const i2c4_groups[] = {
  2166. "i2c4",
  2167. };
  2168. static const char * const i2c5_groups[] = {
  2169. "i2c5",
  2170. };
  2171. static const char * const intc_ex_groups[] = {
  2172. "intc_ex_irq0",
  2173. "intc_ex_irq1",
  2174. "intc_ex_irq2",
  2175. "intc_ex_irq3",
  2176. "intc_ex_irq4",
  2177. "intc_ex_irq5",
  2178. };
  2179. static const char * const mmc_groups[] = {
  2180. "mmc_data1",
  2181. "mmc_data4",
  2182. "mmc_data8",
  2183. "mmc_ctrl",
  2184. "mmc_cd",
  2185. "mmc_wp",
  2186. "mmc_ds",
  2187. };
  2188. static const char * const msiof0_groups[] = {
  2189. "msiof0_clk",
  2190. "msiof0_sync",
  2191. "msiof0_ss1",
  2192. "msiof0_ss2",
  2193. "msiof0_txd",
  2194. "msiof0_rxd",
  2195. };
  2196. static const char * const msiof1_groups[] = {
  2197. "msiof1_clk",
  2198. "msiof1_sync",
  2199. "msiof1_ss1",
  2200. "msiof1_ss2",
  2201. "msiof1_txd",
  2202. "msiof1_rxd",
  2203. };
  2204. static const char * const msiof2_groups[] = {
  2205. "msiof2_clk",
  2206. "msiof2_sync",
  2207. "msiof2_ss1",
  2208. "msiof2_ss2",
  2209. "msiof2_txd",
  2210. "msiof2_rxd",
  2211. };
  2212. static const char * const msiof3_groups[] = {
  2213. "msiof3_clk",
  2214. "msiof3_sync",
  2215. "msiof3_ss1",
  2216. "msiof3_ss2",
  2217. "msiof3_txd",
  2218. "msiof3_rxd",
  2219. };
  2220. static const char * const pwm0_groups[] = {
  2221. "pwm0_a",
  2222. "pwm0_b",
  2223. };
  2224. static const char * const pwm1_groups[] = {
  2225. "pwm1_a",
  2226. "pwm1_b",
  2227. };
  2228. static const char * const pwm2_groups[] = {
  2229. "pwm2_a",
  2230. "pwm2_b",
  2231. };
  2232. static const char * const pwm3_groups[] = {
  2233. "pwm3_a",
  2234. "pwm3_b",
  2235. };
  2236. static const char * const pwm4_groups[] = {
  2237. "pwm4_a",
  2238. "pwm4_b",
  2239. };
  2240. static const char * const qspi0_groups[] = {
  2241. "qspi0_ctrl",
  2242. "qspi0_data2",
  2243. "qspi0_data4",
  2244. };
  2245. static const char * const qspi1_groups[] = {
  2246. "qspi1_ctrl",
  2247. "qspi1_data2",
  2248. "qspi1_data4",
  2249. };
  2250. static const char * const rpc_groups[] = {
  2251. "rpc_clk1",
  2252. "rpc_clk2",
  2253. "rpc_ctrl",
  2254. "rpc_data",
  2255. "rpc_reset",
  2256. "rpc_int",
  2257. "rpc_wp",
  2258. };
  2259. static const char * const scif0_groups[] = {
  2260. "scif0_data",
  2261. "scif0_clk",
  2262. "scif0_ctrl",
  2263. };
  2264. static const char * const scif1_groups[] = {
  2265. "scif1_data_a",
  2266. "scif1_clk",
  2267. "scif1_ctrl",
  2268. "scif1_data_b",
  2269. };
  2270. static const char * const scif3_groups[] = {
  2271. "scif3_data",
  2272. "scif3_clk",
  2273. "scif3_ctrl",
  2274. };
  2275. static const char * const scif4_groups[] = {
  2276. "scif4_data",
  2277. "scif4_clk",
  2278. "scif4_ctrl",
  2279. };
  2280. static const char * const scif_clk_groups[] = {
  2281. "scif_clk_a",
  2282. "scif_clk_b",
  2283. };
  2284. static const char * const tmu_groups[] = {
  2285. "tmu_tclk1_a",
  2286. "tmu_tclk1_b",
  2287. "tmu_tclk2_a",
  2288. "tmu_tclk2_b",
  2289. };
  2290. static const char * const tpu_groups[] = {
  2291. "tpu_to0",
  2292. "tpu_to1",
  2293. "tpu_to2",
  2294. "tpu_to3",
  2295. };
  2296. static const char * const vin0_groups[] = {
  2297. "vin0_data8",
  2298. "vin0_data10",
  2299. "vin0_data12",
  2300. "vin0_data16",
  2301. "vin0_data18",
  2302. "vin0_data20",
  2303. "vin0_data24",
  2304. "vin0_sync",
  2305. "vin0_field",
  2306. "vin0_clkenb",
  2307. "vin0_clk",
  2308. };
  2309. static const char * const vin1_groups[] = {
  2310. "vin1_data8",
  2311. "vin1_data10",
  2312. "vin1_data12",
  2313. "vin1_sync",
  2314. "vin1_field",
  2315. "vin1_clkenb",
  2316. "vin1_clk",
  2317. };
  2318. static const struct sh_pfc_function pinmux_functions[] = {
  2319. SH_PFC_FUNCTION(avb),
  2320. SH_PFC_FUNCTION(canfd0),
  2321. SH_PFC_FUNCTION(canfd1),
  2322. SH_PFC_FUNCTION(canfd_clk),
  2323. SH_PFC_FUNCTION(du),
  2324. SH_PFC_FUNCTION(gether),
  2325. SH_PFC_FUNCTION(hscif0),
  2326. SH_PFC_FUNCTION(hscif1),
  2327. SH_PFC_FUNCTION(hscif2),
  2328. SH_PFC_FUNCTION(hscif3),
  2329. SH_PFC_FUNCTION(i2c0),
  2330. SH_PFC_FUNCTION(i2c1),
  2331. SH_PFC_FUNCTION(i2c2),
  2332. SH_PFC_FUNCTION(i2c3),
  2333. SH_PFC_FUNCTION(i2c4),
  2334. SH_PFC_FUNCTION(i2c5),
  2335. SH_PFC_FUNCTION(intc_ex),
  2336. SH_PFC_FUNCTION(mmc),
  2337. SH_PFC_FUNCTION(msiof0),
  2338. SH_PFC_FUNCTION(msiof1),
  2339. SH_PFC_FUNCTION(msiof2),
  2340. SH_PFC_FUNCTION(msiof3),
  2341. SH_PFC_FUNCTION(pwm0),
  2342. SH_PFC_FUNCTION(pwm1),
  2343. SH_PFC_FUNCTION(pwm2),
  2344. SH_PFC_FUNCTION(pwm3),
  2345. SH_PFC_FUNCTION(pwm4),
  2346. SH_PFC_FUNCTION(qspi0),
  2347. SH_PFC_FUNCTION(qspi1),
  2348. SH_PFC_FUNCTION(rpc),
  2349. SH_PFC_FUNCTION(scif0),
  2350. SH_PFC_FUNCTION(scif1),
  2351. SH_PFC_FUNCTION(scif3),
  2352. SH_PFC_FUNCTION(scif4),
  2353. SH_PFC_FUNCTION(scif_clk),
  2354. SH_PFC_FUNCTION(tmu),
  2355. SH_PFC_FUNCTION(tpu),
  2356. SH_PFC_FUNCTION(vin0),
  2357. SH_PFC_FUNCTION(vin1),
  2358. };
  2359. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  2360. #define F_(x, y) FN_##y
  2361. #define FM(x) FN_##x
  2362. { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
  2363. 0, 0,
  2364. 0, 0,
  2365. 0, 0,
  2366. 0, 0,
  2367. 0, 0,
  2368. 0, 0,
  2369. 0, 0,
  2370. 0, 0,
  2371. 0, 0,
  2372. 0, 0,
  2373. GP_0_21_FN, GPSR0_21,
  2374. GP_0_20_FN, GPSR0_20,
  2375. GP_0_19_FN, GPSR0_19,
  2376. GP_0_18_FN, GPSR0_18,
  2377. GP_0_17_FN, GPSR0_17,
  2378. GP_0_16_FN, GPSR0_16,
  2379. GP_0_15_FN, GPSR0_15,
  2380. GP_0_14_FN, GPSR0_14,
  2381. GP_0_13_FN, GPSR0_13,
  2382. GP_0_12_FN, GPSR0_12,
  2383. GP_0_11_FN, GPSR0_11,
  2384. GP_0_10_FN, GPSR0_10,
  2385. GP_0_9_FN, GPSR0_9,
  2386. GP_0_8_FN, GPSR0_8,
  2387. GP_0_7_FN, GPSR0_7,
  2388. GP_0_6_FN, GPSR0_6,
  2389. GP_0_5_FN, GPSR0_5,
  2390. GP_0_4_FN, GPSR0_4,
  2391. GP_0_3_FN, GPSR0_3,
  2392. GP_0_2_FN, GPSR0_2,
  2393. GP_0_1_FN, GPSR0_1,
  2394. GP_0_0_FN, GPSR0_0, ))
  2395. },
  2396. { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
  2397. 0, 0,
  2398. 0, 0,
  2399. 0, 0,
  2400. 0, 0,
  2401. GP_1_27_FN, GPSR1_27,
  2402. GP_1_26_FN, GPSR1_26,
  2403. GP_1_25_FN, GPSR1_25,
  2404. GP_1_24_FN, GPSR1_24,
  2405. GP_1_23_FN, GPSR1_23,
  2406. GP_1_22_FN, GPSR1_22,
  2407. GP_1_21_FN, GPSR1_21,
  2408. GP_1_20_FN, GPSR1_20,
  2409. GP_1_19_FN, GPSR1_19,
  2410. GP_1_18_FN, GPSR1_18,
  2411. GP_1_17_FN, GPSR1_17,
  2412. GP_1_16_FN, GPSR1_16,
  2413. GP_1_15_FN, GPSR1_15,
  2414. GP_1_14_FN, GPSR1_14,
  2415. GP_1_13_FN, GPSR1_13,
  2416. GP_1_12_FN, GPSR1_12,
  2417. GP_1_11_FN, GPSR1_11,
  2418. GP_1_10_FN, GPSR1_10,
  2419. GP_1_9_FN, GPSR1_9,
  2420. GP_1_8_FN, GPSR1_8,
  2421. GP_1_7_FN, GPSR1_7,
  2422. GP_1_6_FN, GPSR1_6,
  2423. GP_1_5_FN, GPSR1_5,
  2424. GP_1_4_FN, GPSR1_4,
  2425. GP_1_3_FN, GPSR1_3,
  2426. GP_1_2_FN, GPSR1_2,
  2427. GP_1_1_FN, GPSR1_1,
  2428. GP_1_0_FN, GPSR1_0, ))
  2429. },
  2430. { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
  2431. 0, 0,
  2432. 0, 0,
  2433. GP_2_29_FN, GPSR2_29,
  2434. GP_2_28_FN, GPSR2_28,
  2435. GP_2_27_FN, GPSR2_27,
  2436. GP_2_26_FN, GPSR2_26,
  2437. GP_2_25_FN, GPSR2_25,
  2438. GP_2_24_FN, GPSR2_24,
  2439. GP_2_23_FN, GPSR2_23,
  2440. GP_2_22_FN, GPSR2_22,
  2441. GP_2_21_FN, GPSR2_21,
  2442. GP_2_20_FN, GPSR2_20,
  2443. GP_2_19_FN, GPSR2_19,
  2444. GP_2_18_FN, GPSR2_18,
  2445. GP_2_17_FN, GPSR2_17,
  2446. GP_2_16_FN, GPSR2_16,
  2447. GP_2_15_FN, GPSR2_15,
  2448. GP_2_14_FN, GPSR2_14,
  2449. GP_2_13_FN, GPSR2_13,
  2450. GP_2_12_FN, GPSR2_12,
  2451. GP_2_11_FN, GPSR2_11,
  2452. GP_2_10_FN, GPSR2_10,
  2453. GP_2_9_FN, GPSR2_9,
  2454. GP_2_8_FN, GPSR2_8,
  2455. GP_2_7_FN, GPSR2_7,
  2456. GP_2_6_FN, GPSR2_6,
  2457. GP_2_5_FN, GPSR2_5,
  2458. GP_2_4_FN, GPSR2_4,
  2459. GP_2_3_FN, GPSR2_3,
  2460. GP_2_2_FN, GPSR2_2,
  2461. GP_2_1_FN, GPSR2_1,
  2462. GP_2_0_FN, GPSR2_0, ))
  2463. },
  2464. { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
  2465. 0, 0,
  2466. 0, 0,
  2467. 0, 0,
  2468. 0, 0,
  2469. 0, 0,
  2470. 0, 0,
  2471. 0, 0,
  2472. 0, 0,
  2473. 0, 0,
  2474. 0, 0,
  2475. 0, 0,
  2476. 0, 0,
  2477. 0, 0,
  2478. 0, 0,
  2479. 0, 0,
  2480. GP_3_16_FN, GPSR3_16,
  2481. GP_3_15_FN, GPSR3_15,
  2482. GP_3_14_FN, GPSR3_14,
  2483. GP_3_13_FN, GPSR3_13,
  2484. GP_3_12_FN, GPSR3_12,
  2485. GP_3_11_FN, GPSR3_11,
  2486. GP_3_10_FN, GPSR3_10,
  2487. GP_3_9_FN, GPSR3_9,
  2488. GP_3_8_FN, GPSR3_8,
  2489. GP_3_7_FN, GPSR3_7,
  2490. GP_3_6_FN, GPSR3_6,
  2491. GP_3_5_FN, GPSR3_5,
  2492. GP_3_4_FN, GPSR3_4,
  2493. GP_3_3_FN, GPSR3_3,
  2494. GP_3_2_FN, GPSR3_2,
  2495. GP_3_1_FN, GPSR3_1,
  2496. GP_3_0_FN, GPSR3_0, ))
  2497. },
  2498. { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
  2499. 0, 0,
  2500. 0, 0,
  2501. 0, 0,
  2502. 0, 0,
  2503. 0, 0,
  2504. 0, 0,
  2505. 0, 0,
  2506. GP_4_24_FN, GPSR4_24,
  2507. GP_4_23_FN, GPSR4_23,
  2508. GP_4_22_FN, GPSR4_22,
  2509. GP_4_21_FN, GPSR4_21,
  2510. GP_4_20_FN, GPSR4_20,
  2511. GP_4_19_FN, GPSR4_19,
  2512. GP_4_18_FN, GPSR4_18,
  2513. GP_4_17_FN, GPSR4_17,
  2514. GP_4_16_FN, GPSR4_16,
  2515. GP_4_15_FN, GPSR4_15,
  2516. GP_4_14_FN, GPSR4_14,
  2517. GP_4_13_FN, GPSR4_13,
  2518. GP_4_12_FN, GPSR4_12,
  2519. GP_4_11_FN, GPSR4_11,
  2520. GP_4_10_FN, GPSR4_10,
  2521. GP_4_9_FN, GPSR4_9,
  2522. GP_4_8_FN, GPSR4_8,
  2523. GP_4_7_FN, GPSR4_7,
  2524. GP_4_6_FN, GPSR4_6,
  2525. GP_4_5_FN, GPSR4_5,
  2526. GP_4_4_FN, GPSR4_4,
  2527. GP_4_3_FN, GPSR4_3,
  2528. GP_4_2_FN, GPSR4_2,
  2529. GP_4_1_FN, GPSR4_1,
  2530. GP_4_0_FN, GPSR4_0, ))
  2531. },
  2532. { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
  2533. 0, 0,
  2534. 0, 0,
  2535. 0, 0,
  2536. 0, 0,
  2537. 0, 0,
  2538. 0, 0,
  2539. 0, 0,
  2540. 0, 0,
  2541. 0, 0,
  2542. 0, 0,
  2543. 0, 0,
  2544. 0, 0,
  2545. 0, 0,
  2546. 0, 0,
  2547. 0, 0,
  2548. 0, 0,
  2549. 0, 0,
  2550. GP_5_14_FN, GPSR5_14,
  2551. GP_5_13_FN, GPSR5_13,
  2552. GP_5_12_FN, GPSR5_12,
  2553. GP_5_11_FN, GPSR5_11,
  2554. GP_5_10_FN, GPSR5_10,
  2555. GP_5_9_FN, GPSR5_9,
  2556. GP_5_8_FN, GPSR5_8,
  2557. GP_5_7_FN, GPSR5_7,
  2558. GP_5_6_FN, GPSR5_6,
  2559. GP_5_5_FN, GPSR5_5,
  2560. GP_5_4_FN, GPSR5_4,
  2561. GP_5_3_FN, GPSR5_3,
  2562. GP_5_2_FN, GPSR5_2,
  2563. GP_5_1_FN, GPSR5_1,
  2564. GP_5_0_FN, GPSR5_0, ))
  2565. },
  2566. #undef F_
  2567. #undef FM
  2568. #define F_(x, y) x,
  2569. #define FM(x) FN_##x,
  2570. { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
  2571. IP0_31_28
  2572. IP0_27_24
  2573. IP0_23_20
  2574. IP0_19_16
  2575. IP0_15_12
  2576. IP0_11_8
  2577. IP0_7_4
  2578. IP0_3_0 ))
  2579. },
  2580. { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
  2581. IP1_31_28
  2582. IP1_27_24
  2583. IP1_23_20
  2584. IP1_19_16
  2585. IP1_15_12
  2586. IP1_11_8
  2587. IP1_7_4
  2588. IP1_3_0 ))
  2589. },
  2590. { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
  2591. IP2_31_28
  2592. IP2_27_24
  2593. IP2_23_20
  2594. IP2_19_16
  2595. IP2_15_12
  2596. IP2_11_8
  2597. IP2_7_4
  2598. IP2_3_0 ))
  2599. },
  2600. { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
  2601. IP3_31_28
  2602. IP3_27_24
  2603. IP3_23_20
  2604. IP3_19_16
  2605. IP3_15_12
  2606. IP3_11_8
  2607. IP3_7_4
  2608. IP3_3_0 ))
  2609. },
  2610. { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
  2611. IP4_31_28
  2612. IP4_27_24
  2613. IP4_23_20
  2614. IP4_19_16
  2615. IP4_15_12
  2616. IP4_11_8
  2617. IP4_7_4
  2618. IP4_3_0 ))
  2619. },
  2620. { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
  2621. IP5_31_28
  2622. IP5_27_24
  2623. IP5_23_20
  2624. IP5_19_16
  2625. IP5_15_12
  2626. IP5_11_8
  2627. IP5_7_4
  2628. IP5_3_0 ))
  2629. },
  2630. { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
  2631. IP6_31_28
  2632. IP6_27_24
  2633. IP6_23_20
  2634. IP6_19_16
  2635. IP6_15_12
  2636. IP6_11_8
  2637. IP6_7_4
  2638. IP6_3_0 ))
  2639. },
  2640. { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
  2641. IP7_31_28
  2642. IP7_27_24
  2643. IP7_23_20
  2644. IP7_19_16
  2645. IP7_15_12
  2646. IP7_11_8
  2647. IP7_7_4
  2648. IP7_3_0 ))
  2649. },
  2650. { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
  2651. IP8_31_28
  2652. IP8_27_24
  2653. IP8_23_20
  2654. IP8_19_16
  2655. IP8_15_12
  2656. IP8_11_8
  2657. IP8_7_4
  2658. IP8_3_0 ))
  2659. },
  2660. { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
  2661. IP9_31_28
  2662. IP9_27_24
  2663. IP9_23_20
  2664. IP9_19_16
  2665. IP9_15_12
  2666. IP9_11_8
  2667. IP9_7_4
  2668. IP9_3_0 ))
  2669. },
  2670. { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
  2671. IP10_31_28
  2672. IP10_27_24
  2673. IP10_23_20
  2674. IP10_19_16
  2675. IP10_15_12
  2676. IP10_11_8
  2677. IP10_7_4
  2678. IP10_3_0 ))
  2679. },
  2680. #undef F_
  2681. #undef FM
  2682. #define F_(x, y) x,
  2683. #define FM(x) FN_##x,
  2684. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
  2685. GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
  2686. 1, 1, 1, 1, 1),
  2687. GROUP(
  2688. /* RESERVED 31, 30, 29, 28 */
  2689. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2690. /* RESERVED 27, 26, 25, 24 */
  2691. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2692. /* RESERVED 23, 22, 21, 20 */
  2693. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2694. /* RESERVED 19, 18, 17, 16 */
  2695. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2696. /* RESERVED 15, 14, 13, 12 */
  2697. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2698. MOD_SEL0_11
  2699. MOD_SEL0_10
  2700. MOD_SEL0_9
  2701. MOD_SEL0_8
  2702. MOD_SEL0_7
  2703. MOD_SEL0_6
  2704. MOD_SEL0_5
  2705. MOD_SEL0_4
  2706. 0, 0,
  2707. MOD_SEL0_2
  2708. MOD_SEL0_1
  2709. MOD_SEL0_0 ))
  2710. },
  2711. { },
  2712. };
  2713. enum ioctrl_regs {
  2714. POCCTRL0,
  2715. POCCTRL1,
  2716. POCCTRL2,
  2717. POCCTRL3,
  2718. TDSELCTRL,
  2719. };
  2720. static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
  2721. [POCCTRL0] = { 0xe6060380, },
  2722. [POCCTRL1] = { 0xe6060384, },
  2723. [POCCTRL2] = { 0xe6060388, },
  2724. [POCCTRL3] = { 0xe606038c, },
  2725. [TDSELCTRL] = { 0xe60603c0, },
  2726. { /* sentinel */ },
  2727. };
  2728. static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
  2729. u32 *pocctrl)
  2730. {
  2731. int bit = pin & 0x1f;
  2732. *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
  2733. if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
  2734. return bit;
  2735. else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
  2736. return bit + 22;
  2737. *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
  2738. if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
  2739. return bit - 10;
  2740. if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
  2741. (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
  2742. return bit + 7;
  2743. *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
  2744. if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
  2745. return pin - 25;
  2746. return -EINVAL;
  2747. }
  2748. static const struct sh_pfc_soc_operations pinmux_ops = {
  2749. .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
  2750. };
  2751. const struct sh_pfc_soc_info r8a77980_pinmux_info = {
  2752. .name = "r8a77980_pfc",
  2753. .ops = &pinmux_ops,
  2754. .unlock_reg = 0xe6060000, /* PMMR */
  2755. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  2756. .pins = pinmux_pins,
  2757. .nr_pins = ARRAY_SIZE(pinmux_pins),
  2758. .groups = pinmux_groups,
  2759. .nr_groups = ARRAY_SIZE(pinmux_groups),
  2760. .functions = pinmux_functions,
  2761. .nr_functions = ARRAY_SIZE(pinmux_functions),
  2762. .cfg_regs = pinmux_config_regs,
  2763. .ioctrl_regs = pinmux_ioctrl_regs,
  2764. .pinmux_data = pinmux_data,
  2765. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  2766. };