pfc-r8a77970.c 73 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A77970 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2016 Renesas Electronics Corp.
  6. * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
  7. *
  8. * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  9. *
  10. * R-Car Gen3 processor support - PFC hardware block.
  11. *
  12. * Copyright (C) 2015 Renesas Electronics Corporation
  13. */
  14. #include <linux/errno.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include "core.h"
  18. #include "sh_pfc.h"
  19. #define CPU_ALL_GP(fn, sfx) \
  20. PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  21. PORT_GP_28(1, fn, sfx), \
  22. PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  23. PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  24. PORT_GP_6(4, fn, sfx), \
  25. PORT_GP_15(5, fn, sfx)
  26. /*
  27. * F_() : just information
  28. * FM() : macro for FN_xxx / xxx_MARK
  29. */
  30. /* GPSR0 */
  31. #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
  32. #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
  33. #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
  34. #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
  35. #define GPSR0_17 F_(DU_DB7, IP2_7_4)
  36. #define GPSR0_16 F_(DU_DB6, IP2_3_0)
  37. #define GPSR0_15 F_(DU_DB5, IP1_31_28)
  38. #define GPSR0_14 F_(DU_DB4, IP1_27_24)
  39. #define GPSR0_13 F_(DU_DB3, IP1_23_20)
  40. #define GPSR0_12 F_(DU_DB2, IP1_19_16)
  41. #define GPSR0_11 F_(DU_DG7, IP1_15_12)
  42. #define GPSR0_10 F_(DU_DG6, IP1_11_8)
  43. #define GPSR0_9 F_(DU_DG5, IP1_7_4)
  44. #define GPSR0_8 F_(DU_DG4, IP1_3_0)
  45. #define GPSR0_7 F_(DU_DG3, IP0_31_28)
  46. #define GPSR0_6 F_(DU_DG2, IP0_27_24)
  47. #define GPSR0_5 F_(DU_DR7, IP0_23_20)
  48. #define GPSR0_4 F_(DU_DR6, IP0_19_16)
  49. #define GPSR0_3 F_(DU_DR5, IP0_15_12)
  50. #define GPSR0_2 F_(DU_DR4, IP0_11_8)
  51. #define GPSR0_1 F_(DU_DR3, IP0_7_4)
  52. #define GPSR0_0 F_(DU_DR2, IP0_3_0)
  53. /* GPSR1 */
  54. #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
  55. #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
  56. #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
  57. #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
  58. #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
  59. #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
  60. #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
  61. #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
  62. #define GPSR1_19 FM(AVB0_AVTP_MATCH)
  63. #define GPSR1_18 FM(AVB0_LINK)
  64. #define GPSR1_17 FM(AVB0_PHY_INT)
  65. #define GPSR1_16 FM(AVB0_MAGIC)
  66. #define GPSR1_15 FM(AVB0_MDC)
  67. #define GPSR1_14 FM(AVB0_MDIO)
  68. #define GPSR1_13 FM(AVB0_TXCREFCLK)
  69. #define GPSR1_12 FM(AVB0_TD3)
  70. #define GPSR1_11 FM(AVB0_TD2)
  71. #define GPSR1_10 FM(AVB0_TD1)
  72. #define GPSR1_9 FM(AVB0_TD0)
  73. #define GPSR1_8 FM(AVB0_TXC)
  74. #define GPSR1_7 FM(AVB0_TX_CTL)
  75. #define GPSR1_6 FM(AVB0_RD3)
  76. #define GPSR1_5 FM(AVB0_RD2)
  77. #define GPSR1_4 FM(AVB0_RD1)
  78. #define GPSR1_3 FM(AVB0_RD0)
  79. #define GPSR1_2 FM(AVB0_RXC)
  80. #define GPSR1_1 FM(AVB0_RX_CTL)
  81. #define GPSR1_0 F_(IRQ0, IP2_27_24)
  82. /* GPSR2 */
  83. #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
  84. #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
  85. #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
  86. #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
  87. #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
  88. #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
  89. #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
  90. #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
  91. #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
  92. #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
  93. #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
  94. #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
  95. #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
  96. #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
  97. #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
  98. #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
  99. #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
  100. /* GPSR3 */
  101. #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
  102. #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
  103. #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
  104. #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
  105. #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
  106. #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
  107. #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
  108. #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
  109. #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
  110. #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
  111. #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
  112. #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
  113. #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
  114. #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
  115. #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
  116. #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
  117. #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
  118. /* GPSR4 */
  119. #define GPSR4_5 F_(SDA2, IP7_27_24)
  120. #define GPSR4_4 F_(SCL2, IP7_23_20)
  121. #define GPSR4_3 F_(SDA1, IP7_19_16)
  122. #define GPSR4_2 F_(SCL1, IP7_15_12)
  123. #define GPSR4_1 F_(SDA0, IP7_11_8)
  124. #define GPSR4_0 F_(SCL0, IP7_7_4)
  125. /* GPSR5 */
  126. #define GPSR5_14 FM(RPC_INT_N)
  127. #define GPSR5_13 FM(RPC_WP_N)
  128. #define GPSR5_12 FM(RPC_RESET_N)
  129. #define GPSR5_11 FM(QSPI1_SSL)
  130. #define GPSR5_10 FM(QSPI1_IO3)
  131. #define GPSR5_9 FM(QSPI1_IO2)
  132. #define GPSR5_8 FM(QSPI1_MISO_IO1)
  133. #define GPSR5_7 FM(QSPI1_MOSI_IO0)
  134. #define GPSR5_6 FM(QSPI1_SPCLK)
  135. #define GPSR5_5 FM(QSPI0_SSL)
  136. #define GPSR5_4 FM(QSPI0_IO3)
  137. #define GPSR5_3 FM(QSPI0_IO2)
  138. #define GPSR5_2 FM(QSPI0_MISO_IO1)
  139. #define GPSR5_1 FM(QSPI0_MOSI_IO0)
  140. #define GPSR5_0 FM(QSPI0_SPCLK)
  141. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
  142. #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  143. #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  144. #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  145. #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  146. #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  147. #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  148. #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  149. #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  150. #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  151. #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  152. #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  153. #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  154. #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  155. #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  156. #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  157. #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  158. #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  159. #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  160. #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  161. #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  162. #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  163. #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  164. #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  165. #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  166. #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  167. #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  168. #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  169. #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  170. #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  171. #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  172. #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  173. #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  174. #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  175. #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  176. #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  177. #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  178. #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  179. #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  180. #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  181. #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  182. #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  183. #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  184. #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  185. #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  186. #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  187. #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  188. #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  189. #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  190. #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  191. #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  192. #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  193. #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  194. #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  195. #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  196. #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  197. #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  198. #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  199. #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  200. #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  201. #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  202. #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  203. #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  204. #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  205. #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  206. #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  207. #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  208. #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  209. #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  210. #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  211. #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  212. #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  213. #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  214. #define PINMUX_GPSR \
  215. \
  216. GPSR1_27 \
  217. GPSR1_26 \
  218. GPSR1_25 \
  219. GPSR1_24 \
  220. GPSR1_23 \
  221. GPSR1_22 \
  222. GPSR0_21 GPSR1_21 \
  223. GPSR0_20 GPSR1_20 \
  224. GPSR0_19 GPSR1_19 \
  225. GPSR0_18 GPSR1_18 \
  226. GPSR0_17 GPSR1_17 \
  227. GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
  228. GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
  229. GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
  230. GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
  231. GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
  232. GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
  233. GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
  234. GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
  235. GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
  236. GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
  237. GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
  238. GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
  239. GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
  240. GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
  241. GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
  242. GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
  243. GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
  244. #define PINMUX_IPSR \
  245. \
  246. FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
  247. FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
  248. FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
  249. FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
  250. FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
  251. FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
  252. FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
  253. FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
  254. \
  255. FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
  256. FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
  257. FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
  258. FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
  259. FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
  260. FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
  261. FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
  262. FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
  263. \
  264. FM(IP8_3_0) IP8_3_0 \
  265. FM(IP8_7_4) IP8_7_4 \
  266. FM(IP8_11_8) IP8_11_8 \
  267. FM(IP8_15_12) IP8_15_12 \
  268. FM(IP8_19_16) IP8_19_16 \
  269. FM(IP8_23_20) IP8_23_20 \
  270. FM(IP8_27_24) IP8_27_24 \
  271. FM(IP8_31_28) IP8_31_28
  272. /* MOD_SEL0 */ /* 0 */ /* 1 */
  273. #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
  274. #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
  275. #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
  276. #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
  277. #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
  278. #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
  279. #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
  280. #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
  281. #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
  282. #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
  283. #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
  284. #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
  285. #define PINMUX_MOD_SELS \
  286. \
  287. MOD_SEL0_11 \
  288. MOD_SEL0_10 \
  289. MOD_SEL0_9 \
  290. MOD_SEL0_8 \
  291. MOD_SEL0_7 \
  292. MOD_SEL0_6 \
  293. MOD_SEL0_5 \
  294. MOD_SEL0_4 \
  295. MOD_SEL0_3 \
  296. MOD_SEL0_2 \
  297. MOD_SEL0_1 \
  298. MOD_SEL0_0
  299. enum {
  300. PINMUX_RESERVED = 0,
  301. PINMUX_DATA_BEGIN,
  302. GP_ALL(DATA),
  303. PINMUX_DATA_END,
  304. #define F_(x, y)
  305. #define FM(x) FN_##x,
  306. PINMUX_FUNCTION_BEGIN,
  307. GP_ALL(FN),
  308. PINMUX_GPSR
  309. PINMUX_IPSR
  310. PINMUX_MOD_SELS
  311. PINMUX_FUNCTION_END,
  312. #undef F_
  313. #undef FM
  314. #define F_(x, y)
  315. #define FM(x) x##_MARK,
  316. PINMUX_MARK_BEGIN,
  317. PINMUX_GPSR
  318. PINMUX_IPSR
  319. PINMUX_MOD_SELS
  320. PINMUX_MARK_END,
  321. #undef F_
  322. #undef FM
  323. };
  324. static const u16 pinmux_data[] = {
  325. PINMUX_DATA_GP_ALL(),
  326. PINMUX_SINGLE(AVB0_RX_CTL),
  327. PINMUX_SINGLE(AVB0_RXC),
  328. PINMUX_SINGLE(AVB0_RD0),
  329. PINMUX_SINGLE(AVB0_RD1),
  330. PINMUX_SINGLE(AVB0_RD2),
  331. PINMUX_SINGLE(AVB0_RD3),
  332. PINMUX_SINGLE(AVB0_TX_CTL),
  333. PINMUX_SINGLE(AVB0_TXC),
  334. PINMUX_SINGLE(AVB0_TD0),
  335. PINMUX_SINGLE(AVB0_TD1),
  336. PINMUX_SINGLE(AVB0_TD2),
  337. PINMUX_SINGLE(AVB0_TD3),
  338. PINMUX_SINGLE(AVB0_TXCREFCLK),
  339. PINMUX_SINGLE(AVB0_MDIO),
  340. PINMUX_SINGLE(AVB0_MDC),
  341. PINMUX_SINGLE(AVB0_MAGIC),
  342. PINMUX_SINGLE(AVB0_PHY_INT),
  343. PINMUX_SINGLE(AVB0_LINK),
  344. PINMUX_SINGLE(AVB0_AVTP_MATCH),
  345. PINMUX_SINGLE(QSPI0_SPCLK),
  346. PINMUX_SINGLE(QSPI0_MOSI_IO0),
  347. PINMUX_SINGLE(QSPI0_MISO_IO1),
  348. PINMUX_SINGLE(QSPI0_IO2),
  349. PINMUX_SINGLE(QSPI0_IO3),
  350. PINMUX_SINGLE(QSPI0_SSL),
  351. PINMUX_SINGLE(QSPI1_SPCLK),
  352. PINMUX_SINGLE(QSPI1_MOSI_IO0),
  353. PINMUX_SINGLE(QSPI1_MISO_IO1),
  354. PINMUX_SINGLE(QSPI1_IO2),
  355. PINMUX_SINGLE(QSPI1_IO3),
  356. PINMUX_SINGLE(QSPI1_SSL),
  357. PINMUX_SINGLE(RPC_RESET_N),
  358. PINMUX_SINGLE(RPC_WP_N),
  359. PINMUX_SINGLE(RPC_INT_N),
  360. /* IPSR0 */
  361. PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
  362. PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
  363. PINMUX_IPSR_GPSR(IP0_3_0, A0),
  364. PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
  365. PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
  366. PINMUX_IPSR_GPSR(IP0_7_4, A1),
  367. PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
  368. PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
  369. PINMUX_IPSR_GPSR(IP0_11_8, A2),
  370. PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
  371. PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
  372. PINMUX_IPSR_GPSR(IP0_15_12, A3),
  373. PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
  374. PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
  375. PINMUX_IPSR_GPSR(IP0_19_16, A4),
  376. PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
  377. PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
  378. PINMUX_IPSR_GPSR(IP0_23_20, A5),
  379. PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
  380. PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
  381. PINMUX_IPSR_GPSR(IP0_27_24, A6),
  382. PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
  383. PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
  384. PINMUX_IPSR_GPSR(IP0_31_28, A7),
  385. PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
  386. /* IPSR1 */
  387. PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
  388. PINMUX_IPSR_GPSR(IP1_3_0, A8),
  389. PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
  390. PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
  391. PINMUX_IPSR_GPSR(IP1_7_4, A9),
  392. PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
  393. PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
  394. PINMUX_IPSR_GPSR(IP1_11_8, A10),
  395. PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
  396. PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
  397. PINMUX_IPSR_GPSR(IP1_15_12, A11),
  398. PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
  399. PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
  400. PINMUX_IPSR_GPSR(IP1_19_16, A12),
  401. PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
  402. PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
  403. PINMUX_IPSR_GPSR(IP1_23_20, A13),
  404. PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
  405. PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
  406. PINMUX_IPSR_GPSR(IP1_27_24, A14),
  407. PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
  408. PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
  409. PINMUX_IPSR_GPSR(IP1_31_28, A15),
  410. PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
  411. /* IPSR2 */
  412. PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
  413. PINMUX_IPSR_GPSR(IP2_3_0, A16),
  414. PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
  415. PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
  416. PINMUX_IPSR_GPSR(IP2_7_4, A17),
  417. PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
  418. PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
  419. PINMUX_IPSR_GPSR(IP2_11_8, A18),
  420. PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
  421. PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
  422. PINMUX_IPSR_GPSR(IP2_15_12, A19),
  423. PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
  424. PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
  425. PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
  426. PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
  427. PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
  428. PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
  429. PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
  430. PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
  431. PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
  432. PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
  433. /* IPSR3 */
  434. PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
  435. PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
  436. PINMUX_IPSR_GPSR(IP3_3_0, RX3),
  437. PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
  438. PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
  439. PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
  440. PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
  441. PINMUX_IPSR_GPSR(IP3_7_4, TX3),
  442. PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
  443. PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
  444. PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
  445. PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
  446. PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
  447. PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
  448. PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
  449. PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
  450. PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
  451. PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
  452. PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
  453. PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
  454. PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
  455. PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
  456. PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
  457. PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
  458. PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
  459. PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
  460. PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
  461. PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
  462. PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
  463. PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
  464. /* IPSR4 */
  465. PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
  466. PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
  467. PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
  468. PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
  469. PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
  470. PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
  471. PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
  472. PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
  473. PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
  474. PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
  475. PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
  476. PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
  477. PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
  478. PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
  479. PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
  480. PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
  481. PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
  482. PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
  483. PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
  484. PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
  485. PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
  486. PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
  487. PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
  488. PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
  489. PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
  490. PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
  491. PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
  492. PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
  493. PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
  494. /* IPSR5 */
  495. PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
  496. PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
  497. PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
  498. PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
  499. PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
  500. PINMUX_IPSR_GPSR(IP5_7_4, D0),
  501. PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
  502. PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
  503. PINMUX_IPSR_GPSR(IP5_11_8, D1),
  504. PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
  505. PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
  506. PINMUX_IPSR_GPSR(IP5_15_12, D2),
  507. PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
  508. PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
  509. PINMUX_IPSR_GPSR(IP5_19_16, D3),
  510. PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
  511. PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
  512. PINMUX_IPSR_GPSR(IP5_23_20, D4),
  513. PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
  514. PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
  515. PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
  516. PINMUX_IPSR_GPSR(IP5_27_24, D5),
  517. PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
  518. PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
  519. PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
  520. PINMUX_IPSR_GPSR(IP5_31_28, D6),
  521. PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
  522. /* IPSR6 */
  523. PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
  524. PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
  525. PINMUX_IPSR_GPSR(IP6_3_0, D7),
  526. PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
  527. PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
  528. PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
  529. PINMUX_IPSR_GPSR(IP6_7_4, D8),
  530. PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
  531. PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
  532. PINMUX_IPSR_GPSR(IP6_11_8, RX4),
  533. PINMUX_IPSR_GPSR(IP6_11_8, D9),
  534. PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
  535. PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
  536. PINMUX_IPSR_GPSR(IP6_15_12, TX4),
  537. PINMUX_IPSR_GPSR(IP6_15_12, D10),
  538. PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
  539. PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
  540. PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
  541. PINMUX_IPSR_GPSR(IP6_19_16, D11),
  542. PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
  543. PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
  544. PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
  545. PINMUX_IPSR_GPSR(IP6_23_20, D12),
  546. PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
  547. PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
  548. PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
  549. PINMUX_IPSR_GPSR(IP6_27_24, D13),
  550. PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
  551. PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
  552. PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
  553. PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
  554. PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
  555. PINMUX_IPSR_GPSR(IP6_31_28, D14),
  556. /* IPSR7 */
  557. PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
  558. PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
  559. PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
  560. PINMUX_IPSR_GPSR(IP7_3_0, D15),
  561. PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
  562. PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
  563. PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
  564. PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
  565. PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
  566. PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
  567. PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
  568. PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
  569. PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
  570. PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
  571. PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
  572. PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
  573. PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
  574. PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
  575. PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
  576. PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
  577. PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
  578. PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
  579. PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
  580. PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
  581. PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
  582. PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
  583. PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
  584. PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
  585. PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
  586. PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
  587. PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
  588. PINMUX_IPSR_GPSR(IP7_23_20, RX0),
  589. PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
  590. PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
  591. PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
  592. PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
  593. PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
  594. PINMUX_IPSR_GPSR(IP7_27_24, TX0),
  595. PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
  596. PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
  597. PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
  598. /* IPSR8 */
  599. PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
  600. PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
  601. PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
  602. PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
  603. PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
  604. PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
  605. PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
  606. PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
  607. PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
  608. PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
  609. PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
  610. PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
  611. PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
  612. PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
  613. PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
  614. PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
  615. PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
  616. PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
  617. PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
  618. PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
  619. PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
  620. PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
  621. PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
  622. PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
  623. PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
  624. PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
  625. PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
  626. PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
  627. };
  628. static const struct sh_pfc_pin pinmux_pins[] = {
  629. PINMUX_GPIO_GP_ALL(),
  630. };
  631. /* - AVB0 ------------------------------------------------------------------- */
  632. static const unsigned int avb0_link_pins[] = {
  633. /* AVB0_LINK */
  634. RCAR_GP_PIN(1, 18),
  635. };
  636. static const unsigned int avb0_link_mux[] = {
  637. AVB0_LINK_MARK,
  638. };
  639. static const unsigned int avb0_magic_pins[] = {
  640. /* AVB0_MAGIC */
  641. RCAR_GP_PIN(1, 16),
  642. };
  643. static const unsigned int avb0_magic_mux[] = {
  644. AVB0_MAGIC_MARK,
  645. };
  646. static const unsigned int avb0_phy_int_pins[] = {
  647. /* AVB0_PHY_INT */
  648. RCAR_GP_PIN(1, 17),
  649. };
  650. static const unsigned int avb0_phy_int_mux[] = {
  651. AVB0_PHY_INT_MARK,
  652. };
  653. static const unsigned int avb0_mdio_pins[] = {
  654. /* AVB0_MDC, AVB0_MDIO */
  655. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
  656. };
  657. static const unsigned int avb0_mdio_mux[] = {
  658. AVB0_MDC_MARK, AVB0_MDIO_MARK,
  659. };
  660. static const unsigned int avb0_rgmii_pins[] = {
  661. /*
  662. * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
  663. * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
  664. */
  665. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
  666. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
  667. RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
  668. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
  669. RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
  670. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  671. };
  672. static const unsigned int avb0_rgmii_mux[] = {
  673. AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
  674. AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
  675. AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
  676. AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
  677. };
  678. static const unsigned int avb0_txcrefclk_pins[] = {
  679. /* AVB0_TXCREFCLK */
  680. RCAR_GP_PIN(1, 13),
  681. };
  682. static const unsigned int avb0_txcrefclk_mux[] = {
  683. AVB0_TXCREFCLK_MARK,
  684. };
  685. static const unsigned int avb0_avtp_pps_pins[] = {
  686. /* AVB0_AVTP_PPS */
  687. RCAR_GP_PIN(2, 6),
  688. };
  689. static const unsigned int avb0_avtp_pps_mux[] = {
  690. AVB0_AVTP_PPS_MARK,
  691. };
  692. static const unsigned int avb0_avtp_capture_pins[] = {
  693. /* AVB0_AVTP_CAPTURE */
  694. RCAR_GP_PIN(1, 20),
  695. };
  696. static const unsigned int avb0_avtp_capture_mux[] = {
  697. AVB0_AVTP_CAPTURE_MARK,
  698. };
  699. static const unsigned int avb0_avtp_match_pins[] = {
  700. /* AVB0_AVTP_MATCH */
  701. RCAR_GP_PIN(1, 19),
  702. };
  703. static const unsigned int avb0_avtp_match_mux[] = {
  704. AVB0_AVTP_MATCH_MARK,
  705. };
  706. /* - CANFD Clock ------------------------------------------------------------ */
  707. static const unsigned int canfd_clk_a_pins[] = {
  708. /* CANFD_CLK */
  709. RCAR_GP_PIN(1, 25),
  710. };
  711. static const unsigned int canfd_clk_a_mux[] = {
  712. CANFD_CLK_A_MARK,
  713. };
  714. static const unsigned int canfd_clk_b_pins[] = {
  715. /* CANFD_CLK */
  716. RCAR_GP_PIN(3, 8),
  717. };
  718. static const unsigned int canfd_clk_b_mux[] = {
  719. CANFD_CLK_B_MARK,
  720. };
  721. /* - CANFD0 ----------------------------------------------------------------- */
  722. static const unsigned int canfd0_data_a_pins[] = {
  723. /* TX, RX */
  724. RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
  725. };
  726. static const unsigned int canfd0_data_a_mux[] = {
  727. CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
  728. };
  729. static const unsigned int canfd0_data_b_pins[] = {
  730. /* TX, RX */
  731. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  732. };
  733. static const unsigned int canfd0_data_b_mux[] = {
  734. CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
  735. };
  736. /* - CANFD1 ----------------------------------------------------------------- */
  737. static const unsigned int canfd1_data_pins[] = {
  738. /* TX, RX */
  739. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  740. };
  741. static const unsigned int canfd1_data_mux[] = {
  742. CANFD1_TX_MARK, CANFD1_RX_MARK,
  743. };
  744. /* - DU --------------------------------------------------------------------- */
  745. static const unsigned int du_rgb666_pins[] = {
  746. /* R[7:2], G[7:2], B[7:2] */
  747. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
  748. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
  749. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
  750. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
  751. RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
  752. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
  753. };
  754. static const unsigned int du_rgb666_mux[] = {
  755. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
  756. DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
  757. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
  758. DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
  759. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
  760. DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
  761. };
  762. static const unsigned int du_clk_out_pins[] = {
  763. /* DOTCLKOUT */
  764. RCAR_GP_PIN(0, 18),
  765. };
  766. static const unsigned int du_clk_out_mux[] = {
  767. DU_DOTCLKOUT_MARK,
  768. };
  769. static const unsigned int du_sync_pins[] = {
  770. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  771. RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
  772. };
  773. static const unsigned int du_sync_mux[] = {
  774. DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
  775. };
  776. static const unsigned int du_oddf_pins[] = {
  777. /* EXODDF/ODDF/DISP/CDE */
  778. RCAR_GP_PIN(0, 21),
  779. };
  780. static const unsigned int du_oddf_mux[] = {
  781. DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
  782. };
  783. static const unsigned int du_cde_pins[] = {
  784. /* CDE */
  785. RCAR_GP_PIN(1, 22),
  786. };
  787. static const unsigned int du_cde_mux[] = {
  788. DU_CDE_MARK,
  789. };
  790. static const unsigned int du_disp_pins[] = {
  791. /* DISP */
  792. RCAR_GP_PIN(1, 21),
  793. };
  794. static const unsigned int du_disp_mux[] = {
  795. DU_DISP_MARK,
  796. };
  797. /* - HSCIF0 ----------------------------------------------------------------- */
  798. static const unsigned int hscif0_data_pins[] = {
  799. /* HRX, HTX */
  800. RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
  801. };
  802. static const unsigned int hscif0_data_mux[] = {
  803. HRX0_MARK, HTX0_MARK,
  804. };
  805. static const unsigned int hscif0_clk_pins[] = {
  806. /* HSCK */
  807. RCAR_GP_PIN(0, 0),
  808. };
  809. static const unsigned int hscif0_clk_mux[] = {
  810. HSCK0_MARK,
  811. };
  812. static const unsigned int hscif0_ctrl_pins[] = {
  813. /* HRTS#, HCTS# */
  814. RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
  815. };
  816. static const unsigned int hscif0_ctrl_mux[] = {
  817. HRTS0_N_MARK, HCTS0_N_MARK,
  818. };
  819. /* - HSCIF1 ----------------------------------------------------------------- */
  820. static const unsigned int hscif1_data_pins[] = {
  821. /* HRX, HTX */
  822. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  823. };
  824. static const unsigned int hscif1_data_mux[] = {
  825. HRX1_MARK, HTX1_MARK,
  826. };
  827. static const unsigned int hscif1_clk_pins[] = {
  828. /* HSCK */
  829. RCAR_GP_PIN(2, 7),
  830. };
  831. static const unsigned int hscif1_clk_mux[] = {
  832. HSCK1_MARK,
  833. };
  834. static const unsigned int hscif1_ctrl_pins[] = {
  835. /* HRTS#, HCTS# */
  836. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  837. };
  838. static const unsigned int hscif1_ctrl_mux[] = {
  839. HRTS1_N_MARK, HCTS1_N_MARK,
  840. };
  841. /* - HSCIF2 ----------------------------------------------------------------- */
  842. static const unsigned int hscif2_data_pins[] = {
  843. /* HRX, HTX */
  844. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
  845. };
  846. static const unsigned int hscif2_data_mux[] = {
  847. HRX2_MARK, HTX2_MARK,
  848. };
  849. static const unsigned int hscif2_clk_pins[] = {
  850. /* HSCK */
  851. RCAR_GP_PIN(2, 12),
  852. };
  853. static const unsigned int hscif2_clk_mux[] = {
  854. HSCK2_MARK,
  855. };
  856. static const unsigned int hscif2_ctrl_pins[] = {
  857. /* HRTS#, HCTS# */
  858. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  859. };
  860. static const unsigned int hscif2_ctrl_mux[] = {
  861. HRTS2_N_MARK, HCTS2_N_MARK,
  862. };
  863. /* - HSCIF3 ----------------------------------------------------------------- */
  864. static const unsigned int hscif3_data_pins[] = {
  865. /* HRX, HTX */
  866. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
  867. };
  868. static const unsigned int hscif3_data_mux[] = {
  869. HRX3_MARK, HTX3_MARK,
  870. };
  871. static const unsigned int hscif3_clk_pins[] = {
  872. /* HSCK */
  873. RCAR_GP_PIN(2, 0),
  874. };
  875. static const unsigned int hscif3_clk_mux[] = {
  876. HSCK3_MARK,
  877. };
  878. static const unsigned int hscif3_ctrl_pins[] = {
  879. /* HRTS#, HCTS# */
  880. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
  881. };
  882. static const unsigned int hscif3_ctrl_mux[] = {
  883. HRTS3_N_MARK, HCTS3_N_MARK,
  884. };
  885. /* - I2C0 ------------------------------------------------------------------- */
  886. static const unsigned int i2c0_pins[] = {
  887. /* SDA, SCL */
  888. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
  889. };
  890. static const unsigned int i2c0_mux[] = {
  891. SDA0_MARK, SCL0_MARK,
  892. };
  893. /* - I2C1 ------------------------------------------------------------------- */
  894. static const unsigned int i2c1_pins[] = {
  895. /* SDA, SCL */
  896. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  897. };
  898. static const unsigned int i2c1_mux[] = {
  899. SDA1_MARK, SCL1_MARK,
  900. };
  901. /* - I2C2 ------------------------------------------------------------------- */
  902. static const unsigned int i2c2_pins[] = {
  903. /* SDA, SCL */
  904. RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
  905. };
  906. static const unsigned int i2c2_mux[] = {
  907. SDA2_MARK, SCL2_MARK,
  908. };
  909. /* - I2C3 ------------------------------------------------------------------- */
  910. static const unsigned int i2c3_a_pins[] = {
  911. /* SDA, SCL */
  912. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  913. };
  914. static const unsigned int i2c3_a_mux[] = {
  915. SDA3_A_MARK, SCL3_A_MARK,
  916. };
  917. static const unsigned int i2c3_b_pins[] = {
  918. /* SDA, SCL */
  919. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
  920. };
  921. static const unsigned int i2c3_b_mux[] = {
  922. SDA3_B_MARK, SCL3_B_MARK,
  923. };
  924. /* - I2C4 ------------------------------------------------------------------- */
  925. static const unsigned int i2c4_pins[] = {
  926. /* SDA, SCL */
  927. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
  928. };
  929. static const unsigned int i2c4_mux[] = {
  930. SDA4_MARK, SCL4_MARK,
  931. };
  932. /* - INTC-EX ---------------------------------------------------------------- */
  933. static const unsigned int intc_ex_irq0_pins[] = {
  934. /* IRQ0 */
  935. RCAR_GP_PIN(1, 0),
  936. };
  937. static const unsigned int intc_ex_irq0_mux[] = {
  938. IRQ0_MARK,
  939. };
  940. static const unsigned int intc_ex_irq1_pins[] = {
  941. /* IRQ1 */
  942. RCAR_GP_PIN(0, 11),
  943. };
  944. static const unsigned int intc_ex_irq1_mux[] = {
  945. IRQ1_MARK,
  946. };
  947. static const unsigned int intc_ex_irq2_pins[] = {
  948. /* IRQ2 */
  949. RCAR_GP_PIN(0, 12),
  950. };
  951. static const unsigned int intc_ex_irq2_mux[] = {
  952. IRQ2_MARK,
  953. };
  954. static const unsigned int intc_ex_irq3_pins[] = {
  955. /* IRQ3 */
  956. RCAR_GP_PIN(0, 19),
  957. };
  958. static const unsigned int intc_ex_irq3_mux[] = {
  959. IRQ3_MARK,
  960. };
  961. static const unsigned int intc_ex_irq4_pins[] = {
  962. /* IRQ4 */
  963. RCAR_GP_PIN(3, 15),
  964. };
  965. static const unsigned int intc_ex_irq4_mux[] = {
  966. IRQ4_MARK,
  967. };
  968. static const unsigned int intc_ex_irq5_pins[] = {
  969. /* IRQ5 */
  970. RCAR_GP_PIN(3, 16),
  971. };
  972. static const unsigned int intc_ex_irq5_mux[] = {
  973. IRQ5_MARK,
  974. };
  975. /* - MMC -------------------------------------------------------------------- */
  976. static const unsigned int mmc_data1_pins[] = {
  977. /* D0 */
  978. RCAR_GP_PIN(3, 6),
  979. };
  980. static const unsigned int mmc_data1_mux[] = {
  981. MMC_D0_MARK,
  982. };
  983. static const unsigned int mmc_data4_pins[] = {
  984. /* D[0:3] */
  985. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  986. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  987. };
  988. static const unsigned int mmc_data4_mux[] = {
  989. MMC_D0_MARK, MMC_D1_MARK,
  990. MMC_D2_MARK, MMC_D3_MARK,
  991. };
  992. static const unsigned int mmc_data8_pins[] = {
  993. /* D[0:7] */
  994. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  995. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  996. RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  997. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  998. };
  999. static const unsigned int mmc_data8_mux[] = {
  1000. MMC_D0_MARK, MMC_D1_MARK,
  1001. MMC_D2_MARK, MMC_D3_MARK,
  1002. MMC_D4_MARK, MMC_D5_MARK,
  1003. MMC_D6_MARK, MMC_D7_MARK,
  1004. };
  1005. static const unsigned int mmc_ctrl_pins[] = {
  1006. /* CLK, CMD */
  1007. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
  1008. };
  1009. static const unsigned int mmc_ctrl_mux[] = {
  1010. MMC_CLK_MARK, MMC_CMD_MARK,
  1011. };
  1012. /* - MSIOF0 ----------------------------------------------------------------- */
  1013. static const unsigned int msiof0_clk_pins[] = {
  1014. /* SCK */
  1015. RCAR_GP_PIN(4, 2),
  1016. };
  1017. static const unsigned int msiof0_clk_mux[] = {
  1018. MSIOF0_SCK_MARK,
  1019. };
  1020. static const unsigned int msiof0_sync_pins[] = {
  1021. /* SYNC */
  1022. RCAR_GP_PIN(4, 3),
  1023. };
  1024. static const unsigned int msiof0_sync_mux[] = {
  1025. MSIOF0_SYNC_MARK,
  1026. };
  1027. static const unsigned int msiof0_ss1_pins[] = {
  1028. /* SS1 */
  1029. RCAR_GP_PIN(4, 4),
  1030. };
  1031. static const unsigned int msiof0_ss1_mux[] = {
  1032. MSIOF0_SS1_MARK,
  1033. };
  1034. static const unsigned int msiof0_ss2_pins[] = {
  1035. /* SS2 */
  1036. RCAR_GP_PIN(4, 5),
  1037. };
  1038. static const unsigned int msiof0_ss2_mux[] = {
  1039. MSIOF0_SS2_MARK,
  1040. };
  1041. static const unsigned int msiof0_txd_pins[] = {
  1042. /* TXD */
  1043. RCAR_GP_PIN(4, 1),
  1044. };
  1045. static const unsigned int msiof0_txd_mux[] = {
  1046. MSIOF0_TXD_MARK,
  1047. };
  1048. static const unsigned int msiof0_rxd_pins[] = {
  1049. /* RXD */
  1050. RCAR_GP_PIN(4, 0),
  1051. };
  1052. static const unsigned int msiof0_rxd_mux[] = {
  1053. MSIOF0_RXD_MARK,
  1054. };
  1055. /* - MSIOF1 ----------------------------------------------------------------- */
  1056. static const unsigned int msiof1_clk_pins[] = {
  1057. /* SCK */
  1058. RCAR_GP_PIN(3, 2),
  1059. };
  1060. static const unsigned int msiof1_clk_mux[] = {
  1061. MSIOF1_SCK_MARK,
  1062. };
  1063. static const unsigned int msiof1_sync_pins[] = {
  1064. /* SYNC */
  1065. RCAR_GP_PIN(3, 3),
  1066. };
  1067. static const unsigned int msiof1_sync_mux[] = {
  1068. MSIOF1_SYNC_MARK,
  1069. };
  1070. static const unsigned int msiof1_ss1_pins[] = {
  1071. /* SS1 */
  1072. RCAR_GP_PIN(3, 4),
  1073. };
  1074. static const unsigned int msiof1_ss1_mux[] = {
  1075. MSIOF1_SS1_MARK,
  1076. };
  1077. static const unsigned int msiof1_ss2_pins[] = {
  1078. /* SS2 */
  1079. RCAR_GP_PIN(3, 5),
  1080. };
  1081. static const unsigned int msiof1_ss2_mux[] = {
  1082. MSIOF1_SS2_MARK,
  1083. };
  1084. static const unsigned int msiof1_txd_pins[] = {
  1085. /* TXD */
  1086. RCAR_GP_PIN(3, 1),
  1087. };
  1088. static const unsigned int msiof1_txd_mux[] = {
  1089. MSIOF1_TXD_MARK,
  1090. };
  1091. static const unsigned int msiof1_rxd_pins[] = {
  1092. /* RXD */
  1093. RCAR_GP_PIN(3, 0),
  1094. };
  1095. static const unsigned int msiof1_rxd_mux[] = {
  1096. MSIOF1_RXD_MARK,
  1097. };
  1098. /* - MSIOF2 ----------------------------------------------------------------- */
  1099. static const unsigned int msiof2_clk_pins[] = {
  1100. /* SCK */
  1101. RCAR_GP_PIN(2, 0),
  1102. };
  1103. static const unsigned int msiof2_clk_mux[] = {
  1104. MSIOF2_SCK_MARK,
  1105. };
  1106. static const unsigned int msiof2_sync_pins[] = {
  1107. /* SYNC */
  1108. RCAR_GP_PIN(2, 3),
  1109. };
  1110. static const unsigned int msiof2_sync_mux[] = {
  1111. MSIOF2_SYNC_MARK,
  1112. };
  1113. static const unsigned int msiof2_ss1_pins[] = {
  1114. /* SS1 */
  1115. RCAR_GP_PIN(2, 4),
  1116. };
  1117. static const unsigned int msiof2_ss1_mux[] = {
  1118. MSIOF2_SS1_MARK,
  1119. };
  1120. static const unsigned int msiof2_ss2_pins[] = {
  1121. /* SS2 */
  1122. RCAR_GP_PIN(2, 5),
  1123. };
  1124. static const unsigned int msiof2_ss2_mux[] = {
  1125. MSIOF2_SS2_MARK,
  1126. };
  1127. static const unsigned int msiof2_txd_pins[] = {
  1128. /* TXD */
  1129. RCAR_GP_PIN(2, 2),
  1130. };
  1131. static const unsigned int msiof2_txd_mux[] = {
  1132. MSIOF2_TXD_MARK,
  1133. };
  1134. static const unsigned int msiof2_rxd_pins[] = {
  1135. /* RXD */
  1136. RCAR_GP_PIN(2, 1),
  1137. };
  1138. static const unsigned int msiof2_rxd_mux[] = {
  1139. MSIOF2_RXD_MARK,
  1140. };
  1141. /* - MSIOF3 ----------------------------------------------------------------- */
  1142. static const unsigned int msiof3_clk_pins[] = {
  1143. /* SCK */
  1144. RCAR_GP_PIN(0, 20),
  1145. };
  1146. static const unsigned int msiof3_clk_mux[] = {
  1147. MSIOF3_SCK_MARK,
  1148. };
  1149. static const unsigned int msiof3_sync_pins[] = {
  1150. /* SYNC */
  1151. RCAR_GP_PIN(0, 21),
  1152. };
  1153. static const unsigned int msiof3_sync_mux[] = {
  1154. MSIOF3_SYNC_MARK,
  1155. };
  1156. static const unsigned int msiof3_ss1_pins[] = {
  1157. /* SS1 */
  1158. RCAR_GP_PIN(0, 6),
  1159. };
  1160. static const unsigned int msiof3_ss1_mux[] = {
  1161. MSIOF3_SS1_MARK,
  1162. };
  1163. static const unsigned int msiof3_ss2_pins[] = {
  1164. /* SS2 */
  1165. RCAR_GP_PIN(0, 7),
  1166. };
  1167. static const unsigned int msiof3_ss2_mux[] = {
  1168. MSIOF3_SS2_MARK,
  1169. };
  1170. static const unsigned int msiof3_txd_pins[] = {
  1171. /* TXD */
  1172. RCAR_GP_PIN(0, 5),
  1173. };
  1174. static const unsigned int msiof3_txd_mux[] = {
  1175. MSIOF3_TXD_MARK,
  1176. };
  1177. static const unsigned int msiof3_rxd_pins[] = {
  1178. /* RXD */
  1179. RCAR_GP_PIN(0, 4),
  1180. };
  1181. static const unsigned int msiof3_rxd_mux[] = {
  1182. MSIOF3_RXD_MARK,
  1183. };
  1184. /* - PWM0 ------------------------------------------------------------------- */
  1185. static const unsigned int pwm0_a_pins[] = {
  1186. RCAR_GP_PIN(2, 12),
  1187. };
  1188. static const unsigned int pwm0_a_mux[] = {
  1189. PWM0_A_MARK,
  1190. };
  1191. static const unsigned int pwm0_b_pins[] = {
  1192. RCAR_GP_PIN(1, 21),
  1193. };
  1194. static const unsigned int pwm0_b_mux[] = {
  1195. PWM0_B_MARK,
  1196. };
  1197. /* - PWM1 ------------------------------------------------------------------- */
  1198. static const unsigned int pwm1_a_pins[] = {
  1199. RCAR_GP_PIN(2, 13),
  1200. };
  1201. static const unsigned int pwm1_a_mux[] = {
  1202. PWM1_A_MARK,
  1203. };
  1204. static const unsigned int pwm1_b_pins[] = {
  1205. RCAR_GP_PIN(1, 22),
  1206. };
  1207. static const unsigned int pwm1_b_mux[] = {
  1208. PWM1_B_MARK,
  1209. };
  1210. /* - PWM2 ------------------------------------------------------------------- */
  1211. static const unsigned int pwm2_a_pins[] = {
  1212. RCAR_GP_PIN(2, 14),
  1213. };
  1214. static const unsigned int pwm2_a_mux[] = {
  1215. PWM2_A_MARK,
  1216. };
  1217. static const unsigned int pwm2_b_pins[] = {
  1218. RCAR_GP_PIN(1, 23),
  1219. };
  1220. static const unsigned int pwm2_b_mux[] = {
  1221. PWM2_B_MARK,
  1222. };
  1223. /* - PWM3 ------------------------------------------------------------------- */
  1224. static const unsigned int pwm3_a_pins[] = {
  1225. RCAR_GP_PIN(2, 15),
  1226. };
  1227. static const unsigned int pwm3_a_mux[] = {
  1228. PWM3_A_MARK,
  1229. };
  1230. static const unsigned int pwm3_b_pins[] = {
  1231. RCAR_GP_PIN(1, 24),
  1232. };
  1233. static const unsigned int pwm3_b_mux[] = {
  1234. PWM3_B_MARK,
  1235. };
  1236. /* - PWM4 ------------------------------------------------------------------- */
  1237. static const unsigned int pwm4_a_pins[] = {
  1238. RCAR_GP_PIN(2, 16),
  1239. };
  1240. static const unsigned int pwm4_a_mux[] = {
  1241. PWM4_A_MARK,
  1242. };
  1243. static const unsigned int pwm4_b_pins[] = {
  1244. RCAR_GP_PIN(1, 25),
  1245. };
  1246. static const unsigned int pwm4_b_mux[] = {
  1247. PWM4_B_MARK,
  1248. };
  1249. /* - QSPI0 ------------------------------------------------------------------ */
  1250. static const unsigned int qspi0_ctrl_pins[] = {
  1251. /* SPCLK, SSL */
  1252. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
  1253. };
  1254. static const unsigned int qspi0_ctrl_mux[] = {
  1255. QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
  1256. };
  1257. static const unsigned int qspi0_data2_pins[] = {
  1258. /* MOSI_IO0, MISO_IO1 */
  1259. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1260. };
  1261. static const unsigned int qspi0_data2_mux[] = {
  1262. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  1263. };
  1264. static const unsigned int qspi0_data4_pins[] = {
  1265. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  1266. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1267. RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
  1268. };
  1269. static const unsigned int qspi0_data4_mux[] = {
  1270. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  1271. QSPI0_IO2_MARK, QSPI0_IO3_MARK
  1272. };
  1273. /* - QSPI1 ------------------------------------------------------------------ */
  1274. static const unsigned int qspi1_ctrl_pins[] = {
  1275. /* SPCLK, SSL */
  1276. RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
  1277. };
  1278. static const unsigned int qspi1_ctrl_mux[] = {
  1279. QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
  1280. };
  1281. static const unsigned int qspi1_data2_pins[] = {
  1282. /* MOSI_IO0, MISO_IO1 */
  1283. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  1284. };
  1285. static const unsigned int qspi1_data2_mux[] = {
  1286. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  1287. };
  1288. static const unsigned int qspi1_data4_pins[] = {
  1289. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  1290. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  1291. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
  1292. };
  1293. static const unsigned int qspi1_data4_mux[] = {
  1294. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  1295. QSPI1_IO2_MARK, QSPI1_IO3_MARK
  1296. };
  1297. /* - RPC -------------------------------------------------------------------- */
  1298. static const unsigned int rpc_clk1_pins[] = {
  1299. /* Octal-SPI flash: C/SCLK */
  1300. RCAR_GP_PIN(5, 0),
  1301. };
  1302. static const unsigned int rpc_clk1_mux[] = {
  1303. QSPI0_SPCLK_MARK,
  1304. };
  1305. static const unsigned int rpc_clk2_pins[] = {
  1306. /* HyperFlash: CK, CK# */
  1307. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
  1308. };
  1309. static const unsigned int rpc_clk2_mux[] = {
  1310. QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
  1311. };
  1312. static const unsigned int rpc_ctrl_pins[] = {
  1313. /* Octal-SPI flash: S#/CS, DQS */
  1314. /* HyperFlash: CS#, RDS */
  1315. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
  1316. };
  1317. static const unsigned int rpc_ctrl_mux[] = {
  1318. QSPI0_SSL_MARK, QSPI1_SSL_MARK,
  1319. };
  1320. static const unsigned int rpc_data_pins[] = {
  1321. /* DQ[0:7] */
  1322. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1323. RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
  1324. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  1325. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
  1326. };
  1327. static const unsigned int rpc_data_mux[] = {
  1328. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  1329. QSPI0_IO2_MARK, QSPI0_IO3_MARK,
  1330. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  1331. QSPI1_IO2_MARK, QSPI1_IO3_MARK,
  1332. };
  1333. static const unsigned int rpc_reset_pins[] = {
  1334. /* RPC_RESET# */
  1335. RCAR_GP_PIN(5, 12),
  1336. };
  1337. static const unsigned int rpc_reset_mux[] = {
  1338. RPC_RESET_N_MARK,
  1339. };
  1340. static const unsigned int rpc_int_pins[] = {
  1341. /* RPC_INT# */
  1342. RCAR_GP_PIN(5, 14),
  1343. };
  1344. static const unsigned int rpc_int_mux[] = {
  1345. RPC_INT_N_MARK,
  1346. };
  1347. static const unsigned int rpc_wp_pins[] = {
  1348. /* RPC_WP# */
  1349. RCAR_GP_PIN(5, 13),
  1350. };
  1351. static const unsigned int rpc_wp_mux[] = {
  1352. RPC_WP_N_MARK,
  1353. };
  1354. /* - SCIF Clock ------------------------------------------------------------- */
  1355. static const unsigned int scif_clk_a_pins[] = {
  1356. /* SCIF_CLK */
  1357. RCAR_GP_PIN(0, 18),
  1358. };
  1359. static const unsigned int scif_clk_a_mux[] = {
  1360. SCIF_CLK_A_MARK,
  1361. };
  1362. static const unsigned int scif_clk_b_pins[] = {
  1363. /* SCIF_CLK */
  1364. RCAR_GP_PIN(1, 25),
  1365. };
  1366. static const unsigned int scif_clk_b_mux[] = {
  1367. SCIF_CLK_B_MARK,
  1368. };
  1369. /* - SCIF0 ------------------------------------------------------------------ */
  1370. static const unsigned int scif0_data_pins[] = {
  1371. /* RX, TX */
  1372. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1373. };
  1374. static const unsigned int scif0_data_mux[] = {
  1375. RX0_MARK, TX0_MARK,
  1376. };
  1377. static const unsigned int scif0_clk_pins[] = {
  1378. /* SCK */
  1379. RCAR_GP_PIN(4, 1),
  1380. };
  1381. static const unsigned int scif0_clk_mux[] = {
  1382. SCK0_MARK,
  1383. };
  1384. static const unsigned int scif0_ctrl_pins[] = {
  1385. /* RTS#, CTS# */
  1386. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1387. };
  1388. static const unsigned int scif0_ctrl_mux[] = {
  1389. RTS0_N_MARK, CTS0_N_MARK,
  1390. };
  1391. /* - SCIF1 ------------------------------------------------------------------ */
  1392. static const unsigned int scif1_data_a_pins[] = {
  1393. /* RX, TX */
  1394. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1395. };
  1396. static const unsigned int scif1_data_a_mux[] = {
  1397. RX1_A_MARK, TX1_A_MARK,
  1398. };
  1399. static const unsigned int scif1_clk_pins[] = {
  1400. /* SCK */
  1401. RCAR_GP_PIN(2, 5),
  1402. };
  1403. static const unsigned int scif1_clk_mux[] = {
  1404. SCK1_MARK,
  1405. };
  1406. static const unsigned int scif1_ctrl_pins[] = {
  1407. /* RTS#, CTS# */
  1408. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1409. };
  1410. static const unsigned int scif1_ctrl_mux[] = {
  1411. RTS1_N_MARK, CTS1_N_MARK,
  1412. };
  1413. static const unsigned int scif1_data_b_pins[] = {
  1414. /* RX, TX */
  1415. RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
  1416. };
  1417. static const unsigned int scif1_data_b_mux[] = {
  1418. RX1_B_MARK, TX1_B_MARK,
  1419. };
  1420. /* - SCIF3 ------------------------------------------------------------------ */
  1421. static const unsigned int scif3_data_pins[] = {
  1422. /* RX, TX */
  1423. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
  1424. };
  1425. static const unsigned int scif3_data_mux[] = {
  1426. RX3_MARK, TX3_MARK,
  1427. };
  1428. static const unsigned int scif3_clk_pins[] = {
  1429. /* SCK */
  1430. RCAR_GP_PIN(2, 0),
  1431. };
  1432. static const unsigned int scif3_clk_mux[] = {
  1433. SCK3_MARK,
  1434. };
  1435. static const unsigned int scif3_ctrl_pins[] = {
  1436. /* RTS#, CTS# */
  1437. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
  1438. };
  1439. static const unsigned int scif3_ctrl_mux[] = {
  1440. RTS3_N_MARK, CTS3_N_MARK,
  1441. };
  1442. /* - SCIF4 ------------------------------------------------------------------ */
  1443. static const unsigned int scif4_data_pins[] = {
  1444. /* RX, TX */
  1445. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  1446. };
  1447. static const unsigned int scif4_data_mux[] = {
  1448. RX4_MARK, TX4_MARK,
  1449. };
  1450. static const unsigned int scif4_clk_pins[] = {
  1451. /* SCK */
  1452. RCAR_GP_PIN(3, 9),
  1453. };
  1454. static const unsigned int scif4_clk_mux[] = {
  1455. SCK4_MARK,
  1456. };
  1457. static const unsigned int scif4_ctrl_pins[] = {
  1458. /* RTS#, CTS# */
  1459. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
  1460. };
  1461. static const unsigned int scif4_ctrl_mux[] = {
  1462. RTS4_N_MARK, CTS4_N_MARK,
  1463. };
  1464. /* - TMU -------------------------------------------------------------------- */
  1465. static const unsigned int tmu_tclk1_a_pins[] = {
  1466. /* TCLK1 */
  1467. RCAR_GP_PIN(4, 4),
  1468. };
  1469. static const unsigned int tmu_tclk1_a_mux[] = {
  1470. TCLK1_A_MARK,
  1471. };
  1472. static const unsigned int tmu_tclk1_b_pins[] = {
  1473. /* TCLK1 */
  1474. RCAR_GP_PIN(1, 23),
  1475. };
  1476. static const unsigned int tmu_tclk1_b_mux[] = {
  1477. TCLK1_B_MARK,
  1478. };
  1479. static const unsigned int tmu_tclk2_a_pins[] = {
  1480. /* TCLK2 */
  1481. RCAR_GP_PIN(4, 5),
  1482. };
  1483. static const unsigned int tmu_tclk2_a_mux[] = {
  1484. TCLK2_A_MARK,
  1485. };
  1486. static const unsigned int tmu_tclk2_b_pins[] = {
  1487. /* TCLK2 */
  1488. RCAR_GP_PIN(1, 24),
  1489. };
  1490. static const unsigned int tmu_tclk2_b_mux[] = {
  1491. TCLK2_B_MARK,
  1492. };
  1493. /* - VIN0 ------------------------------------------------------------------- */
  1494. static const union vin_data12 vin0_data_pins = {
  1495. .data12 = {
  1496. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
  1497. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  1498. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1499. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  1500. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
  1501. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
  1502. },
  1503. };
  1504. static const union vin_data12 vin0_data_mux = {
  1505. .data12 = {
  1506. VI0_DATA0_MARK, VI0_DATA1_MARK,
  1507. VI0_DATA2_MARK, VI0_DATA3_MARK,
  1508. VI0_DATA4_MARK, VI0_DATA5_MARK,
  1509. VI0_DATA6_MARK, VI0_DATA7_MARK,
  1510. VI0_DATA8_MARK, VI0_DATA9_MARK,
  1511. VI0_DATA10_MARK, VI0_DATA11_MARK,
  1512. },
  1513. };
  1514. static const unsigned int vin0_sync_pins[] = {
  1515. /* HSYNC#, VSYNC# */
  1516. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
  1517. };
  1518. static const unsigned int vin0_sync_mux[] = {
  1519. VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
  1520. };
  1521. static const unsigned int vin0_field_pins[] = {
  1522. /* FIELD */
  1523. RCAR_GP_PIN(2, 16),
  1524. };
  1525. static const unsigned int vin0_field_mux[] = {
  1526. VI0_FIELD_MARK,
  1527. };
  1528. static const unsigned int vin0_clkenb_pins[] = {
  1529. /* CLKENB */
  1530. RCAR_GP_PIN(2, 1),
  1531. };
  1532. static const unsigned int vin0_clkenb_mux[] = {
  1533. VI0_CLKENB_MARK,
  1534. };
  1535. static const unsigned int vin0_clk_pins[] = {
  1536. /* CLK */
  1537. RCAR_GP_PIN(2, 0),
  1538. };
  1539. static const unsigned int vin0_clk_mux[] = {
  1540. VI0_CLK_MARK,
  1541. };
  1542. /* - VIN1 ------------------------------------------------------------------- */
  1543. static const union vin_data12 vin1_data_pins = {
  1544. .data12 = {
  1545. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  1546. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  1547. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1548. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  1549. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
  1550. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  1551. },
  1552. };
  1553. static const union vin_data12 vin1_data_mux = {
  1554. .data12 = {
  1555. VI1_DATA0_MARK, VI1_DATA1_MARK,
  1556. VI1_DATA2_MARK, VI1_DATA3_MARK,
  1557. VI1_DATA4_MARK, VI1_DATA5_MARK,
  1558. VI1_DATA6_MARK, VI1_DATA7_MARK,
  1559. VI1_DATA8_MARK, VI1_DATA9_MARK,
  1560. VI1_DATA10_MARK, VI1_DATA11_MARK,
  1561. },
  1562. };
  1563. static const unsigned int vin1_sync_pins[] = {
  1564. /* HSYNC#, VSYNC# */
  1565. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  1566. };
  1567. static const unsigned int vin1_sync_mux[] = {
  1568. VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
  1569. };
  1570. static const unsigned int vin1_field_pins[] = {
  1571. RCAR_GP_PIN(3, 16),
  1572. };
  1573. static const unsigned int vin1_field_mux[] = {
  1574. /* FIELD */
  1575. VI1_FIELD_MARK,
  1576. };
  1577. static const unsigned int vin1_clkenb_pins[] = {
  1578. RCAR_GP_PIN(3, 1),
  1579. };
  1580. static const unsigned int vin1_clkenb_mux[] = {
  1581. /* CLKENB */
  1582. VI1_CLKENB_MARK,
  1583. };
  1584. static const unsigned int vin1_clk_pins[] = {
  1585. RCAR_GP_PIN(3, 0),
  1586. };
  1587. static const unsigned int vin1_clk_mux[] = {
  1588. /* CLK */
  1589. VI1_CLK_MARK,
  1590. };
  1591. static const struct sh_pfc_pin_group pinmux_groups[] = {
  1592. SH_PFC_PIN_GROUP(avb0_link),
  1593. SH_PFC_PIN_GROUP(avb0_magic),
  1594. SH_PFC_PIN_GROUP(avb0_phy_int),
  1595. SH_PFC_PIN_GROUP(avb0_mdio),
  1596. SH_PFC_PIN_GROUP(avb0_rgmii),
  1597. SH_PFC_PIN_GROUP(avb0_txcrefclk),
  1598. SH_PFC_PIN_GROUP(avb0_avtp_pps),
  1599. SH_PFC_PIN_GROUP(avb0_avtp_capture),
  1600. SH_PFC_PIN_GROUP(avb0_avtp_match),
  1601. SH_PFC_PIN_GROUP(canfd_clk_a),
  1602. SH_PFC_PIN_GROUP(canfd_clk_b),
  1603. SH_PFC_PIN_GROUP(canfd0_data_a),
  1604. SH_PFC_PIN_GROUP(canfd0_data_b),
  1605. SH_PFC_PIN_GROUP(canfd1_data),
  1606. SH_PFC_PIN_GROUP(du_rgb666),
  1607. SH_PFC_PIN_GROUP(du_clk_out),
  1608. SH_PFC_PIN_GROUP(du_sync),
  1609. SH_PFC_PIN_GROUP(du_oddf),
  1610. SH_PFC_PIN_GROUP(du_cde),
  1611. SH_PFC_PIN_GROUP(du_disp),
  1612. SH_PFC_PIN_GROUP(hscif0_data),
  1613. SH_PFC_PIN_GROUP(hscif0_clk),
  1614. SH_PFC_PIN_GROUP(hscif0_ctrl),
  1615. SH_PFC_PIN_GROUP(hscif1_data),
  1616. SH_PFC_PIN_GROUP(hscif1_clk),
  1617. SH_PFC_PIN_GROUP(hscif1_ctrl),
  1618. SH_PFC_PIN_GROUP(hscif2_data),
  1619. SH_PFC_PIN_GROUP(hscif2_clk),
  1620. SH_PFC_PIN_GROUP(hscif2_ctrl),
  1621. SH_PFC_PIN_GROUP(hscif3_data),
  1622. SH_PFC_PIN_GROUP(hscif3_clk),
  1623. SH_PFC_PIN_GROUP(hscif3_ctrl),
  1624. SH_PFC_PIN_GROUP(i2c0),
  1625. SH_PFC_PIN_GROUP(i2c1),
  1626. SH_PFC_PIN_GROUP(i2c2),
  1627. SH_PFC_PIN_GROUP(i2c3_a),
  1628. SH_PFC_PIN_GROUP(i2c3_b),
  1629. SH_PFC_PIN_GROUP(i2c4),
  1630. SH_PFC_PIN_GROUP(intc_ex_irq0),
  1631. SH_PFC_PIN_GROUP(intc_ex_irq1),
  1632. SH_PFC_PIN_GROUP(intc_ex_irq2),
  1633. SH_PFC_PIN_GROUP(intc_ex_irq3),
  1634. SH_PFC_PIN_GROUP(intc_ex_irq4),
  1635. SH_PFC_PIN_GROUP(intc_ex_irq5),
  1636. SH_PFC_PIN_GROUP(mmc_data1),
  1637. SH_PFC_PIN_GROUP(mmc_data4),
  1638. SH_PFC_PIN_GROUP(mmc_data8),
  1639. SH_PFC_PIN_GROUP(mmc_ctrl),
  1640. SH_PFC_PIN_GROUP(msiof0_clk),
  1641. SH_PFC_PIN_GROUP(msiof0_sync),
  1642. SH_PFC_PIN_GROUP(msiof0_ss1),
  1643. SH_PFC_PIN_GROUP(msiof0_ss2),
  1644. SH_PFC_PIN_GROUP(msiof0_txd),
  1645. SH_PFC_PIN_GROUP(msiof0_rxd),
  1646. SH_PFC_PIN_GROUP(msiof1_clk),
  1647. SH_PFC_PIN_GROUP(msiof1_sync),
  1648. SH_PFC_PIN_GROUP(msiof1_ss1),
  1649. SH_PFC_PIN_GROUP(msiof1_ss2),
  1650. SH_PFC_PIN_GROUP(msiof1_txd),
  1651. SH_PFC_PIN_GROUP(msiof1_rxd),
  1652. SH_PFC_PIN_GROUP(msiof2_clk),
  1653. SH_PFC_PIN_GROUP(msiof2_sync),
  1654. SH_PFC_PIN_GROUP(msiof2_ss1),
  1655. SH_PFC_PIN_GROUP(msiof2_ss2),
  1656. SH_PFC_PIN_GROUP(msiof2_txd),
  1657. SH_PFC_PIN_GROUP(msiof2_rxd),
  1658. SH_PFC_PIN_GROUP(msiof3_clk),
  1659. SH_PFC_PIN_GROUP(msiof3_sync),
  1660. SH_PFC_PIN_GROUP(msiof3_ss1),
  1661. SH_PFC_PIN_GROUP(msiof3_ss2),
  1662. SH_PFC_PIN_GROUP(msiof3_txd),
  1663. SH_PFC_PIN_GROUP(msiof3_rxd),
  1664. SH_PFC_PIN_GROUP(pwm0_a),
  1665. SH_PFC_PIN_GROUP(pwm0_b),
  1666. SH_PFC_PIN_GROUP(pwm1_a),
  1667. SH_PFC_PIN_GROUP(pwm1_b),
  1668. SH_PFC_PIN_GROUP(pwm2_a),
  1669. SH_PFC_PIN_GROUP(pwm2_b),
  1670. SH_PFC_PIN_GROUP(pwm3_a),
  1671. SH_PFC_PIN_GROUP(pwm3_b),
  1672. SH_PFC_PIN_GROUP(pwm4_a),
  1673. SH_PFC_PIN_GROUP(pwm4_b),
  1674. SH_PFC_PIN_GROUP(qspi0_ctrl),
  1675. SH_PFC_PIN_GROUP(qspi0_data2),
  1676. SH_PFC_PIN_GROUP(qspi0_data4),
  1677. SH_PFC_PIN_GROUP(qspi1_ctrl),
  1678. SH_PFC_PIN_GROUP(qspi1_data2),
  1679. SH_PFC_PIN_GROUP(qspi1_data4),
  1680. SH_PFC_PIN_GROUP(rpc_clk1),
  1681. SH_PFC_PIN_GROUP(rpc_clk2),
  1682. SH_PFC_PIN_GROUP(rpc_ctrl),
  1683. SH_PFC_PIN_GROUP(rpc_data),
  1684. SH_PFC_PIN_GROUP(rpc_reset),
  1685. SH_PFC_PIN_GROUP(rpc_int),
  1686. SH_PFC_PIN_GROUP(rpc_wp),
  1687. SH_PFC_PIN_GROUP(scif_clk_a),
  1688. SH_PFC_PIN_GROUP(scif_clk_b),
  1689. SH_PFC_PIN_GROUP(scif0_data),
  1690. SH_PFC_PIN_GROUP(scif0_clk),
  1691. SH_PFC_PIN_GROUP(scif0_ctrl),
  1692. SH_PFC_PIN_GROUP(scif1_data_a),
  1693. SH_PFC_PIN_GROUP(scif1_clk),
  1694. SH_PFC_PIN_GROUP(scif1_ctrl),
  1695. SH_PFC_PIN_GROUP(scif1_data_b),
  1696. SH_PFC_PIN_GROUP(scif3_data),
  1697. SH_PFC_PIN_GROUP(scif3_clk),
  1698. SH_PFC_PIN_GROUP(scif3_ctrl),
  1699. SH_PFC_PIN_GROUP(scif4_data),
  1700. SH_PFC_PIN_GROUP(scif4_clk),
  1701. SH_PFC_PIN_GROUP(scif4_ctrl),
  1702. SH_PFC_PIN_GROUP(tmu_tclk1_a),
  1703. SH_PFC_PIN_GROUP(tmu_tclk1_b),
  1704. SH_PFC_PIN_GROUP(tmu_tclk2_a),
  1705. SH_PFC_PIN_GROUP(tmu_tclk2_b),
  1706. VIN_DATA_PIN_GROUP(vin0_data, 8),
  1707. VIN_DATA_PIN_GROUP(vin0_data, 10),
  1708. VIN_DATA_PIN_GROUP(vin0_data, 12),
  1709. SH_PFC_PIN_GROUP(vin0_sync),
  1710. SH_PFC_PIN_GROUP(vin0_field),
  1711. SH_PFC_PIN_GROUP(vin0_clkenb),
  1712. SH_PFC_PIN_GROUP(vin0_clk),
  1713. VIN_DATA_PIN_GROUP(vin1_data, 8),
  1714. VIN_DATA_PIN_GROUP(vin1_data, 10),
  1715. VIN_DATA_PIN_GROUP(vin1_data, 12),
  1716. SH_PFC_PIN_GROUP(vin1_sync),
  1717. SH_PFC_PIN_GROUP(vin1_field),
  1718. SH_PFC_PIN_GROUP(vin1_clkenb),
  1719. SH_PFC_PIN_GROUP(vin1_clk),
  1720. };
  1721. static const char * const avb0_groups[] = {
  1722. "avb0_link",
  1723. "avb0_magic",
  1724. "avb0_phy_int",
  1725. "avb0_mdio",
  1726. "avb0_rgmii",
  1727. "avb0_txcrefclk",
  1728. "avb0_avtp_pps",
  1729. "avb0_avtp_capture",
  1730. "avb0_avtp_match",
  1731. };
  1732. static const char * const canfd_clk_groups[] = {
  1733. "canfd_clk_a",
  1734. "canfd_clk_b",
  1735. };
  1736. static const char * const canfd0_groups[] = {
  1737. "canfd0_data_a",
  1738. "canfd0_data_b",
  1739. };
  1740. static const char * const canfd1_groups[] = {
  1741. "canfd1_data",
  1742. };
  1743. static const char * const du_groups[] = {
  1744. "du_rgb666",
  1745. "du_clk_out",
  1746. "du_sync",
  1747. "du_oddf",
  1748. "du_cde",
  1749. "du_disp",
  1750. };
  1751. static const char * const hscif0_groups[] = {
  1752. "hscif0_data",
  1753. "hscif0_clk",
  1754. "hscif0_ctrl",
  1755. };
  1756. static const char * const hscif1_groups[] = {
  1757. "hscif1_data",
  1758. "hscif1_clk",
  1759. "hscif1_ctrl",
  1760. };
  1761. static const char * const hscif2_groups[] = {
  1762. "hscif2_data",
  1763. "hscif2_clk",
  1764. "hscif2_ctrl",
  1765. };
  1766. static const char * const hscif3_groups[] = {
  1767. "hscif3_data",
  1768. "hscif3_clk",
  1769. "hscif3_ctrl",
  1770. };
  1771. static const char * const i2c0_groups[] = {
  1772. "i2c0",
  1773. };
  1774. static const char * const i2c1_groups[] = {
  1775. "i2c1",
  1776. };
  1777. static const char * const i2c2_groups[] = {
  1778. "i2c2",
  1779. };
  1780. static const char * const i2c3_groups[] = {
  1781. "i2c3_a",
  1782. "i2c3_b",
  1783. };
  1784. static const char * const i2c4_groups[] = {
  1785. "i2c4",
  1786. };
  1787. static const char * const intc_ex_groups[] = {
  1788. "intc_ex_irq0",
  1789. "intc_ex_irq1",
  1790. "intc_ex_irq2",
  1791. "intc_ex_irq3",
  1792. "intc_ex_irq4",
  1793. "intc_ex_irq5",
  1794. };
  1795. static const char * const mmc_groups[] = {
  1796. "mmc_data1",
  1797. "mmc_data4",
  1798. "mmc_data8",
  1799. "mmc_ctrl",
  1800. };
  1801. static const char * const msiof0_groups[] = {
  1802. "msiof0_clk",
  1803. "msiof0_sync",
  1804. "msiof0_ss1",
  1805. "msiof0_ss2",
  1806. "msiof0_txd",
  1807. "msiof0_rxd",
  1808. };
  1809. static const char * const msiof1_groups[] = {
  1810. "msiof1_clk",
  1811. "msiof1_sync",
  1812. "msiof1_ss1",
  1813. "msiof1_ss2",
  1814. "msiof1_txd",
  1815. "msiof1_rxd",
  1816. };
  1817. static const char * const msiof2_groups[] = {
  1818. "msiof2_clk",
  1819. "msiof2_sync",
  1820. "msiof2_ss1",
  1821. "msiof2_ss2",
  1822. "msiof2_txd",
  1823. "msiof2_rxd",
  1824. };
  1825. static const char * const msiof3_groups[] = {
  1826. "msiof3_clk",
  1827. "msiof3_sync",
  1828. "msiof3_ss1",
  1829. "msiof3_ss2",
  1830. "msiof3_txd",
  1831. "msiof3_rxd",
  1832. };
  1833. static const char * const pwm0_groups[] = {
  1834. "pwm0_a",
  1835. "pwm0_b",
  1836. };
  1837. static const char * const pwm1_groups[] = {
  1838. "pwm1_a",
  1839. "pwm1_b",
  1840. };
  1841. static const char * const pwm2_groups[] = {
  1842. "pwm2_a",
  1843. "pwm2_b",
  1844. };
  1845. static const char * const pwm3_groups[] = {
  1846. "pwm3_a",
  1847. "pwm3_b",
  1848. };
  1849. static const char * const pwm4_groups[] = {
  1850. "pwm4_a",
  1851. "pwm4_b",
  1852. };
  1853. static const char * const qspi0_groups[] = {
  1854. "qspi0_ctrl",
  1855. "qspi0_data2",
  1856. "qspi0_data4",
  1857. };
  1858. static const char * const qspi1_groups[] = {
  1859. "qspi1_ctrl",
  1860. "qspi1_data2",
  1861. "qspi1_data4",
  1862. };
  1863. static const char * const rpc_groups[] = {
  1864. "rpc_clk1",
  1865. "rpc_clk2",
  1866. "rpc_ctrl",
  1867. "rpc_data",
  1868. "rpc_reset",
  1869. "rpc_int",
  1870. "rpc_wp",
  1871. };
  1872. static const char * const scif_clk_groups[] = {
  1873. "scif_clk_a",
  1874. "scif_clk_b",
  1875. };
  1876. static const char * const scif0_groups[] = {
  1877. "scif0_data",
  1878. "scif0_clk",
  1879. "scif0_ctrl",
  1880. };
  1881. static const char * const scif1_groups[] = {
  1882. "scif1_data_a",
  1883. "scif1_clk",
  1884. "scif1_ctrl",
  1885. "scif1_data_b",
  1886. };
  1887. static const char * const scif3_groups[] = {
  1888. "scif3_data",
  1889. "scif3_clk",
  1890. "scif3_ctrl",
  1891. };
  1892. static const char * const scif4_groups[] = {
  1893. "scif4_data",
  1894. "scif4_clk",
  1895. "scif4_ctrl",
  1896. };
  1897. static const char * const tmu_groups[] = {
  1898. "tmu_tclk1_a",
  1899. "tmu_tclk1_b",
  1900. "tmu_tclk2_a",
  1901. "tmu_tclk2_b",
  1902. };
  1903. static const char * const vin0_groups[] = {
  1904. "vin0_data8",
  1905. "vin0_data10",
  1906. "vin0_data12",
  1907. "vin0_sync",
  1908. "vin0_field",
  1909. "vin0_clkenb",
  1910. "vin0_clk",
  1911. };
  1912. static const char * const vin1_groups[] = {
  1913. "vin1_data8",
  1914. "vin1_data10",
  1915. "vin1_data12",
  1916. "vin1_sync",
  1917. "vin1_field",
  1918. "vin1_clkenb",
  1919. "vin1_clk",
  1920. };
  1921. static const struct sh_pfc_function pinmux_functions[] = {
  1922. SH_PFC_FUNCTION(avb0),
  1923. SH_PFC_FUNCTION(canfd_clk),
  1924. SH_PFC_FUNCTION(canfd0),
  1925. SH_PFC_FUNCTION(canfd1),
  1926. SH_PFC_FUNCTION(du),
  1927. SH_PFC_FUNCTION(hscif0),
  1928. SH_PFC_FUNCTION(hscif1),
  1929. SH_PFC_FUNCTION(hscif2),
  1930. SH_PFC_FUNCTION(hscif3),
  1931. SH_PFC_FUNCTION(i2c0),
  1932. SH_PFC_FUNCTION(i2c1),
  1933. SH_PFC_FUNCTION(i2c2),
  1934. SH_PFC_FUNCTION(i2c3),
  1935. SH_PFC_FUNCTION(i2c4),
  1936. SH_PFC_FUNCTION(intc_ex),
  1937. SH_PFC_FUNCTION(mmc),
  1938. SH_PFC_FUNCTION(msiof0),
  1939. SH_PFC_FUNCTION(msiof1),
  1940. SH_PFC_FUNCTION(msiof2),
  1941. SH_PFC_FUNCTION(msiof3),
  1942. SH_PFC_FUNCTION(pwm0),
  1943. SH_PFC_FUNCTION(pwm1),
  1944. SH_PFC_FUNCTION(pwm2),
  1945. SH_PFC_FUNCTION(pwm3),
  1946. SH_PFC_FUNCTION(pwm4),
  1947. SH_PFC_FUNCTION(qspi0),
  1948. SH_PFC_FUNCTION(qspi1),
  1949. SH_PFC_FUNCTION(rpc),
  1950. SH_PFC_FUNCTION(scif_clk),
  1951. SH_PFC_FUNCTION(scif0),
  1952. SH_PFC_FUNCTION(scif1),
  1953. SH_PFC_FUNCTION(scif3),
  1954. SH_PFC_FUNCTION(scif4),
  1955. SH_PFC_FUNCTION(tmu),
  1956. SH_PFC_FUNCTION(vin0),
  1957. SH_PFC_FUNCTION(vin1),
  1958. };
  1959. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  1960. #define F_(x, y) FN_##y
  1961. #define FM(x) FN_##x
  1962. { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
  1963. 0, 0,
  1964. 0, 0,
  1965. 0, 0,
  1966. 0, 0,
  1967. 0, 0,
  1968. 0, 0,
  1969. 0, 0,
  1970. 0, 0,
  1971. 0, 0,
  1972. 0, 0,
  1973. GP_0_21_FN, GPSR0_21,
  1974. GP_0_20_FN, GPSR0_20,
  1975. GP_0_19_FN, GPSR0_19,
  1976. GP_0_18_FN, GPSR0_18,
  1977. GP_0_17_FN, GPSR0_17,
  1978. GP_0_16_FN, GPSR0_16,
  1979. GP_0_15_FN, GPSR0_15,
  1980. GP_0_14_FN, GPSR0_14,
  1981. GP_0_13_FN, GPSR0_13,
  1982. GP_0_12_FN, GPSR0_12,
  1983. GP_0_11_FN, GPSR0_11,
  1984. GP_0_10_FN, GPSR0_10,
  1985. GP_0_9_FN, GPSR0_9,
  1986. GP_0_8_FN, GPSR0_8,
  1987. GP_0_7_FN, GPSR0_7,
  1988. GP_0_6_FN, GPSR0_6,
  1989. GP_0_5_FN, GPSR0_5,
  1990. GP_0_4_FN, GPSR0_4,
  1991. GP_0_3_FN, GPSR0_3,
  1992. GP_0_2_FN, GPSR0_2,
  1993. GP_0_1_FN, GPSR0_1,
  1994. GP_0_0_FN, GPSR0_0, ))
  1995. },
  1996. { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
  1997. 0, 0,
  1998. 0, 0,
  1999. 0, 0,
  2000. 0, 0,
  2001. GP_1_27_FN, GPSR1_27,
  2002. GP_1_26_FN, GPSR1_26,
  2003. GP_1_25_FN, GPSR1_25,
  2004. GP_1_24_FN, GPSR1_24,
  2005. GP_1_23_FN, GPSR1_23,
  2006. GP_1_22_FN, GPSR1_22,
  2007. GP_1_21_FN, GPSR1_21,
  2008. GP_1_20_FN, GPSR1_20,
  2009. GP_1_19_FN, GPSR1_19,
  2010. GP_1_18_FN, GPSR1_18,
  2011. GP_1_17_FN, GPSR1_17,
  2012. GP_1_16_FN, GPSR1_16,
  2013. GP_1_15_FN, GPSR1_15,
  2014. GP_1_14_FN, GPSR1_14,
  2015. GP_1_13_FN, GPSR1_13,
  2016. GP_1_12_FN, GPSR1_12,
  2017. GP_1_11_FN, GPSR1_11,
  2018. GP_1_10_FN, GPSR1_10,
  2019. GP_1_9_FN, GPSR1_9,
  2020. GP_1_8_FN, GPSR1_8,
  2021. GP_1_7_FN, GPSR1_7,
  2022. GP_1_6_FN, GPSR1_6,
  2023. GP_1_5_FN, GPSR1_5,
  2024. GP_1_4_FN, GPSR1_4,
  2025. GP_1_3_FN, GPSR1_3,
  2026. GP_1_2_FN, GPSR1_2,
  2027. GP_1_1_FN, GPSR1_1,
  2028. GP_1_0_FN, GPSR1_0, ))
  2029. },
  2030. { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
  2031. 0, 0,
  2032. 0, 0,
  2033. 0, 0,
  2034. 0, 0,
  2035. 0, 0,
  2036. 0, 0,
  2037. 0, 0,
  2038. 0, 0,
  2039. 0, 0,
  2040. 0, 0,
  2041. 0, 0,
  2042. 0, 0,
  2043. 0, 0,
  2044. 0, 0,
  2045. 0, 0,
  2046. GP_2_16_FN, GPSR2_16,
  2047. GP_2_15_FN, GPSR2_15,
  2048. GP_2_14_FN, GPSR2_14,
  2049. GP_2_13_FN, GPSR2_13,
  2050. GP_2_12_FN, GPSR2_12,
  2051. GP_2_11_FN, GPSR2_11,
  2052. GP_2_10_FN, GPSR2_10,
  2053. GP_2_9_FN, GPSR2_9,
  2054. GP_2_8_FN, GPSR2_8,
  2055. GP_2_7_FN, GPSR2_7,
  2056. GP_2_6_FN, GPSR2_6,
  2057. GP_2_5_FN, GPSR2_5,
  2058. GP_2_4_FN, GPSR2_4,
  2059. GP_2_3_FN, GPSR2_3,
  2060. GP_2_2_FN, GPSR2_2,
  2061. GP_2_1_FN, GPSR2_1,
  2062. GP_2_0_FN, GPSR2_0, ))
  2063. },
  2064. { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
  2065. 0, 0,
  2066. 0, 0,
  2067. 0, 0,
  2068. 0, 0,
  2069. 0, 0,
  2070. 0, 0,
  2071. 0, 0,
  2072. 0, 0,
  2073. 0, 0,
  2074. 0, 0,
  2075. 0, 0,
  2076. 0, 0,
  2077. 0, 0,
  2078. 0, 0,
  2079. 0, 0,
  2080. GP_3_16_FN, GPSR3_16,
  2081. GP_3_15_FN, GPSR3_15,
  2082. GP_3_14_FN, GPSR3_14,
  2083. GP_3_13_FN, GPSR3_13,
  2084. GP_3_12_FN, GPSR3_12,
  2085. GP_3_11_FN, GPSR3_11,
  2086. GP_3_10_FN, GPSR3_10,
  2087. GP_3_9_FN, GPSR3_9,
  2088. GP_3_8_FN, GPSR3_8,
  2089. GP_3_7_FN, GPSR3_7,
  2090. GP_3_6_FN, GPSR3_6,
  2091. GP_3_5_FN, GPSR3_5,
  2092. GP_3_4_FN, GPSR3_4,
  2093. GP_3_3_FN, GPSR3_3,
  2094. GP_3_2_FN, GPSR3_2,
  2095. GP_3_1_FN, GPSR3_1,
  2096. GP_3_0_FN, GPSR3_0, ))
  2097. },
  2098. { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
  2099. 0, 0,
  2100. 0, 0,
  2101. 0, 0,
  2102. 0, 0,
  2103. 0, 0,
  2104. 0, 0,
  2105. 0, 0,
  2106. 0, 0,
  2107. 0, 0,
  2108. 0, 0,
  2109. 0, 0,
  2110. 0, 0,
  2111. 0, 0,
  2112. 0, 0,
  2113. 0, 0,
  2114. 0, 0,
  2115. 0, 0,
  2116. 0, 0,
  2117. 0, 0,
  2118. 0, 0,
  2119. 0, 0,
  2120. 0, 0,
  2121. 0, 0,
  2122. 0, 0,
  2123. 0, 0,
  2124. 0, 0,
  2125. GP_4_5_FN, GPSR4_5,
  2126. GP_4_4_FN, GPSR4_4,
  2127. GP_4_3_FN, GPSR4_3,
  2128. GP_4_2_FN, GPSR4_2,
  2129. GP_4_1_FN, GPSR4_1,
  2130. GP_4_0_FN, GPSR4_0, ))
  2131. },
  2132. { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
  2133. 0, 0,
  2134. 0, 0,
  2135. 0, 0,
  2136. 0, 0,
  2137. 0, 0,
  2138. 0, 0,
  2139. 0, 0,
  2140. 0, 0,
  2141. 0, 0,
  2142. 0, 0,
  2143. 0, 0,
  2144. 0, 0,
  2145. 0, 0,
  2146. 0, 0,
  2147. 0, 0,
  2148. 0, 0,
  2149. 0, 0,
  2150. GP_5_14_FN, GPSR5_14,
  2151. GP_5_13_FN, GPSR5_13,
  2152. GP_5_12_FN, GPSR5_12,
  2153. GP_5_11_FN, GPSR5_11,
  2154. GP_5_10_FN, GPSR5_10,
  2155. GP_5_9_FN, GPSR5_9,
  2156. GP_5_8_FN, GPSR5_8,
  2157. GP_5_7_FN, GPSR5_7,
  2158. GP_5_6_FN, GPSR5_6,
  2159. GP_5_5_FN, GPSR5_5,
  2160. GP_5_4_FN, GPSR5_4,
  2161. GP_5_3_FN, GPSR5_3,
  2162. GP_5_2_FN, GPSR5_2,
  2163. GP_5_1_FN, GPSR5_1,
  2164. GP_5_0_FN, GPSR5_0, ))
  2165. },
  2166. #undef F_
  2167. #undef FM
  2168. #define F_(x, y) x,
  2169. #define FM(x) FN_##x,
  2170. { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
  2171. IP0_31_28
  2172. IP0_27_24
  2173. IP0_23_20
  2174. IP0_19_16
  2175. IP0_15_12
  2176. IP0_11_8
  2177. IP0_7_4
  2178. IP0_3_0 ))
  2179. },
  2180. { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
  2181. IP1_31_28
  2182. IP1_27_24
  2183. IP1_23_20
  2184. IP1_19_16
  2185. IP1_15_12
  2186. IP1_11_8
  2187. IP1_7_4
  2188. IP1_3_0 ))
  2189. },
  2190. { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
  2191. IP2_31_28
  2192. IP2_27_24
  2193. IP2_23_20
  2194. IP2_19_16
  2195. IP2_15_12
  2196. IP2_11_8
  2197. IP2_7_4
  2198. IP2_3_0 ))
  2199. },
  2200. { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
  2201. IP3_31_28
  2202. IP3_27_24
  2203. IP3_23_20
  2204. IP3_19_16
  2205. IP3_15_12
  2206. IP3_11_8
  2207. IP3_7_4
  2208. IP3_3_0 ))
  2209. },
  2210. { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
  2211. IP4_31_28
  2212. IP4_27_24
  2213. IP4_23_20
  2214. IP4_19_16
  2215. IP4_15_12
  2216. IP4_11_8
  2217. IP4_7_4
  2218. IP4_3_0 ))
  2219. },
  2220. { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
  2221. IP5_31_28
  2222. IP5_27_24
  2223. IP5_23_20
  2224. IP5_19_16
  2225. IP5_15_12
  2226. IP5_11_8
  2227. IP5_7_4
  2228. IP5_3_0 ))
  2229. },
  2230. { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
  2231. IP6_31_28
  2232. IP6_27_24
  2233. IP6_23_20
  2234. IP6_19_16
  2235. IP6_15_12
  2236. IP6_11_8
  2237. IP6_7_4
  2238. IP6_3_0 ))
  2239. },
  2240. { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
  2241. IP7_31_28
  2242. IP7_27_24
  2243. IP7_23_20
  2244. IP7_19_16
  2245. IP7_15_12
  2246. IP7_11_8
  2247. IP7_7_4
  2248. IP7_3_0 ))
  2249. },
  2250. { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
  2251. IP8_31_28
  2252. IP8_27_24
  2253. IP8_23_20
  2254. IP8_19_16
  2255. IP8_15_12
  2256. IP8_11_8
  2257. IP8_7_4
  2258. IP8_3_0 ))
  2259. },
  2260. #undef F_
  2261. #undef FM
  2262. #define F_(x, y) x,
  2263. #define FM(x) FN_##x,
  2264. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
  2265. GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
  2266. 1, 1, 1, 1, 1),
  2267. GROUP(
  2268. /* RESERVED 31, 30, 29, 28 */
  2269. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2270. /* RESERVED 27, 26, 25, 24 */
  2271. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2272. /* RESERVED 23, 22, 21, 20 */
  2273. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2274. /* RESERVED 19, 18, 17, 16 */
  2275. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2276. /* RESERVED 15, 14, 13, 12 */
  2277. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2278. MOD_SEL0_11
  2279. MOD_SEL0_10
  2280. MOD_SEL0_9
  2281. MOD_SEL0_8
  2282. MOD_SEL0_7
  2283. MOD_SEL0_6
  2284. MOD_SEL0_5
  2285. MOD_SEL0_4
  2286. MOD_SEL0_3
  2287. MOD_SEL0_2
  2288. MOD_SEL0_1
  2289. MOD_SEL0_0 ))
  2290. },
  2291. { },
  2292. };
  2293. enum ioctrl_regs {
  2294. POCCTRL0,
  2295. POCCTRL1,
  2296. POCCTRL2,
  2297. TDSELCTRL,
  2298. };
  2299. static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
  2300. [POCCTRL0] = { 0xe6060380 },
  2301. [POCCTRL1] = { 0xe6060384 },
  2302. [POCCTRL2] = { 0xe6060388 },
  2303. [TDSELCTRL] = { 0xe60603c0, },
  2304. { /* sentinel */ },
  2305. };
  2306. static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
  2307. u32 *pocctrl)
  2308. {
  2309. int bit = pin & 0x1f;
  2310. *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
  2311. if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
  2312. return bit;
  2313. if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
  2314. return bit + 22;
  2315. *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
  2316. if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
  2317. return bit - 10;
  2318. if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
  2319. return bit + 7;
  2320. return -EINVAL;
  2321. }
  2322. static const struct sh_pfc_soc_operations pinmux_ops = {
  2323. .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
  2324. };
  2325. const struct sh_pfc_soc_info r8a77970_pinmux_info = {
  2326. .name = "r8a77970_pfc",
  2327. .ops = &pinmux_ops,
  2328. .unlock_reg = 0xe6060000, /* PMMR */
  2329. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  2330. .pins = pinmux_pins,
  2331. .nr_pins = ARRAY_SIZE(pinmux_pins),
  2332. .groups = pinmux_groups,
  2333. .nr_groups = ARRAY_SIZE(pinmux_groups),
  2334. .functions = pinmux_functions,
  2335. .nr_functions = ARRAY_SIZE(pinmux_functions),
  2336. .cfg_regs = pinmux_config_regs,
  2337. .ioctrl_regs = pinmux_ioctrl_regs,
  2338. .pinmux_data = pinmux_data,
  2339. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  2340. };