pfc-r8a7796.c 202 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
  4. *
  5. * Copyright (C) 2016-2019 Renesas Electronics Corp.
  6. *
  7. * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
  8. *
  9. * R-Car Gen3 processor support - PFC hardware block.
  10. *
  11. * Copyright (C) 2015 Renesas Electronics Corporation
  12. */
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include "core.h"
  16. #include "sh_pfc.h"
  17. #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  18. #define CPU_ALL_GP(fn, sfx) \
  19. PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
  20. PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
  21. PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
  22. PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  23. PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
  24. PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
  25. PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
  26. PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
  27. PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  28. PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
  29. PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
  30. PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  31. #define CPU_ALL_NOGP(fn) \
  32. PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
  33. PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
  34. PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
  35. PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
  36. PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
  37. PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
  38. PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
  39. PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
  40. PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
  41. PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
  42. PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
  43. PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
  44. PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
  45. PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
  46. PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
  47. PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
  48. PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
  49. PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
  50. PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
  51. PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
  52. PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
  53. PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
  54. PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
  55. PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
  56. PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
  57. PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
  58. PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
  59. PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
  60. PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
  61. PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
  62. PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
  63. PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
  64. PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
  65. PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
  66. PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
  67. PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
  68. PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
  69. PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
  70. PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  71. PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  72. PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
  73. PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
  74. PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  75. /*
  76. * F_() : just information
  77. * FM() : macro for FN_xxx / xxx_MARK
  78. */
  79. /* GPSR0 */
  80. #define GPSR0_15 F_(D15, IP7_11_8)
  81. #define GPSR0_14 F_(D14, IP7_7_4)
  82. #define GPSR0_13 F_(D13, IP7_3_0)
  83. #define GPSR0_12 F_(D12, IP6_31_28)
  84. #define GPSR0_11 F_(D11, IP6_27_24)
  85. #define GPSR0_10 F_(D10, IP6_23_20)
  86. #define GPSR0_9 F_(D9, IP6_19_16)
  87. #define GPSR0_8 F_(D8, IP6_15_12)
  88. #define GPSR0_7 F_(D7, IP6_11_8)
  89. #define GPSR0_6 F_(D6, IP6_7_4)
  90. #define GPSR0_5 F_(D5, IP6_3_0)
  91. #define GPSR0_4 F_(D4, IP5_31_28)
  92. #define GPSR0_3 F_(D3, IP5_27_24)
  93. #define GPSR0_2 F_(D2, IP5_23_20)
  94. #define GPSR0_1 F_(D1, IP5_19_16)
  95. #define GPSR0_0 F_(D0, IP5_15_12)
  96. /* GPSR1 */
  97. #define GPSR1_28 FM(CLKOUT)
  98. #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
  99. #define GPSR1_26 F_(WE1_N, IP5_7_4)
  100. #define GPSR1_25 F_(WE0_N, IP5_3_0)
  101. #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
  102. #define GPSR1_23 F_(RD_N, IP4_27_24)
  103. #define GPSR1_22 F_(BS_N, IP4_23_20)
  104. #define GPSR1_21 F_(CS1_N, IP4_19_16)
  105. #define GPSR1_20 F_(CS0_N, IP4_15_12)
  106. #define GPSR1_19 F_(A19, IP4_11_8)
  107. #define GPSR1_18 F_(A18, IP4_7_4)
  108. #define GPSR1_17 F_(A17, IP4_3_0)
  109. #define GPSR1_16 F_(A16, IP3_31_28)
  110. #define GPSR1_15 F_(A15, IP3_27_24)
  111. #define GPSR1_14 F_(A14, IP3_23_20)
  112. #define GPSR1_13 F_(A13, IP3_19_16)
  113. #define GPSR1_12 F_(A12, IP3_15_12)
  114. #define GPSR1_11 F_(A11, IP3_11_8)
  115. #define GPSR1_10 F_(A10, IP3_7_4)
  116. #define GPSR1_9 F_(A9, IP3_3_0)
  117. #define GPSR1_8 F_(A8, IP2_31_28)
  118. #define GPSR1_7 F_(A7, IP2_27_24)
  119. #define GPSR1_6 F_(A6, IP2_23_20)
  120. #define GPSR1_5 F_(A5, IP2_19_16)
  121. #define GPSR1_4 F_(A4, IP2_15_12)
  122. #define GPSR1_3 F_(A3, IP2_11_8)
  123. #define GPSR1_2 F_(A2, IP2_7_4)
  124. #define GPSR1_1 F_(A1, IP2_3_0)
  125. #define GPSR1_0 F_(A0, IP1_31_28)
  126. /* GPSR2 */
  127. #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
  128. #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
  129. #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
  130. #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
  131. #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
  132. #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
  133. #define GPSR2_8 F_(PWM2_A, IP1_27_24)
  134. #define GPSR2_7 F_(PWM1_A, IP1_23_20)
  135. #define GPSR2_6 F_(PWM0, IP1_19_16)
  136. #define GPSR2_5 F_(IRQ5, IP1_15_12)
  137. #define GPSR2_4 F_(IRQ4, IP1_11_8)
  138. #define GPSR2_3 F_(IRQ3, IP1_7_4)
  139. #define GPSR2_2 F_(IRQ2, IP1_3_0)
  140. #define GPSR2_1 F_(IRQ1, IP0_31_28)
  141. #define GPSR2_0 F_(IRQ0, IP0_27_24)
  142. /* GPSR3 */
  143. #define GPSR3_15 F_(SD1_WP, IP11_23_20)
  144. #define GPSR3_14 F_(SD1_CD, IP11_19_16)
  145. #define GPSR3_13 F_(SD0_WP, IP11_15_12)
  146. #define GPSR3_12 F_(SD0_CD, IP11_11_8)
  147. #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
  148. #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
  149. #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
  150. #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
  151. #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
  152. #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
  153. #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
  154. #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
  155. #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
  156. #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
  157. #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
  158. #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
  159. /* GPSR4 */
  160. #define GPSR4_17 F_(SD3_DS, IP11_7_4)
  161. #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
  162. #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
  163. #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
  164. #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
  165. #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
  166. #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
  167. #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
  168. #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
  169. #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
  170. #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
  171. #define GPSR4_6 F_(SD2_DS, IP9_27_24)
  172. #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
  173. #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
  174. #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
  175. #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
  176. #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
  177. #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
  178. /* GPSR5 */
  179. #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
  180. #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
  181. #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
  182. #define GPSR5_22 FM(MSIOF0_RXD)
  183. #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
  184. #define GPSR5_20 FM(MSIOF0_TXD)
  185. #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
  186. #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
  187. #define GPSR5_17 FM(MSIOF0_SCK)
  188. #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
  189. #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
  190. #define GPSR5_14 F_(HTX0, IP13_19_16)
  191. #define GPSR5_13 F_(HRX0, IP13_15_12)
  192. #define GPSR5_12 F_(HSCK0, IP13_11_8)
  193. #define GPSR5_11 F_(RX2_A, IP13_7_4)
  194. #define GPSR5_10 F_(TX2_A, IP13_3_0)
  195. #define GPSR5_9 F_(SCK2, IP12_31_28)
  196. #define GPSR5_8 F_(RTS1_N, IP12_27_24)
  197. #define GPSR5_7 F_(CTS1_N, IP12_23_20)
  198. #define GPSR5_6 F_(TX1_A, IP12_19_16)
  199. #define GPSR5_5 F_(RX1_A, IP12_15_12)
  200. #define GPSR5_4 F_(RTS0_N, IP12_11_8)
  201. #define GPSR5_3 F_(CTS0_N, IP12_7_4)
  202. #define GPSR5_2 F_(TX0, IP12_3_0)
  203. #define GPSR5_1 F_(RX0, IP11_31_28)
  204. #define GPSR5_0 F_(SCK0, IP11_27_24)
  205. /* GPSR6 */
  206. #define GPSR6_31 F_(GP6_31, IP18_7_4)
  207. #define GPSR6_30 F_(GP6_30, IP18_3_0)
  208. #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
  209. #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
  210. #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
  211. #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
  212. #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
  213. #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
  214. #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
  215. #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
  216. #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
  217. #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
  218. #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
  219. #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
  220. #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
  221. #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
  222. #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
  223. #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
  224. #define GPSR6_13 FM(SSI_SDATA5)
  225. #define GPSR6_12 FM(SSI_WS5)
  226. #define GPSR6_11 FM(SSI_SCK5)
  227. #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
  228. #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
  229. #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
  230. #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
  231. #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
  232. #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
  233. #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
  234. #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
  235. #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
  236. #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
  237. #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
  238. /* GPSR7 */
  239. #define GPSR7_3 FM(GP7_03)
  240. #define GPSR7_2 FM(GP7_02)
  241. #define GPSR7_1 FM(AVS2)
  242. #define GPSR7_0 FM(AVS1)
  243. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  244. #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  245. #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  246. #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  247. #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  248. #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  249. #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  250. #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  251. #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  252. #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  253. #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  254. #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  255. #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  256. #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  257. #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  258. #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  259. #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  260. #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  261. #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  262. #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  263. #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  264. #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  265. #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  266. #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  267. #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  268. #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  269. #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  270. #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  271. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  272. #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  273. #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  274. #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  275. #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  276. #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  277. #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  278. #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  279. #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  280. #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  281. #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  282. #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  283. #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  284. #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  285. #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  286. #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  287. #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  288. #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  289. #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  290. #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  291. #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  292. #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  293. #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  294. #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  295. #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  296. #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  297. #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  298. #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  299. #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  300. #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  301. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  302. #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  303. #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  304. #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  305. #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  306. #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  307. #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  308. #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  309. #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  310. #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  311. #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  312. #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  313. #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  314. #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  315. #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  316. #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  317. #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  318. #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  319. #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  320. #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  321. #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  322. #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  323. #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  324. #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  325. #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  326. #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  327. #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  328. #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  329. #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  330. #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  331. #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  332. #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  333. #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  334. #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  335. #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  336. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  337. #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  338. #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  339. #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  340. #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  341. #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  342. #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  343. #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  344. #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  345. #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  346. #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  347. #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  348. #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  349. #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  350. #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  351. #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  352. #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  353. #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  354. #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  355. #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  356. #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  357. #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
  358. #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  359. #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  360. #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  361. #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  362. #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  363. #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  364. #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  365. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  366. #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  367. #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  368. #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  369. #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  370. #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  371. #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  372. #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  373. #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  374. #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  375. #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  376. #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  377. #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  378. #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  379. #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  380. #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  381. #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  382. #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  383. #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  384. #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  385. #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
  386. #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
  387. #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
  388. #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
  389. #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
  390. #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  391. #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
  392. #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
  393. #define PINMUX_GPSR \
  394. \
  395. GPSR6_31 \
  396. GPSR6_30 \
  397. GPSR6_29 \
  398. GPSR1_28 GPSR6_28 \
  399. GPSR1_27 GPSR6_27 \
  400. GPSR1_26 GPSR6_26 \
  401. GPSR1_25 GPSR5_25 GPSR6_25 \
  402. GPSR1_24 GPSR5_24 GPSR6_24 \
  403. GPSR1_23 GPSR5_23 GPSR6_23 \
  404. GPSR1_22 GPSR5_22 GPSR6_22 \
  405. GPSR1_21 GPSR5_21 GPSR6_21 \
  406. GPSR1_20 GPSR5_20 GPSR6_20 \
  407. GPSR1_19 GPSR5_19 GPSR6_19 \
  408. GPSR1_18 GPSR5_18 GPSR6_18 \
  409. GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
  410. GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
  411. GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
  412. GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
  413. GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
  414. GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
  415. GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
  416. GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
  417. GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
  418. GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
  419. GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
  420. GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
  421. GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
  422. GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
  423. GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
  424. GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
  425. GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
  426. GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
  427. #define PINMUX_IPSR \
  428. \
  429. FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
  430. FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
  431. FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
  432. FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
  433. FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
  434. FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
  435. FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
  436. FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
  437. \
  438. FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
  439. FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
  440. FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
  441. FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
  442. FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
  443. FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
  444. FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
  445. FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
  446. \
  447. FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
  448. FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
  449. FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
  450. FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
  451. FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
  452. FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
  453. FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
  454. FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
  455. \
  456. FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
  457. FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
  458. FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
  459. FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
  460. FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
  461. FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
  462. FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
  463. FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
  464. \
  465. FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
  466. FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
  467. FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
  468. FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
  469. FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
  470. FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
  471. FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
  472. FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
  473. /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  474. #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
  475. #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
  476. #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
  477. #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
  478. #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
  479. #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
  480. #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
  481. #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
  482. #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
  483. #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
  484. #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
  485. #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
  486. #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
  487. #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
  488. #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
  489. #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
  490. #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
  491. #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
  492. /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  493. #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
  494. #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  495. #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
  496. #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
  497. #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  498. #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
  499. #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
  500. #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
  501. #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
  502. #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
  503. #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
  504. #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
  505. #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
  506. #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
  507. #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
  508. #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
  509. #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
  510. #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
  511. #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
  512. #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
  513. #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
  514. #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
  515. /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  516. #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
  517. #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
  518. #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
  519. #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
  520. #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
  521. #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  522. #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
  523. #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
  524. #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
  525. #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
  526. #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
  527. #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
  528. #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
  529. #define PINMUX_MOD_SELS \
  530. \
  531. MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
  532. MOD_SEL2_30 \
  533. MOD_SEL1_29_28_27 MOD_SEL2_29 \
  534. MOD_SEL0_28_27 MOD_SEL2_28_27 \
  535. MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
  536. MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
  537. MOD_SEL0_23 MOD_SEL1_23_22_21 \
  538. MOD_SEL0_22 MOD_SEL2_22 \
  539. MOD_SEL0_21 MOD_SEL2_21 \
  540. MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
  541. MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
  542. MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
  543. MOD_SEL2_17 \
  544. MOD_SEL0_16 MOD_SEL1_16 \
  545. MOD_SEL1_15_14 \
  546. MOD_SEL0_14_13 \
  547. MOD_SEL1_13 \
  548. MOD_SEL0_12 MOD_SEL1_12 \
  549. MOD_SEL0_11 MOD_SEL1_11 \
  550. MOD_SEL0_10 MOD_SEL1_10 \
  551. MOD_SEL0_9_8 MOD_SEL1_9 \
  552. MOD_SEL0_7_6 \
  553. MOD_SEL1_6 \
  554. MOD_SEL0_5 MOD_SEL1_5 \
  555. MOD_SEL0_4_3 MOD_SEL1_4 \
  556. MOD_SEL1_3 \
  557. MOD_SEL1_2 \
  558. MOD_SEL1_1 \
  559. MOD_SEL1_0 MOD_SEL2_0
  560. /*
  561. * These pins are not able to be muxed but have other properties
  562. * that can be set, such as drive-strength or pull-up/pull-down enable.
  563. */
  564. #define PINMUX_STATIC \
  565. FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
  566. FM(QSPI0_IO2) FM(QSPI0_IO3) \
  567. FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
  568. FM(QSPI1_IO2) FM(QSPI1_IO3) \
  569. FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
  570. FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
  571. FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
  572. FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
  573. FM(PRESETOUT) \
  574. FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
  575. FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
  576. #define PINMUX_PHYS \
  577. FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
  578. enum {
  579. PINMUX_RESERVED = 0,
  580. PINMUX_DATA_BEGIN,
  581. GP_ALL(DATA),
  582. PINMUX_DATA_END,
  583. #define F_(x, y)
  584. #define FM(x) FN_##x,
  585. PINMUX_FUNCTION_BEGIN,
  586. GP_ALL(FN),
  587. PINMUX_GPSR
  588. PINMUX_IPSR
  589. PINMUX_MOD_SELS
  590. PINMUX_FUNCTION_END,
  591. #undef F_
  592. #undef FM
  593. #define F_(x, y)
  594. #define FM(x) x##_MARK,
  595. PINMUX_MARK_BEGIN,
  596. PINMUX_GPSR
  597. PINMUX_IPSR
  598. PINMUX_MOD_SELS
  599. PINMUX_STATIC
  600. PINMUX_PHYS
  601. PINMUX_MARK_END,
  602. #undef F_
  603. #undef FM
  604. };
  605. static const u16 pinmux_data[] = {
  606. PINMUX_DATA_GP_ALL(),
  607. PINMUX_SINGLE(AVS1),
  608. PINMUX_SINGLE(AVS2),
  609. PINMUX_SINGLE(CLKOUT),
  610. PINMUX_SINGLE(GP7_03),
  611. PINMUX_SINGLE(GP7_02),
  612. PINMUX_SINGLE(MSIOF0_RXD),
  613. PINMUX_SINGLE(MSIOF0_SCK),
  614. PINMUX_SINGLE(MSIOF0_TXD),
  615. PINMUX_SINGLE(SSI_SCK5),
  616. PINMUX_SINGLE(SSI_SDATA5),
  617. PINMUX_SINGLE(SSI_WS5),
  618. /* IPSR0 */
  619. PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
  620. PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
  621. PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
  622. PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
  623. PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
  624. PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
  625. PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
  626. PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
  627. PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
  628. PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
  629. PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
  630. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  631. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  632. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  633. PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
  634. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  635. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  636. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  637. PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
  638. PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
  639. PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
  640. PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
  641. PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
  642. PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
  643. PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
  644. PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
  645. PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
  646. PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
  647. PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
  648. PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
  649. PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
  650. PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
  651. PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
  652. /* IPSR1 */
  653. PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
  654. PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
  655. PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
  656. PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
  657. PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
  658. PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
  659. PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
  660. PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
  661. PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
  662. PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
  663. PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
  664. PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
  665. PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
  666. PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
  667. PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
  668. PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
  669. PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
  670. PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
  671. PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
  672. PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
  673. PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
  674. PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
  675. PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
  676. PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
  677. PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
  678. PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
  679. PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
  680. PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
  681. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
  682. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  683. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
  684. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  685. PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
  686. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
  687. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  688. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  689. PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
  690. PINMUX_IPSR_GPSR(IP1_31_28, A0),
  691. PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
  692. PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
  693. PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
  694. PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
  695. PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
  696. /* IPSR2 */
  697. PINMUX_IPSR_GPSR(IP2_3_0, A1),
  698. PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
  699. PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
  700. PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
  701. PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
  702. PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
  703. PINMUX_IPSR_GPSR(IP2_7_4, A2),
  704. PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
  705. PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
  706. PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
  707. PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
  708. PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
  709. PINMUX_IPSR_GPSR(IP2_11_8, A3),
  710. PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
  711. PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
  712. PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
  713. PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
  714. PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
  715. PINMUX_IPSR_GPSR(IP2_15_12, A4),
  716. PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
  717. PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
  718. PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
  719. PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
  720. PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
  721. PINMUX_IPSR_GPSR(IP2_19_16, A5),
  722. PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
  723. PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
  724. PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
  725. PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
  726. PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
  727. PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
  728. PINMUX_IPSR_GPSR(IP2_23_20, A6),
  729. PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
  730. PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
  731. PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
  732. PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
  733. PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
  734. PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
  735. PINMUX_IPSR_GPSR(IP2_27_24, A7),
  736. PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
  737. PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
  738. PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
  739. PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
  740. PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
  741. PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
  742. PINMUX_IPSR_GPSR(IP2_31_28, A8),
  743. PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
  744. PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
  745. PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
  746. PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
  747. PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
  748. PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
  749. /* IPSR3 */
  750. PINMUX_IPSR_GPSR(IP3_3_0, A9),
  751. PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
  752. PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
  753. PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
  754. PINMUX_IPSR_GPSR(IP3_7_4, A10),
  755. PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
  756. PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
  757. PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
  758. PINMUX_IPSR_GPSR(IP3_11_8, A11),
  759. PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
  760. PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
  761. PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
  762. PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
  763. PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
  764. PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
  765. PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
  766. PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
  767. PINMUX_IPSR_GPSR(IP3_15_12, A12),
  768. PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
  769. PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
  770. PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
  771. PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
  772. PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
  773. PINMUX_IPSR_GPSR(IP3_19_16, A13),
  774. PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
  775. PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
  776. PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
  777. PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
  778. PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
  779. PINMUX_IPSR_GPSR(IP3_23_20, A14),
  780. PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
  781. PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
  782. PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
  783. PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
  784. PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
  785. PINMUX_IPSR_GPSR(IP3_27_24, A15),
  786. PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
  787. PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
  788. PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
  789. PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
  790. PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
  791. PINMUX_IPSR_GPSR(IP3_31_28, A16),
  792. PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
  793. PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
  794. PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
  795. /* IPSR4 */
  796. PINMUX_IPSR_GPSR(IP4_3_0, A17),
  797. PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
  798. PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
  799. PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
  800. PINMUX_IPSR_GPSR(IP4_7_4, A18),
  801. PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
  802. PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
  803. PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
  804. PINMUX_IPSR_GPSR(IP4_11_8, A19),
  805. PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
  806. PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
  807. PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
  808. PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
  809. PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
  810. PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
  811. PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
  812. PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
  813. PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
  814. PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
  815. PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
  816. PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
  817. PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
  818. PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
  819. PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
  820. PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
  821. PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
  822. PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
  823. PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
  824. PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
  825. PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
  826. PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
  827. PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
  828. PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
  829. PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
  830. PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
  831. PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
  832. PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
  833. /* IPSR5 */
  834. PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
  835. PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
  836. PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
  837. PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
  838. PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
  839. PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
  840. PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
  841. PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
  842. PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
  843. PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
  844. PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
  845. PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
  846. PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
  847. PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
  848. PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
  849. PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
  850. PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
  851. PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
  852. PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
  853. PINMUX_IPSR_GPSR(IP5_15_12, D0),
  854. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
  855. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
  856. PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
  857. PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
  858. PINMUX_IPSR_GPSR(IP5_19_16, D1),
  859. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
  860. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
  861. PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
  862. PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
  863. PINMUX_IPSR_GPSR(IP5_23_20, D2),
  864. PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
  865. PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
  866. PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
  867. PINMUX_IPSR_GPSR(IP5_27_24, D3),
  868. PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
  869. PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
  870. PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
  871. PINMUX_IPSR_GPSR(IP5_31_28, D4),
  872. PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
  873. PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
  874. PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
  875. /* IPSR6 */
  876. PINMUX_IPSR_GPSR(IP6_3_0, D5),
  877. PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
  878. PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
  879. PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
  880. PINMUX_IPSR_GPSR(IP6_7_4, D6),
  881. PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
  882. PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
  883. PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
  884. PINMUX_IPSR_GPSR(IP6_11_8, D7),
  885. PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
  886. PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
  887. PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
  888. PINMUX_IPSR_GPSR(IP6_15_12, D8),
  889. PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
  890. PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
  891. PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
  892. PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
  893. PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
  894. PINMUX_IPSR_GPSR(IP6_19_16, D9),
  895. PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
  896. PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
  897. PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
  898. PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
  899. PINMUX_IPSR_GPSR(IP6_23_20, D10),
  900. PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
  901. PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
  902. PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
  903. PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
  904. PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
  905. PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
  906. PINMUX_IPSR_GPSR(IP6_27_24, D11),
  907. PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
  908. PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
  909. PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
  910. PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
  911. PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
  912. PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
  913. PINMUX_IPSR_GPSR(IP6_31_28, D12),
  914. PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
  915. PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
  916. PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
  917. PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
  918. PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
  919. /* IPSR7 */
  920. PINMUX_IPSR_GPSR(IP7_3_0, D13),
  921. PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
  922. PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
  923. PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
  924. PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
  925. PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
  926. PINMUX_IPSR_GPSR(IP7_7_4, D14),
  927. PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
  928. PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
  929. PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
  930. PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
  931. PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
  932. PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
  933. PINMUX_IPSR_GPSR(IP7_11_8, D15),
  934. PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
  935. PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
  936. PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
  937. PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
  938. PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
  939. PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
  940. PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
  941. PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
  942. PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
  943. PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
  944. PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
  945. PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
  946. PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
  947. PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
  948. PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
  949. PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
  950. PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
  951. PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
  952. PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
  953. PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
  954. /* IPSR8 */
  955. PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
  956. PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
  957. PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
  958. PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
  959. PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
  960. PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
  961. PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
  962. PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
  963. PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
  964. PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
  965. PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
  966. PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
  967. PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
  968. PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
  969. PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
  970. PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
  971. PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
  972. PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
  973. PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
  974. PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
  975. PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
  976. PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
  977. PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
  978. PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
  979. PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
  980. PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
  981. PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
  982. PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
  983. PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
  984. PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
  985. PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
  986. PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
  987. PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
  988. PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
  989. PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
  990. PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
  991. PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
  992. PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
  993. PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
  994. PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
  995. /* IPSR9 */
  996. PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
  997. PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
  998. PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
  999. PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
  1000. PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
  1001. PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
  1002. PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
  1003. PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
  1004. PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
  1005. PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
  1006. PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
  1007. PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
  1008. PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
  1009. PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
  1010. PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
  1011. PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
  1012. /* IPSR10 */
  1013. PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
  1014. PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
  1015. PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
  1016. PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
  1017. PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
  1018. PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
  1019. PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
  1020. PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
  1021. PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
  1022. PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
  1023. PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
  1024. PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
  1025. PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
  1026. PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
  1027. PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
  1028. PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
  1029. PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
  1030. PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
  1031. PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
  1032. /* IPSR11 */
  1033. PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
  1034. PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
  1035. PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
  1036. PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
  1037. PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
  1038. PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
  1039. PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
  1040. PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
  1041. PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
  1042. PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
  1043. PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
  1044. PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
  1045. PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
  1046. PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
  1047. PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1048. PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
  1049. PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
  1050. PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
  1051. PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1052. PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
  1053. PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
  1054. PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
  1055. PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
  1056. PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
  1057. PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
  1058. PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
  1059. PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
  1060. PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
  1061. PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
  1062. PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
  1063. PINMUX_IPSR_GPSR(IP11_31_28, RX0),
  1064. PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
  1065. PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
  1066. PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
  1067. PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
  1068. /* IPSR12 */
  1069. PINMUX_IPSR_GPSR(IP12_3_0, TX0),
  1070. PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
  1071. PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
  1072. PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
  1073. PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
  1074. PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
  1075. PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
  1076. PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
  1077. PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
  1078. PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
  1079. PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
  1080. PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
  1081. PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
  1082. PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
  1083. PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
  1084. PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
  1085. PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
  1086. PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
  1087. PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
  1088. PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
  1089. PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
  1090. PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
  1091. PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
  1092. PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
  1093. PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
  1094. PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
  1095. PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
  1096. PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
  1097. PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
  1098. PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
  1099. PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
  1100. PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
  1101. PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
  1102. PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
  1103. PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
  1104. PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
  1105. PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
  1106. PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
  1107. PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
  1108. PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
  1109. PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
  1110. PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
  1111. PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
  1112. PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
  1113. PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
  1114. PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
  1115. PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
  1116. PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
  1117. PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
  1118. PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
  1119. PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
  1120. PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
  1121. /* IPSR13 */
  1122. PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
  1123. PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
  1124. PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
  1125. PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
  1126. PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
  1127. PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
  1128. PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
  1129. PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
  1130. PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
  1131. PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
  1132. PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
  1133. PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
  1134. PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
  1135. PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
  1136. PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
  1137. PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
  1138. PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
  1139. PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
  1140. PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
  1141. PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
  1142. PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
  1143. PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
  1144. PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
  1145. PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
  1146. PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
  1147. PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
  1148. PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
  1149. PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
  1150. PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
  1151. PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
  1152. PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
  1153. PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
  1154. PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
  1155. PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
  1156. PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
  1157. PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
  1158. PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
  1159. PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
  1160. PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
  1161. PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
  1162. PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
  1163. PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
  1164. PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
  1165. PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
  1166. PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
  1167. PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
  1168. PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
  1169. PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
  1170. PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
  1171. PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
  1172. PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
  1173. /* IPSR14 */
  1174. PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
  1175. PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
  1176. PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
  1177. PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
  1178. PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
  1179. PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
  1180. PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
  1181. PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
  1182. PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
  1183. PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
  1184. PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
  1185. PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
  1186. PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
  1187. PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
  1188. PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
  1189. PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
  1190. PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
  1191. PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
  1192. PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
  1193. PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
  1194. PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
  1195. PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
  1196. PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
  1197. PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
  1198. PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
  1199. PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
  1200. PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
  1201. PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
  1202. PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
  1203. PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
  1204. PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
  1205. PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
  1206. /* IPSR15 */
  1207. PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
  1208. PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
  1209. PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
  1210. PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
  1211. PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
  1212. PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
  1213. PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
  1214. PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
  1215. PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
  1216. PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
  1217. PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
  1218. PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
  1219. PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
  1220. PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
  1221. PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
  1222. PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
  1223. PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
  1224. PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
  1225. PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
  1226. PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
  1227. PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
  1228. PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
  1229. PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
  1230. PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
  1231. PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
  1232. PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
  1233. PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
  1234. PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
  1235. PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
  1236. PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
  1237. PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
  1238. PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
  1239. PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
  1240. PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
  1241. PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
  1242. PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
  1243. PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
  1244. PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
  1245. /* IPSR16 */
  1246. PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
  1247. PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
  1248. PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
  1249. PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
  1250. PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
  1251. PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
  1252. PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
  1253. PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
  1254. PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
  1255. PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
  1256. PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
  1257. PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
  1258. PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
  1259. PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
  1260. PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
  1261. PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
  1262. PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
  1263. PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
  1264. PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
  1265. PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
  1266. PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
  1267. PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
  1268. PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
  1269. PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
  1270. PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
  1271. PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
  1272. PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
  1273. PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
  1274. PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
  1275. PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
  1276. PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
  1277. PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
  1278. PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
  1279. PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
  1280. PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
  1281. PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
  1282. PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
  1283. PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
  1284. PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
  1285. PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
  1286. PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
  1287. PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
  1288. PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
  1289. /* IPSR17 */
  1290. PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
  1291. PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
  1292. PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
  1293. PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
  1294. PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
  1295. PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
  1296. PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
  1297. PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
  1298. PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
  1299. PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
  1300. PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
  1301. PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
  1302. PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
  1303. PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
  1304. PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
  1305. PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
  1306. PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
  1307. PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
  1308. PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
  1309. PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
  1310. PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
  1311. PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
  1312. PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
  1313. PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
  1314. PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
  1315. PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
  1316. PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
  1317. PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
  1318. PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
  1319. PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
  1320. PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
  1321. PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
  1322. PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
  1323. PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
  1324. PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
  1325. PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
  1326. PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
  1327. PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
  1328. PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
  1329. PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
  1330. PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
  1331. PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
  1332. PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
  1333. PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
  1334. PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
  1335. PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
  1336. PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
  1337. PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
  1338. PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
  1339. PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
  1340. PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
  1341. PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
  1342. PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
  1343. PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
  1344. PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
  1345. PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
  1346. PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
  1347. /* IPSR18 */
  1348. PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
  1349. PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
  1350. PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
  1351. PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
  1352. PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
  1353. PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
  1354. PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
  1355. PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
  1356. PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
  1357. PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
  1358. PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
  1359. PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
  1360. PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
  1361. PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
  1362. PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
  1363. PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
  1364. PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
  1365. PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
  1366. /*
  1367. * Static pins can not be muxed between different functions but
  1368. * still need mark entries in the pinmux list. Add each static
  1369. * pin to the list without an associated function. The sh-pfc
  1370. * core will do the right thing and skip trying to mux the pin
  1371. * while still applying configuration to it.
  1372. */
  1373. #define FM(x) PINMUX_DATA(x##_MARK, 0),
  1374. PINMUX_STATIC
  1375. #undef FM
  1376. };
  1377. /*
  1378. * Pins not associated with a GPIO port.
  1379. */
  1380. enum {
  1381. GP_ASSIGN_LAST(),
  1382. NOGP_ALL(),
  1383. };
  1384. static const struct sh_pfc_pin pinmux_pins[] = {
  1385. PINMUX_GPIO_GP_ALL(),
  1386. PINMUX_NOGP_ALL(),
  1387. };
  1388. /* - AUDIO CLOCK ------------------------------------------------------------ */
  1389. static const unsigned int audio_clk_a_a_pins[] = {
  1390. /* CLK A */
  1391. RCAR_GP_PIN(6, 22),
  1392. };
  1393. static const unsigned int audio_clk_a_a_mux[] = {
  1394. AUDIO_CLKA_A_MARK,
  1395. };
  1396. static const unsigned int audio_clk_a_b_pins[] = {
  1397. /* CLK A */
  1398. RCAR_GP_PIN(5, 4),
  1399. };
  1400. static const unsigned int audio_clk_a_b_mux[] = {
  1401. AUDIO_CLKA_B_MARK,
  1402. };
  1403. static const unsigned int audio_clk_a_c_pins[] = {
  1404. /* CLK A */
  1405. RCAR_GP_PIN(5, 19),
  1406. };
  1407. static const unsigned int audio_clk_a_c_mux[] = {
  1408. AUDIO_CLKA_C_MARK,
  1409. };
  1410. static const unsigned int audio_clk_b_a_pins[] = {
  1411. /* CLK B */
  1412. RCAR_GP_PIN(5, 12),
  1413. };
  1414. static const unsigned int audio_clk_b_a_mux[] = {
  1415. AUDIO_CLKB_A_MARK,
  1416. };
  1417. static const unsigned int audio_clk_b_b_pins[] = {
  1418. /* CLK B */
  1419. RCAR_GP_PIN(6, 23),
  1420. };
  1421. static const unsigned int audio_clk_b_b_mux[] = {
  1422. AUDIO_CLKB_B_MARK,
  1423. };
  1424. static const unsigned int audio_clk_c_a_pins[] = {
  1425. /* CLK C */
  1426. RCAR_GP_PIN(5, 21),
  1427. };
  1428. static const unsigned int audio_clk_c_a_mux[] = {
  1429. AUDIO_CLKC_A_MARK,
  1430. };
  1431. static const unsigned int audio_clk_c_b_pins[] = {
  1432. /* CLK C */
  1433. RCAR_GP_PIN(5, 0),
  1434. };
  1435. static const unsigned int audio_clk_c_b_mux[] = {
  1436. AUDIO_CLKC_B_MARK,
  1437. };
  1438. static const unsigned int audio_clkout_a_pins[] = {
  1439. /* CLKOUT */
  1440. RCAR_GP_PIN(5, 18),
  1441. };
  1442. static const unsigned int audio_clkout_a_mux[] = {
  1443. AUDIO_CLKOUT_A_MARK,
  1444. };
  1445. static const unsigned int audio_clkout_b_pins[] = {
  1446. /* CLKOUT */
  1447. RCAR_GP_PIN(6, 28),
  1448. };
  1449. static const unsigned int audio_clkout_b_mux[] = {
  1450. AUDIO_CLKOUT_B_MARK,
  1451. };
  1452. static const unsigned int audio_clkout_c_pins[] = {
  1453. /* CLKOUT */
  1454. RCAR_GP_PIN(5, 3),
  1455. };
  1456. static const unsigned int audio_clkout_c_mux[] = {
  1457. AUDIO_CLKOUT_C_MARK,
  1458. };
  1459. static const unsigned int audio_clkout_d_pins[] = {
  1460. /* CLKOUT */
  1461. RCAR_GP_PIN(5, 21),
  1462. };
  1463. static const unsigned int audio_clkout_d_mux[] = {
  1464. AUDIO_CLKOUT_D_MARK,
  1465. };
  1466. static const unsigned int audio_clkout1_a_pins[] = {
  1467. /* CLKOUT1 */
  1468. RCAR_GP_PIN(5, 15),
  1469. };
  1470. static const unsigned int audio_clkout1_a_mux[] = {
  1471. AUDIO_CLKOUT1_A_MARK,
  1472. };
  1473. static const unsigned int audio_clkout1_b_pins[] = {
  1474. /* CLKOUT1 */
  1475. RCAR_GP_PIN(6, 29),
  1476. };
  1477. static const unsigned int audio_clkout1_b_mux[] = {
  1478. AUDIO_CLKOUT1_B_MARK,
  1479. };
  1480. static const unsigned int audio_clkout2_a_pins[] = {
  1481. /* CLKOUT2 */
  1482. RCAR_GP_PIN(5, 16),
  1483. };
  1484. static const unsigned int audio_clkout2_a_mux[] = {
  1485. AUDIO_CLKOUT2_A_MARK,
  1486. };
  1487. static const unsigned int audio_clkout2_b_pins[] = {
  1488. /* CLKOUT2 */
  1489. RCAR_GP_PIN(6, 30),
  1490. };
  1491. static const unsigned int audio_clkout2_b_mux[] = {
  1492. AUDIO_CLKOUT2_B_MARK,
  1493. };
  1494. static const unsigned int audio_clkout3_a_pins[] = {
  1495. /* CLKOUT3 */
  1496. RCAR_GP_PIN(5, 19),
  1497. };
  1498. static const unsigned int audio_clkout3_a_mux[] = {
  1499. AUDIO_CLKOUT3_A_MARK,
  1500. };
  1501. static const unsigned int audio_clkout3_b_pins[] = {
  1502. /* CLKOUT3 */
  1503. RCAR_GP_PIN(6, 31),
  1504. };
  1505. static const unsigned int audio_clkout3_b_mux[] = {
  1506. AUDIO_CLKOUT3_B_MARK,
  1507. };
  1508. /* - EtherAVB --------------------------------------------------------------- */
  1509. static const unsigned int avb_link_pins[] = {
  1510. /* AVB_LINK */
  1511. RCAR_GP_PIN(2, 12),
  1512. };
  1513. static const unsigned int avb_link_mux[] = {
  1514. AVB_LINK_MARK,
  1515. };
  1516. static const unsigned int avb_magic_pins[] = {
  1517. /* AVB_MAGIC_ */
  1518. RCAR_GP_PIN(2, 10),
  1519. };
  1520. static const unsigned int avb_magic_mux[] = {
  1521. AVB_MAGIC_MARK,
  1522. };
  1523. static const unsigned int avb_phy_int_pins[] = {
  1524. /* AVB_PHY_INT */
  1525. RCAR_GP_PIN(2, 11),
  1526. };
  1527. static const unsigned int avb_phy_int_mux[] = {
  1528. AVB_PHY_INT_MARK,
  1529. };
  1530. static const unsigned int avb_mdio_pins[] = {
  1531. /* AVB_MDC, AVB_MDIO */
  1532. RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
  1533. };
  1534. static const unsigned int avb_mdio_mux[] = {
  1535. AVB_MDC_MARK, AVB_MDIO_MARK,
  1536. };
  1537. static const unsigned int avb_mii_pins[] = {
  1538. /*
  1539. * AVB_TX_CTL, AVB_TXC, AVB_TD0,
  1540. * AVB_TD1, AVB_TD2, AVB_TD3,
  1541. * AVB_RX_CTL, AVB_RXC, AVB_RD0,
  1542. * AVB_RD1, AVB_RD2, AVB_RD3,
  1543. * AVB_TXCREFCLK
  1544. */
  1545. PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
  1546. PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
  1547. PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
  1548. PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
  1549. PIN_AVB_TXCREFCLK,
  1550. };
  1551. static const unsigned int avb_mii_mux[] = {
  1552. AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
  1553. AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
  1554. AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
  1555. AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
  1556. AVB_TXCREFCLK_MARK,
  1557. };
  1558. static const unsigned int avb_avtp_pps_pins[] = {
  1559. /* AVB_AVTP_PPS */
  1560. RCAR_GP_PIN(2, 6),
  1561. };
  1562. static const unsigned int avb_avtp_pps_mux[] = {
  1563. AVB_AVTP_PPS_MARK,
  1564. };
  1565. static const unsigned int avb_avtp_match_a_pins[] = {
  1566. /* AVB_AVTP_MATCH_A */
  1567. RCAR_GP_PIN(2, 13),
  1568. };
  1569. static const unsigned int avb_avtp_match_a_mux[] = {
  1570. AVB_AVTP_MATCH_A_MARK,
  1571. };
  1572. static const unsigned int avb_avtp_capture_a_pins[] = {
  1573. /* AVB_AVTP_CAPTURE_A */
  1574. RCAR_GP_PIN(2, 14),
  1575. };
  1576. static const unsigned int avb_avtp_capture_a_mux[] = {
  1577. AVB_AVTP_CAPTURE_A_MARK,
  1578. };
  1579. static const unsigned int avb_avtp_match_b_pins[] = {
  1580. /* AVB_AVTP_MATCH_B */
  1581. RCAR_GP_PIN(1, 8),
  1582. };
  1583. static const unsigned int avb_avtp_match_b_mux[] = {
  1584. AVB_AVTP_MATCH_B_MARK,
  1585. };
  1586. static const unsigned int avb_avtp_capture_b_pins[] = {
  1587. /* AVB_AVTP_CAPTURE_B */
  1588. RCAR_GP_PIN(1, 11),
  1589. };
  1590. static const unsigned int avb_avtp_capture_b_mux[] = {
  1591. AVB_AVTP_CAPTURE_B_MARK,
  1592. };
  1593. /* - CAN ------------------------------------------------------------------ */
  1594. static const unsigned int can0_data_a_pins[] = {
  1595. /* TX, RX */
  1596. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1597. };
  1598. static const unsigned int can0_data_a_mux[] = {
  1599. CAN0_TX_A_MARK, CAN0_RX_A_MARK,
  1600. };
  1601. static const unsigned int can0_data_b_pins[] = {
  1602. /* TX, RX */
  1603. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1604. };
  1605. static const unsigned int can0_data_b_mux[] = {
  1606. CAN0_TX_B_MARK, CAN0_RX_B_MARK,
  1607. };
  1608. static const unsigned int can1_data_pins[] = {
  1609. /* TX, RX */
  1610. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1611. };
  1612. static const unsigned int can1_data_mux[] = {
  1613. CAN1_TX_MARK, CAN1_RX_MARK,
  1614. };
  1615. /* - CAN Clock -------------------------------------------------------------- */
  1616. static const unsigned int can_clk_pins[] = {
  1617. /* CLK */
  1618. RCAR_GP_PIN(1, 25),
  1619. };
  1620. static const unsigned int can_clk_mux[] = {
  1621. CAN_CLK_MARK,
  1622. };
  1623. /* - CAN FD --------------------------------------------------------------- */
  1624. static const unsigned int canfd0_data_a_pins[] = {
  1625. /* TX, RX */
  1626. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1627. };
  1628. static const unsigned int canfd0_data_a_mux[] = {
  1629. CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
  1630. };
  1631. static const unsigned int canfd0_data_b_pins[] = {
  1632. /* TX, RX */
  1633. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1634. };
  1635. static const unsigned int canfd0_data_b_mux[] = {
  1636. CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
  1637. };
  1638. static const unsigned int canfd1_data_pins[] = {
  1639. /* TX, RX */
  1640. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1641. };
  1642. static const unsigned int canfd1_data_mux[] = {
  1643. CANFD1_TX_MARK, CANFD1_RX_MARK,
  1644. };
  1645. /* - DRIF0 --------------------------------------------------------------- */
  1646. static const unsigned int drif0_ctrl_a_pins[] = {
  1647. /* CLK, SYNC */
  1648. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1649. };
  1650. static const unsigned int drif0_ctrl_a_mux[] = {
  1651. RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
  1652. };
  1653. static const unsigned int drif0_data0_a_pins[] = {
  1654. /* D0 */
  1655. RCAR_GP_PIN(6, 10),
  1656. };
  1657. static const unsigned int drif0_data0_a_mux[] = {
  1658. RIF0_D0_A_MARK,
  1659. };
  1660. static const unsigned int drif0_data1_a_pins[] = {
  1661. /* D1 */
  1662. RCAR_GP_PIN(6, 7),
  1663. };
  1664. static const unsigned int drif0_data1_a_mux[] = {
  1665. RIF0_D1_A_MARK,
  1666. };
  1667. static const unsigned int drif0_ctrl_b_pins[] = {
  1668. /* CLK, SYNC */
  1669. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  1670. };
  1671. static const unsigned int drif0_ctrl_b_mux[] = {
  1672. RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
  1673. };
  1674. static const unsigned int drif0_data0_b_pins[] = {
  1675. /* D0 */
  1676. RCAR_GP_PIN(5, 1),
  1677. };
  1678. static const unsigned int drif0_data0_b_mux[] = {
  1679. RIF0_D0_B_MARK,
  1680. };
  1681. static const unsigned int drif0_data1_b_pins[] = {
  1682. /* D1 */
  1683. RCAR_GP_PIN(5, 2),
  1684. };
  1685. static const unsigned int drif0_data1_b_mux[] = {
  1686. RIF0_D1_B_MARK,
  1687. };
  1688. static const unsigned int drif0_ctrl_c_pins[] = {
  1689. /* CLK, SYNC */
  1690. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
  1691. };
  1692. static const unsigned int drif0_ctrl_c_mux[] = {
  1693. RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
  1694. };
  1695. static const unsigned int drif0_data0_c_pins[] = {
  1696. /* D0 */
  1697. RCAR_GP_PIN(5, 13),
  1698. };
  1699. static const unsigned int drif0_data0_c_mux[] = {
  1700. RIF0_D0_C_MARK,
  1701. };
  1702. static const unsigned int drif0_data1_c_pins[] = {
  1703. /* D1 */
  1704. RCAR_GP_PIN(5, 14),
  1705. };
  1706. static const unsigned int drif0_data1_c_mux[] = {
  1707. RIF0_D1_C_MARK,
  1708. };
  1709. /* - DRIF1 --------------------------------------------------------------- */
  1710. static const unsigned int drif1_ctrl_a_pins[] = {
  1711. /* CLK, SYNC */
  1712. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1713. };
  1714. static const unsigned int drif1_ctrl_a_mux[] = {
  1715. RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
  1716. };
  1717. static const unsigned int drif1_data0_a_pins[] = {
  1718. /* D0 */
  1719. RCAR_GP_PIN(6, 19),
  1720. };
  1721. static const unsigned int drif1_data0_a_mux[] = {
  1722. RIF1_D0_A_MARK,
  1723. };
  1724. static const unsigned int drif1_data1_a_pins[] = {
  1725. /* D1 */
  1726. RCAR_GP_PIN(6, 20),
  1727. };
  1728. static const unsigned int drif1_data1_a_mux[] = {
  1729. RIF1_D1_A_MARK,
  1730. };
  1731. static const unsigned int drif1_ctrl_b_pins[] = {
  1732. /* CLK, SYNC */
  1733. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
  1734. };
  1735. static const unsigned int drif1_ctrl_b_mux[] = {
  1736. RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
  1737. };
  1738. static const unsigned int drif1_data0_b_pins[] = {
  1739. /* D0 */
  1740. RCAR_GP_PIN(5, 7),
  1741. };
  1742. static const unsigned int drif1_data0_b_mux[] = {
  1743. RIF1_D0_B_MARK,
  1744. };
  1745. static const unsigned int drif1_data1_b_pins[] = {
  1746. /* D1 */
  1747. RCAR_GP_PIN(5, 8),
  1748. };
  1749. static const unsigned int drif1_data1_b_mux[] = {
  1750. RIF1_D1_B_MARK,
  1751. };
  1752. static const unsigned int drif1_ctrl_c_pins[] = {
  1753. /* CLK, SYNC */
  1754. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
  1755. };
  1756. static const unsigned int drif1_ctrl_c_mux[] = {
  1757. RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
  1758. };
  1759. static const unsigned int drif1_data0_c_pins[] = {
  1760. /* D0 */
  1761. RCAR_GP_PIN(5, 6),
  1762. };
  1763. static const unsigned int drif1_data0_c_mux[] = {
  1764. RIF1_D0_C_MARK,
  1765. };
  1766. static const unsigned int drif1_data1_c_pins[] = {
  1767. /* D1 */
  1768. RCAR_GP_PIN(5, 10),
  1769. };
  1770. static const unsigned int drif1_data1_c_mux[] = {
  1771. RIF1_D1_C_MARK,
  1772. };
  1773. /* - DRIF2 --------------------------------------------------------------- */
  1774. static const unsigned int drif2_ctrl_a_pins[] = {
  1775. /* CLK, SYNC */
  1776. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1777. };
  1778. static const unsigned int drif2_ctrl_a_mux[] = {
  1779. RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
  1780. };
  1781. static const unsigned int drif2_data0_a_pins[] = {
  1782. /* D0 */
  1783. RCAR_GP_PIN(6, 7),
  1784. };
  1785. static const unsigned int drif2_data0_a_mux[] = {
  1786. RIF2_D0_A_MARK,
  1787. };
  1788. static const unsigned int drif2_data1_a_pins[] = {
  1789. /* D1 */
  1790. RCAR_GP_PIN(6, 10),
  1791. };
  1792. static const unsigned int drif2_data1_a_mux[] = {
  1793. RIF2_D1_A_MARK,
  1794. };
  1795. static const unsigned int drif2_ctrl_b_pins[] = {
  1796. /* CLK, SYNC */
  1797. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  1798. };
  1799. static const unsigned int drif2_ctrl_b_mux[] = {
  1800. RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
  1801. };
  1802. static const unsigned int drif2_data0_b_pins[] = {
  1803. /* D0 */
  1804. RCAR_GP_PIN(6, 30),
  1805. };
  1806. static const unsigned int drif2_data0_b_mux[] = {
  1807. RIF2_D0_B_MARK,
  1808. };
  1809. static const unsigned int drif2_data1_b_pins[] = {
  1810. /* D1 */
  1811. RCAR_GP_PIN(6, 31),
  1812. };
  1813. static const unsigned int drif2_data1_b_mux[] = {
  1814. RIF2_D1_B_MARK,
  1815. };
  1816. /* - DRIF3 --------------------------------------------------------------- */
  1817. static const unsigned int drif3_ctrl_a_pins[] = {
  1818. /* CLK, SYNC */
  1819. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1820. };
  1821. static const unsigned int drif3_ctrl_a_mux[] = {
  1822. RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
  1823. };
  1824. static const unsigned int drif3_data0_a_pins[] = {
  1825. /* D0 */
  1826. RCAR_GP_PIN(6, 19),
  1827. };
  1828. static const unsigned int drif3_data0_a_mux[] = {
  1829. RIF3_D0_A_MARK,
  1830. };
  1831. static const unsigned int drif3_data1_a_pins[] = {
  1832. /* D1 */
  1833. RCAR_GP_PIN(6, 20),
  1834. };
  1835. static const unsigned int drif3_data1_a_mux[] = {
  1836. RIF3_D1_A_MARK,
  1837. };
  1838. static const unsigned int drif3_ctrl_b_pins[] = {
  1839. /* CLK, SYNC */
  1840. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  1841. };
  1842. static const unsigned int drif3_ctrl_b_mux[] = {
  1843. RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
  1844. };
  1845. static const unsigned int drif3_data0_b_pins[] = {
  1846. /* D0 */
  1847. RCAR_GP_PIN(6, 28),
  1848. };
  1849. static const unsigned int drif3_data0_b_mux[] = {
  1850. RIF3_D0_B_MARK,
  1851. };
  1852. static const unsigned int drif3_data1_b_pins[] = {
  1853. /* D1 */
  1854. RCAR_GP_PIN(6, 29),
  1855. };
  1856. static const unsigned int drif3_data1_b_mux[] = {
  1857. RIF3_D1_B_MARK,
  1858. };
  1859. /* - DU --------------------------------------------------------------------- */
  1860. static const unsigned int du_rgb666_pins[] = {
  1861. /* R[7:2], G[7:2], B[7:2] */
  1862. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1863. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1864. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1865. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1866. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1867. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1868. };
  1869. static const unsigned int du_rgb666_mux[] = {
  1870. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1871. DU_DR3_MARK, DU_DR2_MARK,
  1872. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1873. DU_DG3_MARK, DU_DG2_MARK,
  1874. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1875. DU_DB3_MARK, DU_DB2_MARK,
  1876. };
  1877. static const unsigned int du_rgb888_pins[] = {
  1878. /* R[7:0], G[7:0], B[7:0] */
  1879. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1880. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1881. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
  1882. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1883. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1884. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  1885. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1886. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1887. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
  1888. };
  1889. static const unsigned int du_rgb888_mux[] = {
  1890. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1891. DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
  1892. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1893. DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
  1894. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1895. DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
  1896. };
  1897. static const unsigned int du_clk_out_0_pins[] = {
  1898. /* CLKOUT */
  1899. RCAR_GP_PIN(1, 27),
  1900. };
  1901. static const unsigned int du_clk_out_0_mux[] = {
  1902. DU_DOTCLKOUT0_MARK
  1903. };
  1904. static const unsigned int du_clk_out_1_pins[] = {
  1905. /* CLKOUT */
  1906. RCAR_GP_PIN(2, 3),
  1907. };
  1908. static const unsigned int du_clk_out_1_mux[] = {
  1909. DU_DOTCLKOUT1_MARK
  1910. };
  1911. static const unsigned int du_sync_pins[] = {
  1912. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1913. RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
  1914. };
  1915. static const unsigned int du_sync_mux[] = {
  1916. DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
  1917. };
  1918. static const unsigned int du_oddf_pins[] = {
  1919. /* EXDISP/EXODDF/EXCDE */
  1920. RCAR_GP_PIN(2, 2),
  1921. };
  1922. static const unsigned int du_oddf_mux[] = {
  1923. DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
  1924. };
  1925. static const unsigned int du_cde_pins[] = {
  1926. /* CDE */
  1927. RCAR_GP_PIN(2, 0),
  1928. };
  1929. static const unsigned int du_cde_mux[] = {
  1930. DU_CDE_MARK,
  1931. };
  1932. static const unsigned int du_disp_pins[] = {
  1933. /* DISP */
  1934. RCAR_GP_PIN(2, 1),
  1935. };
  1936. static const unsigned int du_disp_mux[] = {
  1937. DU_DISP_MARK,
  1938. };
  1939. /* - HSCIF0 ----------------------------------------------------------------- */
  1940. static const unsigned int hscif0_data_pins[] = {
  1941. /* RX, TX */
  1942. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  1943. };
  1944. static const unsigned int hscif0_data_mux[] = {
  1945. HRX0_MARK, HTX0_MARK,
  1946. };
  1947. static const unsigned int hscif0_clk_pins[] = {
  1948. /* SCK */
  1949. RCAR_GP_PIN(5, 12),
  1950. };
  1951. static const unsigned int hscif0_clk_mux[] = {
  1952. HSCK0_MARK,
  1953. };
  1954. static const unsigned int hscif0_ctrl_pins[] = {
  1955. /* RTS, CTS */
  1956. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
  1957. };
  1958. static const unsigned int hscif0_ctrl_mux[] = {
  1959. HRTS0_N_MARK, HCTS0_N_MARK,
  1960. };
  1961. /* - HSCIF1 ----------------------------------------------------------------- */
  1962. static const unsigned int hscif1_data_a_pins[] = {
  1963. /* RX, TX */
  1964. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  1965. };
  1966. static const unsigned int hscif1_data_a_mux[] = {
  1967. HRX1_A_MARK, HTX1_A_MARK,
  1968. };
  1969. static const unsigned int hscif1_clk_a_pins[] = {
  1970. /* SCK */
  1971. RCAR_GP_PIN(6, 21),
  1972. };
  1973. static const unsigned int hscif1_clk_a_mux[] = {
  1974. HSCK1_A_MARK,
  1975. };
  1976. static const unsigned int hscif1_ctrl_a_pins[] = {
  1977. /* RTS, CTS */
  1978. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  1979. };
  1980. static const unsigned int hscif1_ctrl_a_mux[] = {
  1981. HRTS1_N_A_MARK, HCTS1_N_A_MARK,
  1982. };
  1983. static const unsigned int hscif1_data_b_pins[] = {
  1984. /* RX, TX */
  1985. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1986. };
  1987. static const unsigned int hscif1_data_b_mux[] = {
  1988. HRX1_B_MARK, HTX1_B_MARK,
  1989. };
  1990. static const unsigned int hscif1_clk_b_pins[] = {
  1991. /* SCK */
  1992. RCAR_GP_PIN(5, 0),
  1993. };
  1994. static const unsigned int hscif1_clk_b_mux[] = {
  1995. HSCK1_B_MARK,
  1996. };
  1997. static const unsigned int hscif1_ctrl_b_pins[] = {
  1998. /* RTS, CTS */
  1999. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  2000. };
  2001. static const unsigned int hscif1_ctrl_b_mux[] = {
  2002. HRTS1_N_B_MARK, HCTS1_N_B_MARK,
  2003. };
  2004. /* - HSCIF2 ----------------------------------------------------------------- */
  2005. static const unsigned int hscif2_data_a_pins[] = {
  2006. /* RX, TX */
  2007. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  2008. };
  2009. static const unsigned int hscif2_data_a_mux[] = {
  2010. HRX2_A_MARK, HTX2_A_MARK,
  2011. };
  2012. static const unsigned int hscif2_clk_a_pins[] = {
  2013. /* SCK */
  2014. RCAR_GP_PIN(6, 10),
  2015. };
  2016. static const unsigned int hscif2_clk_a_mux[] = {
  2017. HSCK2_A_MARK,
  2018. };
  2019. static const unsigned int hscif2_ctrl_a_pins[] = {
  2020. /* RTS, CTS */
  2021. RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
  2022. };
  2023. static const unsigned int hscif2_ctrl_a_mux[] = {
  2024. HRTS2_N_A_MARK, HCTS2_N_A_MARK,
  2025. };
  2026. static const unsigned int hscif2_data_b_pins[] = {
  2027. /* RX, TX */
  2028. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  2029. };
  2030. static const unsigned int hscif2_data_b_mux[] = {
  2031. HRX2_B_MARK, HTX2_B_MARK,
  2032. };
  2033. static const unsigned int hscif2_clk_b_pins[] = {
  2034. /* SCK */
  2035. RCAR_GP_PIN(6, 21),
  2036. };
  2037. static const unsigned int hscif2_clk_b_mux[] = {
  2038. HSCK2_B_MARK,
  2039. };
  2040. static const unsigned int hscif2_ctrl_b_pins[] = {
  2041. /* RTS, CTS */
  2042. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
  2043. };
  2044. static const unsigned int hscif2_ctrl_b_mux[] = {
  2045. HRTS2_N_B_MARK, HCTS2_N_B_MARK,
  2046. };
  2047. static const unsigned int hscif2_data_c_pins[] = {
  2048. /* RX, TX */
  2049. RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
  2050. };
  2051. static const unsigned int hscif2_data_c_mux[] = {
  2052. HRX2_C_MARK, HTX2_C_MARK,
  2053. };
  2054. static const unsigned int hscif2_clk_c_pins[] = {
  2055. /* SCK */
  2056. RCAR_GP_PIN(6, 24),
  2057. };
  2058. static const unsigned int hscif2_clk_c_mux[] = {
  2059. HSCK2_C_MARK,
  2060. };
  2061. static const unsigned int hscif2_ctrl_c_pins[] = {
  2062. /* RTS, CTS */
  2063. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
  2064. };
  2065. static const unsigned int hscif2_ctrl_c_mux[] = {
  2066. HRTS2_N_C_MARK, HCTS2_N_C_MARK,
  2067. };
  2068. /* - HSCIF3 ----------------------------------------------------------------- */
  2069. static const unsigned int hscif3_data_a_pins[] = {
  2070. /* RX, TX */
  2071. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  2072. };
  2073. static const unsigned int hscif3_data_a_mux[] = {
  2074. HRX3_A_MARK, HTX3_A_MARK,
  2075. };
  2076. static const unsigned int hscif3_clk_pins[] = {
  2077. /* SCK */
  2078. RCAR_GP_PIN(1, 22),
  2079. };
  2080. static const unsigned int hscif3_clk_mux[] = {
  2081. HSCK3_MARK,
  2082. };
  2083. static const unsigned int hscif3_ctrl_pins[] = {
  2084. /* RTS, CTS */
  2085. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2086. };
  2087. static const unsigned int hscif3_ctrl_mux[] = {
  2088. HRTS3_N_MARK, HCTS3_N_MARK,
  2089. };
  2090. static const unsigned int hscif3_data_b_pins[] = {
  2091. /* RX, TX */
  2092. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  2093. };
  2094. static const unsigned int hscif3_data_b_mux[] = {
  2095. HRX3_B_MARK, HTX3_B_MARK,
  2096. };
  2097. static const unsigned int hscif3_data_c_pins[] = {
  2098. /* RX, TX */
  2099. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2100. };
  2101. static const unsigned int hscif3_data_c_mux[] = {
  2102. HRX3_C_MARK, HTX3_C_MARK,
  2103. };
  2104. static const unsigned int hscif3_data_d_pins[] = {
  2105. /* RX, TX */
  2106. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2107. };
  2108. static const unsigned int hscif3_data_d_mux[] = {
  2109. HRX3_D_MARK, HTX3_D_MARK,
  2110. };
  2111. /* - HSCIF4 ----------------------------------------------------------------- */
  2112. static const unsigned int hscif4_data_a_pins[] = {
  2113. /* RX, TX */
  2114. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  2115. };
  2116. static const unsigned int hscif4_data_a_mux[] = {
  2117. HRX4_A_MARK, HTX4_A_MARK,
  2118. };
  2119. static const unsigned int hscif4_clk_pins[] = {
  2120. /* SCK */
  2121. RCAR_GP_PIN(1, 11),
  2122. };
  2123. static const unsigned int hscif4_clk_mux[] = {
  2124. HSCK4_MARK,
  2125. };
  2126. static const unsigned int hscif4_ctrl_pins[] = {
  2127. /* RTS, CTS */
  2128. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
  2129. };
  2130. static const unsigned int hscif4_ctrl_mux[] = {
  2131. HRTS4_N_MARK, HCTS4_N_MARK,
  2132. };
  2133. static const unsigned int hscif4_data_b_pins[] = {
  2134. /* RX, TX */
  2135. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2136. };
  2137. static const unsigned int hscif4_data_b_mux[] = {
  2138. HRX4_B_MARK, HTX4_B_MARK,
  2139. };
  2140. /* - I2C -------------------------------------------------------------------- */
  2141. static const unsigned int i2c0_pins[] = {
  2142. /* SCL, SDA */
  2143. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2144. };
  2145. static const unsigned int i2c0_mux[] = {
  2146. SCL0_MARK, SDA0_MARK,
  2147. };
  2148. static const unsigned int i2c1_a_pins[] = {
  2149. /* SDA, SCL */
  2150. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  2151. };
  2152. static const unsigned int i2c1_a_mux[] = {
  2153. SDA1_A_MARK, SCL1_A_MARK,
  2154. };
  2155. static const unsigned int i2c1_b_pins[] = {
  2156. /* SDA, SCL */
  2157. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
  2158. };
  2159. static const unsigned int i2c1_b_mux[] = {
  2160. SDA1_B_MARK, SCL1_B_MARK,
  2161. };
  2162. static const unsigned int i2c2_a_pins[] = {
  2163. /* SDA, SCL */
  2164. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  2165. };
  2166. static const unsigned int i2c2_a_mux[] = {
  2167. SDA2_A_MARK, SCL2_A_MARK,
  2168. };
  2169. static const unsigned int i2c2_b_pins[] = {
  2170. /* SDA, SCL */
  2171. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
  2172. };
  2173. static const unsigned int i2c2_b_mux[] = {
  2174. SDA2_B_MARK, SCL2_B_MARK,
  2175. };
  2176. static const unsigned int i2c3_pins[] = {
  2177. /* SCL, SDA */
  2178. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2179. };
  2180. static const unsigned int i2c3_mux[] = {
  2181. SCL3_MARK, SDA3_MARK,
  2182. };
  2183. static const unsigned int i2c5_pins[] = {
  2184. /* SCL, SDA */
  2185. RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
  2186. };
  2187. static const unsigned int i2c5_mux[] = {
  2188. SCL5_MARK, SDA5_MARK,
  2189. };
  2190. static const unsigned int i2c6_a_pins[] = {
  2191. /* SDA, SCL */
  2192. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2193. };
  2194. static const unsigned int i2c6_a_mux[] = {
  2195. SDA6_A_MARK, SCL6_A_MARK,
  2196. };
  2197. static const unsigned int i2c6_b_pins[] = {
  2198. /* SDA, SCL */
  2199. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2200. };
  2201. static const unsigned int i2c6_b_mux[] = {
  2202. SDA6_B_MARK, SCL6_B_MARK,
  2203. };
  2204. static const unsigned int i2c6_c_pins[] = {
  2205. /* SDA, SCL */
  2206. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
  2207. };
  2208. static const unsigned int i2c6_c_mux[] = {
  2209. SDA6_C_MARK, SCL6_C_MARK,
  2210. };
  2211. /* - INTC-EX ---------------------------------------------------------------- */
  2212. static const unsigned int intc_ex_irq0_pins[] = {
  2213. /* IRQ0 */
  2214. RCAR_GP_PIN(2, 0),
  2215. };
  2216. static const unsigned int intc_ex_irq0_mux[] = {
  2217. IRQ0_MARK,
  2218. };
  2219. static const unsigned int intc_ex_irq1_pins[] = {
  2220. /* IRQ1 */
  2221. RCAR_GP_PIN(2, 1),
  2222. };
  2223. static const unsigned int intc_ex_irq1_mux[] = {
  2224. IRQ1_MARK,
  2225. };
  2226. static const unsigned int intc_ex_irq2_pins[] = {
  2227. /* IRQ2 */
  2228. RCAR_GP_PIN(2, 2),
  2229. };
  2230. static const unsigned int intc_ex_irq2_mux[] = {
  2231. IRQ2_MARK,
  2232. };
  2233. static const unsigned int intc_ex_irq3_pins[] = {
  2234. /* IRQ3 */
  2235. RCAR_GP_PIN(2, 3),
  2236. };
  2237. static const unsigned int intc_ex_irq3_mux[] = {
  2238. IRQ3_MARK,
  2239. };
  2240. static const unsigned int intc_ex_irq4_pins[] = {
  2241. /* IRQ4 */
  2242. RCAR_GP_PIN(2, 4),
  2243. };
  2244. static const unsigned int intc_ex_irq4_mux[] = {
  2245. IRQ4_MARK,
  2246. };
  2247. static const unsigned int intc_ex_irq5_pins[] = {
  2248. /* IRQ5 */
  2249. RCAR_GP_PIN(2, 5),
  2250. };
  2251. static const unsigned int intc_ex_irq5_mux[] = {
  2252. IRQ5_MARK,
  2253. };
  2254. /* - MSIOF0 ----------------------------------------------------------------- */
  2255. static const unsigned int msiof0_clk_pins[] = {
  2256. /* SCK */
  2257. RCAR_GP_PIN(5, 17),
  2258. };
  2259. static const unsigned int msiof0_clk_mux[] = {
  2260. MSIOF0_SCK_MARK,
  2261. };
  2262. static const unsigned int msiof0_sync_pins[] = {
  2263. /* SYNC */
  2264. RCAR_GP_PIN(5, 18),
  2265. };
  2266. static const unsigned int msiof0_sync_mux[] = {
  2267. MSIOF0_SYNC_MARK,
  2268. };
  2269. static const unsigned int msiof0_ss1_pins[] = {
  2270. /* SS1 */
  2271. RCAR_GP_PIN(5, 19),
  2272. };
  2273. static const unsigned int msiof0_ss1_mux[] = {
  2274. MSIOF0_SS1_MARK,
  2275. };
  2276. static const unsigned int msiof0_ss2_pins[] = {
  2277. /* SS2 */
  2278. RCAR_GP_PIN(5, 21),
  2279. };
  2280. static const unsigned int msiof0_ss2_mux[] = {
  2281. MSIOF0_SS2_MARK,
  2282. };
  2283. static const unsigned int msiof0_txd_pins[] = {
  2284. /* TXD */
  2285. RCAR_GP_PIN(5, 20),
  2286. };
  2287. static const unsigned int msiof0_txd_mux[] = {
  2288. MSIOF0_TXD_MARK,
  2289. };
  2290. static const unsigned int msiof0_rxd_pins[] = {
  2291. /* RXD */
  2292. RCAR_GP_PIN(5, 22),
  2293. };
  2294. static const unsigned int msiof0_rxd_mux[] = {
  2295. MSIOF0_RXD_MARK,
  2296. };
  2297. /* - MSIOF1 ----------------------------------------------------------------- */
  2298. static const unsigned int msiof1_clk_a_pins[] = {
  2299. /* SCK */
  2300. RCAR_GP_PIN(6, 8),
  2301. };
  2302. static const unsigned int msiof1_clk_a_mux[] = {
  2303. MSIOF1_SCK_A_MARK,
  2304. };
  2305. static const unsigned int msiof1_sync_a_pins[] = {
  2306. /* SYNC */
  2307. RCAR_GP_PIN(6, 9),
  2308. };
  2309. static const unsigned int msiof1_sync_a_mux[] = {
  2310. MSIOF1_SYNC_A_MARK,
  2311. };
  2312. static const unsigned int msiof1_ss1_a_pins[] = {
  2313. /* SS1 */
  2314. RCAR_GP_PIN(6, 5),
  2315. };
  2316. static const unsigned int msiof1_ss1_a_mux[] = {
  2317. MSIOF1_SS1_A_MARK,
  2318. };
  2319. static const unsigned int msiof1_ss2_a_pins[] = {
  2320. /* SS2 */
  2321. RCAR_GP_PIN(6, 6),
  2322. };
  2323. static const unsigned int msiof1_ss2_a_mux[] = {
  2324. MSIOF1_SS2_A_MARK,
  2325. };
  2326. static const unsigned int msiof1_txd_a_pins[] = {
  2327. /* TXD */
  2328. RCAR_GP_PIN(6, 7),
  2329. };
  2330. static const unsigned int msiof1_txd_a_mux[] = {
  2331. MSIOF1_TXD_A_MARK,
  2332. };
  2333. static const unsigned int msiof1_rxd_a_pins[] = {
  2334. /* RXD */
  2335. RCAR_GP_PIN(6, 10),
  2336. };
  2337. static const unsigned int msiof1_rxd_a_mux[] = {
  2338. MSIOF1_RXD_A_MARK,
  2339. };
  2340. static const unsigned int msiof1_clk_b_pins[] = {
  2341. /* SCK */
  2342. RCAR_GP_PIN(5, 9),
  2343. };
  2344. static const unsigned int msiof1_clk_b_mux[] = {
  2345. MSIOF1_SCK_B_MARK,
  2346. };
  2347. static const unsigned int msiof1_sync_b_pins[] = {
  2348. /* SYNC */
  2349. RCAR_GP_PIN(5, 3),
  2350. };
  2351. static const unsigned int msiof1_sync_b_mux[] = {
  2352. MSIOF1_SYNC_B_MARK,
  2353. };
  2354. static const unsigned int msiof1_ss1_b_pins[] = {
  2355. /* SS1 */
  2356. RCAR_GP_PIN(5, 4),
  2357. };
  2358. static const unsigned int msiof1_ss1_b_mux[] = {
  2359. MSIOF1_SS1_B_MARK,
  2360. };
  2361. static const unsigned int msiof1_ss2_b_pins[] = {
  2362. /* SS2 */
  2363. RCAR_GP_PIN(5, 0),
  2364. };
  2365. static const unsigned int msiof1_ss2_b_mux[] = {
  2366. MSIOF1_SS2_B_MARK,
  2367. };
  2368. static const unsigned int msiof1_txd_b_pins[] = {
  2369. /* TXD */
  2370. RCAR_GP_PIN(5, 8),
  2371. };
  2372. static const unsigned int msiof1_txd_b_mux[] = {
  2373. MSIOF1_TXD_B_MARK,
  2374. };
  2375. static const unsigned int msiof1_rxd_b_pins[] = {
  2376. /* RXD */
  2377. RCAR_GP_PIN(5, 7),
  2378. };
  2379. static const unsigned int msiof1_rxd_b_mux[] = {
  2380. MSIOF1_RXD_B_MARK,
  2381. };
  2382. static const unsigned int msiof1_clk_c_pins[] = {
  2383. /* SCK */
  2384. RCAR_GP_PIN(6, 17),
  2385. };
  2386. static const unsigned int msiof1_clk_c_mux[] = {
  2387. MSIOF1_SCK_C_MARK,
  2388. };
  2389. static const unsigned int msiof1_sync_c_pins[] = {
  2390. /* SYNC */
  2391. RCAR_GP_PIN(6, 18),
  2392. };
  2393. static const unsigned int msiof1_sync_c_mux[] = {
  2394. MSIOF1_SYNC_C_MARK,
  2395. };
  2396. static const unsigned int msiof1_ss1_c_pins[] = {
  2397. /* SS1 */
  2398. RCAR_GP_PIN(6, 21),
  2399. };
  2400. static const unsigned int msiof1_ss1_c_mux[] = {
  2401. MSIOF1_SS1_C_MARK,
  2402. };
  2403. static const unsigned int msiof1_ss2_c_pins[] = {
  2404. /* SS2 */
  2405. RCAR_GP_PIN(6, 27),
  2406. };
  2407. static const unsigned int msiof1_ss2_c_mux[] = {
  2408. MSIOF1_SS2_C_MARK,
  2409. };
  2410. static const unsigned int msiof1_txd_c_pins[] = {
  2411. /* TXD */
  2412. RCAR_GP_PIN(6, 20),
  2413. };
  2414. static const unsigned int msiof1_txd_c_mux[] = {
  2415. MSIOF1_TXD_C_MARK,
  2416. };
  2417. static const unsigned int msiof1_rxd_c_pins[] = {
  2418. /* RXD */
  2419. RCAR_GP_PIN(6, 19),
  2420. };
  2421. static const unsigned int msiof1_rxd_c_mux[] = {
  2422. MSIOF1_RXD_C_MARK,
  2423. };
  2424. static const unsigned int msiof1_clk_d_pins[] = {
  2425. /* SCK */
  2426. RCAR_GP_PIN(5, 12),
  2427. };
  2428. static const unsigned int msiof1_clk_d_mux[] = {
  2429. MSIOF1_SCK_D_MARK,
  2430. };
  2431. static const unsigned int msiof1_sync_d_pins[] = {
  2432. /* SYNC */
  2433. RCAR_GP_PIN(5, 15),
  2434. };
  2435. static const unsigned int msiof1_sync_d_mux[] = {
  2436. MSIOF1_SYNC_D_MARK,
  2437. };
  2438. static const unsigned int msiof1_ss1_d_pins[] = {
  2439. /* SS1 */
  2440. RCAR_GP_PIN(5, 16),
  2441. };
  2442. static const unsigned int msiof1_ss1_d_mux[] = {
  2443. MSIOF1_SS1_D_MARK,
  2444. };
  2445. static const unsigned int msiof1_ss2_d_pins[] = {
  2446. /* SS2 */
  2447. RCAR_GP_PIN(5, 21),
  2448. };
  2449. static const unsigned int msiof1_ss2_d_mux[] = {
  2450. MSIOF1_SS2_D_MARK,
  2451. };
  2452. static const unsigned int msiof1_txd_d_pins[] = {
  2453. /* TXD */
  2454. RCAR_GP_PIN(5, 14),
  2455. };
  2456. static const unsigned int msiof1_txd_d_mux[] = {
  2457. MSIOF1_TXD_D_MARK,
  2458. };
  2459. static const unsigned int msiof1_rxd_d_pins[] = {
  2460. /* RXD */
  2461. RCAR_GP_PIN(5, 13),
  2462. };
  2463. static const unsigned int msiof1_rxd_d_mux[] = {
  2464. MSIOF1_RXD_D_MARK,
  2465. };
  2466. static const unsigned int msiof1_clk_e_pins[] = {
  2467. /* SCK */
  2468. RCAR_GP_PIN(3, 0),
  2469. };
  2470. static const unsigned int msiof1_clk_e_mux[] = {
  2471. MSIOF1_SCK_E_MARK,
  2472. };
  2473. static const unsigned int msiof1_sync_e_pins[] = {
  2474. /* SYNC */
  2475. RCAR_GP_PIN(3, 1),
  2476. };
  2477. static const unsigned int msiof1_sync_e_mux[] = {
  2478. MSIOF1_SYNC_E_MARK,
  2479. };
  2480. static const unsigned int msiof1_ss1_e_pins[] = {
  2481. /* SS1 */
  2482. RCAR_GP_PIN(3, 4),
  2483. };
  2484. static const unsigned int msiof1_ss1_e_mux[] = {
  2485. MSIOF1_SS1_E_MARK,
  2486. };
  2487. static const unsigned int msiof1_ss2_e_pins[] = {
  2488. /* SS2 */
  2489. RCAR_GP_PIN(3, 5),
  2490. };
  2491. static const unsigned int msiof1_ss2_e_mux[] = {
  2492. MSIOF1_SS2_E_MARK,
  2493. };
  2494. static const unsigned int msiof1_txd_e_pins[] = {
  2495. /* TXD */
  2496. RCAR_GP_PIN(3, 3),
  2497. };
  2498. static const unsigned int msiof1_txd_e_mux[] = {
  2499. MSIOF1_TXD_E_MARK,
  2500. };
  2501. static const unsigned int msiof1_rxd_e_pins[] = {
  2502. /* RXD */
  2503. RCAR_GP_PIN(3, 2),
  2504. };
  2505. static const unsigned int msiof1_rxd_e_mux[] = {
  2506. MSIOF1_RXD_E_MARK,
  2507. };
  2508. static const unsigned int msiof1_clk_f_pins[] = {
  2509. /* SCK */
  2510. RCAR_GP_PIN(5, 23),
  2511. };
  2512. static const unsigned int msiof1_clk_f_mux[] = {
  2513. MSIOF1_SCK_F_MARK,
  2514. };
  2515. static const unsigned int msiof1_sync_f_pins[] = {
  2516. /* SYNC */
  2517. RCAR_GP_PIN(5, 24),
  2518. };
  2519. static const unsigned int msiof1_sync_f_mux[] = {
  2520. MSIOF1_SYNC_F_MARK,
  2521. };
  2522. static const unsigned int msiof1_ss1_f_pins[] = {
  2523. /* SS1 */
  2524. RCAR_GP_PIN(6, 1),
  2525. };
  2526. static const unsigned int msiof1_ss1_f_mux[] = {
  2527. MSIOF1_SS1_F_MARK,
  2528. };
  2529. static const unsigned int msiof1_ss2_f_pins[] = {
  2530. /* SS2 */
  2531. RCAR_GP_PIN(6, 2),
  2532. };
  2533. static const unsigned int msiof1_ss2_f_mux[] = {
  2534. MSIOF1_SS2_F_MARK,
  2535. };
  2536. static const unsigned int msiof1_txd_f_pins[] = {
  2537. /* TXD */
  2538. RCAR_GP_PIN(6, 0),
  2539. };
  2540. static const unsigned int msiof1_txd_f_mux[] = {
  2541. MSIOF1_TXD_F_MARK,
  2542. };
  2543. static const unsigned int msiof1_rxd_f_pins[] = {
  2544. /* RXD */
  2545. RCAR_GP_PIN(5, 25),
  2546. };
  2547. static const unsigned int msiof1_rxd_f_mux[] = {
  2548. MSIOF1_RXD_F_MARK,
  2549. };
  2550. static const unsigned int msiof1_clk_g_pins[] = {
  2551. /* SCK */
  2552. RCAR_GP_PIN(3, 6),
  2553. };
  2554. static const unsigned int msiof1_clk_g_mux[] = {
  2555. MSIOF1_SCK_G_MARK,
  2556. };
  2557. static const unsigned int msiof1_sync_g_pins[] = {
  2558. /* SYNC */
  2559. RCAR_GP_PIN(3, 7),
  2560. };
  2561. static const unsigned int msiof1_sync_g_mux[] = {
  2562. MSIOF1_SYNC_G_MARK,
  2563. };
  2564. static const unsigned int msiof1_ss1_g_pins[] = {
  2565. /* SS1 */
  2566. RCAR_GP_PIN(3, 10),
  2567. };
  2568. static const unsigned int msiof1_ss1_g_mux[] = {
  2569. MSIOF1_SS1_G_MARK,
  2570. };
  2571. static const unsigned int msiof1_ss2_g_pins[] = {
  2572. /* SS2 */
  2573. RCAR_GP_PIN(3, 11),
  2574. };
  2575. static const unsigned int msiof1_ss2_g_mux[] = {
  2576. MSIOF1_SS2_G_MARK,
  2577. };
  2578. static const unsigned int msiof1_txd_g_pins[] = {
  2579. /* TXD */
  2580. RCAR_GP_PIN(3, 9),
  2581. };
  2582. static const unsigned int msiof1_txd_g_mux[] = {
  2583. MSIOF1_TXD_G_MARK,
  2584. };
  2585. static const unsigned int msiof1_rxd_g_pins[] = {
  2586. /* RXD */
  2587. RCAR_GP_PIN(3, 8),
  2588. };
  2589. static const unsigned int msiof1_rxd_g_mux[] = {
  2590. MSIOF1_RXD_G_MARK,
  2591. };
  2592. /* - MSIOF2 ----------------------------------------------------------------- */
  2593. static const unsigned int msiof2_clk_a_pins[] = {
  2594. /* SCK */
  2595. RCAR_GP_PIN(1, 9),
  2596. };
  2597. static const unsigned int msiof2_clk_a_mux[] = {
  2598. MSIOF2_SCK_A_MARK,
  2599. };
  2600. static const unsigned int msiof2_sync_a_pins[] = {
  2601. /* SYNC */
  2602. RCAR_GP_PIN(1, 8),
  2603. };
  2604. static const unsigned int msiof2_sync_a_mux[] = {
  2605. MSIOF2_SYNC_A_MARK,
  2606. };
  2607. static const unsigned int msiof2_ss1_a_pins[] = {
  2608. /* SS1 */
  2609. RCAR_GP_PIN(1, 6),
  2610. };
  2611. static const unsigned int msiof2_ss1_a_mux[] = {
  2612. MSIOF2_SS1_A_MARK,
  2613. };
  2614. static const unsigned int msiof2_ss2_a_pins[] = {
  2615. /* SS2 */
  2616. RCAR_GP_PIN(1, 7),
  2617. };
  2618. static const unsigned int msiof2_ss2_a_mux[] = {
  2619. MSIOF2_SS2_A_MARK,
  2620. };
  2621. static const unsigned int msiof2_txd_a_pins[] = {
  2622. /* TXD */
  2623. RCAR_GP_PIN(1, 11),
  2624. };
  2625. static const unsigned int msiof2_txd_a_mux[] = {
  2626. MSIOF2_TXD_A_MARK,
  2627. };
  2628. static const unsigned int msiof2_rxd_a_pins[] = {
  2629. /* RXD */
  2630. RCAR_GP_PIN(1, 10),
  2631. };
  2632. static const unsigned int msiof2_rxd_a_mux[] = {
  2633. MSIOF2_RXD_A_MARK,
  2634. };
  2635. static const unsigned int msiof2_clk_b_pins[] = {
  2636. /* SCK */
  2637. RCAR_GP_PIN(0, 4),
  2638. };
  2639. static const unsigned int msiof2_clk_b_mux[] = {
  2640. MSIOF2_SCK_B_MARK,
  2641. };
  2642. static const unsigned int msiof2_sync_b_pins[] = {
  2643. /* SYNC */
  2644. RCAR_GP_PIN(0, 5),
  2645. };
  2646. static const unsigned int msiof2_sync_b_mux[] = {
  2647. MSIOF2_SYNC_B_MARK,
  2648. };
  2649. static const unsigned int msiof2_ss1_b_pins[] = {
  2650. /* SS1 */
  2651. RCAR_GP_PIN(0, 0),
  2652. };
  2653. static const unsigned int msiof2_ss1_b_mux[] = {
  2654. MSIOF2_SS1_B_MARK,
  2655. };
  2656. static const unsigned int msiof2_ss2_b_pins[] = {
  2657. /* SS2 */
  2658. RCAR_GP_PIN(0, 1),
  2659. };
  2660. static const unsigned int msiof2_ss2_b_mux[] = {
  2661. MSIOF2_SS2_B_MARK,
  2662. };
  2663. static const unsigned int msiof2_txd_b_pins[] = {
  2664. /* TXD */
  2665. RCAR_GP_PIN(0, 7),
  2666. };
  2667. static const unsigned int msiof2_txd_b_mux[] = {
  2668. MSIOF2_TXD_B_MARK,
  2669. };
  2670. static const unsigned int msiof2_rxd_b_pins[] = {
  2671. /* RXD */
  2672. RCAR_GP_PIN(0, 6),
  2673. };
  2674. static const unsigned int msiof2_rxd_b_mux[] = {
  2675. MSIOF2_RXD_B_MARK,
  2676. };
  2677. static const unsigned int msiof2_clk_c_pins[] = {
  2678. /* SCK */
  2679. RCAR_GP_PIN(2, 12),
  2680. };
  2681. static const unsigned int msiof2_clk_c_mux[] = {
  2682. MSIOF2_SCK_C_MARK,
  2683. };
  2684. static const unsigned int msiof2_sync_c_pins[] = {
  2685. /* SYNC */
  2686. RCAR_GP_PIN(2, 11),
  2687. };
  2688. static const unsigned int msiof2_sync_c_mux[] = {
  2689. MSIOF2_SYNC_C_MARK,
  2690. };
  2691. static const unsigned int msiof2_ss1_c_pins[] = {
  2692. /* SS1 */
  2693. RCAR_GP_PIN(2, 10),
  2694. };
  2695. static const unsigned int msiof2_ss1_c_mux[] = {
  2696. MSIOF2_SS1_C_MARK,
  2697. };
  2698. static const unsigned int msiof2_ss2_c_pins[] = {
  2699. /* SS2 */
  2700. RCAR_GP_PIN(2, 9),
  2701. };
  2702. static const unsigned int msiof2_ss2_c_mux[] = {
  2703. MSIOF2_SS2_C_MARK,
  2704. };
  2705. static const unsigned int msiof2_txd_c_pins[] = {
  2706. /* TXD */
  2707. RCAR_GP_PIN(2, 14),
  2708. };
  2709. static const unsigned int msiof2_txd_c_mux[] = {
  2710. MSIOF2_TXD_C_MARK,
  2711. };
  2712. static const unsigned int msiof2_rxd_c_pins[] = {
  2713. /* RXD */
  2714. RCAR_GP_PIN(2, 13),
  2715. };
  2716. static const unsigned int msiof2_rxd_c_mux[] = {
  2717. MSIOF2_RXD_C_MARK,
  2718. };
  2719. static const unsigned int msiof2_clk_d_pins[] = {
  2720. /* SCK */
  2721. RCAR_GP_PIN(0, 8),
  2722. };
  2723. static const unsigned int msiof2_clk_d_mux[] = {
  2724. MSIOF2_SCK_D_MARK,
  2725. };
  2726. static const unsigned int msiof2_sync_d_pins[] = {
  2727. /* SYNC */
  2728. RCAR_GP_PIN(0, 9),
  2729. };
  2730. static const unsigned int msiof2_sync_d_mux[] = {
  2731. MSIOF2_SYNC_D_MARK,
  2732. };
  2733. static const unsigned int msiof2_ss1_d_pins[] = {
  2734. /* SS1 */
  2735. RCAR_GP_PIN(0, 12),
  2736. };
  2737. static const unsigned int msiof2_ss1_d_mux[] = {
  2738. MSIOF2_SS1_D_MARK,
  2739. };
  2740. static const unsigned int msiof2_ss2_d_pins[] = {
  2741. /* SS2 */
  2742. RCAR_GP_PIN(0, 13),
  2743. };
  2744. static const unsigned int msiof2_ss2_d_mux[] = {
  2745. MSIOF2_SS2_D_MARK,
  2746. };
  2747. static const unsigned int msiof2_txd_d_pins[] = {
  2748. /* TXD */
  2749. RCAR_GP_PIN(0, 11),
  2750. };
  2751. static const unsigned int msiof2_txd_d_mux[] = {
  2752. MSIOF2_TXD_D_MARK,
  2753. };
  2754. static const unsigned int msiof2_rxd_d_pins[] = {
  2755. /* RXD */
  2756. RCAR_GP_PIN(0, 10),
  2757. };
  2758. static const unsigned int msiof2_rxd_d_mux[] = {
  2759. MSIOF2_RXD_D_MARK,
  2760. };
  2761. /* - MSIOF3 ----------------------------------------------------------------- */
  2762. static const unsigned int msiof3_clk_a_pins[] = {
  2763. /* SCK */
  2764. RCAR_GP_PIN(0, 0),
  2765. };
  2766. static const unsigned int msiof3_clk_a_mux[] = {
  2767. MSIOF3_SCK_A_MARK,
  2768. };
  2769. static const unsigned int msiof3_sync_a_pins[] = {
  2770. /* SYNC */
  2771. RCAR_GP_PIN(0, 1),
  2772. };
  2773. static const unsigned int msiof3_sync_a_mux[] = {
  2774. MSIOF3_SYNC_A_MARK,
  2775. };
  2776. static const unsigned int msiof3_ss1_a_pins[] = {
  2777. /* SS1 */
  2778. RCAR_GP_PIN(0, 14),
  2779. };
  2780. static const unsigned int msiof3_ss1_a_mux[] = {
  2781. MSIOF3_SS1_A_MARK,
  2782. };
  2783. static const unsigned int msiof3_ss2_a_pins[] = {
  2784. /* SS2 */
  2785. RCAR_GP_PIN(0, 15),
  2786. };
  2787. static const unsigned int msiof3_ss2_a_mux[] = {
  2788. MSIOF3_SS2_A_MARK,
  2789. };
  2790. static const unsigned int msiof3_txd_a_pins[] = {
  2791. /* TXD */
  2792. RCAR_GP_PIN(0, 3),
  2793. };
  2794. static const unsigned int msiof3_txd_a_mux[] = {
  2795. MSIOF3_TXD_A_MARK,
  2796. };
  2797. static const unsigned int msiof3_rxd_a_pins[] = {
  2798. /* RXD */
  2799. RCAR_GP_PIN(0, 2),
  2800. };
  2801. static const unsigned int msiof3_rxd_a_mux[] = {
  2802. MSIOF3_RXD_A_MARK,
  2803. };
  2804. static const unsigned int msiof3_clk_b_pins[] = {
  2805. /* SCK */
  2806. RCAR_GP_PIN(1, 2),
  2807. };
  2808. static const unsigned int msiof3_clk_b_mux[] = {
  2809. MSIOF3_SCK_B_MARK,
  2810. };
  2811. static const unsigned int msiof3_sync_b_pins[] = {
  2812. /* SYNC */
  2813. RCAR_GP_PIN(1, 0),
  2814. };
  2815. static const unsigned int msiof3_sync_b_mux[] = {
  2816. MSIOF3_SYNC_B_MARK,
  2817. };
  2818. static const unsigned int msiof3_ss1_b_pins[] = {
  2819. /* SS1 */
  2820. RCAR_GP_PIN(1, 4),
  2821. };
  2822. static const unsigned int msiof3_ss1_b_mux[] = {
  2823. MSIOF3_SS1_B_MARK,
  2824. };
  2825. static const unsigned int msiof3_ss2_b_pins[] = {
  2826. /* SS2 */
  2827. RCAR_GP_PIN(1, 5),
  2828. };
  2829. static const unsigned int msiof3_ss2_b_mux[] = {
  2830. MSIOF3_SS2_B_MARK,
  2831. };
  2832. static const unsigned int msiof3_txd_b_pins[] = {
  2833. /* TXD */
  2834. RCAR_GP_PIN(1, 1),
  2835. };
  2836. static const unsigned int msiof3_txd_b_mux[] = {
  2837. MSIOF3_TXD_B_MARK,
  2838. };
  2839. static const unsigned int msiof3_rxd_b_pins[] = {
  2840. /* RXD */
  2841. RCAR_GP_PIN(1, 3),
  2842. };
  2843. static const unsigned int msiof3_rxd_b_mux[] = {
  2844. MSIOF3_RXD_B_MARK,
  2845. };
  2846. static const unsigned int msiof3_clk_c_pins[] = {
  2847. /* SCK */
  2848. RCAR_GP_PIN(1, 12),
  2849. };
  2850. static const unsigned int msiof3_clk_c_mux[] = {
  2851. MSIOF3_SCK_C_MARK,
  2852. };
  2853. static const unsigned int msiof3_sync_c_pins[] = {
  2854. /* SYNC */
  2855. RCAR_GP_PIN(1, 13),
  2856. };
  2857. static const unsigned int msiof3_sync_c_mux[] = {
  2858. MSIOF3_SYNC_C_MARK,
  2859. };
  2860. static const unsigned int msiof3_txd_c_pins[] = {
  2861. /* TXD */
  2862. RCAR_GP_PIN(1, 15),
  2863. };
  2864. static const unsigned int msiof3_txd_c_mux[] = {
  2865. MSIOF3_TXD_C_MARK,
  2866. };
  2867. static const unsigned int msiof3_rxd_c_pins[] = {
  2868. /* RXD */
  2869. RCAR_GP_PIN(1, 14),
  2870. };
  2871. static const unsigned int msiof3_rxd_c_mux[] = {
  2872. MSIOF3_RXD_C_MARK,
  2873. };
  2874. static const unsigned int msiof3_clk_d_pins[] = {
  2875. /* SCK */
  2876. RCAR_GP_PIN(1, 22),
  2877. };
  2878. static const unsigned int msiof3_clk_d_mux[] = {
  2879. MSIOF3_SCK_D_MARK,
  2880. };
  2881. static const unsigned int msiof3_sync_d_pins[] = {
  2882. /* SYNC */
  2883. RCAR_GP_PIN(1, 23),
  2884. };
  2885. static const unsigned int msiof3_sync_d_mux[] = {
  2886. MSIOF3_SYNC_D_MARK,
  2887. };
  2888. static const unsigned int msiof3_ss1_d_pins[] = {
  2889. /* SS1 */
  2890. RCAR_GP_PIN(1, 26),
  2891. };
  2892. static const unsigned int msiof3_ss1_d_mux[] = {
  2893. MSIOF3_SS1_D_MARK,
  2894. };
  2895. static const unsigned int msiof3_txd_d_pins[] = {
  2896. /* TXD */
  2897. RCAR_GP_PIN(1, 25),
  2898. };
  2899. static const unsigned int msiof3_txd_d_mux[] = {
  2900. MSIOF3_TXD_D_MARK,
  2901. };
  2902. static const unsigned int msiof3_rxd_d_pins[] = {
  2903. /* RXD */
  2904. RCAR_GP_PIN(1, 24),
  2905. };
  2906. static const unsigned int msiof3_rxd_d_mux[] = {
  2907. MSIOF3_RXD_D_MARK,
  2908. };
  2909. static const unsigned int msiof3_clk_e_pins[] = {
  2910. /* SCK */
  2911. RCAR_GP_PIN(2, 3),
  2912. };
  2913. static const unsigned int msiof3_clk_e_mux[] = {
  2914. MSIOF3_SCK_E_MARK,
  2915. };
  2916. static const unsigned int msiof3_sync_e_pins[] = {
  2917. /* SYNC */
  2918. RCAR_GP_PIN(2, 2),
  2919. };
  2920. static const unsigned int msiof3_sync_e_mux[] = {
  2921. MSIOF3_SYNC_E_MARK,
  2922. };
  2923. static const unsigned int msiof3_ss1_e_pins[] = {
  2924. /* SS1 */
  2925. RCAR_GP_PIN(2, 1),
  2926. };
  2927. static const unsigned int msiof3_ss1_e_mux[] = {
  2928. MSIOF3_SS1_E_MARK,
  2929. };
  2930. static const unsigned int msiof3_ss2_e_pins[] = {
  2931. /* SS2 */
  2932. RCAR_GP_PIN(2, 0),
  2933. };
  2934. static const unsigned int msiof3_ss2_e_mux[] = {
  2935. MSIOF3_SS2_E_MARK,
  2936. };
  2937. static const unsigned int msiof3_txd_e_pins[] = {
  2938. /* TXD */
  2939. RCAR_GP_PIN(2, 5),
  2940. };
  2941. static const unsigned int msiof3_txd_e_mux[] = {
  2942. MSIOF3_TXD_E_MARK,
  2943. };
  2944. static const unsigned int msiof3_rxd_e_pins[] = {
  2945. /* RXD */
  2946. RCAR_GP_PIN(2, 4),
  2947. };
  2948. static const unsigned int msiof3_rxd_e_mux[] = {
  2949. MSIOF3_RXD_E_MARK,
  2950. };
  2951. /* - PWM0 --------------------------------------------------------------------*/
  2952. static const unsigned int pwm0_pins[] = {
  2953. /* PWM */
  2954. RCAR_GP_PIN(2, 6),
  2955. };
  2956. static const unsigned int pwm0_mux[] = {
  2957. PWM0_MARK,
  2958. };
  2959. /* - PWM1 --------------------------------------------------------------------*/
  2960. static const unsigned int pwm1_a_pins[] = {
  2961. /* PWM */
  2962. RCAR_GP_PIN(2, 7),
  2963. };
  2964. static const unsigned int pwm1_a_mux[] = {
  2965. PWM1_A_MARK,
  2966. };
  2967. static const unsigned int pwm1_b_pins[] = {
  2968. /* PWM */
  2969. RCAR_GP_PIN(1, 8),
  2970. };
  2971. static const unsigned int pwm1_b_mux[] = {
  2972. PWM1_B_MARK,
  2973. };
  2974. /* - PWM2 --------------------------------------------------------------------*/
  2975. static const unsigned int pwm2_a_pins[] = {
  2976. /* PWM */
  2977. RCAR_GP_PIN(2, 8),
  2978. };
  2979. static const unsigned int pwm2_a_mux[] = {
  2980. PWM2_A_MARK,
  2981. };
  2982. static const unsigned int pwm2_b_pins[] = {
  2983. /* PWM */
  2984. RCAR_GP_PIN(1, 11),
  2985. };
  2986. static const unsigned int pwm2_b_mux[] = {
  2987. PWM2_B_MARK,
  2988. };
  2989. /* - PWM3 --------------------------------------------------------------------*/
  2990. static const unsigned int pwm3_a_pins[] = {
  2991. /* PWM */
  2992. RCAR_GP_PIN(1, 0),
  2993. };
  2994. static const unsigned int pwm3_a_mux[] = {
  2995. PWM3_A_MARK,
  2996. };
  2997. static const unsigned int pwm3_b_pins[] = {
  2998. /* PWM */
  2999. RCAR_GP_PIN(2, 2),
  3000. };
  3001. static const unsigned int pwm3_b_mux[] = {
  3002. PWM3_B_MARK,
  3003. };
  3004. /* - PWM4 --------------------------------------------------------------------*/
  3005. static const unsigned int pwm4_a_pins[] = {
  3006. /* PWM */
  3007. RCAR_GP_PIN(1, 1),
  3008. };
  3009. static const unsigned int pwm4_a_mux[] = {
  3010. PWM4_A_MARK,
  3011. };
  3012. static const unsigned int pwm4_b_pins[] = {
  3013. /* PWM */
  3014. RCAR_GP_PIN(2, 3),
  3015. };
  3016. static const unsigned int pwm4_b_mux[] = {
  3017. PWM4_B_MARK,
  3018. };
  3019. /* - PWM5 --------------------------------------------------------------------*/
  3020. static const unsigned int pwm5_a_pins[] = {
  3021. /* PWM */
  3022. RCAR_GP_PIN(1, 2),
  3023. };
  3024. static const unsigned int pwm5_a_mux[] = {
  3025. PWM5_A_MARK,
  3026. };
  3027. static const unsigned int pwm5_b_pins[] = {
  3028. /* PWM */
  3029. RCAR_GP_PIN(2, 4),
  3030. };
  3031. static const unsigned int pwm5_b_mux[] = {
  3032. PWM5_B_MARK,
  3033. };
  3034. /* - PWM6 --------------------------------------------------------------------*/
  3035. static const unsigned int pwm6_a_pins[] = {
  3036. /* PWM */
  3037. RCAR_GP_PIN(1, 3),
  3038. };
  3039. static const unsigned int pwm6_a_mux[] = {
  3040. PWM6_A_MARK,
  3041. };
  3042. static const unsigned int pwm6_b_pins[] = {
  3043. /* PWM */
  3044. RCAR_GP_PIN(2, 5),
  3045. };
  3046. static const unsigned int pwm6_b_mux[] = {
  3047. PWM6_B_MARK,
  3048. };
  3049. /* - SCIF0 ------------------------------------------------------------------ */
  3050. static const unsigned int scif0_data_pins[] = {
  3051. /* RX, TX */
  3052. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  3053. };
  3054. static const unsigned int scif0_data_mux[] = {
  3055. RX0_MARK, TX0_MARK,
  3056. };
  3057. static const unsigned int scif0_clk_pins[] = {
  3058. /* SCK */
  3059. RCAR_GP_PIN(5, 0),
  3060. };
  3061. static const unsigned int scif0_clk_mux[] = {
  3062. SCK0_MARK,
  3063. };
  3064. static const unsigned int scif0_ctrl_pins[] = {
  3065. /* RTS, CTS */
  3066. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  3067. };
  3068. static const unsigned int scif0_ctrl_mux[] = {
  3069. RTS0_N_MARK, CTS0_N_MARK,
  3070. };
  3071. /* - SCIF1 ------------------------------------------------------------------ */
  3072. static const unsigned int scif1_data_a_pins[] = {
  3073. /* RX, TX */
  3074. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  3075. };
  3076. static const unsigned int scif1_data_a_mux[] = {
  3077. RX1_A_MARK, TX1_A_MARK,
  3078. };
  3079. static const unsigned int scif1_clk_pins[] = {
  3080. /* SCK */
  3081. RCAR_GP_PIN(6, 21),
  3082. };
  3083. static const unsigned int scif1_clk_mux[] = {
  3084. SCK1_MARK,
  3085. };
  3086. static const unsigned int scif1_ctrl_pins[] = {
  3087. /* RTS, CTS */
  3088. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  3089. };
  3090. static const unsigned int scif1_ctrl_mux[] = {
  3091. RTS1_N_MARK, CTS1_N_MARK,
  3092. };
  3093. static const unsigned int scif1_data_b_pins[] = {
  3094. /* RX, TX */
  3095. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
  3096. };
  3097. static const unsigned int scif1_data_b_mux[] = {
  3098. RX1_B_MARK, TX1_B_MARK,
  3099. };
  3100. /* - SCIF2 ------------------------------------------------------------------ */
  3101. static const unsigned int scif2_data_a_pins[] = {
  3102. /* RX, TX */
  3103. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  3104. };
  3105. static const unsigned int scif2_data_a_mux[] = {
  3106. RX2_A_MARK, TX2_A_MARK,
  3107. };
  3108. static const unsigned int scif2_clk_pins[] = {
  3109. /* SCK */
  3110. RCAR_GP_PIN(5, 9),
  3111. };
  3112. static const unsigned int scif2_clk_mux[] = {
  3113. SCK2_MARK,
  3114. };
  3115. static const unsigned int scif2_data_b_pins[] = {
  3116. /* RX, TX */
  3117. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3118. };
  3119. static const unsigned int scif2_data_b_mux[] = {
  3120. RX2_B_MARK, TX2_B_MARK,
  3121. };
  3122. /* - SCIF3 ------------------------------------------------------------------ */
  3123. static const unsigned int scif3_data_a_pins[] = {
  3124. /* RX, TX */
  3125. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  3126. };
  3127. static const unsigned int scif3_data_a_mux[] = {
  3128. RX3_A_MARK, TX3_A_MARK,
  3129. };
  3130. static const unsigned int scif3_clk_pins[] = {
  3131. /* SCK */
  3132. RCAR_GP_PIN(1, 22),
  3133. };
  3134. static const unsigned int scif3_clk_mux[] = {
  3135. SCK3_MARK,
  3136. };
  3137. static const unsigned int scif3_ctrl_pins[] = {
  3138. /* RTS, CTS */
  3139. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  3140. };
  3141. static const unsigned int scif3_ctrl_mux[] = {
  3142. RTS3_N_MARK, CTS3_N_MARK,
  3143. };
  3144. static const unsigned int scif3_data_b_pins[] = {
  3145. /* RX, TX */
  3146. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  3147. };
  3148. static const unsigned int scif3_data_b_mux[] = {
  3149. RX3_B_MARK, TX3_B_MARK,
  3150. };
  3151. /* - SCIF4 ------------------------------------------------------------------ */
  3152. static const unsigned int scif4_data_a_pins[] = {
  3153. /* RX, TX */
  3154. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
  3155. };
  3156. static const unsigned int scif4_data_a_mux[] = {
  3157. RX4_A_MARK, TX4_A_MARK,
  3158. };
  3159. static const unsigned int scif4_clk_a_pins[] = {
  3160. /* SCK */
  3161. RCAR_GP_PIN(2, 10),
  3162. };
  3163. static const unsigned int scif4_clk_a_mux[] = {
  3164. SCK4_A_MARK,
  3165. };
  3166. static const unsigned int scif4_ctrl_a_pins[] = {
  3167. /* RTS, CTS */
  3168. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  3169. };
  3170. static const unsigned int scif4_ctrl_a_mux[] = {
  3171. RTS4_N_A_MARK, CTS4_N_A_MARK,
  3172. };
  3173. static const unsigned int scif4_data_b_pins[] = {
  3174. /* RX, TX */
  3175. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3176. };
  3177. static const unsigned int scif4_data_b_mux[] = {
  3178. RX4_B_MARK, TX4_B_MARK,
  3179. };
  3180. static const unsigned int scif4_clk_b_pins[] = {
  3181. /* SCK */
  3182. RCAR_GP_PIN(1, 5),
  3183. };
  3184. static const unsigned int scif4_clk_b_mux[] = {
  3185. SCK4_B_MARK,
  3186. };
  3187. static const unsigned int scif4_ctrl_b_pins[] = {
  3188. /* RTS, CTS */
  3189. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
  3190. };
  3191. static const unsigned int scif4_ctrl_b_mux[] = {
  3192. RTS4_N_B_MARK, CTS4_N_B_MARK,
  3193. };
  3194. static const unsigned int scif4_data_c_pins[] = {
  3195. /* RX, TX */
  3196. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3197. };
  3198. static const unsigned int scif4_data_c_mux[] = {
  3199. RX4_C_MARK, TX4_C_MARK,
  3200. };
  3201. static const unsigned int scif4_clk_c_pins[] = {
  3202. /* SCK */
  3203. RCAR_GP_PIN(0, 8),
  3204. };
  3205. static const unsigned int scif4_clk_c_mux[] = {
  3206. SCK4_C_MARK,
  3207. };
  3208. static const unsigned int scif4_ctrl_c_pins[] = {
  3209. /* RTS, CTS */
  3210. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  3211. };
  3212. static const unsigned int scif4_ctrl_c_mux[] = {
  3213. RTS4_N_C_MARK, CTS4_N_C_MARK,
  3214. };
  3215. /* - SCIF5 ------------------------------------------------------------------ */
  3216. static const unsigned int scif5_data_a_pins[] = {
  3217. /* RX, TX */
  3218. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3219. };
  3220. static const unsigned int scif5_data_a_mux[] = {
  3221. RX5_A_MARK, TX5_A_MARK,
  3222. };
  3223. static const unsigned int scif5_clk_a_pins[] = {
  3224. /* SCK */
  3225. RCAR_GP_PIN(6, 21),
  3226. };
  3227. static const unsigned int scif5_clk_a_mux[] = {
  3228. SCK5_A_MARK,
  3229. };
  3230. static const unsigned int scif5_data_b_pins[] = {
  3231. /* RX, TX */
  3232. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
  3233. };
  3234. static const unsigned int scif5_data_b_mux[] = {
  3235. RX5_B_MARK, TX5_B_MARK,
  3236. };
  3237. static const unsigned int scif5_clk_b_pins[] = {
  3238. /* SCK */
  3239. RCAR_GP_PIN(5, 0),
  3240. };
  3241. static const unsigned int scif5_clk_b_mux[] = {
  3242. SCK5_B_MARK,
  3243. };
  3244. /* - SCIF Clock ------------------------------------------------------------- */
  3245. static const unsigned int scif_clk_a_pins[] = {
  3246. /* SCIF_CLK */
  3247. RCAR_GP_PIN(6, 23),
  3248. };
  3249. static const unsigned int scif_clk_a_mux[] = {
  3250. SCIF_CLK_A_MARK,
  3251. };
  3252. static const unsigned int scif_clk_b_pins[] = {
  3253. /* SCIF_CLK */
  3254. RCAR_GP_PIN(5, 9),
  3255. };
  3256. static const unsigned int scif_clk_b_mux[] = {
  3257. SCIF_CLK_B_MARK,
  3258. };
  3259. /* - SDHI0 ------------------------------------------------------------------ */
  3260. static const unsigned int sdhi0_data1_pins[] = {
  3261. /* D0 */
  3262. RCAR_GP_PIN(3, 2),
  3263. };
  3264. static const unsigned int sdhi0_data1_mux[] = {
  3265. SD0_DAT0_MARK,
  3266. };
  3267. static const unsigned int sdhi0_data4_pins[] = {
  3268. /* D[0:3] */
  3269. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  3270. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  3271. };
  3272. static const unsigned int sdhi0_data4_mux[] = {
  3273. SD0_DAT0_MARK, SD0_DAT1_MARK,
  3274. SD0_DAT2_MARK, SD0_DAT3_MARK,
  3275. };
  3276. static const unsigned int sdhi0_ctrl_pins[] = {
  3277. /* CLK, CMD */
  3278. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  3279. };
  3280. static const unsigned int sdhi0_ctrl_mux[] = {
  3281. SD0_CLK_MARK, SD0_CMD_MARK,
  3282. };
  3283. static const unsigned int sdhi0_cd_pins[] = {
  3284. /* CD */
  3285. RCAR_GP_PIN(3, 12),
  3286. };
  3287. static const unsigned int sdhi0_cd_mux[] = {
  3288. SD0_CD_MARK,
  3289. };
  3290. static const unsigned int sdhi0_wp_pins[] = {
  3291. /* WP */
  3292. RCAR_GP_PIN(3, 13),
  3293. };
  3294. static const unsigned int sdhi0_wp_mux[] = {
  3295. SD0_WP_MARK,
  3296. };
  3297. /* - SDHI1 ------------------------------------------------------------------ */
  3298. static const unsigned int sdhi1_data1_pins[] = {
  3299. /* D0 */
  3300. RCAR_GP_PIN(3, 8),
  3301. };
  3302. static const unsigned int sdhi1_data1_mux[] = {
  3303. SD1_DAT0_MARK,
  3304. };
  3305. static const unsigned int sdhi1_data4_pins[] = {
  3306. /* D[0:3] */
  3307. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3308. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3309. };
  3310. static const unsigned int sdhi1_data4_mux[] = {
  3311. SD1_DAT0_MARK, SD1_DAT1_MARK,
  3312. SD1_DAT2_MARK, SD1_DAT3_MARK,
  3313. };
  3314. static const unsigned int sdhi1_ctrl_pins[] = {
  3315. /* CLK, CMD */
  3316. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  3317. };
  3318. static const unsigned int sdhi1_ctrl_mux[] = {
  3319. SD1_CLK_MARK, SD1_CMD_MARK,
  3320. };
  3321. static const unsigned int sdhi1_cd_pins[] = {
  3322. /* CD */
  3323. RCAR_GP_PIN(3, 14),
  3324. };
  3325. static const unsigned int sdhi1_cd_mux[] = {
  3326. SD1_CD_MARK,
  3327. };
  3328. static const unsigned int sdhi1_wp_pins[] = {
  3329. /* WP */
  3330. RCAR_GP_PIN(3, 15),
  3331. };
  3332. static const unsigned int sdhi1_wp_mux[] = {
  3333. SD1_WP_MARK,
  3334. };
  3335. /* - SDHI2 ------------------------------------------------------------------ */
  3336. static const unsigned int sdhi2_data1_pins[] = {
  3337. /* D0 */
  3338. RCAR_GP_PIN(4, 2),
  3339. };
  3340. static const unsigned int sdhi2_data1_mux[] = {
  3341. SD2_DAT0_MARK,
  3342. };
  3343. static const unsigned int sdhi2_data4_pins[] = {
  3344. /* D[0:3] */
  3345. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  3346. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  3347. };
  3348. static const unsigned int sdhi2_data4_mux[] = {
  3349. SD2_DAT0_MARK, SD2_DAT1_MARK,
  3350. SD2_DAT2_MARK, SD2_DAT3_MARK,
  3351. };
  3352. static const unsigned int sdhi2_data8_pins[] = {
  3353. /* D[0:7] */
  3354. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  3355. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  3356. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3357. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3358. };
  3359. static const unsigned int sdhi2_data8_mux[] = {
  3360. SD2_DAT0_MARK, SD2_DAT1_MARK,
  3361. SD2_DAT2_MARK, SD2_DAT3_MARK,
  3362. SD2_DAT4_MARK, SD2_DAT5_MARK,
  3363. SD2_DAT6_MARK, SD2_DAT7_MARK,
  3364. };
  3365. static const unsigned int sdhi2_ctrl_pins[] = {
  3366. /* CLK, CMD */
  3367. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  3368. };
  3369. static const unsigned int sdhi2_ctrl_mux[] = {
  3370. SD2_CLK_MARK, SD2_CMD_MARK,
  3371. };
  3372. static const unsigned int sdhi2_cd_a_pins[] = {
  3373. /* CD */
  3374. RCAR_GP_PIN(4, 13),
  3375. };
  3376. static const unsigned int sdhi2_cd_a_mux[] = {
  3377. SD2_CD_A_MARK,
  3378. };
  3379. static const unsigned int sdhi2_cd_b_pins[] = {
  3380. /* CD */
  3381. RCAR_GP_PIN(5, 10),
  3382. };
  3383. static const unsigned int sdhi2_cd_b_mux[] = {
  3384. SD2_CD_B_MARK,
  3385. };
  3386. static const unsigned int sdhi2_wp_a_pins[] = {
  3387. /* WP */
  3388. RCAR_GP_PIN(4, 14),
  3389. };
  3390. static const unsigned int sdhi2_wp_a_mux[] = {
  3391. SD2_WP_A_MARK,
  3392. };
  3393. static const unsigned int sdhi2_wp_b_pins[] = {
  3394. /* WP */
  3395. RCAR_GP_PIN(5, 11),
  3396. };
  3397. static const unsigned int sdhi2_wp_b_mux[] = {
  3398. SD2_WP_B_MARK,
  3399. };
  3400. static const unsigned int sdhi2_ds_pins[] = {
  3401. /* DS */
  3402. RCAR_GP_PIN(4, 6),
  3403. };
  3404. static const unsigned int sdhi2_ds_mux[] = {
  3405. SD2_DS_MARK,
  3406. };
  3407. /* - SDHI3 ------------------------------------------------------------------ */
  3408. static const unsigned int sdhi3_data1_pins[] = {
  3409. /* D0 */
  3410. RCAR_GP_PIN(4, 9),
  3411. };
  3412. static const unsigned int sdhi3_data1_mux[] = {
  3413. SD3_DAT0_MARK,
  3414. };
  3415. static const unsigned int sdhi3_data4_pins[] = {
  3416. /* D[0:3] */
  3417. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3418. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3419. };
  3420. static const unsigned int sdhi3_data4_mux[] = {
  3421. SD3_DAT0_MARK, SD3_DAT1_MARK,
  3422. SD3_DAT2_MARK, SD3_DAT3_MARK,
  3423. };
  3424. static const unsigned int sdhi3_data8_pins[] = {
  3425. /* D[0:7] */
  3426. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3427. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3428. RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
  3429. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
  3430. };
  3431. static const unsigned int sdhi3_data8_mux[] = {
  3432. SD3_DAT0_MARK, SD3_DAT1_MARK,
  3433. SD3_DAT2_MARK, SD3_DAT3_MARK,
  3434. SD3_DAT4_MARK, SD3_DAT5_MARK,
  3435. SD3_DAT6_MARK, SD3_DAT7_MARK,
  3436. };
  3437. static const unsigned int sdhi3_ctrl_pins[] = {
  3438. /* CLK, CMD */
  3439. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
  3440. };
  3441. static const unsigned int sdhi3_ctrl_mux[] = {
  3442. SD3_CLK_MARK, SD3_CMD_MARK,
  3443. };
  3444. static const unsigned int sdhi3_cd_pins[] = {
  3445. /* CD */
  3446. RCAR_GP_PIN(4, 15),
  3447. };
  3448. static const unsigned int sdhi3_cd_mux[] = {
  3449. SD3_CD_MARK,
  3450. };
  3451. static const unsigned int sdhi3_wp_pins[] = {
  3452. /* WP */
  3453. RCAR_GP_PIN(4, 16),
  3454. };
  3455. static const unsigned int sdhi3_wp_mux[] = {
  3456. SD3_WP_MARK,
  3457. };
  3458. static const unsigned int sdhi3_ds_pins[] = {
  3459. /* DS */
  3460. RCAR_GP_PIN(4, 17),
  3461. };
  3462. static const unsigned int sdhi3_ds_mux[] = {
  3463. SD3_DS_MARK,
  3464. };
  3465. /* - SSI -------------------------------------------------------------------- */
  3466. static const unsigned int ssi0_data_pins[] = {
  3467. /* SDATA */
  3468. RCAR_GP_PIN(6, 2),
  3469. };
  3470. static const unsigned int ssi0_data_mux[] = {
  3471. SSI_SDATA0_MARK,
  3472. };
  3473. static const unsigned int ssi01239_ctrl_pins[] = {
  3474. /* SCK, WS */
  3475. RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
  3476. };
  3477. static const unsigned int ssi01239_ctrl_mux[] = {
  3478. SSI_SCK01239_MARK, SSI_WS01239_MARK,
  3479. };
  3480. static const unsigned int ssi1_data_a_pins[] = {
  3481. /* SDATA */
  3482. RCAR_GP_PIN(6, 3),
  3483. };
  3484. static const unsigned int ssi1_data_a_mux[] = {
  3485. SSI_SDATA1_A_MARK,
  3486. };
  3487. static const unsigned int ssi1_data_b_pins[] = {
  3488. /* SDATA */
  3489. RCAR_GP_PIN(5, 12),
  3490. };
  3491. static const unsigned int ssi1_data_b_mux[] = {
  3492. SSI_SDATA1_B_MARK,
  3493. };
  3494. static const unsigned int ssi1_ctrl_a_pins[] = {
  3495. /* SCK, WS */
  3496. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3497. };
  3498. static const unsigned int ssi1_ctrl_a_mux[] = {
  3499. SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
  3500. };
  3501. static const unsigned int ssi1_ctrl_b_pins[] = {
  3502. /* SCK, WS */
  3503. RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
  3504. };
  3505. static const unsigned int ssi1_ctrl_b_mux[] = {
  3506. SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
  3507. };
  3508. static const unsigned int ssi2_data_a_pins[] = {
  3509. /* SDATA */
  3510. RCAR_GP_PIN(6, 4),
  3511. };
  3512. static const unsigned int ssi2_data_a_mux[] = {
  3513. SSI_SDATA2_A_MARK,
  3514. };
  3515. static const unsigned int ssi2_data_b_pins[] = {
  3516. /* SDATA */
  3517. RCAR_GP_PIN(5, 13),
  3518. };
  3519. static const unsigned int ssi2_data_b_mux[] = {
  3520. SSI_SDATA2_B_MARK,
  3521. };
  3522. static const unsigned int ssi2_ctrl_a_pins[] = {
  3523. /* SCK, WS */
  3524. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3525. };
  3526. static const unsigned int ssi2_ctrl_a_mux[] = {
  3527. SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
  3528. };
  3529. static const unsigned int ssi2_ctrl_b_pins[] = {
  3530. /* SCK, WS */
  3531. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3532. };
  3533. static const unsigned int ssi2_ctrl_b_mux[] = {
  3534. SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
  3535. };
  3536. static const unsigned int ssi3_data_pins[] = {
  3537. /* SDATA */
  3538. RCAR_GP_PIN(6, 7),
  3539. };
  3540. static const unsigned int ssi3_data_mux[] = {
  3541. SSI_SDATA3_MARK,
  3542. };
  3543. static const unsigned int ssi349_ctrl_pins[] = {
  3544. /* SCK, WS */
  3545. RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
  3546. };
  3547. static const unsigned int ssi349_ctrl_mux[] = {
  3548. SSI_SCK349_MARK, SSI_WS349_MARK,
  3549. };
  3550. static const unsigned int ssi4_data_pins[] = {
  3551. /* SDATA */
  3552. RCAR_GP_PIN(6, 10),
  3553. };
  3554. static const unsigned int ssi4_data_mux[] = {
  3555. SSI_SDATA4_MARK,
  3556. };
  3557. static const unsigned int ssi4_ctrl_pins[] = {
  3558. /* SCK, WS */
  3559. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  3560. };
  3561. static const unsigned int ssi4_ctrl_mux[] = {
  3562. SSI_SCK4_MARK, SSI_WS4_MARK,
  3563. };
  3564. static const unsigned int ssi5_data_pins[] = {
  3565. /* SDATA */
  3566. RCAR_GP_PIN(6, 13),
  3567. };
  3568. static const unsigned int ssi5_data_mux[] = {
  3569. SSI_SDATA5_MARK,
  3570. };
  3571. static const unsigned int ssi5_ctrl_pins[] = {
  3572. /* SCK, WS */
  3573. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  3574. };
  3575. static const unsigned int ssi5_ctrl_mux[] = {
  3576. SSI_SCK5_MARK, SSI_WS5_MARK,
  3577. };
  3578. static const unsigned int ssi6_data_pins[] = {
  3579. /* SDATA */
  3580. RCAR_GP_PIN(6, 16),
  3581. };
  3582. static const unsigned int ssi6_data_mux[] = {
  3583. SSI_SDATA6_MARK,
  3584. };
  3585. static const unsigned int ssi6_ctrl_pins[] = {
  3586. /* SCK, WS */
  3587. RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
  3588. };
  3589. static const unsigned int ssi6_ctrl_mux[] = {
  3590. SSI_SCK6_MARK, SSI_WS6_MARK,
  3591. };
  3592. static const unsigned int ssi7_data_pins[] = {
  3593. /* SDATA */
  3594. RCAR_GP_PIN(6, 19),
  3595. };
  3596. static const unsigned int ssi7_data_mux[] = {
  3597. SSI_SDATA7_MARK,
  3598. };
  3599. static const unsigned int ssi78_ctrl_pins[] = {
  3600. /* SCK, WS */
  3601. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  3602. };
  3603. static const unsigned int ssi78_ctrl_mux[] = {
  3604. SSI_SCK78_MARK, SSI_WS78_MARK,
  3605. };
  3606. static const unsigned int ssi8_data_pins[] = {
  3607. /* SDATA */
  3608. RCAR_GP_PIN(6, 20),
  3609. };
  3610. static const unsigned int ssi8_data_mux[] = {
  3611. SSI_SDATA8_MARK,
  3612. };
  3613. static const unsigned int ssi9_data_a_pins[] = {
  3614. /* SDATA */
  3615. RCAR_GP_PIN(6, 21),
  3616. };
  3617. static const unsigned int ssi9_data_a_mux[] = {
  3618. SSI_SDATA9_A_MARK,
  3619. };
  3620. static const unsigned int ssi9_data_b_pins[] = {
  3621. /* SDATA */
  3622. RCAR_GP_PIN(5, 14),
  3623. };
  3624. static const unsigned int ssi9_data_b_mux[] = {
  3625. SSI_SDATA9_B_MARK,
  3626. };
  3627. static const unsigned int ssi9_ctrl_a_pins[] = {
  3628. /* SCK, WS */
  3629. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3630. };
  3631. static const unsigned int ssi9_ctrl_a_mux[] = {
  3632. SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
  3633. };
  3634. static const unsigned int ssi9_ctrl_b_pins[] = {
  3635. /* SCK, WS */
  3636. RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
  3637. };
  3638. static const unsigned int ssi9_ctrl_b_mux[] = {
  3639. SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
  3640. };
  3641. /* - TMU -------------------------------------------------------------------- */
  3642. static const unsigned int tmu_tclk1_a_pins[] = {
  3643. /* TCLK */
  3644. RCAR_GP_PIN(6, 23),
  3645. };
  3646. static const unsigned int tmu_tclk1_a_mux[] = {
  3647. TCLK1_A_MARK,
  3648. };
  3649. static const unsigned int tmu_tclk1_b_pins[] = {
  3650. /* TCLK */
  3651. RCAR_GP_PIN(5, 19),
  3652. };
  3653. static const unsigned int tmu_tclk1_b_mux[] = {
  3654. TCLK1_B_MARK,
  3655. };
  3656. static const unsigned int tmu_tclk2_a_pins[] = {
  3657. /* TCLK */
  3658. RCAR_GP_PIN(6, 19),
  3659. };
  3660. static const unsigned int tmu_tclk2_a_mux[] = {
  3661. TCLK2_A_MARK,
  3662. };
  3663. static const unsigned int tmu_tclk2_b_pins[] = {
  3664. /* TCLK */
  3665. RCAR_GP_PIN(6, 28),
  3666. };
  3667. static const unsigned int tmu_tclk2_b_mux[] = {
  3668. TCLK2_B_MARK,
  3669. };
  3670. /* - TPU ------------------------------------------------------------------- */
  3671. static const unsigned int tpu_to0_pins[] = {
  3672. /* TPU0TO0 */
  3673. RCAR_GP_PIN(6, 28),
  3674. };
  3675. static const unsigned int tpu_to0_mux[] = {
  3676. TPU0TO0_MARK,
  3677. };
  3678. static const unsigned int tpu_to1_pins[] = {
  3679. /* TPU0TO1 */
  3680. RCAR_GP_PIN(6, 29),
  3681. };
  3682. static const unsigned int tpu_to1_mux[] = {
  3683. TPU0TO1_MARK,
  3684. };
  3685. static const unsigned int tpu_to2_pins[] = {
  3686. /* TPU0TO2 */
  3687. RCAR_GP_PIN(6, 30),
  3688. };
  3689. static const unsigned int tpu_to2_mux[] = {
  3690. TPU0TO2_MARK,
  3691. };
  3692. static const unsigned int tpu_to3_pins[] = {
  3693. /* TPU0TO3 */
  3694. RCAR_GP_PIN(6, 31),
  3695. };
  3696. static const unsigned int tpu_to3_mux[] = {
  3697. TPU0TO3_MARK,
  3698. };
  3699. /* - USB0 ------------------------------------------------------------------- */
  3700. static const unsigned int usb0_pins[] = {
  3701. /* PWEN, OVC */
  3702. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  3703. };
  3704. static const unsigned int usb0_mux[] = {
  3705. USB0_PWEN_MARK, USB0_OVC_MARK,
  3706. };
  3707. /* - USB1 ------------------------------------------------------------------- */
  3708. static const unsigned int usb1_pins[] = {
  3709. /* PWEN, OVC */
  3710. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3711. };
  3712. static const unsigned int usb1_mux[] = {
  3713. USB1_PWEN_MARK, USB1_OVC_MARK,
  3714. };
  3715. /* - USB30 ------------------------------------------------------------------ */
  3716. static const unsigned int usb30_pins[] = {
  3717. /* PWEN, OVC */
  3718. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3719. };
  3720. static const unsigned int usb30_mux[] = {
  3721. USB30_PWEN_MARK, USB30_OVC_MARK,
  3722. };
  3723. /* - VIN4 ------------------------------------------------------------------- */
  3724. static const unsigned int vin4_data18_a_pins[] = {
  3725. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3726. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3727. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  3728. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3729. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3730. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3731. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3732. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3733. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3734. };
  3735. static const unsigned int vin4_data18_a_mux[] = {
  3736. VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
  3737. VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
  3738. VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
  3739. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3740. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3741. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3742. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3743. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3744. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3745. };
  3746. static const unsigned int vin4_data18_b_pins[] = {
  3747. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
  3748. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
  3749. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  3750. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3751. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3752. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3753. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3754. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3755. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3756. };
  3757. static const unsigned int vin4_data18_b_mux[] = {
  3758. VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
  3759. VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
  3760. VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
  3761. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3762. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3763. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3764. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3765. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3766. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3767. };
  3768. static const union vin_data vin4_data_a_pins = {
  3769. .data24 = {
  3770. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  3771. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3772. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3773. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  3774. RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
  3775. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3776. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3777. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3778. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3779. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3780. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3781. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3782. },
  3783. };
  3784. static const union vin_data vin4_data_a_mux = {
  3785. .data24 = {
  3786. VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
  3787. VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
  3788. VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
  3789. VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
  3790. VI4_DATA8_MARK, VI4_DATA9_MARK,
  3791. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3792. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3793. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3794. VI4_DATA16_MARK, VI4_DATA17_MARK,
  3795. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3796. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3797. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3798. },
  3799. };
  3800. static const union vin_data vin4_data_b_pins = {
  3801. .data24 = {
  3802. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  3803. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
  3804. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
  3805. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  3806. RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
  3807. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  3808. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3809. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3810. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3811. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3812. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3813. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3814. },
  3815. };
  3816. static const union vin_data vin4_data_b_mux = {
  3817. .data24 = {
  3818. VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
  3819. VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
  3820. VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
  3821. VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
  3822. VI4_DATA8_MARK, VI4_DATA9_MARK,
  3823. VI4_DATA10_MARK, VI4_DATA11_MARK,
  3824. VI4_DATA12_MARK, VI4_DATA13_MARK,
  3825. VI4_DATA14_MARK, VI4_DATA15_MARK,
  3826. VI4_DATA16_MARK, VI4_DATA17_MARK,
  3827. VI4_DATA18_MARK, VI4_DATA19_MARK,
  3828. VI4_DATA20_MARK, VI4_DATA21_MARK,
  3829. VI4_DATA22_MARK, VI4_DATA23_MARK,
  3830. },
  3831. };
  3832. static const unsigned int vin4_sync_pins[] = {
  3833. /* HSYNC#, VSYNC# */
  3834. RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
  3835. };
  3836. static const unsigned int vin4_sync_mux[] = {
  3837. VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
  3838. };
  3839. static const unsigned int vin4_field_pins[] = {
  3840. /* FIELD */
  3841. RCAR_GP_PIN(1, 16),
  3842. };
  3843. static const unsigned int vin4_field_mux[] = {
  3844. VI4_FIELD_MARK,
  3845. };
  3846. static const unsigned int vin4_clkenb_pins[] = {
  3847. /* CLKENB */
  3848. RCAR_GP_PIN(1, 19),
  3849. };
  3850. static const unsigned int vin4_clkenb_mux[] = {
  3851. VI4_CLKENB_MARK,
  3852. };
  3853. static const unsigned int vin4_clk_pins[] = {
  3854. /* CLK */
  3855. RCAR_GP_PIN(1, 27),
  3856. };
  3857. static const unsigned int vin4_clk_mux[] = {
  3858. VI4_CLK_MARK,
  3859. };
  3860. /* - VIN5 ------------------------------------------------------------------- */
  3861. static const union vin_data16 vin5_data_pins = {
  3862. .data16 = {
  3863. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3864. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3865. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3866. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3867. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  3868. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
  3869. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3870. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3871. },
  3872. };
  3873. static const union vin_data16 vin5_data_mux = {
  3874. .data16 = {
  3875. VI5_DATA0_MARK, VI5_DATA1_MARK,
  3876. VI5_DATA2_MARK, VI5_DATA3_MARK,
  3877. VI5_DATA4_MARK, VI5_DATA5_MARK,
  3878. VI5_DATA6_MARK, VI5_DATA7_MARK,
  3879. VI5_DATA8_MARK, VI5_DATA9_MARK,
  3880. VI5_DATA10_MARK, VI5_DATA11_MARK,
  3881. VI5_DATA12_MARK, VI5_DATA13_MARK,
  3882. VI5_DATA14_MARK, VI5_DATA15_MARK,
  3883. },
  3884. };
  3885. static const unsigned int vin5_sync_pins[] = {
  3886. /* HSYNC#, VSYNC# */
  3887. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
  3888. };
  3889. static const unsigned int vin5_sync_mux[] = {
  3890. VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
  3891. };
  3892. static const unsigned int vin5_field_pins[] = {
  3893. RCAR_GP_PIN(1, 11),
  3894. };
  3895. static const unsigned int vin5_field_mux[] = {
  3896. /* FIELD */
  3897. VI5_FIELD_MARK,
  3898. };
  3899. static const unsigned int vin5_clkenb_pins[] = {
  3900. RCAR_GP_PIN(1, 20),
  3901. };
  3902. static const unsigned int vin5_clkenb_mux[] = {
  3903. /* CLKENB */
  3904. VI5_CLKENB_MARK,
  3905. };
  3906. static const unsigned int vin5_clk_pins[] = {
  3907. RCAR_GP_PIN(1, 21),
  3908. };
  3909. static const unsigned int vin5_clk_mux[] = {
  3910. /* CLK */
  3911. VI5_CLK_MARK,
  3912. };
  3913. static const struct {
  3914. struct sh_pfc_pin_group common[316];
  3915. struct sh_pfc_pin_group automotive[30];
  3916. } pinmux_groups = {
  3917. .common = {
  3918. SH_PFC_PIN_GROUP(audio_clk_a_a),
  3919. SH_PFC_PIN_GROUP(audio_clk_a_b),
  3920. SH_PFC_PIN_GROUP(audio_clk_a_c),
  3921. SH_PFC_PIN_GROUP(audio_clk_b_a),
  3922. SH_PFC_PIN_GROUP(audio_clk_b_b),
  3923. SH_PFC_PIN_GROUP(audio_clk_c_a),
  3924. SH_PFC_PIN_GROUP(audio_clk_c_b),
  3925. SH_PFC_PIN_GROUP(audio_clkout_a),
  3926. SH_PFC_PIN_GROUP(audio_clkout_b),
  3927. SH_PFC_PIN_GROUP(audio_clkout_c),
  3928. SH_PFC_PIN_GROUP(audio_clkout_d),
  3929. SH_PFC_PIN_GROUP(audio_clkout1_a),
  3930. SH_PFC_PIN_GROUP(audio_clkout1_b),
  3931. SH_PFC_PIN_GROUP(audio_clkout2_a),
  3932. SH_PFC_PIN_GROUP(audio_clkout2_b),
  3933. SH_PFC_PIN_GROUP(audio_clkout3_a),
  3934. SH_PFC_PIN_GROUP(audio_clkout3_b),
  3935. SH_PFC_PIN_GROUP(avb_link),
  3936. SH_PFC_PIN_GROUP(avb_magic),
  3937. SH_PFC_PIN_GROUP(avb_phy_int),
  3938. SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
  3939. SH_PFC_PIN_GROUP(avb_mdio),
  3940. SH_PFC_PIN_GROUP(avb_mii),
  3941. SH_PFC_PIN_GROUP(avb_avtp_pps),
  3942. SH_PFC_PIN_GROUP(avb_avtp_match_a),
  3943. SH_PFC_PIN_GROUP(avb_avtp_capture_a),
  3944. SH_PFC_PIN_GROUP(avb_avtp_match_b),
  3945. SH_PFC_PIN_GROUP(avb_avtp_capture_b),
  3946. SH_PFC_PIN_GROUP(can0_data_a),
  3947. SH_PFC_PIN_GROUP(can0_data_b),
  3948. SH_PFC_PIN_GROUP(can1_data),
  3949. SH_PFC_PIN_GROUP(can_clk),
  3950. SH_PFC_PIN_GROUP(canfd0_data_a),
  3951. SH_PFC_PIN_GROUP(canfd0_data_b),
  3952. SH_PFC_PIN_GROUP(canfd1_data),
  3953. SH_PFC_PIN_GROUP(du_rgb666),
  3954. SH_PFC_PIN_GROUP(du_rgb888),
  3955. SH_PFC_PIN_GROUP(du_clk_out_0),
  3956. SH_PFC_PIN_GROUP(du_clk_out_1),
  3957. SH_PFC_PIN_GROUP(du_sync),
  3958. SH_PFC_PIN_GROUP(du_oddf),
  3959. SH_PFC_PIN_GROUP(du_cde),
  3960. SH_PFC_PIN_GROUP(du_disp),
  3961. SH_PFC_PIN_GROUP(hscif0_data),
  3962. SH_PFC_PIN_GROUP(hscif0_clk),
  3963. SH_PFC_PIN_GROUP(hscif0_ctrl),
  3964. SH_PFC_PIN_GROUP(hscif1_data_a),
  3965. SH_PFC_PIN_GROUP(hscif1_clk_a),
  3966. SH_PFC_PIN_GROUP(hscif1_ctrl_a),
  3967. SH_PFC_PIN_GROUP(hscif1_data_b),
  3968. SH_PFC_PIN_GROUP(hscif1_clk_b),
  3969. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  3970. SH_PFC_PIN_GROUP(hscif2_data_a),
  3971. SH_PFC_PIN_GROUP(hscif2_clk_a),
  3972. SH_PFC_PIN_GROUP(hscif2_ctrl_a),
  3973. SH_PFC_PIN_GROUP(hscif2_data_b),
  3974. SH_PFC_PIN_GROUP(hscif2_clk_b),
  3975. SH_PFC_PIN_GROUP(hscif2_ctrl_b),
  3976. SH_PFC_PIN_GROUP(hscif2_data_c),
  3977. SH_PFC_PIN_GROUP(hscif2_clk_c),
  3978. SH_PFC_PIN_GROUP(hscif2_ctrl_c),
  3979. SH_PFC_PIN_GROUP(hscif3_data_a),
  3980. SH_PFC_PIN_GROUP(hscif3_clk),
  3981. SH_PFC_PIN_GROUP(hscif3_ctrl),
  3982. SH_PFC_PIN_GROUP(hscif3_data_b),
  3983. SH_PFC_PIN_GROUP(hscif3_data_c),
  3984. SH_PFC_PIN_GROUP(hscif3_data_d),
  3985. SH_PFC_PIN_GROUP(hscif4_data_a),
  3986. SH_PFC_PIN_GROUP(hscif4_clk),
  3987. SH_PFC_PIN_GROUP(hscif4_ctrl),
  3988. SH_PFC_PIN_GROUP(hscif4_data_b),
  3989. SH_PFC_PIN_GROUP(i2c0),
  3990. SH_PFC_PIN_GROUP(i2c1_a),
  3991. SH_PFC_PIN_GROUP(i2c1_b),
  3992. SH_PFC_PIN_GROUP(i2c2_a),
  3993. SH_PFC_PIN_GROUP(i2c2_b),
  3994. SH_PFC_PIN_GROUP(i2c3),
  3995. SH_PFC_PIN_GROUP(i2c5),
  3996. SH_PFC_PIN_GROUP(i2c6_a),
  3997. SH_PFC_PIN_GROUP(i2c6_b),
  3998. SH_PFC_PIN_GROUP(i2c6_c),
  3999. SH_PFC_PIN_GROUP(intc_ex_irq0),
  4000. SH_PFC_PIN_GROUP(intc_ex_irq1),
  4001. SH_PFC_PIN_GROUP(intc_ex_irq2),
  4002. SH_PFC_PIN_GROUP(intc_ex_irq3),
  4003. SH_PFC_PIN_GROUP(intc_ex_irq4),
  4004. SH_PFC_PIN_GROUP(intc_ex_irq5),
  4005. SH_PFC_PIN_GROUP(msiof0_clk),
  4006. SH_PFC_PIN_GROUP(msiof0_sync),
  4007. SH_PFC_PIN_GROUP(msiof0_ss1),
  4008. SH_PFC_PIN_GROUP(msiof0_ss2),
  4009. SH_PFC_PIN_GROUP(msiof0_txd),
  4010. SH_PFC_PIN_GROUP(msiof0_rxd),
  4011. SH_PFC_PIN_GROUP(msiof1_clk_a),
  4012. SH_PFC_PIN_GROUP(msiof1_sync_a),
  4013. SH_PFC_PIN_GROUP(msiof1_ss1_a),
  4014. SH_PFC_PIN_GROUP(msiof1_ss2_a),
  4015. SH_PFC_PIN_GROUP(msiof1_txd_a),
  4016. SH_PFC_PIN_GROUP(msiof1_rxd_a),
  4017. SH_PFC_PIN_GROUP(msiof1_clk_b),
  4018. SH_PFC_PIN_GROUP(msiof1_sync_b),
  4019. SH_PFC_PIN_GROUP(msiof1_ss1_b),
  4020. SH_PFC_PIN_GROUP(msiof1_ss2_b),
  4021. SH_PFC_PIN_GROUP(msiof1_txd_b),
  4022. SH_PFC_PIN_GROUP(msiof1_rxd_b),
  4023. SH_PFC_PIN_GROUP(msiof1_clk_c),
  4024. SH_PFC_PIN_GROUP(msiof1_sync_c),
  4025. SH_PFC_PIN_GROUP(msiof1_ss1_c),
  4026. SH_PFC_PIN_GROUP(msiof1_ss2_c),
  4027. SH_PFC_PIN_GROUP(msiof1_txd_c),
  4028. SH_PFC_PIN_GROUP(msiof1_rxd_c),
  4029. SH_PFC_PIN_GROUP(msiof1_clk_d),
  4030. SH_PFC_PIN_GROUP(msiof1_sync_d),
  4031. SH_PFC_PIN_GROUP(msiof1_ss1_d),
  4032. SH_PFC_PIN_GROUP(msiof1_ss2_d),
  4033. SH_PFC_PIN_GROUP(msiof1_txd_d),
  4034. SH_PFC_PIN_GROUP(msiof1_rxd_d),
  4035. SH_PFC_PIN_GROUP(msiof1_clk_e),
  4036. SH_PFC_PIN_GROUP(msiof1_sync_e),
  4037. SH_PFC_PIN_GROUP(msiof1_ss1_e),
  4038. SH_PFC_PIN_GROUP(msiof1_ss2_e),
  4039. SH_PFC_PIN_GROUP(msiof1_txd_e),
  4040. SH_PFC_PIN_GROUP(msiof1_rxd_e),
  4041. SH_PFC_PIN_GROUP(msiof1_clk_f),
  4042. SH_PFC_PIN_GROUP(msiof1_sync_f),
  4043. SH_PFC_PIN_GROUP(msiof1_ss1_f),
  4044. SH_PFC_PIN_GROUP(msiof1_ss2_f),
  4045. SH_PFC_PIN_GROUP(msiof1_txd_f),
  4046. SH_PFC_PIN_GROUP(msiof1_rxd_f),
  4047. SH_PFC_PIN_GROUP(msiof1_clk_g),
  4048. SH_PFC_PIN_GROUP(msiof1_sync_g),
  4049. SH_PFC_PIN_GROUP(msiof1_ss1_g),
  4050. SH_PFC_PIN_GROUP(msiof1_ss2_g),
  4051. SH_PFC_PIN_GROUP(msiof1_txd_g),
  4052. SH_PFC_PIN_GROUP(msiof1_rxd_g),
  4053. SH_PFC_PIN_GROUP(msiof2_clk_a),
  4054. SH_PFC_PIN_GROUP(msiof2_sync_a),
  4055. SH_PFC_PIN_GROUP(msiof2_ss1_a),
  4056. SH_PFC_PIN_GROUP(msiof2_ss2_a),
  4057. SH_PFC_PIN_GROUP(msiof2_txd_a),
  4058. SH_PFC_PIN_GROUP(msiof2_rxd_a),
  4059. SH_PFC_PIN_GROUP(msiof2_clk_b),
  4060. SH_PFC_PIN_GROUP(msiof2_sync_b),
  4061. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  4062. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  4063. SH_PFC_PIN_GROUP(msiof2_txd_b),
  4064. SH_PFC_PIN_GROUP(msiof2_rxd_b),
  4065. SH_PFC_PIN_GROUP(msiof2_clk_c),
  4066. SH_PFC_PIN_GROUP(msiof2_sync_c),
  4067. SH_PFC_PIN_GROUP(msiof2_ss1_c),
  4068. SH_PFC_PIN_GROUP(msiof2_ss2_c),
  4069. SH_PFC_PIN_GROUP(msiof2_txd_c),
  4070. SH_PFC_PIN_GROUP(msiof2_rxd_c),
  4071. SH_PFC_PIN_GROUP(msiof2_clk_d),
  4072. SH_PFC_PIN_GROUP(msiof2_sync_d),
  4073. SH_PFC_PIN_GROUP(msiof2_ss1_d),
  4074. SH_PFC_PIN_GROUP(msiof2_ss2_d),
  4075. SH_PFC_PIN_GROUP(msiof2_txd_d),
  4076. SH_PFC_PIN_GROUP(msiof2_rxd_d),
  4077. SH_PFC_PIN_GROUP(msiof3_clk_a),
  4078. SH_PFC_PIN_GROUP(msiof3_sync_a),
  4079. SH_PFC_PIN_GROUP(msiof3_ss1_a),
  4080. SH_PFC_PIN_GROUP(msiof3_ss2_a),
  4081. SH_PFC_PIN_GROUP(msiof3_txd_a),
  4082. SH_PFC_PIN_GROUP(msiof3_rxd_a),
  4083. SH_PFC_PIN_GROUP(msiof3_clk_b),
  4084. SH_PFC_PIN_GROUP(msiof3_sync_b),
  4085. SH_PFC_PIN_GROUP(msiof3_ss1_b),
  4086. SH_PFC_PIN_GROUP(msiof3_ss2_b),
  4087. SH_PFC_PIN_GROUP(msiof3_txd_b),
  4088. SH_PFC_PIN_GROUP(msiof3_rxd_b),
  4089. SH_PFC_PIN_GROUP(msiof3_clk_c),
  4090. SH_PFC_PIN_GROUP(msiof3_sync_c),
  4091. SH_PFC_PIN_GROUP(msiof3_txd_c),
  4092. SH_PFC_PIN_GROUP(msiof3_rxd_c),
  4093. SH_PFC_PIN_GROUP(msiof3_clk_d),
  4094. SH_PFC_PIN_GROUP(msiof3_sync_d),
  4095. SH_PFC_PIN_GROUP(msiof3_ss1_d),
  4096. SH_PFC_PIN_GROUP(msiof3_txd_d),
  4097. SH_PFC_PIN_GROUP(msiof3_rxd_d),
  4098. SH_PFC_PIN_GROUP(msiof3_clk_e),
  4099. SH_PFC_PIN_GROUP(msiof3_sync_e),
  4100. SH_PFC_PIN_GROUP(msiof3_ss1_e),
  4101. SH_PFC_PIN_GROUP(msiof3_ss2_e),
  4102. SH_PFC_PIN_GROUP(msiof3_txd_e),
  4103. SH_PFC_PIN_GROUP(msiof3_rxd_e),
  4104. SH_PFC_PIN_GROUP(pwm0),
  4105. SH_PFC_PIN_GROUP(pwm1_a),
  4106. SH_PFC_PIN_GROUP(pwm1_b),
  4107. SH_PFC_PIN_GROUP(pwm2_a),
  4108. SH_PFC_PIN_GROUP(pwm2_b),
  4109. SH_PFC_PIN_GROUP(pwm3_a),
  4110. SH_PFC_PIN_GROUP(pwm3_b),
  4111. SH_PFC_PIN_GROUP(pwm4_a),
  4112. SH_PFC_PIN_GROUP(pwm4_b),
  4113. SH_PFC_PIN_GROUP(pwm5_a),
  4114. SH_PFC_PIN_GROUP(pwm5_b),
  4115. SH_PFC_PIN_GROUP(pwm6_a),
  4116. SH_PFC_PIN_GROUP(pwm6_b),
  4117. SH_PFC_PIN_GROUP(scif0_data),
  4118. SH_PFC_PIN_GROUP(scif0_clk),
  4119. SH_PFC_PIN_GROUP(scif0_ctrl),
  4120. SH_PFC_PIN_GROUP(scif1_data_a),
  4121. SH_PFC_PIN_GROUP(scif1_clk),
  4122. SH_PFC_PIN_GROUP(scif1_ctrl),
  4123. SH_PFC_PIN_GROUP(scif1_data_b),
  4124. SH_PFC_PIN_GROUP(scif2_data_a),
  4125. SH_PFC_PIN_GROUP(scif2_clk),
  4126. SH_PFC_PIN_GROUP(scif2_data_b),
  4127. SH_PFC_PIN_GROUP(scif3_data_a),
  4128. SH_PFC_PIN_GROUP(scif3_clk),
  4129. SH_PFC_PIN_GROUP(scif3_ctrl),
  4130. SH_PFC_PIN_GROUP(scif3_data_b),
  4131. SH_PFC_PIN_GROUP(scif4_data_a),
  4132. SH_PFC_PIN_GROUP(scif4_clk_a),
  4133. SH_PFC_PIN_GROUP(scif4_ctrl_a),
  4134. SH_PFC_PIN_GROUP(scif4_data_b),
  4135. SH_PFC_PIN_GROUP(scif4_clk_b),
  4136. SH_PFC_PIN_GROUP(scif4_ctrl_b),
  4137. SH_PFC_PIN_GROUP(scif4_data_c),
  4138. SH_PFC_PIN_GROUP(scif4_clk_c),
  4139. SH_PFC_PIN_GROUP(scif4_ctrl_c),
  4140. SH_PFC_PIN_GROUP(scif5_data_a),
  4141. SH_PFC_PIN_GROUP(scif5_clk_a),
  4142. SH_PFC_PIN_GROUP(scif5_data_b),
  4143. SH_PFC_PIN_GROUP(scif5_clk_b),
  4144. SH_PFC_PIN_GROUP(scif_clk_a),
  4145. SH_PFC_PIN_GROUP(scif_clk_b),
  4146. SH_PFC_PIN_GROUP(sdhi0_data1),
  4147. SH_PFC_PIN_GROUP(sdhi0_data4),
  4148. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  4149. SH_PFC_PIN_GROUP(sdhi0_cd),
  4150. SH_PFC_PIN_GROUP(sdhi0_wp),
  4151. SH_PFC_PIN_GROUP(sdhi1_data1),
  4152. SH_PFC_PIN_GROUP(sdhi1_data4),
  4153. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  4154. SH_PFC_PIN_GROUP(sdhi1_cd),
  4155. SH_PFC_PIN_GROUP(sdhi1_wp),
  4156. SH_PFC_PIN_GROUP(sdhi2_data1),
  4157. SH_PFC_PIN_GROUP(sdhi2_data4),
  4158. SH_PFC_PIN_GROUP(sdhi2_data8),
  4159. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  4160. SH_PFC_PIN_GROUP(sdhi2_cd_a),
  4161. SH_PFC_PIN_GROUP(sdhi2_wp_a),
  4162. SH_PFC_PIN_GROUP(sdhi2_cd_b),
  4163. SH_PFC_PIN_GROUP(sdhi2_wp_b),
  4164. SH_PFC_PIN_GROUP(sdhi2_ds),
  4165. SH_PFC_PIN_GROUP(sdhi3_data1),
  4166. SH_PFC_PIN_GROUP(sdhi3_data4),
  4167. SH_PFC_PIN_GROUP(sdhi3_data8),
  4168. SH_PFC_PIN_GROUP(sdhi3_ctrl),
  4169. SH_PFC_PIN_GROUP(sdhi3_cd),
  4170. SH_PFC_PIN_GROUP(sdhi3_wp),
  4171. SH_PFC_PIN_GROUP(sdhi3_ds),
  4172. SH_PFC_PIN_GROUP(ssi0_data),
  4173. SH_PFC_PIN_GROUP(ssi01239_ctrl),
  4174. SH_PFC_PIN_GROUP(ssi1_data_a),
  4175. SH_PFC_PIN_GROUP(ssi1_data_b),
  4176. SH_PFC_PIN_GROUP(ssi1_ctrl_a),
  4177. SH_PFC_PIN_GROUP(ssi1_ctrl_b),
  4178. SH_PFC_PIN_GROUP(ssi2_data_a),
  4179. SH_PFC_PIN_GROUP(ssi2_data_b),
  4180. SH_PFC_PIN_GROUP(ssi2_ctrl_a),
  4181. SH_PFC_PIN_GROUP(ssi2_ctrl_b),
  4182. SH_PFC_PIN_GROUP(ssi3_data),
  4183. SH_PFC_PIN_GROUP(ssi349_ctrl),
  4184. SH_PFC_PIN_GROUP(ssi4_data),
  4185. SH_PFC_PIN_GROUP(ssi4_ctrl),
  4186. SH_PFC_PIN_GROUP(ssi5_data),
  4187. SH_PFC_PIN_GROUP(ssi5_ctrl),
  4188. SH_PFC_PIN_GROUP(ssi6_data),
  4189. SH_PFC_PIN_GROUP(ssi6_ctrl),
  4190. SH_PFC_PIN_GROUP(ssi7_data),
  4191. SH_PFC_PIN_GROUP(ssi78_ctrl),
  4192. SH_PFC_PIN_GROUP(ssi8_data),
  4193. SH_PFC_PIN_GROUP(ssi9_data_a),
  4194. SH_PFC_PIN_GROUP(ssi9_data_b),
  4195. SH_PFC_PIN_GROUP(ssi9_ctrl_a),
  4196. SH_PFC_PIN_GROUP(ssi9_ctrl_b),
  4197. SH_PFC_PIN_GROUP(tmu_tclk1_a),
  4198. SH_PFC_PIN_GROUP(tmu_tclk1_b),
  4199. SH_PFC_PIN_GROUP(tmu_tclk2_a),
  4200. SH_PFC_PIN_GROUP(tmu_tclk2_b),
  4201. SH_PFC_PIN_GROUP(tpu_to0),
  4202. SH_PFC_PIN_GROUP(tpu_to1),
  4203. SH_PFC_PIN_GROUP(tpu_to2),
  4204. SH_PFC_PIN_GROUP(tpu_to3),
  4205. SH_PFC_PIN_GROUP(usb0),
  4206. SH_PFC_PIN_GROUP(usb1),
  4207. SH_PFC_PIN_GROUP(usb30),
  4208. VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
  4209. VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
  4210. VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
  4211. VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
  4212. SH_PFC_PIN_GROUP(vin4_data18_a),
  4213. VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
  4214. VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
  4215. VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
  4216. VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
  4217. VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
  4218. VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
  4219. SH_PFC_PIN_GROUP(vin4_data18_b),
  4220. VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
  4221. VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
  4222. SH_PFC_PIN_GROUP(vin4_sync),
  4223. SH_PFC_PIN_GROUP(vin4_field),
  4224. SH_PFC_PIN_GROUP(vin4_clkenb),
  4225. SH_PFC_PIN_GROUP(vin4_clk),
  4226. VIN_DATA_PIN_GROUP(vin5_data, 8),
  4227. VIN_DATA_PIN_GROUP(vin5_data, 10),
  4228. VIN_DATA_PIN_GROUP(vin5_data, 12),
  4229. VIN_DATA_PIN_GROUP(vin5_data, 16),
  4230. SH_PFC_PIN_GROUP(vin5_sync),
  4231. SH_PFC_PIN_GROUP(vin5_field),
  4232. SH_PFC_PIN_GROUP(vin5_clkenb),
  4233. SH_PFC_PIN_GROUP(vin5_clk),
  4234. },
  4235. .automotive = {
  4236. SH_PFC_PIN_GROUP(drif0_ctrl_a),
  4237. SH_PFC_PIN_GROUP(drif0_data0_a),
  4238. SH_PFC_PIN_GROUP(drif0_data1_a),
  4239. SH_PFC_PIN_GROUP(drif0_ctrl_b),
  4240. SH_PFC_PIN_GROUP(drif0_data0_b),
  4241. SH_PFC_PIN_GROUP(drif0_data1_b),
  4242. SH_PFC_PIN_GROUP(drif0_ctrl_c),
  4243. SH_PFC_PIN_GROUP(drif0_data0_c),
  4244. SH_PFC_PIN_GROUP(drif0_data1_c),
  4245. SH_PFC_PIN_GROUP(drif1_ctrl_a),
  4246. SH_PFC_PIN_GROUP(drif1_data0_a),
  4247. SH_PFC_PIN_GROUP(drif1_data1_a),
  4248. SH_PFC_PIN_GROUP(drif1_ctrl_b),
  4249. SH_PFC_PIN_GROUP(drif1_data0_b),
  4250. SH_PFC_PIN_GROUP(drif1_data1_b),
  4251. SH_PFC_PIN_GROUP(drif1_ctrl_c),
  4252. SH_PFC_PIN_GROUP(drif1_data0_c),
  4253. SH_PFC_PIN_GROUP(drif1_data1_c),
  4254. SH_PFC_PIN_GROUP(drif2_ctrl_a),
  4255. SH_PFC_PIN_GROUP(drif2_data0_a),
  4256. SH_PFC_PIN_GROUP(drif2_data1_a),
  4257. SH_PFC_PIN_GROUP(drif2_ctrl_b),
  4258. SH_PFC_PIN_GROUP(drif2_data0_b),
  4259. SH_PFC_PIN_GROUP(drif2_data1_b),
  4260. SH_PFC_PIN_GROUP(drif3_ctrl_a),
  4261. SH_PFC_PIN_GROUP(drif3_data0_a),
  4262. SH_PFC_PIN_GROUP(drif3_data1_a),
  4263. SH_PFC_PIN_GROUP(drif3_ctrl_b),
  4264. SH_PFC_PIN_GROUP(drif3_data0_b),
  4265. SH_PFC_PIN_GROUP(drif3_data1_b),
  4266. }
  4267. };
  4268. static const char * const audio_clk_groups[] = {
  4269. "audio_clk_a_a",
  4270. "audio_clk_a_b",
  4271. "audio_clk_a_c",
  4272. "audio_clk_b_a",
  4273. "audio_clk_b_b",
  4274. "audio_clk_c_a",
  4275. "audio_clk_c_b",
  4276. "audio_clkout_a",
  4277. "audio_clkout_b",
  4278. "audio_clkout_c",
  4279. "audio_clkout_d",
  4280. "audio_clkout1_a",
  4281. "audio_clkout1_b",
  4282. "audio_clkout2_a",
  4283. "audio_clkout2_b",
  4284. "audio_clkout3_a",
  4285. "audio_clkout3_b",
  4286. };
  4287. static const char * const avb_groups[] = {
  4288. "avb_link",
  4289. "avb_magic",
  4290. "avb_phy_int",
  4291. "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
  4292. "avb_mdio",
  4293. "avb_mii",
  4294. "avb_avtp_pps",
  4295. "avb_avtp_match_a",
  4296. "avb_avtp_capture_a",
  4297. "avb_avtp_match_b",
  4298. "avb_avtp_capture_b",
  4299. };
  4300. static const char * const can0_groups[] = {
  4301. "can0_data_a",
  4302. "can0_data_b",
  4303. };
  4304. static const char * const can1_groups[] = {
  4305. "can1_data",
  4306. };
  4307. static const char * const can_clk_groups[] = {
  4308. "can_clk",
  4309. };
  4310. static const char * const canfd0_groups[] = {
  4311. "canfd0_data_a",
  4312. "canfd0_data_b",
  4313. };
  4314. static const char * const canfd1_groups[] = {
  4315. "canfd1_data",
  4316. };
  4317. static const char * const drif0_groups[] = {
  4318. "drif0_ctrl_a",
  4319. "drif0_data0_a",
  4320. "drif0_data1_a",
  4321. "drif0_ctrl_b",
  4322. "drif0_data0_b",
  4323. "drif0_data1_b",
  4324. "drif0_ctrl_c",
  4325. "drif0_data0_c",
  4326. "drif0_data1_c",
  4327. };
  4328. static const char * const drif1_groups[] = {
  4329. "drif1_ctrl_a",
  4330. "drif1_data0_a",
  4331. "drif1_data1_a",
  4332. "drif1_ctrl_b",
  4333. "drif1_data0_b",
  4334. "drif1_data1_b",
  4335. "drif1_ctrl_c",
  4336. "drif1_data0_c",
  4337. "drif1_data1_c",
  4338. };
  4339. static const char * const drif2_groups[] = {
  4340. "drif2_ctrl_a",
  4341. "drif2_data0_a",
  4342. "drif2_data1_a",
  4343. "drif2_ctrl_b",
  4344. "drif2_data0_b",
  4345. "drif2_data1_b",
  4346. };
  4347. static const char * const drif3_groups[] = {
  4348. "drif3_ctrl_a",
  4349. "drif3_data0_a",
  4350. "drif3_data1_a",
  4351. "drif3_ctrl_b",
  4352. "drif3_data0_b",
  4353. "drif3_data1_b",
  4354. };
  4355. static const char * const du_groups[] = {
  4356. "du_rgb666",
  4357. "du_rgb888",
  4358. "du_clk_out_0",
  4359. "du_clk_out_1",
  4360. "du_sync",
  4361. "du_oddf",
  4362. "du_cde",
  4363. "du_disp",
  4364. };
  4365. static const char * const hscif0_groups[] = {
  4366. "hscif0_data",
  4367. "hscif0_clk",
  4368. "hscif0_ctrl",
  4369. };
  4370. static const char * const hscif1_groups[] = {
  4371. "hscif1_data_a",
  4372. "hscif1_clk_a",
  4373. "hscif1_ctrl_a",
  4374. "hscif1_data_b",
  4375. "hscif1_clk_b",
  4376. "hscif1_ctrl_b",
  4377. };
  4378. static const char * const hscif2_groups[] = {
  4379. "hscif2_data_a",
  4380. "hscif2_clk_a",
  4381. "hscif2_ctrl_a",
  4382. "hscif2_data_b",
  4383. "hscif2_clk_b",
  4384. "hscif2_ctrl_b",
  4385. "hscif2_data_c",
  4386. "hscif2_clk_c",
  4387. "hscif2_ctrl_c",
  4388. };
  4389. static const char * const hscif3_groups[] = {
  4390. "hscif3_data_a",
  4391. "hscif3_clk",
  4392. "hscif3_ctrl",
  4393. "hscif3_data_b",
  4394. "hscif3_data_c",
  4395. "hscif3_data_d",
  4396. };
  4397. static const char * const hscif4_groups[] = {
  4398. "hscif4_data_a",
  4399. "hscif4_clk",
  4400. "hscif4_ctrl",
  4401. "hscif4_data_b",
  4402. };
  4403. static const char * const i2c0_groups[] = {
  4404. "i2c0",
  4405. };
  4406. static const char * const i2c1_groups[] = {
  4407. "i2c1_a",
  4408. "i2c1_b",
  4409. };
  4410. static const char * const i2c2_groups[] = {
  4411. "i2c2_a",
  4412. "i2c2_b",
  4413. };
  4414. static const char * const i2c3_groups[] = {
  4415. "i2c3",
  4416. };
  4417. static const char * const i2c5_groups[] = {
  4418. "i2c5",
  4419. };
  4420. static const char * const i2c6_groups[] = {
  4421. "i2c6_a",
  4422. "i2c6_b",
  4423. "i2c6_c",
  4424. };
  4425. static const char * const intc_ex_groups[] = {
  4426. "intc_ex_irq0",
  4427. "intc_ex_irq1",
  4428. "intc_ex_irq2",
  4429. "intc_ex_irq3",
  4430. "intc_ex_irq4",
  4431. "intc_ex_irq5",
  4432. };
  4433. static const char * const msiof0_groups[] = {
  4434. "msiof0_clk",
  4435. "msiof0_sync",
  4436. "msiof0_ss1",
  4437. "msiof0_ss2",
  4438. "msiof0_txd",
  4439. "msiof0_rxd",
  4440. };
  4441. static const char * const msiof1_groups[] = {
  4442. "msiof1_clk_a",
  4443. "msiof1_sync_a",
  4444. "msiof1_ss1_a",
  4445. "msiof1_ss2_a",
  4446. "msiof1_txd_a",
  4447. "msiof1_rxd_a",
  4448. "msiof1_clk_b",
  4449. "msiof1_sync_b",
  4450. "msiof1_ss1_b",
  4451. "msiof1_ss2_b",
  4452. "msiof1_txd_b",
  4453. "msiof1_rxd_b",
  4454. "msiof1_clk_c",
  4455. "msiof1_sync_c",
  4456. "msiof1_ss1_c",
  4457. "msiof1_ss2_c",
  4458. "msiof1_txd_c",
  4459. "msiof1_rxd_c",
  4460. "msiof1_clk_d",
  4461. "msiof1_sync_d",
  4462. "msiof1_ss1_d",
  4463. "msiof1_ss2_d",
  4464. "msiof1_txd_d",
  4465. "msiof1_rxd_d",
  4466. "msiof1_clk_e",
  4467. "msiof1_sync_e",
  4468. "msiof1_ss1_e",
  4469. "msiof1_ss2_e",
  4470. "msiof1_txd_e",
  4471. "msiof1_rxd_e",
  4472. "msiof1_clk_f",
  4473. "msiof1_sync_f",
  4474. "msiof1_ss1_f",
  4475. "msiof1_ss2_f",
  4476. "msiof1_txd_f",
  4477. "msiof1_rxd_f",
  4478. "msiof1_clk_g",
  4479. "msiof1_sync_g",
  4480. "msiof1_ss1_g",
  4481. "msiof1_ss2_g",
  4482. "msiof1_txd_g",
  4483. "msiof1_rxd_g",
  4484. };
  4485. static const char * const msiof2_groups[] = {
  4486. "msiof2_clk_a",
  4487. "msiof2_sync_a",
  4488. "msiof2_ss1_a",
  4489. "msiof2_ss2_a",
  4490. "msiof2_txd_a",
  4491. "msiof2_rxd_a",
  4492. "msiof2_clk_b",
  4493. "msiof2_sync_b",
  4494. "msiof2_ss1_b",
  4495. "msiof2_ss2_b",
  4496. "msiof2_txd_b",
  4497. "msiof2_rxd_b",
  4498. "msiof2_clk_c",
  4499. "msiof2_sync_c",
  4500. "msiof2_ss1_c",
  4501. "msiof2_ss2_c",
  4502. "msiof2_txd_c",
  4503. "msiof2_rxd_c",
  4504. "msiof2_clk_d",
  4505. "msiof2_sync_d",
  4506. "msiof2_ss1_d",
  4507. "msiof2_ss2_d",
  4508. "msiof2_txd_d",
  4509. "msiof2_rxd_d",
  4510. };
  4511. static const char * const msiof3_groups[] = {
  4512. "msiof3_clk_a",
  4513. "msiof3_sync_a",
  4514. "msiof3_ss1_a",
  4515. "msiof3_ss2_a",
  4516. "msiof3_txd_a",
  4517. "msiof3_rxd_a",
  4518. "msiof3_clk_b",
  4519. "msiof3_sync_b",
  4520. "msiof3_ss1_b",
  4521. "msiof3_ss2_b",
  4522. "msiof3_txd_b",
  4523. "msiof3_rxd_b",
  4524. "msiof3_clk_c",
  4525. "msiof3_sync_c",
  4526. "msiof3_txd_c",
  4527. "msiof3_rxd_c",
  4528. "msiof3_clk_d",
  4529. "msiof3_sync_d",
  4530. "msiof3_ss1_d",
  4531. "msiof3_txd_d",
  4532. "msiof3_rxd_d",
  4533. "msiof3_clk_e",
  4534. "msiof3_sync_e",
  4535. "msiof3_ss1_e",
  4536. "msiof3_ss2_e",
  4537. "msiof3_txd_e",
  4538. "msiof3_rxd_e",
  4539. };
  4540. static const char * const pwm0_groups[] = {
  4541. "pwm0",
  4542. };
  4543. static const char * const pwm1_groups[] = {
  4544. "pwm1_a",
  4545. "pwm1_b",
  4546. };
  4547. static const char * const pwm2_groups[] = {
  4548. "pwm2_a",
  4549. "pwm2_b",
  4550. };
  4551. static const char * const pwm3_groups[] = {
  4552. "pwm3_a",
  4553. "pwm3_b",
  4554. };
  4555. static const char * const pwm4_groups[] = {
  4556. "pwm4_a",
  4557. "pwm4_b",
  4558. };
  4559. static const char * const pwm5_groups[] = {
  4560. "pwm5_a",
  4561. "pwm5_b",
  4562. };
  4563. static const char * const pwm6_groups[] = {
  4564. "pwm6_a",
  4565. "pwm6_b",
  4566. };
  4567. static const char * const scif0_groups[] = {
  4568. "scif0_data",
  4569. "scif0_clk",
  4570. "scif0_ctrl",
  4571. };
  4572. static const char * const scif1_groups[] = {
  4573. "scif1_data_a",
  4574. "scif1_clk",
  4575. "scif1_ctrl",
  4576. "scif1_data_b",
  4577. };
  4578. static const char * const scif2_groups[] = {
  4579. "scif2_data_a",
  4580. "scif2_clk",
  4581. "scif2_data_b",
  4582. };
  4583. static const char * const scif3_groups[] = {
  4584. "scif3_data_a",
  4585. "scif3_clk",
  4586. "scif3_ctrl",
  4587. "scif3_data_b",
  4588. };
  4589. static const char * const scif4_groups[] = {
  4590. "scif4_data_a",
  4591. "scif4_clk_a",
  4592. "scif4_ctrl_a",
  4593. "scif4_data_b",
  4594. "scif4_clk_b",
  4595. "scif4_ctrl_b",
  4596. "scif4_data_c",
  4597. "scif4_clk_c",
  4598. "scif4_ctrl_c",
  4599. };
  4600. static const char * const scif5_groups[] = {
  4601. "scif5_data_a",
  4602. "scif5_clk_a",
  4603. "scif5_data_b",
  4604. "scif5_clk_b",
  4605. };
  4606. static const char * const scif_clk_groups[] = {
  4607. "scif_clk_a",
  4608. "scif_clk_b",
  4609. };
  4610. static const char * const sdhi0_groups[] = {
  4611. "sdhi0_data1",
  4612. "sdhi0_data4",
  4613. "sdhi0_ctrl",
  4614. "sdhi0_cd",
  4615. "sdhi0_wp",
  4616. };
  4617. static const char * const sdhi1_groups[] = {
  4618. "sdhi1_data1",
  4619. "sdhi1_data4",
  4620. "sdhi1_ctrl",
  4621. "sdhi1_cd",
  4622. "sdhi1_wp",
  4623. };
  4624. static const char * const sdhi2_groups[] = {
  4625. "sdhi2_data1",
  4626. "sdhi2_data4",
  4627. "sdhi2_data8",
  4628. "sdhi2_ctrl",
  4629. "sdhi2_cd_a",
  4630. "sdhi2_wp_a",
  4631. "sdhi2_cd_b",
  4632. "sdhi2_wp_b",
  4633. "sdhi2_ds",
  4634. };
  4635. static const char * const sdhi3_groups[] = {
  4636. "sdhi3_data1",
  4637. "sdhi3_data4",
  4638. "sdhi3_data8",
  4639. "sdhi3_ctrl",
  4640. "sdhi3_cd",
  4641. "sdhi3_wp",
  4642. "sdhi3_ds",
  4643. };
  4644. static const char * const ssi_groups[] = {
  4645. "ssi0_data",
  4646. "ssi01239_ctrl",
  4647. "ssi1_data_a",
  4648. "ssi1_data_b",
  4649. "ssi1_ctrl_a",
  4650. "ssi1_ctrl_b",
  4651. "ssi2_data_a",
  4652. "ssi2_data_b",
  4653. "ssi2_ctrl_a",
  4654. "ssi2_ctrl_b",
  4655. "ssi3_data",
  4656. "ssi349_ctrl",
  4657. "ssi4_data",
  4658. "ssi4_ctrl",
  4659. "ssi5_data",
  4660. "ssi5_ctrl",
  4661. "ssi6_data",
  4662. "ssi6_ctrl",
  4663. "ssi7_data",
  4664. "ssi78_ctrl",
  4665. "ssi8_data",
  4666. "ssi9_data_a",
  4667. "ssi9_data_b",
  4668. "ssi9_ctrl_a",
  4669. "ssi9_ctrl_b",
  4670. };
  4671. static const char * const tmu_groups[] = {
  4672. "tmu_tclk1_a",
  4673. "tmu_tclk1_b",
  4674. "tmu_tclk2_a",
  4675. "tmu_tclk2_b",
  4676. };
  4677. static const char * const tpu_groups[] = {
  4678. "tpu_to0",
  4679. "tpu_to1",
  4680. "tpu_to2",
  4681. "tpu_to3",
  4682. };
  4683. static const char * const usb0_groups[] = {
  4684. "usb0",
  4685. };
  4686. static const char * const usb1_groups[] = {
  4687. "usb1",
  4688. };
  4689. static const char * const usb30_groups[] = {
  4690. "usb30",
  4691. };
  4692. static const char * const vin4_groups[] = {
  4693. "vin4_data8_a",
  4694. "vin4_data10_a",
  4695. "vin4_data12_a",
  4696. "vin4_data16_a",
  4697. "vin4_data18_a",
  4698. "vin4_data20_a",
  4699. "vin4_data24_a",
  4700. "vin4_data8_b",
  4701. "vin4_data10_b",
  4702. "vin4_data12_b",
  4703. "vin4_data16_b",
  4704. "vin4_data18_b",
  4705. "vin4_data20_b",
  4706. "vin4_data24_b",
  4707. "vin4_sync",
  4708. "vin4_field",
  4709. "vin4_clkenb",
  4710. "vin4_clk",
  4711. };
  4712. static const char * const vin5_groups[] = {
  4713. "vin5_data8",
  4714. "vin5_data10",
  4715. "vin5_data12",
  4716. "vin5_data16",
  4717. "vin5_sync",
  4718. "vin5_field",
  4719. "vin5_clkenb",
  4720. "vin5_clk",
  4721. };
  4722. static const struct {
  4723. struct sh_pfc_function common[50];
  4724. struct sh_pfc_function automotive[4];
  4725. } pinmux_functions = {
  4726. .common = {
  4727. SH_PFC_FUNCTION(audio_clk),
  4728. SH_PFC_FUNCTION(avb),
  4729. SH_PFC_FUNCTION(can0),
  4730. SH_PFC_FUNCTION(can1),
  4731. SH_PFC_FUNCTION(can_clk),
  4732. SH_PFC_FUNCTION(canfd0),
  4733. SH_PFC_FUNCTION(canfd1),
  4734. SH_PFC_FUNCTION(du),
  4735. SH_PFC_FUNCTION(hscif0),
  4736. SH_PFC_FUNCTION(hscif1),
  4737. SH_PFC_FUNCTION(hscif2),
  4738. SH_PFC_FUNCTION(hscif3),
  4739. SH_PFC_FUNCTION(hscif4),
  4740. SH_PFC_FUNCTION(i2c0),
  4741. SH_PFC_FUNCTION(i2c1),
  4742. SH_PFC_FUNCTION(i2c2),
  4743. SH_PFC_FUNCTION(i2c3),
  4744. SH_PFC_FUNCTION(i2c5),
  4745. SH_PFC_FUNCTION(i2c6),
  4746. SH_PFC_FUNCTION(intc_ex),
  4747. SH_PFC_FUNCTION(msiof0),
  4748. SH_PFC_FUNCTION(msiof1),
  4749. SH_PFC_FUNCTION(msiof2),
  4750. SH_PFC_FUNCTION(msiof3),
  4751. SH_PFC_FUNCTION(pwm0),
  4752. SH_PFC_FUNCTION(pwm1),
  4753. SH_PFC_FUNCTION(pwm2),
  4754. SH_PFC_FUNCTION(pwm3),
  4755. SH_PFC_FUNCTION(pwm4),
  4756. SH_PFC_FUNCTION(pwm5),
  4757. SH_PFC_FUNCTION(pwm6),
  4758. SH_PFC_FUNCTION(scif0),
  4759. SH_PFC_FUNCTION(scif1),
  4760. SH_PFC_FUNCTION(scif2),
  4761. SH_PFC_FUNCTION(scif3),
  4762. SH_PFC_FUNCTION(scif4),
  4763. SH_PFC_FUNCTION(scif5),
  4764. SH_PFC_FUNCTION(scif_clk),
  4765. SH_PFC_FUNCTION(sdhi0),
  4766. SH_PFC_FUNCTION(sdhi1),
  4767. SH_PFC_FUNCTION(sdhi2),
  4768. SH_PFC_FUNCTION(sdhi3),
  4769. SH_PFC_FUNCTION(ssi),
  4770. SH_PFC_FUNCTION(tmu),
  4771. SH_PFC_FUNCTION(tpu),
  4772. SH_PFC_FUNCTION(usb0),
  4773. SH_PFC_FUNCTION(usb1),
  4774. SH_PFC_FUNCTION(usb30),
  4775. SH_PFC_FUNCTION(vin4),
  4776. SH_PFC_FUNCTION(vin5),
  4777. },
  4778. .automotive = {
  4779. SH_PFC_FUNCTION(drif0),
  4780. SH_PFC_FUNCTION(drif1),
  4781. SH_PFC_FUNCTION(drif2),
  4782. SH_PFC_FUNCTION(drif3),
  4783. }
  4784. };
  4785. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  4786. #define F_(x, y) FN_##y
  4787. #define FM(x) FN_##x
  4788. { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
  4789. 0, 0,
  4790. 0, 0,
  4791. 0, 0,
  4792. 0, 0,
  4793. 0, 0,
  4794. 0, 0,
  4795. 0, 0,
  4796. 0, 0,
  4797. 0, 0,
  4798. 0, 0,
  4799. 0, 0,
  4800. 0, 0,
  4801. 0, 0,
  4802. 0, 0,
  4803. 0, 0,
  4804. 0, 0,
  4805. GP_0_15_FN, GPSR0_15,
  4806. GP_0_14_FN, GPSR0_14,
  4807. GP_0_13_FN, GPSR0_13,
  4808. GP_0_12_FN, GPSR0_12,
  4809. GP_0_11_FN, GPSR0_11,
  4810. GP_0_10_FN, GPSR0_10,
  4811. GP_0_9_FN, GPSR0_9,
  4812. GP_0_8_FN, GPSR0_8,
  4813. GP_0_7_FN, GPSR0_7,
  4814. GP_0_6_FN, GPSR0_6,
  4815. GP_0_5_FN, GPSR0_5,
  4816. GP_0_4_FN, GPSR0_4,
  4817. GP_0_3_FN, GPSR0_3,
  4818. GP_0_2_FN, GPSR0_2,
  4819. GP_0_1_FN, GPSR0_1,
  4820. GP_0_0_FN, GPSR0_0, ))
  4821. },
  4822. { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
  4823. 0, 0,
  4824. 0, 0,
  4825. 0, 0,
  4826. GP_1_28_FN, GPSR1_28,
  4827. GP_1_27_FN, GPSR1_27,
  4828. GP_1_26_FN, GPSR1_26,
  4829. GP_1_25_FN, GPSR1_25,
  4830. GP_1_24_FN, GPSR1_24,
  4831. GP_1_23_FN, GPSR1_23,
  4832. GP_1_22_FN, GPSR1_22,
  4833. GP_1_21_FN, GPSR1_21,
  4834. GP_1_20_FN, GPSR1_20,
  4835. GP_1_19_FN, GPSR1_19,
  4836. GP_1_18_FN, GPSR1_18,
  4837. GP_1_17_FN, GPSR1_17,
  4838. GP_1_16_FN, GPSR1_16,
  4839. GP_1_15_FN, GPSR1_15,
  4840. GP_1_14_FN, GPSR1_14,
  4841. GP_1_13_FN, GPSR1_13,
  4842. GP_1_12_FN, GPSR1_12,
  4843. GP_1_11_FN, GPSR1_11,
  4844. GP_1_10_FN, GPSR1_10,
  4845. GP_1_9_FN, GPSR1_9,
  4846. GP_1_8_FN, GPSR1_8,
  4847. GP_1_7_FN, GPSR1_7,
  4848. GP_1_6_FN, GPSR1_6,
  4849. GP_1_5_FN, GPSR1_5,
  4850. GP_1_4_FN, GPSR1_4,
  4851. GP_1_3_FN, GPSR1_3,
  4852. GP_1_2_FN, GPSR1_2,
  4853. GP_1_1_FN, GPSR1_1,
  4854. GP_1_0_FN, GPSR1_0, ))
  4855. },
  4856. { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
  4857. 0, 0,
  4858. 0, 0,
  4859. 0, 0,
  4860. 0, 0,
  4861. 0, 0,
  4862. 0, 0,
  4863. 0, 0,
  4864. 0, 0,
  4865. 0, 0,
  4866. 0, 0,
  4867. 0, 0,
  4868. 0, 0,
  4869. 0, 0,
  4870. 0, 0,
  4871. 0, 0,
  4872. 0, 0,
  4873. 0, 0,
  4874. GP_2_14_FN, GPSR2_14,
  4875. GP_2_13_FN, GPSR2_13,
  4876. GP_2_12_FN, GPSR2_12,
  4877. GP_2_11_FN, GPSR2_11,
  4878. GP_2_10_FN, GPSR2_10,
  4879. GP_2_9_FN, GPSR2_9,
  4880. GP_2_8_FN, GPSR2_8,
  4881. GP_2_7_FN, GPSR2_7,
  4882. GP_2_6_FN, GPSR2_6,
  4883. GP_2_5_FN, GPSR2_5,
  4884. GP_2_4_FN, GPSR2_4,
  4885. GP_2_3_FN, GPSR2_3,
  4886. GP_2_2_FN, GPSR2_2,
  4887. GP_2_1_FN, GPSR2_1,
  4888. GP_2_0_FN, GPSR2_0, ))
  4889. },
  4890. { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
  4891. 0, 0,
  4892. 0, 0,
  4893. 0, 0,
  4894. 0, 0,
  4895. 0, 0,
  4896. 0, 0,
  4897. 0, 0,
  4898. 0, 0,
  4899. 0, 0,
  4900. 0, 0,
  4901. 0, 0,
  4902. 0, 0,
  4903. 0, 0,
  4904. 0, 0,
  4905. 0, 0,
  4906. 0, 0,
  4907. GP_3_15_FN, GPSR3_15,
  4908. GP_3_14_FN, GPSR3_14,
  4909. GP_3_13_FN, GPSR3_13,
  4910. GP_3_12_FN, GPSR3_12,
  4911. GP_3_11_FN, GPSR3_11,
  4912. GP_3_10_FN, GPSR3_10,
  4913. GP_3_9_FN, GPSR3_9,
  4914. GP_3_8_FN, GPSR3_8,
  4915. GP_3_7_FN, GPSR3_7,
  4916. GP_3_6_FN, GPSR3_6,
  4917. GP_3_5_FN, GPSR3_5,
  4918. GP_3_4_FN, GPSR3_4,
  4919. GP_3_3_FN, GPSR3_3,
  4920. GP_3_2_FN, GPSR3_2,
  4921. GP_3_1_FN, GPSR3_1,
  4922. GP_3_0_FN, GPSR3_0, ))
  4923. },
  4924. { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
  4925. 0, 0,
  4926. 0, 0,
  4927. 0, 0,
  4928. 0, 0,
  4929. 0, 0,
  4930. 0, 0,
  4931. 0, 0,
  4932. 0, 0,
  4933. 0, 0,
  4934. 0, 0,
  4935. 0, 0,
  4936. 0, 0,
  4937. 0, 0,
  4938. 0, 0,
  4939. GP_4_17_FN, GPSR4_17,
  4940. GP_4_16_FN, GPSR4_16,
  4941. GP_4_15_FN, GPSR4_15,
  4942. GP_4_14_FN, GPSR4_14,
  4943. GP_4_13_FN, GPSR4_13,
  4944. GP_4_12_FN, GPSR4_12,
  4945. GP_4_11_FN, GPSR4_11,
  4946. GP_4_10_FN, GPSR4_10,
  4947. GP_4_9_FN, GPSR4_9,
  4948. GP_4_8_FN, GPSR4_8,
  4949. GP_4_7_FN, GPSR4_7,
  4950. GP_4_6_FN, GPSR4_6,
  4951. GP_4_5_FN, GPSR4_5,
  4952. GP_4_4_FN, GPSR4_4,
  4953. GP_4_3_FN, GPSR4_3,
  4954. GP_4_2_FN, GPSR4_2,
  4955. GP_4_1_FN, GPSR4_1,
  4956. GP_4_0_FN, GPSR4_0, ))
  4957. },
  4958. { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
  4959. 0, 0,
  4960. 0, 0,
  4961. 0, 0,
  4962. 0, 0,
  4963. 0, 0,
  4964. 0, 0,
  4965. GP_5_25_FN, GPSR5_25,
  4966. GP_5_24_FN, GPSR5_24,
  4967. GP_5_23_FN, GPSR5_23,
  4968. GP_5_22_FN, GPSR5_22,
  4969. GP_5_21_FN, GPSR5_21,
  4970. GP_5_20_FN, GPSR5_20,
  4971. GP_5_19_FN, GPSR5_19,
  4972. GP_5_18_FN, GPSR5_18,
  4973. GP_5_17_FN, GPSR5_17,
  4974. GP_5_16_FN, GPSR5_16,
  4975. GP_5_15_FN, GPSR5_15,
  4976. GP_5_14_FN, GPSR5_14,
  4977. GP_5_13_FN, GPSR5_13,
  4978. GP_5_12_FN, GPSR5_12,
  4979. GP_5_11_FN, GPSR5_11,
  4980. GP_5_10_FN, GPSR5_10,
  4981. GP_5_9_FN, GPSR5_9,
  4982. GP_5_8_FN, GPSR5_8,
  4983. GP_5_7_FN, GPSR5_7,
  4984. GP_5_6_FN, GPSR5_6,
  4985. GP_5_5_FN, GPSR5_5,
  4986. GP_5_4_FN, GPSR5_4,
  4987. GP_5_3_FN, GPSR5_3,
  4988. GP_5_2_FN, GPSR5_2,
  4989. GP_5_1_FN, GPSR5_1,
  4990. GP_5_0_FN, GPSR5_0, ))
  4991. },
  4992. { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
  4993. GP_6_31_FN, GPSR6_31,
  4994. GP_6_30_FN, GPSR6_30,
  4995. GP_6_29_FN, GPSR6_29,
  4996. GP_6_28_FN, GPSR6_28,
  4997. GP_6_27_FN, GPSR6_27,
  4998. GP_6_26_FN, GPSR6_26,
  4999. GP_6_25_FN, GPSR6_25,
  5000. GP_6_24_FN, GPSR6_24,
  5001. GP_6_23_FN, GPSR6_23,
  5002. GP_6_22_FN, GPSR6_22,
  5003. GP_6_21_FN, GPSR6_21,
  5004. GP_6_20_FN, GPSR6_20,
  5005. GP_6_19_FN, GPSR6_19,
  5006. GP_6_18_FN, GPSR6_18,
  5007. GP_6_17_FN, GPSR6_17,
  5008. GP_6_16_FN, GPSR6_16,
  5009. GP_6_15_FN, GPSR6_15,
  5010. GP_6_14_FN, GPSR6_14,
  5011. GP_6_13_FN, GPSR6_13,
  5012. GP_6_12_FN, GPSR6_12,
  5013. GP_6_11_FN, GPSR6_11,
  5014. GP_6_10_FN, GPSR6_10,
  5015. GP_6_9_FN, GPSR6_9,
  5016. GP_6_8_FN, GPSR6_8,
  5017. GP_6_7_FN, GPSR6_7,
  5018. GP_6_6_FN, GPSR6_6,
  5019. GP_6_5_FN, GPSR6_5,
  5020. GP_6_4_FN, GPSR6_4,
  5021. GP_6_3_FN, GPSR6_3,
  5022. GP_6_2_FN, GPSR6_2,
  5023. GP_6_1_FN, GPSR6_1,
  5024. GP_6_0_FN, GPSR6_0, ))
  5025. },
  5026. { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
  5027. 0, 0,
  5028. 0, 0,
  5029. 0, 0,
  5030. 0, 0,
  5031. 0, 0,
  5032. 0, 0,
  5033. 0, 0,
  5034. 0, 0,
  5035. 0, 0,
  5036. 0, 0,
  5037. 0, 0,
  5038. 0, 0,
  5039. 0, 0,
  5040. 0, 0,
  5041. 0, 0,
  5042. 0, 0,
  5043. 0, 0,
  5044. 0, 0,
  5045. 0, 0,
  5046. 0, 0,
  5047. 0, 0,
  5048. 0, 0,
  5049. 0, 0,
  5050. 0, 0,
  5051. 0, 0,
  5052. 0, 0,
  5053. 0, 0,
  5054. 0, 0,
  5055. GP_7_3_FN, GPSR7_3,
  5056. GP_7_2_FN, GPSR7_2,
  5057. GP_7_1_FN, GPSR7_1,
  5058. GP_7_0_FN, GPSR7_0, ))
  5059. },
  5060. #undef F_
  5061. #undef FM
  5062. #define F_(x, y) x,
  5063. #define FM(x) FN_##x,
  5064. { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
  5065. IP0_31_28
  5066. IP0_27_24
  5067. IP0_23_20
  5068. IP0_19_16
  5069. IP0_15_12
  5070. IP0_11_8
  5071. IP0_7_4
  5072. IP0_3_0 ))
  5073. },
  5074. { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
  5075. IP1_31_28
  5076. IP1_27_24
  5077. IP1_23_20
  5078. IP1_19_16
  5079. IP1_15_12
  5080. IP1_11_8
  5081. IP1_7_4
  5082. IP1_3_0 ))
  5083. },
  5084. { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
  5085. IP2_31_28
  5086. IP2_27_24
  5087. IP2_23_20
  5088. IP2_19_16
  5089. IP2_15_12
  5090. IP2_11_8
  5091. IP2_7_4
  5092. IP2_3_0 ))
  5093. },
  5094. { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
  5095. IP3_31_28
  5096. IP3_27_24
  5097. IP3_23_20
  5098. IP3_19_16
  5099. IP3_15_12
  5100. IP3_11_8
  5101. IP3_7_4
  5102. IP3_3_0 ))
  5103. },
  5104. { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
  5105. IP4_31_28
  5106. IP4_27_24
  5107. IP4_23_20
  5108. IP4_19_16
  5109. IP4_15_12
  5110. IP4_11_8
  5111. IP4_7_4
  5112. IP4_3_0 ))
  5113. },
  5114. { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
  5115. IP5_31_28
  5116. IP5_27_24
  5117. IP5_23_20
  5118. IP5_19_16
  5119. IP5_15_12
  5120. IP5_11_8
  5121. IP5_7_4
  5122. IP5_3_0 ))
  5123. },
  5124. { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
  5125. IP6_31_28
  5126. IP6_27_24
  5127. IP6_23_20
  5128. IP6_19_16
  5129. IP6_15_12
  5130. IP6_11_8
  5131. IP6_7_4
  5132. IP6_3_0 ))
  5133. },
  5134. { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
  5135. IP7_31_28
  5136. IP7_27_24
  5137. IP7_23_20
  5138. IP7_19_16
  5139. /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5140. IP7_11_8
  5141. IP7_7_4
  5142. IP7_3_0 ))
  5143. },
  5144. { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
  5145. IP8_31_28
  5146. IP8_27_24
  5147. IP8_23_20
  5148. IP8_19_16
  5149. IP8_15_12
  5150. IP8_11_8
  5151. IP8_7_4
  5152. IP8_3_0 ))
  5153. },
  5154. { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
  5155. IP9_31_28
  5156. IP9_27_24
  5157. IP9_23_20
  5158. IP9_19_16
  5159. IP9_15_12
  5160. IP9_11_8
  5161. IP9_7_4
  5162. IP9_3_0 ))
  5163. },
  5164. { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
  5165. IP10_31_28
  5166. IP10_27_24
  5167. IP10_23_20
  5168. IP10_19_16
  5169. IP10_15_12
  5170. IP10_11_8
  5171. IP10_7_4
  5172. IP10_3_0 ))
  5173. },
  5174. { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
  5175. IP11_31_28
  5176. IP11_27_24
  5177. IP11_23_20
  5178. IP11_19_16
  5179. IP11_15_12
  5180. IP11_11_8
  5181. IP11_7_4
  5182. IP11_3_0 ))
  5183. },
  5184. { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
  5185. IP12_31_28
  5186. IP12_27_24
  5187. IP12_23_20
  5188. IP12_19_16
  5189. IP12_15_12
  5190. IP12_11_8
  5191. IP12_7_4
  5192. IP12_3_0 ))
  5193. },
  5194. { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
  5195. IP13_31_28
  5196. IP13_27_24
  5197. IP13_23_20
  5198. IP13_19_16
  5199. IP13_15_12
  5200. IP13_11_8
  5201. IP13_7_4
  5202. IP13_3_0 ))
  5203. },
  5204. { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
  5205. IP14_31_28
  5206. IP14_27_24
  5207. IP14_23_20
  5208. IP14_19_16
  5209. IP14_15_12
  5210. IP14_11_8
  5211. IP14_7_4
  5212. IP14_3_0 ))
  5213. },
  5214. { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
  5215. IP15_31_28
  5216. IP15_27_24
  5217. IP15_23_20
  5218. IP15_19_16
  5219. IP15_15_12
  5220. IP15_11_8
  5221. IP15_7_4
  5222. IP15_3_0 ))
  5223. },
  5224. { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
  5225. IP16_31_28
  5226. IP16_27_24
  5227. IP16_23_20
  5228. IP16_19_16
  5229. IP16_15_12
  5230. IP16_11_8
  5231. IP16_7_4
  5232. IP16_3_0 ))
  5233. },
  5234. { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
  5235. IP17_31_28
  5236. IP17_27_24
  5237. IP17_23_20
  5238. IP17_19_16
  5239. IP17_15_12
  5240. IP17_11_8
  5241. IP17_7_4
  5242. IP17_3_0 ))
  5243. },
  5244. { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
  5245. /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5246. /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5247. /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5248. /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5249. /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5250. /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5251. IP18_7_4
  5252. IP18_3_0 ))
  5253. },
  5254. #undef F_
  5255. #undef FM
  5256. #define F_(x, y) x,
  5257. #define FM(x) FN_##x,
  5258. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
  5259. GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
  5260. 1, 1, 1, 2, 2, 1, 2, 3),
  5261. GROUP(
  5262. MOD_SEL0_31_30_29
  5263. MOD_SEL0_28_27
  5264. MOD_SEL0_26_25_24
  5265. MOD_SEL0_23
  5266. MOD_SEL0_22
  5267. MOD_SEL0_21
  5268. MOD_SEL0_20
  5269. MOD_SEL0_19
  5270. MOD_SEL0_18_17
  5271. MOD_SEL0_16
  5272. 0, 0, /* RESERVED 15 */
  5273. MOD_SEL0_14_13
  5274. MOD_SEL0_12
  5275. MOD_SEL0_11
  5276. MOD_SEL0_10
  5277. MOD_SEL0_9_8
  5278. MOD_SEL0_7_6
  5279. MOD_SEL0_5
  5280. MOD_SEL0_4_3
  5281. /* RESERVED 2, 1, 0 */
  5282. 0, 0, 0, 0, 0, 0, 0, 0 ))
  5283. },
  5284. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
  5285. GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
  5286. 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
  5287. GROUP(
  5288. MOD_SEL1_31_30
  5289. MOD_SEL1_29_28_27
  5290. MOD_SEL1_26
  5291. MOD_SEL1_25_24
  5292. MOD_SEL1_23_22_21
  5293. MOD_SEL1_20
  5294. MOD_SEL1_19
  5295. MOD_SEL1_18_17
  5296. MOD_SEL1_16
  5297. MOD_SEL1_15_14
  5298. MOD_SEL1_13
  5299. MOD_SEL1_12
  5300. MOD_SEL1_11
  5301. MOD_SEL1_10
  5302. MOD_SEL1_9
  5303. 0, 0, 0, 0, /* RESERVED 8, 7 */
  5304. MOD_SEL1_6
  5305. MOD_SEL1_5
  5306. MOD_SEL1_4
  5307. MOD_SEL1_3
  5308. MOD_SEL1_2
  5309. MOD_SEL1_1
  5310. MOD_SEL1_0 ))
  5311. },
  5312. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
  5313. GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
  5314. 1, 4, 4, 4, 3, 1),
  5315. GROUP(
  5316. MOD_SEL2_31
  5317. MOD_SEL2_30
  5318. MOD_SEL2_29
  5319. MOD_SEL2_28_27
  5320. MOD_SEL2_26
  5321. MOD_SEL2_25_24_23
  5322. MOD_SEL2_22
  5323. MOD_SEL2_21
  5324. MOD_SEL2_20
  5325. MOD_SEL2_19
  5326. MOD_SEL2_18
  5327. MOD_SEL2_17
  5328. /* RESERVED 16 */
  5329. 0, 0,
  5330. /* RESERVED 15, 14, 13, 12 */
  5331. 0, 0, 0, 0, 0, 0, 0, 0,
  5332. 0, 0, 0, 0, 0, 0, 0, 0,
  5333. /* RESERVED 11, 10, 9, 8 */
  5334. 0, 0, 0, 0, 0, 0, 0, 0,
  5335. 0, 0, 0, 0, 0, 0, 0, 0,
  5336. /* RESERVED 7, 6, 5, 4 */
  5337. 0, 0, 0, 0, 0, 0, 0, 0,
  5338. 0, 0, 0, 0, 0, 0, 0, 0,
  5339. /* RESERVED 3, 2, 1 */
  5340. 0, 0, 0, 0, 0, 0, 0, 0,
  5341. MOD_SEL2_0 ))
  5342. },
  5343. { },
  5344. };
  5345. static const struct pinmux_drive_reg pinmux_drive_regs[] = {
  5346. { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
  5347. { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
  5348. { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
  5349. { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
  5350. { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
  5351. { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
  5352. { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
  5353. { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
  5354. { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
  5355. } },
  5356. { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
  5357. { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
  5358. { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
  5359. { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
  5360. { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
  5361. { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
  5362. { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
  5363. { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
  5364. { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
  5365. } },
  5366. { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
  5367. { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
  5368. { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
  5369. { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
  5370. { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
  5371. { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
  5372. { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
  5373. { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
  5374. { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
  5375. } },
  5376. { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
  5377. { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
  5378. { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
  5379. { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
  5380. { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
  5381. { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
  5382. { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
  5383. { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
  5384. { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
  5385. } },
  5386. { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
  5387. { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
  5388. { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
  5389. { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
  5390. { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
  5391. { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
  5392. { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
  5393. { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
  5394. { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
  5395. } },
  5396. { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
  5397. { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
  5398. { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
  5399. { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
  5400. { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
  5401. { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
  5402. { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
  5403. { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
  5404. { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
  5405. } },
  5406. { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
  5407. { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
  5408. { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
  5409. { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
  5410. { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
  5411. { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
  5412. { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
  5413. { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
  5414. { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
  5415. } },
  5416. { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
  5417. { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
  5418. { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
  5419. { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
  5420. { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
  5421. { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
  5422. { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
  5423. { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
  5424. { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
  5425. } },
  5426. { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
  5427. { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
  5428. { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
  5429. { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
  5430. { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
  5431. { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
  5432. { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
  5433. { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
  5434. { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
  5435. } },
  5436. { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
  5437. { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
  5438. { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
  5439. { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
  5440. { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
  5441. { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
  5442. { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
  5443. { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
  5444. { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
  5445. } },
  5446. { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
  5447. { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
  5448. { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
  5449. { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
  5450. { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
  5451. { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
  5452. { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
  5453. { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
  5454. { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
  5455. } },
  5456. { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
  5457. { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
  5458. { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
  5459. { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
  5460. { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
  5461. { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
  5462. { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
  5463. { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
  5464. { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
  5465. } },
  5466. { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
  5467. { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
  5468. { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
  5469. { PIN_TMS, 4, 2 }, /* TMS */
  5470. } },
  5471. { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
  5472. { PIN_TDO, 28, 2 }, /* TDO */
  5473. { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
  5474. { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
  5475. { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
  5476. { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
  5477. { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
  5478. { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
  5479. { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
  5480. } },
  5481. { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
  5482. { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
  5483. { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
  5484. { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
  5485. { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
  5486. { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
  5487. { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
  5488. { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
  5489. { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
  5490. } },
  5491. { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
  5492. { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
  5493. { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
  5494. { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
  5495. { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
  5496. { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
  5497. { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
  5498. { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
  5499. { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
  5500. } },
  5501. { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
  5502. { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
  5503. { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
  5504. { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
  5505. { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
  5506. { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
  5507. { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
  5508. { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
  5509. { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
  5510. } },
  5511. { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
  5512. { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
  5513. { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
  5514. { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
  5515. { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
  5516. { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
  5517. { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
  5518. { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
  5519. { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
  5520. } },
  5521. { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
  5522. { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
  5523. { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
  5524. { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
  5525. { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
  5526. { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
  5527. { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
  5528. { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
  5529. { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
  5530. } },
  5531. { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
  5532. { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
  5533. { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
  5534. { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
  5535. { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
  5536. { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
  5537. { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
  5538. { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
  5539. { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
  5540. } },
  5541. { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
  5542. { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
  5543. { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
  5544. { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
  5545. { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
  5546. { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
  5547. { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
  5548. { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
  5549. { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
  5550. } },
  5551. { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
  5552. { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
  5553. { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
  5554. { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
  5555. { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
  5556. { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
  5557. { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
  5558. { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
  5559. { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
  5560. } },
  5561. { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
  5562. { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
  5563. { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
  5564. { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
  5565. { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
  5566. { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
  5567. { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
  5568. { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
  5569. { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
  5570. } },
  5571. { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
  5572. { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
  5573. { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
  5574. { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
  5575. { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
  5576. { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
  5577. { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
  5578. { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
  5579. { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
  5580. } },
  5581. { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
  5582. { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
  5583. { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
  5584. { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
  5585. { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
  5586. { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
  5587. { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
  5588. { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
  5589. } },
  5590. { },
  5591. };
  5592. enum ioctrl_regs {
  5593. POCCTRL,
  5594. TDSELCTRL,
  5595. };
  5596. static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
  5597. [POCCTRL] = { 0xe6060380, },
  5598. [TDSELCTRL] = { 0xe60603c0, },
  5599. { /* sentinel */ },
  5600. };
  5601. static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
  5602. {
  5603. int bit = -EINVAL;
  5604. *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
  5605. if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
  5606. bit = pin & 0x1f;
  5607. if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
  5608. bit = (pin & 0x1f) + 12;
  5609. return bit;
  5610. }
  5611. static const struct pinmux_bias_reg pinmux_bias_regs[] = {
  5612. { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
  5613. [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
  5614. [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
  5615. [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
  5616. [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
  5617. [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
  5618. [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
  5619. [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
  5620. [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
  5621. [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
  5622. [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
  5623. [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
  5624. [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
  5625. [12] = PIN_RPC_INT_N, /* RPC_INT# */
  5626. [13] = PIN_RPC_WP_N, /* RPC_WP# */
  5627. [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
  5628. [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
  5629. [16] = PIN_AVB_RXC, /* AVB_RXC */
  5630. [17] = PIN_AVB_RD0, /* AVB_RD0 */
  5631. [18] = PIN_AVB_RD1, /* AVB_RD1 */
  5632. [19] = PIN_AVB_RD2, /* AVB_RD2 */
  5633. [20] = PIN_AVB_RD3, /* AVB_RD3 */
  5634. [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
  5635. [22] = PIN_AVB_TXC, /* AVB_TXC */
  5636. [23] = PIN_AVB_TD0, /* AVB_TD0 */
  5637. [24] = PIN_AVB_TD1, /* AVB_TD1 */
  5638. [25] = PIN_AVB_TD2, /* AVB_TD2 */
  5639. [26] = PIN_AVB_TD3, /* AVB_TD3 */
  5640. [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
  5641. [28] = PIN_AVB_MDIO, /* AVB_MDIO */
  5642. [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
  5643. [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
  5644. [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
  5645. } },
  5646. { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
  5647. [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
  5648. [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
  5649. [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
  5650. [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
  5651. [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
  5652. [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
  5653. [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
  5654. [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
  5655. [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
  5656. [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
  5657. [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
  5658. [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
  5659. [12] = RCAR_GP_PIN(1, 0), /* A0 */
  5660. [13] = RCAR_GP_PIN(1, 1), /* A1 */
  5661. [14] = RCAR_GP_PIN(1, 2), /* A2 */
  5662. [15] = RCAR_GP_PIN(1, 3), /* A3 */
  5663. [16] = RCAR_GP_PIN(1, 4), /* A4 */
  5664. [17] = RCAR_GP_PIN(1, 5), /* A5 */
  5665. [18] = RCAR_GP_PIN(1, 6), /* A6 */
  5666. [19] = RCAR_GP_PIN(1, 7), /* A7 */
  5667. [20] = RCAR_GP_PIN(1, 8), /* A8 */
  5668. [21] = RCAR_GP_PIN(1, 9), /* A9 */
  5669. [22] = RCAR_GP_PIN(1, 10), /* A10 */
  5670. [23] = RCAR_GP_PIN(1, 11), /* A11 */
  5671. [24] = RCAR_GP_PIN(1, 12), /* A12 */
  5672. [25] = RCAR_GP_PIN(1, 13), /* A13 */
  5673. [26] = RCAR_GP_PIN(1, 14), /* A14 */
  5674. [27] = RCAR_GP_PIN(1, 15), /* A15 */
  5675. [28] = RCAR_GP_PIN(1, 16), /* A16 */
  5676. [29] = RCAR_GP_PIN(1, 17), /* A17 */
  5677. [30] = RCAR_GP_PIN(1, 18), /* A18 */
  5678. [31] = RCAR_GP_PIN(1, 19), /* A19 */
  5679. } },
  5680. { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
  5681. [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
  5682. [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
  5683. [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
  5684. [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
  5685. [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
  5686. [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
  5687. [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
  5688. [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
  5689. [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
  5690. [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
  5691. [10] = RCAR_GP_PIN(0, 0), /* D0 */
  5692. [11] = RCAR_GP_PIN(0, 1), /* D1 */
  5693. [12] = RCAR_GP_PIN(0, 2), /* D2 */
  5694. [13] = RCAR_GP_PIN(0, 3), /* D3 */
  5695. [14] = RCAR_GP_PIN(0, 4), /* D4 */
  5696. [15] = RCAR_GP_PIN(0, 5), /* D5 */
  5697. [16] = RCAR_GP_PIN(0, 6), /* D6 */
  5698. [17] = RCAR_GP_PIN(0, 7), /* D7 */
  5699. [18] = RCAR_GP_PIN(0, 8), /* D8 */
  5700. [19] = RCAR_GP_PIN(0, 9), /* D9 */
  5701. [20] = RCAR_GP_PIN(0, 10), /* D10 */
  5702. [21] = RCAR_GP_PIN(0, 11), /* D11 */
  5703. [22] = RCAR_GP_PIN(0, 12), /* D12 */
  5704. [23] = RCAR_GP_PIN(0, 13), /* D13 */
  5705. [24] = RCAR_GP_PIN(0, 14), /* D14 */
  5706. [25] = RCAR_GP_PIN(0, 15), /* D15 */
  5707. [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
  5708. [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
  5709. [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
  5710. [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
  5711. [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
  5712. [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
  5713. } },
  5714. { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
  5715. [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
  5716. [ 1] = SH_PFC_PIN_NONE,
  5717. [ 2] = PIN_FSCLKST, /* FSCLKST */
  5718. [ 3] = PIN_EXTALR, /* EXTALR*/
  5719. [ 4] = PIN_TRST_N, /* TRST# */
  5720. [ 5] = PIN_TCK, /* TCK */
  5721. [ 6] = PIN_TMS, /* TMS */
  5722. [ 7] = PIN_TDI, /* TDI */
  5723. [ 8] = SH_PFC_PIN_NONE,
  5724. [ 9] = PIN_ASEBRK, /* ASEBRK */
  5725. [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
  5726. [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
  5727. [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
  5728. [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
  5729. [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
  5730. [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
  5731. [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
  5732. [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
  5733. [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
  5734. [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
  5735. [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
  5736. [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
  5737. [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
  5738. [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
  5739. [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
  5740. [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
  5741. [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
  5742. [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
  5743. [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
  5744. [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
  5745. [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
  5746. [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
  5747. } },
  5748. { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
  5749. [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
  5750. [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
  5751. [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
  5752. [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
  5753. [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
  5754. [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
  5755. [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
  5756. [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
  5757. [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
  5758. [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
  5759. [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
  5760. [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
  5761. [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
  5762. [13] = RCAR_GP_PIN(5, 1), /* RX0 */
  5763. [14] = RCAR_GP_PIN(5, 2), /* TX0 */
  5764. [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
  5765. [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
  5766. [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
  5767. [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
  5768. [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
  5769. [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
  5770. [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
  5771. [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
  5772. [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
  5773. [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
  5774. [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
  5775. [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
  5776. [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
  5777. [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
  5778. [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
  5779. [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
  5780. [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
  5781. } },
  5782. { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
  5783. [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
  5784. [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
  5785. [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
  5786. [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
  5787. [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
  5788. [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
  5789. [ 6] = PIN_MLB_REF, /* MLB_REF */
  5790. [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
  5791. [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
  5792. [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
  5793. [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
  5794. [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
  5795. [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
  5796. [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
  5797. [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
  5798. [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
  5799. [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
  5800. [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
  5801. [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
  5802. [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
  5803. [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
  5804. [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
  5805. [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
  5806. [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
  5807. [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
  5808. [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
  5809. [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
  5810. [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
  5811. [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
  5812. [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
  5813. [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
  5814. [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
  5815. } },
  5816. { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
  5817. [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
  5818. [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
  5819. [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
  5820. [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
  5821. [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
  5822. [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
  5823. [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
  5824. [ 7] = PIN_PRESET_N, /* PRESET# */
  5825. [ 8] = SH_PFC_PIN_NONE,
  5826. [ 9] = SH_PFC_PIN_NONE,
  5827. [10] = SH_PFC_PIN_NONE,
  5828. [11] = SH_PFC_PIN_NONE,
  5829. [12] = SH_PFC_PIN_NONE,
  5830. [13] = SH_PFC_PIN_NONE,
  5831. [14] = SH_PFC_PIN_NONE,
  5832. [15] = SH_PFC_PIN_NONE,
  5833. [16] = SH_PFC_PIN_NONE,
  5834. [17] = SH_PFC_PIN_NONE,
  5835. [18] = SH_PFC_PIN_NONE,
  5836. [19] = SH_PFC_PIN_NONE,
  5837. [20] = SH_PFC_PIN_NONE,
  5838. [21] = SH_PFC_PIN_NONE,
  5839. [22] = SH_PFC_PIN_NONE,
  5840. [23] = SH_PFC_PIN_NONE,
  5841. [24] = SH_PFC_PIN_NONE,
  5842. [25] = SH_PFC_PIN_NONE,
  5843. [26] = SH_PFC_PIN_NONE,
  5844. [27] = SH_PFC_PIN_NONE,
  5845. [28] = SH_PFC_PIN_NONE,
  5846. [29] = SH_PFC_PIN_NONE,
  5847. [30] = SH_PFC_PIN_NONE,
  5848. [31] = SH_PFC_PIN_NONE,
  5849. } },
  5850. { /* sentinel */ },
  5851. };
  5852. static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
  5853. unsigned int pin)
  5854. {
  5855. const struct pinmux_bias_reg *reg;
  5856. unsigned int bit;
  5857. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  5858. if (!reg)
  5859. return PIN_CONFIG_BIAS_DISABLE;
  5860. if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
  5861. return PIN_CONFIG_BIAS_DISABLE;
  5862. else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
  5863. return PIN_CONFIG_BIAS_PULL_UP;
  5864. else
  5865. return PIN_CONFIG_BIAS_PULL_DOWN;
  5866. }
  5867. static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  5868. unsigned int bias)
  5869. {
  5870. const struct pinmux_bias_reg *reg;
  5871. u32 enable, updown;
  5872. unsigned int bit;
  5873. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  5874. if (!reg)
  5875. return;
  5876. enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
  5877. if (bias != PIN_CONFIG_BIAS_DISABLE)
  5878. enable |= BIT(bit);
  5879. updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
  5880. if (bias == PIN_CONFIG_BIAS_PULL_UP)
  5881. updown |= BIT(bit);
  5882. sh_pfc_write(pfc, reg->pud, updown);
  5883. sh_pfc_write(pfc, reg->puen, enable);
  5884. }
  5885. static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
  5886. .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
  5887. .get_bias = r8a7796_pinmux_get_bias,
  5888. .set_bias = r8a7796_pinmux_set_bias,
  5889. };
  5890. #ifdef CONFIG_PINCTRL_PFC_R8A774A1
  5891. const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
  5892. .name = "r8a774a1_pfc",
  5893. .ops = &r8a7796_pinmux_ops,
  5894. .unlock_reg = 0xe6060000, /* PMMR */
  5895. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5896. .pins = pinmux_pins,
  5897. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5898. .groups = pinmux_groups.common,
  5899. .nr_groups = ARRAY_SIZE(pinmux_groups.common),
  5900. .functions = pinmux_functions.common,
  5901. .nr_functions = ARRAY_SIZE(pinmux_functions.common),
  5902. .cfg_regs = pinmux_config_regs,
  5903. .drive_regs = pinmux_drive_regs,
  5904. .bias_regs = pinmux_bias_regs,
  5905. .ioctrl_regs = pinmux_ioctrl_regs,
  5906. .pinmux_data = pinmux_data,
  5907. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5908. };
  5909. #endif
  5910. #ifdef CONFIG_PINCTRL_PFC_R8A77960
  5911. const struct sh_pfc_soc_info r8a77960_pinmux_info = {
  5912. .name = "r8a77960_pfc",
  5913. .ops = &r8a7796_pinmux_ops,
  5914. .unlock_reg = 0xe6060000, /* PMMR */
  5915. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5916. .pins = pinmux_pins,
  5917. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5918. .groups = pinmux_groups.common,
  5919. .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
  5920. ARRAY_SIZE(pinmux_groups.automotive),
  5921. .functions = pinmux_functions.common,
  5922. .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
  5923. ARRAY_SIZE(pinmux_functions.automotive),
  5924. .cfg_regs = pinmux_config_regs,
  5925. .drive_regs = pinmux_drive_regs,
  5926. .bias_regs = pinmux_bias_regs,
  5927. .ioctrl_regs = pinmux_ioctrl_regs,
  5928. .pinmux_data = pinmux_data,
  5929. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5930. };
  5931. #endif
  5932. #ifdef CONFIG_PINCTRL_PFC_R8A77961
  5933. const struct sh_pfc_soc_info r8a77961_pinmux_info = {
  5934. .name = "r8a77961_pfc",
  5935. .ops = &r8a7796_pinmux_ops,
  5936. .unlock_reg = 0xe6060000, /* PMMR */
  5937. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5938. .pins = pinmux_pins,
  5939. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5940. .groups = pinmux_groups.common,
  5941. .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
  5942. ARRAY_SIZE(pinmux_groups.automotive),
  5943. .functions = pinmux_functions.common,
  5944. .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
  5945. ARRAY_SIZE(pinmux_functions.automotive),
  5946. .cfg_regs = pinmux_config_regs,
  5947. .drive_regs = pinmux_drive_regs,
  5948. .bias_regs = pinmux_bias_regs,
  5949. .ioctrl_regs = pinmux_ioctrl_regs,
  5950. .pinmux_data = pinmux_data,
  5951. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5952. };
  5953. #endif