pfc-r8a77950.c 189 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A77950 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2015-2017 Renesas Electronics Corporation
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/kernel.h>
  9. #include "core.h"
  10. #include "sh_pfc.h"
  11. #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  12. #define CPU_ALL_GP(fn, sfx) \
  13. PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
  14. PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
  15. PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
  16. PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  17. PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
  18. PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
  19. PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
  20. PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
  21. PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
  22. PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
  23. PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
  24. PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  25. #define CPU_ALL_NOGP(fn) \
  26. PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
  27. PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
  28. PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
  29. PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
  30. PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
  31. PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
  32. PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
  33. PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
  34. PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
  35. PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
  36. PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
  37. PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
  38. PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
  39. PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
  40. PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
  41. PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
  42. PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
  43. PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
  44. PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
  45. PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
  46. PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
  47. PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
  48. PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
  49. PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
  50. PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
  51. PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
  52. PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
  53. PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
  54. PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
  55. PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
  56. PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
  57. PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
  58. PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
  59. PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
  60. PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
  61. PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
  62. PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
  63. PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
  64. PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
  65. PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  66. PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  67. PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
  68. PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
  69. PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  70. /*
  71. * F_() : just information
  72. * FM() : macro for FN_xxx / xxx_MARK
  73. */
  74. /* GPSR0 */
  75. #define GPSR0_15 F_(D15, IP7_11_8)
  76. #define GPSR0_14 F_(D14, IP7_7_4)
  77. #define GPSR0_13 F_(D13, IP7_3_0)
  78. #define GPSR0_12 F_(D12, IP6_31_28)
  79. #define GPSR0_11 F_(D11, IP6_27_24)
  80. #define GPSR0_10 F_(D10, IP6_23_20)
  81. #define GPSR0_9 F_(D9, IP6_19_16)
  82. #define GPSR0_8 F_(D8, IP6_15_12)
  83. #define GPSR0_7 F_(D7, IP6_11_8)
  84. #define GPSR0_6 F_(D6, IP6_7_4)
  85. #define GPSR0_5 F_(D5, IP6_3_0)
  86. #define GPSR0_4 F_(D4, IP5_31_28)
  87. #define GPSR0_3 F_(D3, IP5_27_24)
  88. #define GPSR0_2 F_(D2, IP5_23_20)
  89. #define GPSR0_1 F_(D1, IP5_19_16)
  90. #define GPSR0_0 F_(D0, IP5_15_12)
  91. /* GPSR1 */
  92. #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
  93. #define GPSR1_26 F_(WE1_N, IP5_7_4)
  94. #define GPSR1_25 F_(WE0_N, IP5_3_0)
  95. #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
  96. #define GPSR1_23 F_(RD_N, IP4_27_24)
  97. #define GPSR1_22 F_(BS_N, IP4_23_20)
  98. #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
  99. #define GPSR1_20 F_(CS0_N, IP4_15_12)
  100. #define GPSR1_19 F_(A19, IP4_11_8)
  101. #define GPSR1_18 F_(A18, IP4_7_4)
  102. #define GPSR1_17 F_(A17, IP4_3_0)
  103. #define GPSR1_16 F_(A16, IP3_31_28)
  104. #define GPSR1_15 F_(A15, IP3_27_24)
  105. #define GPSR1_14 F_(A14, IP3_23_20)
  106. #define GPSR1_13 F_(A13, IP3_19_16)
  107. #define GPSR1_12 F_(A12, IP3_15_12)
  108. #define GPSR1_11 F_(A11, IP3_11_8)
  109. #define GPSR1_10 F_(A10, IP3_7_4)
  110. #define GPSR1_9 F_(A9, IP3_3_0)
  111. #define GPSR1_8 F_(A8, IP2_31_28)
  112. #define GPSR1_7 F_(A7, IP2_27_24)
  113. #define GPSR1_6 F_(A6, IP2_23_20)
  114. #define GPSR1_5 F_(A5, IP2_19_16)
  115. #define GPSR1_4 F_(A4, IP2_15_12)
  116. #define GPSR1_3 F_(A3, IP2_11_8)
  117. #define GPSR1_2 F_(A2, IP2_7_4)
  118. #define GPSR1_1 F_(A1, IP2_3_0)
  119. #define GPSR1_0 F_(A0, IP1_31_28)
  120. /* GPSR2 */
  121. #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
  122. #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
  123. #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
  124. #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
  125. #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
  126. #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
  127. #define GPSR2_8 F_(PWM2_A, IP1_27_24)
  128. #define GPSR2_7 F_(PWM1_A, IP1_23_20)
  129. #define GPSR2_6 F_(PWM0, IP1_19_16)
  130. #define GPSR2_5 F_(IRQ5, IP1_15_12)
  131. #define GPSR2_4 F_(IRQ4, IP1_11_8)
  132. #define GPSR2_3 F_(IRQ3, IP1_7_4)
  133. #define GPSR2_2 F_(IRQ2, IP1_3_0)
  134. #define GPSR2_1 F_(IRQ1, IP0_31_28)
  135. #define GPSR2_0 F_(IRQ0, IP0_27_24)
  136. /* GPSR3 */
  137. #define GPSR3_15 F_(SD1_WP, IP10_23_20)
  138. #define GPSR3_14 F_(SD1_CD, IP10_19_16)
  139. #define GPSR3_13 F_(SD0_WP, IP10_15_12)
  140. #define GPSR3_12 F_(SD0_CD, IP10_11_8)
  141. #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
  142. #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
  143. #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
  144. #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
  145. #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
  146. #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
  147. #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
  148. #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
  149. #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
  150. #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
  151. #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
  152. #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
  153. /* GPSR4 */
  154. #define GPSR4_17 FM(SD3_DS)
  155. #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
  156. #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
  157. #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
  158. #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
  159. #define GPSR4_12 FM(SD3_DAT3)
  160. #define GPSR4_11 FM(SD3_DAT2)
  161. #define GPSR4_10 FM(SD3_DAT1)
  162. #define GPSR4_9 FM(SD3_DAT0)
  163. #define GPSR4_8 FM(SD3_CMD)
  164. #define GPSR4_7 FM(SD3_CLK)
  165. #define GPSR4_6 F_(SD2_DS, IP9_23_20)
  166. #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
  167. #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
  168. #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
  169. #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
  170. #define GPSR4_1 FM(SD2_CMD)
  171. #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
  172. /* GPSR5 */
  173. #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
  174. #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
  175. #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
  176. #define GPSR5_22 FM(MSIOF0_RXD)
  177. #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
  178. #define GPSR5_20 FM(MSIOF0_TXD)
  179. #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
  180. #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
  181. #define GPSR5_17 FM(MSIOF0_SCK)
  182. #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
  183. #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
  184. #define GPSR5_14 F_(HTX0, IP12_19_16)
  185. #define GPSR5_13 F_(HRX0, IP12_15_12)
  186. #define GPSR5_12 F_(HSCK0, IP12_11_8)
  187. #define GPSR5_11 F_(RX2_A, IP12_7_4)
  188. #define GPSR5_10 F_(TX2_A, IP12_3_0)
  189. #define GPSR5_9 F_(SCK2, IP11_31_28)
  190. #define GPSR5_8 F_(RTS1_N, IP11_27_24)
  191. #define GPSR5_7 F_(CTS1_N, IP11_23_20)
  192. #define GPSR5_6 F_(TX1_A, IP11_19_16)
  193. #define GPSR5_5 F_(RX1_A, IP11_15_12)
  194. #define GPSR5_4 F_(RTS0_N, IP11_11_8)
  195. #define GPSR5_3 F_(CTS0_N, IP11_7_4)
  196. #define GPSR5_2 F_(TX0, IP11_3_0)
  197. #define GPSR5_1 F_(RX0, IP10_31_28)
  198. #define GPSR5_0 F_(SCK0, IP10_27_24)
  199. /* GPSR6 */
  200. #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
  201. #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
  202. #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
  203. #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
  204. #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
  205. #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
  206. #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
  207. #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
  208. #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
  209. #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
  210. #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
  211. #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
  212. #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
  213. #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
  214. #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
  215. #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
  216. #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
  217. #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
  218. #define GPSR6_13 FM(SSI_SDATA5)
  219. #define GPSR6_12 FM(SSI_WS5)
  220. #define GPSR6_11 FM(SSI_SCK5)
  221. #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
  222. #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
  223. #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
  224. #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
  225. #define GPSR6_6 F_(SSI_WS349, IP14_15_12)
  226. #define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
  227. #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
  228. #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
  229. #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
  230. #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
  231. #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
  232. /* GPSR7 */
  233. #define GPSR7_3 FM(GP7_03)
  234. #define GPSR7_2 FM(GP7_02)
  235. #define GPSR7_1 FM(AVS2)
  236. #define GPSR7_0 FM(AVS1)
  237. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  238. #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  239. #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  240. #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  241. #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  242. #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  243. #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  244. #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  245. #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  246. #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  247. #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  248. #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  249. #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  250. #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  251. #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  252. #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  253. #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  254. #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  255. #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  256. #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  257. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  258. #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  259. #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  260. #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  261. #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  262. #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  263. #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  264. #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  265. #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  266. #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  267. #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  268. #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  269. #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  270. #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  271. #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  272. #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  273. #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  274. #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  275. #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  276. #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  277. #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  278. #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  279. #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  280. #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  281. #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  282. #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  283. #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  284. #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  285. #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  286. #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  287. #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  288. #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  289. #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  290. #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  291. #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  292. #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  293. #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  294. #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  295. #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  296. #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  297. #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  298. #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  299. #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  300. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  301. #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  302. #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  303. #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  304. #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  305. #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  306. #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  307. #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  308. #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  309. #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  310. #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  311. #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  312. #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  313. #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  314. #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  315. #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  316. #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  317. #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  318. #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  319. #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  320. #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  321. #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  322. #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  323. #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  324. #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  325. #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  326. #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  327. #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  328. #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  329. #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  330. #define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  331. #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  332. #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  333. #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  334. #define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  335. #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  336. #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  337. #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  338. #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  339. #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  340. #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  341. #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  342. #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  343. /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
  344. #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  345. #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  346. #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  347. #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  348. #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  349. #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  350. #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  351. #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  352. #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  353. #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  354. #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  355. #define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  356. #define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  357. #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  358. #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  359. #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  360. #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  361. #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  362. #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  363. #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  364. #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  365. #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  366. #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  367. #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  368. #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  369. #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  370. #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  371. #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  372. #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  373. #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  374. #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  375. #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  376. #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  377. #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  378. #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
  379. #define PINMUX_GPSR \
  380. \
  381. GPSR6_31 \
  382. GPSR6_30 \
  383. GPSR6_29 \
  384. GPSR6_28 \
  385. GPSR1_27 GPSR6_27 \
  386. GPSR1_26 GPSR6_26 \
  387. GPSR1_25 GPSR5_25 GPSR6_25 \
  388. GPSR1_24 GPSR5_24 GPSR6_24 \
  389. GPSR1_23 GPSR5_23 GPSR6_23 \
  390. GPSR1_22 GPSR5_22 GPSR6_22 \
  391. GPSR1_21 GPSR5_21 GPSR6_21 \
  392. GPSR1_20 GPSR5_20 GPSR6_20 \
  393. GPSR1_19 GPSR5_19 GPSR6_19 \
  394. GPSR1_18 GPSR5_18 GPSR6_18 \
  395. GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
  396. GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
  397. GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
  398. GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
  399. GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
  400. GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
  401. GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
  402. GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
  403. GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
  404. GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
  405. GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
  406. GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
  407. GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
  408. GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
  409. GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
  410. GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
  411. GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
  412. GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
  413. #define PINMUX_IPSR \
  414. \
  415. FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
  416. FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
  417. FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
  418. FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
  419. FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
  420. FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
  421. FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
  422. FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
  423. \
  424. FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
  425. FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
  426. FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
  427. FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
  428. FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
  429. FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
  430. FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
  431. FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
  432. \
  433. FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
  434. FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
  435. FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
  436. FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
  437. FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
  438. FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
  439. FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
  440. FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
  441. \
  442. FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
  443. FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
  444. FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
  445. FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
  446. FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
  447. FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
  448. FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
  449. FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
  450. \
  451. FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
  452. FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
  453. FM(IP16_11_8) IP16_11_8 \
  454. FM(IP16_15_12) IP16_15_12 \
  455. FM(IP16_19_16) IP16_19_16 \
  456. FM(IP16_23_20) IP16_23_20 \
  457. FM(IP16_27_24) IP16_27_24 \
  458. FM(IP16_31_28) IP16_31_28
  459. /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  460. #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
  461. #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
  462. #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
  463. #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
  464. #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
  465. #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
  466. #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
  467. #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
  468. #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
  469. #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
  470. #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
  471. #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
  472. #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
  473. #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
  474. #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
  475. #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
  476. #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
  477. #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
  478. #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
  479. #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
  480. #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
  481. /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
  482. #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
  483. #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  484. #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
  485. #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
  486. #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
  487. #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
  488. #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
  489. #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
  490. #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
  491. #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
  492. #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
  493. #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
  494. #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
  495. #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
  496. #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
  497. #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
  498. #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
  499. #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
  500. #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
  501. #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
  502. #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
  503. #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
  504. /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
  505. #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
  506. #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
  507. #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
  508. #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
  509. #define PINMUX_MOD_SELS\
  510. \
  511. MOD_SEL1_31_30 MOD_SEL2_31 \
  512. MOD_SEL0_30_29 MOD_SEL2_30 \
  513. MOD_SEL1_29_28_27 MOD_SEL2_29 \
  514. MOD_SEL0_28_27 \
  515. \
  516. MOD_SEL0_26_25_24 MOD_SEL1_26 \
  517. MOD_SEL1_25_24 \
  518. \
  519. MOD_SEL0_23 MOD_SEL1_23_22_21 \
  520. MOD_SEL0_22 \
  521. MOD_SEL0_21_20 \
  522. MOD_SEL1_20 \
  523. MOD_SEL0_19 MOD_SEL1_19 \
  524. MOD_SEL0_18 MOD_SEL1_18_17 \
  525. MOD_SEL0_17 \
  526. MOD_SEL0_16_15 MOD_SEL1_16 \
  527. MOD_SEL1_15_14 \
  528. MOD_SEL0_14 \
  529. MOD_SEL0_13 MOD_SEL1_13 \
  530. MOD_SEL0_12 MOD_SEL1_12 \
  531. MOD_SEL0_11 MOD_SEL1_11 \
  532. MOD_SEL0_10 MOD_SEL1_10 \
  533. MOD_SEL0_9 MOD_SEL1_9 \
  534. MOD_SEL0_8 \
  535. MOD_SEL0_7_6 \
  536. MOD_SEL1_6 \
  537. MOD_SEL0_5_4 MOD_SEL1_5 \
  538. MOD_SEL1_4 \
  539. MOD_SEL0_3 MOD_SEL1_3 \
  540. MOD_SEL0_2_1 MOD_SEL1_2 \
  541. MOD_SEL1_1 \
  542. MOD_SEL1_0 MOD_SEL2_0
  543. /*
  544. * These pins are not able to be muxed but have other properties
  545. * that can be set, such as drive-strength or pull-up/pull-down enable.
  546. */
  547. #define PINMUX_STATIC \
  548. FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
  549. FM(QSPI0_IO2) FM(QSPI0_IO3) \
  550. FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
  551. FM(QSPI1_IO2) FM(QSPI1_IO3) \
  552. FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
  553. FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
  554. FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
  555. FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
  556. FM(CLKOUT) FM(PRESETOUT) \
  557. FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
  558. FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
  559. #define PINMUX_PHYS \
  560. FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
  561. enum {
  562. PINMUX_RESERVED = 0,
  563. PINMUX_DATA_BEGIN,
  564. GP_ALL(DATA),
  565. PINMUX_DATA_END,
  566. #define F_(x, y)
  567. #define FM(x) FN_##x,
  568. PINMUX_FUNCTION_BEGIN,
  569. GP_ALL(FN),
  570. PINMUX_GPSR
  571. PINMUX_IPSR
  572. PINMUX_MOD_SELS
  573. PINMUX_FUNCTION_END,
  574. #undef F_
  575. #undef FM
  576. #define F_(x, y)
  577. #define FM(x) x##_MARK,
  578. PINMUX_MARK_BEGIN,
  579. PINMUX_GPSR
  580. PINMUX_IPSR
  581. PINMUX_MOD_SELS
  582. PINMUX_STATIC
  583. PINMUX_PHYS
  584. PINMUX_MARK_END,
  585. #undef F_
  586. #undef FM
  587. };
  588. static const u16 pinmux_data[] = {
  589. PINMUX_DATA_GP_ALL(),
  590. PINMUX_SINGLE(AVS1),
  591. PINMUX_SINGLE(AVS2),
  592. PINMUX_SINGLE(GP7_02),
  593. PINMUX_SINGLE(GP7_03),
  594. PINMUX_SINGLE(MSIOF0_RXD),
  595. PINMUX_SINGLE(MSIOF0_SCK),
  596. PINMUX_SINGLE(MSIOF0_TXD),
  597. PINMUX_SINGLE(SD2_CMD),
  598. PINMUX_SINGLE(SD3_CLK),
  599. PINMUX_SINGLE(SD3_CMD),
  600. PINMUX_SINGLE(SD3_DAT0),
  601. PINMUX_SINGLE(SD3_DAT1),
  602. PINMUX_SINGLE(SD3_DAT2),
  603. PINMUX_SINGLE(SD3_DAT3),
  604. PINMUX_SINGLE(SD3_DS),
  605. PINMUX_SINGLE(SSI_SCK5),
  606. PINMUX_SINGLE(SSI_SDATA5),
  607. PINMUX_SINGLE(SSI_WS5),
  608. /* IPSR0 */
  609. PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
  610. PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
  611. PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
  612. PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
  613. PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
  614. PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
  615. PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
  616. PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
  617. PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
  618. PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
  619. PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
  620. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  621. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  622. PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  623. PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
  624. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
  625. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
  626. PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
  627. PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
  628. PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
  629. PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
  630. PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
  631. PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
  632. PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
  633. PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
  634. PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
  635. PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
  636. PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
  637. PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
  638. PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
  639. PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
  640. /* IPSR1 */
  641. PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
  642. PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
  643. PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
  644. PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
  645. PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
  646. PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
  647. PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
  648. PINMUX_IPSR_GPSR(IP1_7_4, A25),
  649. PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
  650. PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
  651. PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
  652. PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
  653. PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
  654. PINMUX_IPSR_GPSR(IP1_11_8, A24),
  655. PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
  656. PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
  657. PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
  658. PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
  659. PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
  660. PINMUX_IPSR_GPSR(IP1_15_12, A23),
  661. PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
  662. PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
  663. PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
  664. PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
  665. PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
  666. PINMUX_IPSR_GPSR(IP1_19_16, A22),
  667. PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
  668. PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
  669. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
  670. PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
  671. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  672. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
  673. PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  674. PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
  675. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
  676. PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
  677. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
  678. PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
  679. PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
  680. PINMUX_IPSR_GPSR(IP1_31_28, A0),
  681. PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
  682. PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
  683. PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
  684. PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
  685. PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
  686. /* IPSR2 */
  687. PINMUX_IPSR_GPSR(IP2_3_0, A1),
  688. PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
  689. PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
  690. PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
  691. PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
  692. PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
  693. PINMUX_IPSR_GPSR(IP2_7_4, A2),
  694. PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
  695. PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
  696. PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
  697. PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
  698. PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
  699. PINMUX_IPSR_GPSR(IP2_11_8, A3),
  700. PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
  701. PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
  702. PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
  703. PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
  704. PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
  705. PINMUX_IPSR_GPSR(IP2_15_12, A4),
  706. PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
  707. PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
  708. PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
  709. PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
  710. PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
  711. PINMUX_IPSR_GPSR(IP2_19_16, A5),
  712. PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
  713. PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
  714. PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
  715. PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
  716. PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
  717. PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
  718. PINMUX_IPSR_GPSR(IP2_23_20, A6),
  719. PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
  720. PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
  721. PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
  722. PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
  723. PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
  724. PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
  725. PINMUX_IPSR_GPSR(IP2_27_24, A7),
  726. PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
  727. PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
  728. PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
  729. PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
  730. PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
  731. PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
  732. PINMUX_IPSR_GPSR(IP2_31_28, A8),
  733. PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
  734. PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
  735. PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
  736. PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
  737. PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
  738. PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
  739. /* IPSR3 */
  740. PINMUX_IPSR_GPSR(IP3_3_0, A9),
  741. PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
  742. PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
  743. PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
  744. PINMUX_IPSR_GPSR(IP3_7_4, A10),
  745. PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
  746. PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
  747. PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
  748. PINMUX_IPSR_GPSR(IP3_11_8, A11),
  749. PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
  750. PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
  751. PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
  752. PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
  753. PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
  754. PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
  755. PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
  756. PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
  757. PINMUX_IPSR_GPSR(IP3_15_12, A12),
  758. PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
  759. PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
  760. PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
  761. PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
  762. PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
  763. PINMUX_IPSR_GPSR(IP3_19_16, A13),
  764. PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
  765. PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
  766. PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
  767. PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
  768. PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
  769. PINMUX_IPSR_GPSR(IP3_23_20, A14),
  770. PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
  771. PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
  772. PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
  773. PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
  774. PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
  775. PINMUX_IPSR_GPSR(IP3_27_24, A15),
  776. PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
  777. PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
  778. PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
  779. PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
  780. PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
  781. PINMUX_IPSR_GPSR(IP3_31_28, A16),
  782. PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
  783. PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
  784. PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
  785. /* IPSR4 */
  786. PINMUX_IPSR_GPSR(IP4_3_0, A17),
  787. PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
  788. PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
  789. PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
  790. PINMUX_IPSR_GPSR(IP4_7_4, A18),
  791. PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
  792. PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
  793. PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
  794. PINMUX_IPSR_GPSR(IP4_11_8, A19),
  795. PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
  796. PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
  797. PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
  798. PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
  799. PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
  800. PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
  801. PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
  802. PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
  803. PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
  804. PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
  805. PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
  806. PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
  807. PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
  808. PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
  809. PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
  810. PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
  811. PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
  812. PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
  813. PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
  814. PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
  815. PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
  816. PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
  817. PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
  818. PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
  819. PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
  820. PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
  821. PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
  822. PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
  823. /* IPSR5 */
  824. PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
  825. PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
  826. PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
  827. PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
  828. PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
  829. PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
  830. PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
  831. PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
  832. PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
  833. PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
  834. PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
  835. PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
  836. PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
  837. PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
  838. PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
  839. PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
  840. PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
  841. PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
  842. PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
  843. PINMUX_IPSR_GPSR(IP5_15_12, D0),
  844. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
  845. PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
  846. PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
  847. PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
  848. PINMUX_IPSR_GPSR(IP5_19_16, D1),
  849. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
  850. PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
  851. PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
  852. PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
  853. PINMUX_IPSR_GPSR(IP5_23_20, D2),
  854. PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
  855. PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
  856. PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
  857. PINMUX_IPSR_GPSR(IP5_27_24, D3),
  858. PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
  859. PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
  860. PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
  861. PINMUX_IPSR_GPSR(IP5_31_28, D4),
  862. PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
  863. PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
  864. PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
  865. /* IPSR6 */
  866. PINMUX_IPSR_GPSR(IP6_3_0, D5),
  867. PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
  868. PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
  869. PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
  870. PINMUX_IPSR_GPSR(IP6_7_4, D6),
  871. PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
  872. PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
  873. PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
  874. PINMUX_IPSR_GPSR(IP6_11_8, D7),
  875. PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
  876. PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
  877. PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
  878. PINMUX_IPSR_GPSR(IP6_15_12, D8),
  879. PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
  880. PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
  881. PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
  882. PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
  883. PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
  884. PINMUX_IPSR_GPSR(IP6_19_16, D9),
  885. PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
  886. PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
  887. PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
  888. PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
  889. PINMUX_IPSR_GPSR(IP6_23_20, D10),
  890. PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
  891. PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
  892. PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
  893. PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
  894. PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
  895. PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
  896. PINMUX_IPSR_GPSR(IP6_27_24, D11),
  897. PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
  898. PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
  899. PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
  900. PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
  901. PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
  902. PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
  903. PINMUX_IPSR_GPSR(IP6_31_28, D12),
  904. PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
  905. PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
  906. PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
  907. PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
  908. PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
  909. /* IPSR7 */
  910. PINMUX_IPSR_GPSR(IP7_3_0, D13),
  911. PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
  912. PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
  913. PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
  914. PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
  915. PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
  916. PINMUX_IPSR_GPSR(IP7_7_4, D14),
  917. PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
  918. PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
  919. PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
  920. PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
  921. PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
  922. PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
  923. PINMUX_IPSR_GPSR(IP7_11_8, D15),
  924. PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
  925. PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
  926. PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
  927. PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
  928. PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
  929. PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
  930. PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
  931. PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
  932. PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
  933. PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
  934. PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
  935. PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
  936. PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
  937. PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
  938. PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
  939. PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
  940. PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
  941. PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
  942. PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
  943. PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
  944. PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
  945. /* IPSR8 */
  946. PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
  947. PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
  948. PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
  949. PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
  950. PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
  951. PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
  952. PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
  953. PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
  954. PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
  955. PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
  956. PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
  957. PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
  958. PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
  959. PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
  960. PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
  961. PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
  962. PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
  963. PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
  964. PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
  965. PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
  966. PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
  967. PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
  968. PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
  969. PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
  970. PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
  971. PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
  972. PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
  973. PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
  974. PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
  975. PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
  976. PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
  977. PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
  978. PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
  979. PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
  980. PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
  981. /* IPSR9 */
  982. PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
  983. PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
  984. PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
  985. PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
  986. PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
  987. PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
  988. PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
  989. PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
  990. PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
  991. PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
  992. PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
  993. /* IPSR10 */
  994. PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
  995. PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
  996. PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
  997. PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
  998. PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
  999. PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
  1000. PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
  1001. PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
  1002. PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
  1003. PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
  1004. PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1005. PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
  1006. PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
  1007. PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
  1008. PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
  1009. PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
  1010. PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
  1011. PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
  1012. PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
  1013. PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
  1014. PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
  1015. PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
  1016. PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
  1017. PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
  1018. PINMUX_IPSR_GPSR(IP10_31_28, RX0),
  1019. PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
  1020. PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
  1021. PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
  1022. PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
  1023. /* IPSR11 */
  1024. PINMUX_IPSR_GPSR(IP11_3_0, TX0),
  1025. PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
  1026. PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
  1027. PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
  1028. PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
  1029. PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
  1030. PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
  1031. PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
  1032. PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
  1033. PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
  1034. PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
  1035. PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
  1036. PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
  1037. PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
  1038. PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
  1039. PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
  1040. PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
  1041. PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
  1042. PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
  1043. PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
  1044. PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
  1045. PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
  1046. PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
  1047. PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
  1048. PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
  1049. PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
  1050. PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
  1051. PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
  1052. PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
  1053. PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
  1054. PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
  1055. PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
  1056. PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
  1057. PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
  1058. PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
  1059. PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
  1060. PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
  1061. PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
  1062. PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
  1063. PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
  1064. PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
  1065. PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
  1066. PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
  1067. PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
  1068. PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
  1069. PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
  1070. PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
  1071. PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
  1072. PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
  1073. PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
  1074. PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
  1075. PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
  1076. /* IPSR12 */
  1077. PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
  1078. PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
  1079. PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
  1080. PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
  1081. PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
  1082. PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
  1083. PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
  1084. PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
  1085. PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
  1086. PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
  1087. PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
  1088. PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
  1089. PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
  1090. PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
  1091. PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
  1092. PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
  1093. PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
  1094. PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
  1095. PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
  1096. PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
  1097. PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
  1098. PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
  1099. PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
  1100. PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
  1101. PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
  1102. PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
  1103. PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
  1104. PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
  1105. PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
  1106. PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
  1107. PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
  1108. PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
  1109. PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
  1110. PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
  1111. PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
  1112. PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
  1113. PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
  1114. PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
  1115. PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
  1116. PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
  1117. PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
  1118. PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
  1119. PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
  1120. PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
  1121. PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
  1122. PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
  1123. PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
  1124. PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
  1125. /* IPSR13 */
  1126. PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
  1127. PINMUX_IPSR_GPSR(IP13_3_0, RX5),
  1128. PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
  1129. PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
  1130. PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
  1131. PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
  1132. PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
  1133. PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
  1134. PINMUX_IPSR_GPSR(IP13_7_4, TX5),
  1135. PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
  1136. PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
  1137. PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
  1138. PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
  1139. PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
  1140. PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
  1141. PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
  1142. PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
  1143. PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
  1144. PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
  1145. PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
  1146. PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
  1147. PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
  1148. PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
  1149. PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
  1150. PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
  1151. PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
  1152. PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
  1153. PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
  1154. PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
  1155. PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
  1156. PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
  1157. /* IPSR14 */
  1158. PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
  1159. PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
  1160. PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
  1161. PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
  1162. PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
  1163. PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
  1164. PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
  1165. PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
  1166. PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
  1167. PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
  1168. PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
  1169. PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
  1170. PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
  1171. PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
  1172. PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
  1173. PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
  1174. PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
  1175. PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
  1176. PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
  1177. PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
  1178. PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
  1179. PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
  1180. PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
  1181. PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
  1182. PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
  1183. PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
  1184. PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
  1185. PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
  1186. PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
  1187. PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
  1188. PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
  1189. PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
  1190. PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
  1191. PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
  1192. PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
  1193. PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
  1194. PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
  1195. PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
  1196. /* IPSR15 */
  1197. PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
  1198. PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
  1199. PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
  1200. PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
  1201. PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
  1202. PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
  1203. PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
  1204. PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
  1205. PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
  1206. PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
  1207. PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
  1208. PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
  1209. PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
  1210. PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
  1211. PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
  1212. PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
  1213. PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
  1214. PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
  1215. PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
  1216. PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
  1217. PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
  1218. PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
  1219. PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
  1220. PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
  1221. PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
  1222. PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
  1223. PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
  1224. PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
  1225. PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
  1226. PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
  1227. PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
  1228. PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
  1229. PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
  1230. PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
  1231. PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
  1232. PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
  1233. PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
  1234. PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
  1235. PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
  1236. PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
  1237. PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
  1238. PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
  1239. PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
  1240. PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
  1241. PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
  1242. PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
  1243. /* IPSR16 */
  1244. PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
  1245. PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
  1246. PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
  1247. PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
  1248. PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
  1249. PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
  1250. PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
  1251. PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
  1252. PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
  1253. PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
  1254. PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
  1255. PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
  1256. PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
  1257. PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
  1258. PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
  1259. PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
  1260. PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
  1261. PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
  1262. PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
  1263. PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
  1264. PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
  1265. PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
  1266. PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
  1267. PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
  1268. PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
  1269. PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
  1270. PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
  1271. PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
  1272. PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
  1273. PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
  1274. PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
  1275. PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
  1276. PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
  1277. PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
  1278. PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
  1279. PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
  1280. PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
  1281. PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
  1282. PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
  1283. PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
  1284. PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
  1285. PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
  1286. PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
  1287. PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
  1288. PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
  1289. PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
  1290. PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
  1291. PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
  1292. PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
  1293. PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
  1294. PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
  1295. /* IPSR17 */
  1296. PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
  1297. PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
  1298. PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
  1299. PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
  1300. PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
  1301. PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
  1302. PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
  1303. PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
  1304. PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
  1305. PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
  1306. PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
  1307. PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
  1308. PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
  1309. PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
  1310. /*
  1311. * Static pins can not be muxed between different functions but
  1312. * still need mark entries in the pinmux list. Add each static
  1313. * pin to the list without an associated function. The sh-pfc
  1314. * core will do the right thing and skip trying to mux the pin
  1315. * while still applying configuration to it.
  1316. */
  1317. #define FM(x) PINMUX_DATA(x##_MARK, 0),
  1318. PINMUX_STATIC
  1319. #undef FM
  1320. };
  1321. /*
  1322. * Pins not associated with a GPIO port.
  1323. */
  1324. enum {
  1325. GP_ASSIGN_LAST(),
  1326. NOGP_ALL(),
  1327. };
  1328. static const struct sh_pfc_pin pinmux_pins[] = {
  1329. PINMUX_GPIO_GP_ALL(),
  1330. PINMUX_NOGP_ALL(),
  1331. };
  1332. /* - AUDIO CLOCK ------------------------------------------------------------ */
  1333. static const unsigned int audio_clk_a_a_pins[] = {
  1334. /* CLK A */
  1335. RCAR_GP_PIN(6, 22),
  1336. };
  1337. static const unsigned int audio_clk_a_a_mux[] = {
  1338. AUDIO_CLKA_A_MARK,
  1339. };
  1340. static const unsigned int audio_clk_a_b_pins[] = {
  1341. /* CLK A */
  1342. RCAR_GP_PIN(5, 4),
  1343. };
  1344. static const unsigned int audio_clk_a_b_mux[] = {
  1345. AUDIO_CLKA_B_MARK,
  1346. };
  1347. static const unsigned int audio_clk_a_c_pins[] = {
  1348. /* CLK A */
  1349. RCAR_GP_PIN(5, 19),
  1350. };
  1351. static const unsigned int audio_clk_a_c_mux[] = {
  1352. AUDIO_CLKA_C_MARK,
  1353. };
  1354. static const unsigned int audio_clk_b_a_pins[] = {
  1355. /* CLK B */
  1356. RCAR_GP_PIN(5, 12),
  1357. };
  1358. static const unsigned int audio_clk_b_a_mux[] = {
  1359. AUDIO_CLKB_A_MARK,
  1360. };
  1361. static const unsigned int audio_clk_b_b_pins[] = {
  1362. /* CLK B */
  1363. RCAR_GP_PIN(6, 23),
  1364. };
  1365. static const unsigned int audio_clk_b_b_mux[] = {
  1366. AUDIO_CLKB_B_MARK,
  1367. };
  1368. static const unsigned int audio_clk_c_a_pins[] = {
  1369. /* CLK C */
  1370. RCAR_GP_PIN(5, 21),
  1371. };
  1372. static const unsigned int audio_clk_c_a_mux[] = {
  1373. AUDIO_CLKC_A_MARK,
  1374. };
  1375. static const unsigned int audio_clk_c_b_pins[] = {
  1376. /* CLK C */
  1377. RCAR_GP_PIN(5, 0),
  1378. };
  1379. static const unsigned int audio_clk_c_b_mux[] = {
  1380. AUDIO_CLKC_B_MARK,
  1381. };
  1382. static const unsigned int audio_clkout_a_pins[] = {
  1383. /* CLKOUT */
  1384. RCAR_GP_PIN(5, 18),
  1385. };
  1386. static const unsigned int audio_clkout_a_mux[] = {
  1387. AUDIO_CLKOUT_A_MARK,
  1388. };
  1389. static const unsigned int audio_clkout_b_pins[] = {
  1390. /* CLKOUT */
  1391. RCAR_GP_PIN(6, 28),
  1392. };
  1393. static const unsigned int audio_clkout_b_mux[] = {
  1394. AUDIO_CLKOUT_B_MARK,
  1395. };
  1396. static const unsigned int audio_clkout_c_pins[] = {
  1397. /* CLKOUT */
  1398. RCAR_GP_PIN(5, 3),
  1399. };
  1400. static const unsigned int audio_clkout_c_mux[] = {
  1401. AUDIO_CLKOUT_C_MARK,
  1402. };
  1403. static const unsigned int audio_clkout_d_pins[] = {
  1404. /* CLKOUT */
  1405. RCAR_GP_PIN(5, 21),
  1406. };
  1407. static const unsigned int audio_clkout_d_mux[] = {
  1408. AUDIO_CLKOUT_D_MARK,
  1409. };
  1410. static const unsigned int audio_clkout1_a_pins[] = {
  1411. /* CLKOUT1 */
  1412. RCAR_GP_PIN(5, 15),
  1413. };
  1414. static const unsigned int audio_clkout1_a_mux[] = {
  1415. AUDIO_CLKOUT1_A_MARK,
  1416. };
  1417. static const unsigned int audio_clkout1_b_pins[] = {
  1418. /* CLKOUT1 */
  1419. RCAR_GP_PIN(6, 29),
  1420. };
  1421. static const unsigned int audio_clkout1_b_mux[] = {
  1422. AUDIO_CLKOUT1_B_MARK,
  1423. };
  1424. static const unsigned int audio_clkout2_a_pins[] = {
  1425. /* CLKOUT2 */
  1426. RCAR_GP_PIN(5, 16),
  1427. };
  1428. static const unsigned int audio_clkout2_a_mux[] = {
  1429. AUDIO_CLKOUT2_A_MARK,
  1430. };
  1431. static const unsigned int audio_clkout2_b_pins[] = {
  1432. /* CLKOUT2 */
  1433. RCAR_GP_PIN(6, 30),
  1434. };
  1435. static const unsigned int audio_clkout2_b_mux[] = {
  1436. AUDIO_CLKOUT2_B_MARK,
  1437. };
  1438. static const unsigned int audio_clkout3_a_pins[] = {
  1439. /* CLKOUT3 */
  1440. RCAR_GP_PIN(5, 19),
  1441. };
  1442. static const unsigned int audio_clkout3_a_mux[] = {
  1443. AUDIO_CLKOUT3_A_MARK,
  1444. };
  1445. static const unsigned int audio_clkout3_b_pins[] = {
  1446. /* CLKOUT3 */
  1447. RCAR_GP_PIN(6, 31),
  1448. };
  1449. static const unsigned int audio_clkout3_b_mux[] = {
  1450. AUDIO_CLKOUT3_B_MARK,
  1451. };
  1452. /* - EtherAVB --------------------------------------------------------------- */
  1453. static const unsigned int avb_link_pins[] = {
  1454. /* AVB_LINK */
  1455. RCAR_GP_PIN(2, 12),
  1456. };
  1457. static const unsigned int avb_link_mux[] = {
  1458. AVB_LINK_MARK,
  1459. };
  1460. static const unsigned int avb_magic_pins[] = {
  1461. /* AVB_MAGIC_ */
  1462. RCAR_GP_PIN(2, 10),
  1463. };
  1464. static const unsigned int avb_magic_mux[] = {
  1465. AVB_MAGIC_MARK,
  1466. };
  1467. static const unsigned int avb_phy_int_pins[] = {
  1468. /* AVB_PHY_INT */
  1469. RCAR_GP_PIN(2, 11),
  1470. };
  1471. static const unsigned int avb_phy_int_mux[] = {
  1472. AVB_PHY_INT_MARK,
  1473. };
  1474. static const unsigned int avb_mdio_pins[] = {
  1475. /* AVB_MDC, AVB_MDIO */
  1476. RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
  1477. };
  1478. static const unsigned int avb_mdio_mux[] = {
  1479. AVB_MDC_MARK, AVB_MDIO_MARK,
  1480. };
  1481. static const unsigned int avb_mii_pins[] = {
  1482. /*
  1483. * AVB_TX_CTL, AVB_TXC, AVB_TD0,
  1484. * AVB_TD1, AVB_TD2, AVB_TD3,
  1485. * AVB_RX_CTL, AVB_RXC, AVB_RD0,
  1486. * AVB_RD1, AVB_RD2, AVB_RD3,
  1487. * AVB_TXCREFCLK
  1488. */
  1489. PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
  1490. PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
  1491. PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
  1492. PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
  1493. PIN_AVB_TXCREFCLK,
  1494. };
  1495. static const unsigned int avb_mii_mux[] = {
  1496. AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
  1497. AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
  1498. AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
  1499. AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
  1500. AVB_TXCREFCLK_MARK,
  1501. };
  1502. static const unsigned int avb_avtp_pps_pins[] = {
  1503. /* AVB_AVTP_PPS */
  1504. RCAR_GP_PIN(2, 6),
  1505. };
  1506. static const unsigned int avb_avtp_pps_mux[] = {
  1507. AVB_AVTP_PPS_MARK,
  1508. };
  1509. static const unsigned int avb_avtp_match_a_pins[] = {
  1510. /* AVB_AVTP_MATCH_A */
  1511. RCAR_GP_PIN(2, 13),
  1512. };
  1513. static const unsigned int avb_avtp_match_a_mux[] = {
  1514. AVB_AVTP_MATCH_A_MARK,
  1515. };
  1516. static const unsigned int avb_avtp_capture_a_pins[] = {
  1517. /* AVB_AVTP_CAPTURE_A */
  1518. RCAR_GP_PIN(2, 14),
  1519. };
  1520. static const unsigned int avb_avtp_capture_a_mux[] = {
  1521. AVB_AVTP_CAPTURE_A_MARK,
  1522. };
  1523. static const unsigned int avb_avtp_match_b_pins[] = {
  1524. /* AVB_AVTP_MATCH_B */
  1525. RCAR_GP_PIN(1, 8),
  1526. };
  1527. static const unsigned int avb_avtp_match_b_mux[] = {
  1528. AVB_AVTP_MATCH_B_MARK,
  1529. };
  1530. static const unsigned int avb_avtp_capture_b_pins[] = {
  1531. /* AVB_AVTP_CAPTURE_B */
  1532. RCAR_GP_PIN(1, 11),
  1533. };
  1534. static const unsigned int avb_avtp_capture_b_mux[] = {
  1535. AVB_AVTP_CAPTURE_B_MARK,
  1536. };
  1537. /* - CAN ------------------------------------------------------------------ */
  1538. static const unsigned int can0_data_a_pins[] = {
  1539. /* TX, RX */
  1540. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1541. };
  1542. static const unsigned int can0_data_a_mux[] = {
  1543. CAN0_TX_A_MARK, CAN0_RX_A_MARK,
  1544. };
  1545. static const unsigned int can0_data_b_pins[] = {
  1546. /* TX, RX */
  1547. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1548. };
  1549. static const unsigned int can0_data_b_mux[] = {
  1550. CAN0_TX_B_MARK, CAN0_RX_B_MARK,
  1551. };
  1552. static const unsigned int can1_data_pins[] = {
  1553. /* TX, RX */
  1554. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1555. };
  1556. static const unsigned int can1_data_mux[] = {
  1557. CAN1_TX_MARK, CAN1_RX_MARK,
  1558. };
  1559. /* - CAN Clock -------------------------------------------------------------- */
  1560. static const unsigned int can_clk_pins[] = {
  1561. /* CLK */
  1562. RCAR_GP_PIN(1, 25),
  1563. };
  1564. static const unsigned int can_clk_mux[] = {
  1565. CAN_CLK_MARK,
  1566. };
  1567. /* - CAN FD --------------------------------------------------------------- */
  1568. static const unsigned int canfd0_data_a_pins[] = {
  1569. /* TX, RX */
  1570. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1571. };
  1572. static const unsigned int canfd0_data_a_mux[] = {
  1573. CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
  1574. };
  1575. static const unsigned int canfd0_data_b_pins[] = {
  1576. /* TX, RX */
  1577. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1578. };
  1579. static const unsigned int canfd0_data_b_mux[] = {
  1580. CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
  1581. };
  1582. static const unsigned int canfd1_data_pins[] = {
  1583. /* TX, RX */
  1584. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
  1585. };
  1586. static const unsigned int canfd1_data_mux[] = {
  1587. CANFD1_TX_MARK, CANFD1_RX_MARK,
  1588. };
  1589. /* - DRIF0 --------------------------------------------------------------- */
  1590. static const unsigned int drif0_ctrl_a_pins[] = {
  1591. /* CLK, SYNC */
  1592. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1593. };
  1594. static const unsigned int drif0_ctrl_a_mux[] = {
  1595. RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
  1596. };
  1597. static const unsigned int drif0_data0_a_pins[] = {
  1598. /* D0 */
  1599. RCAR_GP_PIN(6, 10),
  1600. };
  1601. static const unsigned int drif0_data0_a_mux[] = {
  1602. RIF0_D0_A_MARK,
  1603. };
  1604. static const unsigned int drif0_data1_a_pins[] = {
  1605. /* D1 */
  1606. RCAR_GP_PIN(6, 7),
  1607. };
  1608. static const unsigned int drif0_data1_a_mux[] = {
  1609. RIF0_D1_A_MARK,
  1610. };
  1611. static const unsigned int drif0_ctrl_b_pins[] = {
  1612. /* CLK, SYNC */
  1613. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  1614. };
  1615. static const unsigned int drif0_ctrl_b_mux[] = {
  1616. RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
  1617. };
  1618. static const unsigned int drif0_data0_b_pins[] = {
  1619. /* D0 */
  1620. RCAR_GP_PIN(5, 1),
  1621. };
  1622. static const unsigned int drif0_data0_b_mux[] = {
  1623. RIF0_D0_B_MARK,
  1624. };
  1625. static const unsigned int drif0_data1_b_pins[] = {
  1626. /* D1 */
  1627. RCAR_GP_PIN(5, 2),
  1628. };
  1629. static const unsigned int drif0_data1_b_mux[] = {
  1630. RIF0_D1_B_MARK,
  1631. };
  1632. static const unsigned int drif0_ctrl_c_pins[] = {
  1633. /* CLK, SYNC */
  1634. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
  1635. };
  1636. static const unsigned int drif0_ctrl_c_mux[] = {
  1637. RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
  1638. };
  1639. static const unsigned int drif0_data0_c_pins[] = {
  1640. /* D0 */
  1641. RCAR_GP_PIN(5, 13),
  1642. };
  1643. static const unsigned int drif0_data0_c_mux[] = {
  1644. RIF0_D0_C_MARK,
  1645. };
  1646. static const unsigned int drif0_data1_c_pins[] = {
  1647. /* D1 */
  1648. RCAR_GP_PIN(5, 14),
  1649. };
  1650. static const unsigned int drif0_data1_c_mux[] = {
  1651. RIF0_D1_C_MARK,
  1652. };
  1653. /* - DRIF1 --------------------------------------------------------------- */
  1654. static const unsigned int drif1_ctrl_a_pins[] = {
  1655. /* CLK, SYNC */
  1656. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1657. };
  1658. static const unsigned int drif1_ctrl_a_mux[] = {
  1659. RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
  1660. };
  1661. static const unsigned int drif1_data0_a_pins[] = {
  1662. /* D0 */
  1663. RCAR_GP_PIN(6, 19),
  1664. };
  1665. static const unsigned int drif1_data0_a_mux[] = {
  1666. RIF1_D0_A_MARK,
  1667. };
  1668. static const unsigned int drif1_data1_a_pins[] = {
  1669. /* D1 */
  1670. RCAR_GP_PIN(6, 20),
  1671. };
  1672. static const unsigned int drif1_data1_a_mux[] = {
  1673. RIF1_D1_A_MARK,
  1674. };
  1675. static const unsigned int drif1_ctrl_b_pins[] = {
  1676. /* CLK, SYNC */
  1677. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
  1678. };
  1679. static const unsigned int drif1_ctrl_b_mux[] = {
  1680. RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
  1681. };
  1682. static const unsigned int drif1_data0_b_pins[] = {
  1683. /* D0 */
  1684. RCAR_GP_PIN(5, 7),
  1685. };
  1686. static const unsigned int drif1_data0_b_mux[] = {
  1687. RIF1_D0_B_MARK,
  1688. };
  1689. static const unsigned int drif1_data1_b_pins[] = {
  1690. /* D1 */
  1691. RCAR_GP_PIN(5, 8),
  1692. };
  1693. static const unsigned int drif1_data1_b_mux[] = {
  1694. RIF1_D1_B_MARK,
  1695. };
  1696. static const unsigned int drif1_ctrl_c_pins[] = {
  1697. /* CLK, SYNC */
  1698. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
  1699. };
  1700. static const unsigned int drif1_ctrl_c_mux[] = {
  1701. RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
  1702. };
  1703. static const unsigned int drif1_data0_c_pins[] = {
  1704. /* D0 */
  1705. RCAR_GP_PIN(5, 6),
  1706. };
  1707. static const unsigned int drif1_data0_c_mux[] = {
  1708. RIF1_D0_C_MARK,
  1709. };
  1710. static const unsigned int drif1_data1_c_pins[] = {
  1711. /* D1 */
  1712. RCAR_GP_PIN(5, 10),
  1713. };
  1714. static const unsigned int drif1_data1_c_mux[] = {
  1715. RIF1_D1_C_MARK,
  1716. };
  1717. /* - DRIF2 --------------------------------------------------------------- */
  1718. static const unsigned int drif2_ctrl_a_pins[] = {
  1719. /* CLK, SYNC */
  1720. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1721. };
  1722. static const unsigned int drif2_ctrl_a_mux[] = {
  1723. RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
  1724. };
  1725. static const unsigned int drif2_data0_a_pins[] = {
  1726. /* D0 */
  1727. RCAR_GP_PIN(6, 7),
  1728. };
  1729. static const unsigned int drif2_data0_a_mux[] = {
  1730. RIF2_D0_A_MARK,
  1731. };
  1732. static const unsigned int drif2_data1_a_pins[] = {
  1733. /* D1 */
  1734. RCAR_GP_PIN(6, 10),
  1735. };
  1736. static const unsigned int drif2_data1_a_mux[] = {
  1737. RIF2_D1_A_MARK,
  1738. };
  1739. static const unsigned int drif2_ctrl_b_pins[] = {
  1740. /* CLK, SYNC */
  1741. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  1742. };
  1743. static const unsigned int drif2_ctrl_b_mux[] = {
  1744. RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
  1745. };
  1746. static const unsigned int drif2_data0_b_pins[] = {
  1747. /* D0 */
  1748. RCAR_GP_PIN(6, 30),
  1749. };
  1750. static const unsigned int drif2_data0_b_mux[] = {
  1751. RIF2_D0_B_MARK,
  1752. };
  1753. static const unsigned int drif2_data1_b_pins[] = {
  1754. /* D1 */
  1755. RCAR_GP_PIN(6, 31),
  1756. };
  1757. static const unsigned int drif2_data1_b_mux[] = {
  1758. RIF2_D1_B_MARK,
  1759. };
  1760. /* - DRIF3 --------------------------------------------------------------- */
  1761. static const unsigned int drif3_ctrl_a_pins[] = {
  1762. /* CLK, SYNC */
  1763. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1764. };
  1765. static const unsigned int drif3_ctrl_a_mux[] = {
  1766. RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
  1767. };
  1768. static const unsigned int drif3_data0_a_pins[] = {
  1769. /* D0 */
  1770. RCAR_GP_PIN(6, 19),
  1771. };
  1772. static const unsigned int drif3_data0_a_mux[] = {
  1773. RIF3_D0_A_MARK,
  1774. };
  1775. static const unsigned int drif3_data1_a_pins[] = {
  1776. /* D1 */
  1777. RCAR_GP_PIN(6, 20),
  1778. };
  1779. static const unsigned int drif3_data1_a_mux[] = {
  1780. RIF3_D1_A_MARK,
  1781. };
  1782. static const unsigned int drif3_ctrl_b_pins[] = {
  1783. /* CLK, SYNC */
  1784. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  1785. };
  1786. static const unsigned int drif3_ctrl_b_mux[] = {
  1787. RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
  1788. };
  1789. static const unsigned int drif3_data0_b_pins[] = {
  1790. /* D0 */
  1791. RCAR_GP_PIN(6, 28),
  1792. };
  1793. static const unsigned int drif3_data0_b_mux[] = {
  1794. RIF3_D0_B_MARK,
  1795. };
  1796. static const unsigned int drif3_data1_b_pins[] = {
  1797. /* D1 */
  1798. RCAR_GP_PIN(6, 29),
  1799. };
  1800. static const unsigned int drif3_data1_b_mux[] = {
  1801. RIF3_D1_B_MARK,
  1802. };
  1803. /* - DU --------------------------------------------------------------------- */
  1804. static const unsigned int du_rgb666_pins[] = {
  1805. /* R[7:2], G[7:2], B[7:2] */
  1806. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1807. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1808. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1809. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1810. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1811. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1812. };
  1813. static const unsigned int du_rgb666_mux[] = {
  1814. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1815. DU_DR3_MARK, DU_DR2_MARK,
  1816. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1817. DU_DG3_MARK, DU_DG2_MARK,
  1818. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1819. DU_DB3_MARK, DU_DB2_MARK,
  1820. };
  1821. static const unsigned int du_rgb888_pins[] = {
  1822. /* R[7:0], G[7:0], B[7:0] */
  1823. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
  1824. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  1825. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
  1826. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  1827. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
  1828. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  1829. RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
  1830. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
  1831. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
  1832. };
  1833. static const unsigned int du_rgb888_mux[] = {
  1834. DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
  1835. DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
  1836. DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
  1837. DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
  1838. DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
  1839. DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
  1840. };
  1841. static const unsigned int du_clk_out_0_pins[] = {
  1842. /* CLKOUT */
  1843. RCAR_GP_PIN(1, 27),
  1844. };
  1845. static const unsigned int du_clk_out_0_mux[] = {
  1846. DU_DOTCLKOUT0_MARK
  1847. };
  1848. static const unsigned int du_clk_out_1_pins[] = {
  1849. /* CLKOUT */
  1850. RCAR_GP_PIN(2, 3),
  1851. };
  1852. static const unsigned int du_clk_out_1_mux[] = {
  1853. DU_DOTCLKOUT1_MARK
  1854. };
  1855. static const unsigned int du_sync_pins[] = {
  1856. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1857. RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
  1858. };
  1859. static const unsigned int du_sync_mux[] = {
  1860. DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
  1861. };
  1862. static const unsigned int du_oddf_pins[] = {
  1863. /* EXDISP/EXODDF/EXCDE */
  1864. RCAR_GP_PIN(2, 2),
  1865. };
  1866. static const unsigned int du_oddf_mux[] = {
  1867. DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
  1868. };
  1869. static const unsigned int du_cde_pins[] = {
  1870. /* CDE */
  1871. RCAR_GP_PIN(2, 0),
  1872. };
  1873. static const unsigned int du_cde_mux[] = {
  1874. DU_CDE_MARK,
  1875. };
  1876. static const unsigned int du_disp_pins[] = {
  1877. /* DISP */
  1878. RCAR_GP_PIN(2, 1),
  1879. };
  1880. static const unsigned int du_disp_mux[] = {
  1881. DU_DISP_MARK,
  1882. };
  1883. /* - HSCIF0 ----------------------------------------------------------------- */
  1884. static const unsigned int hscif0_data_pins[] = {
  1885. /* RX, TX */
  1886. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  1887. };
  1888. static const unsigned int hscif0_data_mux[] = {
  1889. HRX0_MARK, HTX0_MARK,
  1890. };
  1891. static const unsigned int hscif0_clk_pins[] = {
  1892. /* SCK */
  1893. RCAR_GP_PIN(5, 12),
  1894. };
  1895. static const unsigned int hscif0_clk_mux[] = {
  1896. HSCK0_MARK,
  1897. };
  1898. static const unsigned int hscif0_ctrl_pins[] = {
  1899. /* RTS, CTS */
  1900. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
  1901. };
  1902. static const unsigned int hscif0_ctrl_mux[] = {
  1903. HRTS0_N_MARK, HCTS0_N_MARK,
  1904. };
  1905. /* - HSCIF1 ----------------------------------------------------------------- */
  1906. static const unsigned int hscif1_data_a_pins[] = {
  1907. /* RX, TX */
  1908. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  1909. };
  1910. static const unsigned int hscif1_data_a_mux[] = {
  1911. HRX1_A_MARK, HTX1_A_MARK,
  1912. };
  1913. static const unsigned int hscif1_clk_a_pins[] = {
  1914. /* SCK */
  1915. RCAR_GP_PIN(6, 21),
  1916. };
  1917. static const unsigned int hscif1_clk_a_mux[] = {
  1918. HSCK1_A_MARK,
  1919. };
  1920. static const unsigned int hscif1_ctrl_a_pins[] = {
  1921. /* RTS, CTS */
  1922. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  1923. };
  1924. static const unsigned int hscif1_ctrl_a_mux[] = {
  1925. HRTS1_N_A_MARK, HCTS1_N_A_MARK,
  1926. };
  1927. static const unsigned int hscif1_data_b_pins[] = {
  1928. /* RX, TX */
  1929. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1930. };
  1931. static const unsigned int hscif1_data_b_mux[] = {
  1932. HRX1_B_MARK, HTX1_B_MARK,
  1933. };
  1934. static const unsigned int hscif1_clk_b_pins[] = {
  1935. /* SCK */
  1936. RCAR_GP_PIN(5, 0),
  1937. };
  1938. static const unsigned int hscif1_clk_b_mux[] = {
  1939. HSCK1_B_MARK,
  1940. };
  1941. static const unsigned int hscif1_ctrl_b_pins[] = {
  1942. /* RTS, CTS */
  1943. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  1944. };
  1945. static const unsigned int hscif1_ctrl_b_mux[] = {
  1946. HRTS1_N_B_MARK, HCTS1_N_B_MARK,
  1947. };
  1948. /* - HSCIF2 ----------------------------------------------------------------- */
  1949. static const unsigned int hscif2_data_a_pins[] = {
  1950. /* RX, TX */
  1951. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  1952. };
  1953. static const unsigned int hscif2_data_a_mux[] = {
  1954. HRX2_A_MARK, HTX2_A_MARK,
  1955. };
  1956. static const unsigned int hscif2_clk_a_pins[] = {
  1957. /* SCK */
  1958. RCAR_GP_PIN(6, 10),
  1959. };
  1960. static const unsigned int hscif2_clk_a_mux[] = {
  1961. HSCK2_A_MARK,
  1962. };
  1963. static const unsigned int hscif2_ctrl_a_pins[] = {
  1964. /* RTS, CTS */
  1965. RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
  1966. };
  1967. static const unsigned int hscif2_ctrl_a_mux[] = {
  1968. HRTS2_N_A_MARK, HCTS2_N_A_MARK,
  1969. };
  1970. static const unsigned int hscif2_data_b_pins[] = {
  1971. /* RX, TX */
  1972. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  1973. };
  1974. static const unsigned int hscif2_data_b_mux[] = {
  1975. HRX2_B_MARK, HTX2_B_MARK,
  1976. };
  1977. static const unsigned int hscif2_clk_b_pins[] = {
  1978. /* SCK */
  1979. RCAR_GP_PIN(6, 21),
  1980. };
  1981. static const unsigned int hscif2_clk_b_mux[] = {
  1982. HSCK2_B_MARK,
  1983. };
  1984. static const unsigned int hscif2_ctrl_b_pins[] = {
  1985. /* RTS, CTS */
  1986. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
  1987. };
  1988. static const unsigned int hscif2_ctrl_b_mux[] = {
  1989. HRTS2_N_B_MARK, HCTS2_N_B_MARK,
  1990. };
  1991. /* - HSCIF3 ----------------------------------------------------------------- */
  1992. static const unsigned int hscif3_data_a_pins[] = {
  1993. /* RX, TX */
  1994. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  1995. };
  1996. static const unsigned int hscif3_data_a_mux[] = {
  1997. HRX3_A_MARK, HTX3_A_MARK,
  1998. };
  1999. static const unsigned int hscif3_clk_pins[] = {
  2000. /* SCK */
  2001. RCAR_GP_PIN(1, 22),
  2002. };
  2003. static const unsigned int hscif3_clk_mux[] = {
  2004. HSCK3_MARK,
  2005. };
  2006. static const unsigned int hscif3_ctrl_pins[] = {
  2007. /* RTS, CTS */
  2008. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2009. };
  2010. static const unsigned int hscif3_ctrl_mux[] = {
  2011. HRTS3_N_MARK, HCTS3_N_MARK,
  2012. };
  2013. static const unsigned int hscif3_data_b_pins[] = {
  2014. /* RX, TX */
  2015. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  2016. };
  2017. static const unsigned int hscif3_data_b_mux[] = {
  2018. HRX3_B_MARK, HTX3_B_MARK,
  2019. };
  2020. static const unsigned int hscif3_data_c_pins[] = {
  2021. /* RX, TX */
  2022. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2023. };
  2024. static const unsigned int hscif3_data_c_mux[] = {
  2025. HRX3_C_MARK, HTX3_C_MARK,
  2026. };
  2027. static const unsigned int hscif3_data_d_pins[] = {
  2028. /* RX, TX */
  2029. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2030. };
  2031. static const unsigned int hscif3_data_d_mux[] = {
  2032. HRX3_D_MARK, HTX3_D_MARK,
  2033. };
  2034. /* - HSCIF4 ----------------------------------------------------------------- */
  2035. static const unsigned int hscif4_data_a_pins[] = {
  2036. /* RX, TX */
  2037. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  2038. };
  2039. static const unsigned int hscif4_data_a_mux[] = {
  2040. HRX4_A_MARK, HTX4_A_MARK,
  2041. };
  2042. static const unsigned int hscif4_clk_pins[] = {
  2043. /* SCK */
  2044. RCAR_GP_PIN(1, 11),
  2045. };
  2046. static const unsigned int hscif4_clk_mux[] = {
  2047. HSCK4_MARK,
  2048. };
  2049. static const unsigned int hscif4_ctrl_pins[] = {
  2050. /* RTS, CTS */
  2051. RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
  2052. };
  2053. static const unsigned int hscif4_ctrl_mux[] = {
  2054. HRTS4_N_MARK, HCTS4_N_MARK,
  2055. };
  2056. static const unsigned int hscif4_data_b_pins[] = {
  2057. /* RX, TX */
  2058. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2059. };
  2060. static const unsigned int hscif4_data_b_mux[] = {
  2061. HRX4_B_MARK, HTX4_B_MARK,
  2062. };
  2063. /* - I2C -------------------------------------------------------------------- */
  2064. static const unsigned int i2c0_pins[] = {
  2065. /* SCL, SDA */
  2066. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2067. };
  2068. static const unsigned int i2c0_mux[] = {
  2069. SCL0_MARK, SDA0_MARK,
  2070. };
  2071. static const unsigned int i2c1_a_pins[] = {
  2072. /* SDA, SCL */
  2073. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  2074. };
  2075. static const unsigned int i2c1_a_mux[] = {
  2076. SDA1_A_MARK, SCL1_A_MARK,
  2077. };
  2078. static const unsigned int i2c1_b_pins[] = {
  2079. /* SDA, SCL */
  2080. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
  2081. };
  2082. static const unsigned int i2c1_b_mux[] = {
  2083. SDA1_B_MARK, SCL1_B_MARK,
  2084. };
  2085. static const unsigned int i2c2_a_pins[] = {
  2086. /* SDA, SCL */
  2087. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
  2088. };
  2089. static const unsigned int i2c2_a_mux[] = {
  2090. SDA2_A_MARK, SCL2_A_MARK,
  2091. };
  2092. static const unsigned int i2c2_b_pins[] = {
  2093. /* SDA, SCL */
  2094. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
  2095. };
  2096. static const unsigned int i2c2_b_mux[] = {
  2097. SDA2_B_MARK, SCL2_B_MARK,
  2098. };
  2099. static const unsigned int i2c3_pins[] = {
  2100. /* SCL, SDA */
  2101. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  2102. };
  2103. static const unsigned int i2c3_mux[] = {
  2104. SCL3_MARK, SDA3_MARK,
  2105. };
  2106. static const unsigned int i2c5_pins[] = {
  2107. /* SCL, SDA */
  2108. RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
  2109. };
  2110. static const unsigned int i2c5_mux[] = {
  2111. SCL5_MARK, SDA5_MARK,
  2112. };
  2113. static const unsigned int i2c6_a_pins[] = {
  2114. /* SDA, SCL */
  2115. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  2116. };
  2117. static const unsigned int i2c6_a_mux[] = {
  2118. SDA6_A_MARK, SCL6_A_MARK,
  2119. };
  2120. static const unsigned int i2c6_b_pins[] = {
  2121. /* SDA, SCL */
  2122. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  2123. };
  2124. static const unsigned int i2c6_b_mux[] = {
  2125. SDA6_B_MARK, SCL6_B_MARK,
  2126. };
  2127. static const unsigned int i2c6_c_pins[] = {
  2128. /* SDA, SCL */
  2129. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
  2130. };
  2131. static const unsigned int i2c6_c_mux[] = {
  2132. SDA6_C_MARK, SCL6_C_MARK,
  2133. };
  2134. /* - INTC-EX ---------------------------------------------------------------- */
  2135. static const unsigned int intc_ex_irq0_pins[] = {
  2136. /* IRQ0 */
  2137. RCAR_GP_PIN(2, 0),
  2138. };
  2139. static const unsigned int intc_ex_irq0_mux[] = {
  2140. IRQ0_MARK,
  2141. };
  2142. static const unsigned int intc_ex_irq1_pins[] = {
  2143. /* IRQ1 */
  2144. RCAR_GP_PIN(2, 1),
  2145. };
  2146. static const unsigned int intc_ex_irq1_mux[] = {
  2147. IRQ1_MARK,
  2148. };
  2149. static const unsigned int intc_ex_irq2_pins[] = {
  2150. /* IRQ2 */
  2151. RCAR_GP_PIN(2, 2),
  2152. };
  2153. static const unsigned int intc_ex_irq2_mux[] = {
  2154. IRQ2_MARK,
  2155. };
  2156. static const unsigned int intc_ex_irq3_pins[] = {
  2157. /* IRQ3 */
  2158. RCAR_GP_PIN(2, 3),
  2159. };
  2160. static const unsigned int intc_ex_irq3_mux[] = {
  2161. IRQ3_MARK,
  2162. };
  2163. static const unsigned int intc_ex_irq4_pins[] = {
  2164. /* IRQ4 */
  2165. RCAR_GP_PIN(2, 4),
  2166. };
  2167. static const unsigned int intc_ex_irq4_mux[] = {
  2168. IRQ4_MARK,
  2169. };
  2170. static const unsigned int intc_ex_irq5_pins[] = {
  2171. /* IRQ5 */
  2172. RCAR_GP_PIN(2, 5),
  2173. };
  2174. static const unsigned int intc_ex_irq5_mux[] = {
  2175. IRQ5_MARK,
  2176. };
  2177. /* - MSIOF0 ----------------------------------------------------------------- */
  2178. static const unsigned int msiof0_clk_pins[] = {
  2179. /* SCK */
  2180. RCAR_GP_PIN(5, 17),
  2181. };
  2182. static const unsigned int msiof0_clk_mux[] = {
  2183. MSIOF0_SCK_MARK,
  2184. };
  2185. static const unsigned int msiof0_sync_pins[] = {
  2186. /* SYNC */
  2187. RCAR_GP_PIN(5, 18),
  2188. };
  2189. static const unsigned int msiof0_sync_mux[] = {
  2190. MSIOF0_SYNC_MARK,
  2191. };
  2192. static const unsigned int msiof0_ss1_pins[] = {
  2193. /* SS1 */
  2194. RCAR_GP_PIN(5, 19),
  2195. };
  2196. static const unsigned int msiof0_ss1_mux[] = {
  2197. MSIOF0_SS1_MARK,
  2198. };
  2199. static const unsigned int msiof0_ss2_pins[] = {
  2200. /* SS2 */
  2201. RCAR_GP_PIN(5, 21),
  2202. };
  2203. static const unsigned int msiof0_ss2_mux[] = {
  2204. MSIOF0_SS2_MARK,
  2205. };
  2206. static const unsigned int msiof0_txd_pins[] = {
  2207. /* TXD */
  2208. RCAR_GP_PIN(5, 20),
  2209. };
  2210. static const unsigned int msiof0_txd_mux[] = {
  2211. MSIOF0_TXD_MARK,
  2212. };
  2213. static const unsigned int msiof0_rxd_pins[] = {
  2214. /* RXD */
  2215. RCAR_GP_PIN(5, 22),
  2216. };
  2217. static const unsigned int msiof0_rxd_mux[] = {
  2218. MSIOF0_RXD_MARK,
  2219. };
  2220. /* - MSIOF1 ----------------------------------------------------------------- */
  2221. static const unsigned int msiof1_clk_a_pins[] = {
  2222. /* SCK */
  2223. RCAR_GP_PIN(6, 8),
  2224. };
  2225. static const unsigned int msiof1_clk_a_mux[] = {
  2226. MSIOF1_SCK_A_MARK,
  2227. };
  2228. static const unsigned int msiof1_sync_a_pins[] = {
  2229. /* SYNC */
  2230. RCAR_GP_PIN(6, 9),
  2231. };
  2232. static const unsigned int msiof1_sync_a_mux[] = {
  2233. MSIOF1_SYNC_A_MARK,
  2234. };
  2235. static const unsigned int msiof1_ss1_a_pins[] = {
  2236. /* SS1 */
  2237. RCAR_GP_PIN(6, 5),
  2238. };
  2239. static const unsigned int msiof1_ss1_a_mux[] = {
  2240. MSIOF1_SS1_A_MARK,
  2241. };
  2242. static const unsigned int msiof1_ss2_a_pins[] = {
  2243. /* SS2 */
  2244. RCAR_GP_PIN(6, 6),
  2245. };
  2246. static const unsigned int msiof1_ss2_a_mux[] = {
  2247. MSIOF1_SS2_A_MARK,
  2248. };
  2249. static const unsigned int msiof1_txd_a_pins[] = {
  2250. /* TXD */
  2251. RCAR_GP_PIN(6, 7),
  2252. };
  2253. static const unsigned int msiof1_txd_a_mux[] = {
  2254. MSIOF1_TXD_A_MARK,
  2255. };
  2256. static const unsigned int msiof1_rxd_a_pins[] = {
  2257. /* RXD */
  2258. RCAR_GP_PIN(6, 10),
  2259. };
  2260. static const unsigned int msiof1_rxd_a_mux[] = {
  2261. MSIOF1_RXD_A_MARK,
  2262. };
  2263. static const unsigned int msiof1_clk_b_pins[] = {
  2264. /* SCK */
  2265. RCAR_GP_PIN(5, 9),
  2266. };
  2267. static const unsigned int msiof1_clk_b_mux[] = {
  2268. MSIOF1_SCK_B_MARK,
  2269. };
  2270. static const unsigned int msiof1_sync_b_pins[] = {
  2271. /* SYNC */
  2272. RCAR_GP_PIN(5, 3),
  2273. };
  2274. static const unsigned int msiof1_sync_b_mux[] = {
  2275. MSIOF1_SYNC_B_MARK,
  2276. };
  2277. static const unsigned int msiof1_ss1_b_pins[] = {
  2278. /* SS1 */
  2279. RCAR_GP_PIN(5, 4),
  2280. };
  2281. static const unsigned int msiof1_ss1_b_mux[] = {
  2282. MSIOF1_SS1_B_MARK,
  2283. };
  2284. static const unsigned int msiof1_ss2_b_pins[] = {
  2285. /* SS2 */
  2286. RCAR_GP_PIN(5, 0),
  2287. };
  2288. static const unsigned int msiof1_ss2_b_mux[] = {
  2289. MSIOF1_SS2_B_MARK,
  2290. };
  2291. static const unsigned int msiof1_txd_b_pins[] = {
  2292. /* TXD */
  2293. RCAR_GP_PIN(5, 8),
  2294. };
  2295. static const unsigned int msiof1_txd_b_mux[] = {
  2296. MSIOF1_TXD_B_MARK,
  2297. };
  2298. static const unsigned int msiof1_rxd_b_pins[] = {
  2299. /* RXD */
  2300. RCAR_GP_PIN(5, 7),
  2301. };
  2302. static const unsigned int msiof1_rxd_b_mux[] = {
  2303. MSIOF1_RXD_B_MARK,
  2304. };
  2305. static const unsigned int msiof1_clk_c_pins[] = {
  2306. /* SCK */
  2307. RCAR_GP_PIN(6, 17),
  2308. };
  2309. static const unsigned int msiof1_clk_c_mux[] = {
  2310. MSIOF1_SCK_C_MARK,
  2311. };
  2312. static const unsigned int msiof1_sync_c_pins[] = {
  2313. /* SYNC */
  2314. RCAR_GP_PIN(6, 18),
  2315. };
  2316. static const unsigned int msiof1_sync_c_mux[] = {
  2317. MSIOF1_SYNC_C_MARK,
  2318. };
  2319. static const unsigned int msiof1_ss1_c_pins[] = {
  2320. /* SS1 */
  2321. RCAR_GP_PIN(6, 21),
  2322. };
  2323. static const unsigned int msiof1_ss1_c_mux[] = {
  2324. MSIOF1_SS1_C_MARK,
  2325. };
  2326. static const unsigned int msiof1_ss2_c_pins[] = {
  2327. /* SS2 */
  2328. RCAR_GP_PIN(6, 27),
  2329. };
  2330. static const unsigned int msiof1_ss2_c_mux[] = {
  2331. MSIOF1_SS2_C_MARK,
  2332. };
  2333. static const unsigned int msiof1_txd_c_pins[] = {
  2334. /* TXD */
  2335. RCAR_GP_PIN(6, 20),
  2336. };
  2337. static const unsigned int msiof1_txd_c_mux[] = {
  2338. MSIOF1_TXD_C_MARK,
  2339. };
  2340. static const unsigned int msiof1_rxd_c_pins[] = {
  2341. /* RXD */
  2342. RCAR_GP_PIN(6, 19),
  2343. };
  2344. static const unsigned int msiof1_rxd_c_mux[] = {
  2345. MSIOF1_RXD_C_MARK,
  2346. };
  2347. static const unsigned int msiof1_clk_d_pins[] = {
  2348. /* SCK */
  2349. RCAR_GP_PIN(5, 12),
  2350. };
  2351. static const unsigned int msiof1_clk_d_mux[] = {
  2352. MSIOF1_SCK_D_MARK,
  2353. };
  2354. static const unsigned int msiof1_sync_d_pins[] = {
  2355. /* SYNC */
  2356. RCAR_GP_PIN(5, 15),
  2357. };
  2358. static const unsigned int msiof1_sync_d_mux[] = {
  2359. MSIOF1_SYNC_D_MARK,
  2360. };
  2361. static const unsigned int msiof1_ss1_d_pins[] = {
  2362. /* SS1 */
  2363. RCAR_GP_PIN(5, 16),
  2364. };
  2365. static const unsigned int msiof1_ss1_d_mux[] = {
  2366. MSIOF1_SS1_D_MARK,
  2367. };
  2368. static const unsigned int msiof1_ss2_d_pins[] = {
  2369. /* SS2 */
  2370. RCAR_GP_PIN(5, 21),
  2371. };
  2372. static const unsigned int msiof1_ss2_d_mux[] = {
  2373. MSIOF1_SS2_D_MARK,
  2374. };
  2375. static const unsigned int msiof1_txd_d_pins[] = {
  2376. /* TXD */
  2377. RCAR_GP_PIN(5, 14),
  2378. };
  2379. static const unsigned int msiof1_txd_d_mux[] = {
  2380. MSIOF1_TXD_D_MARK,
  2381. };
  2382. static const unsigned int msiof1_rxd_d_pins[] = {
  2383. /* RXD */
  2384. RCAR_GP_PIN(5, 13),
  2385. };
  2386. static const unsigned int msiof1_rxd_d_mux[] = {
  2387. MSIOF1_RXD_D_MARK,
  2388. };
  2389. static const unsigned int msiof1_clk_e_pins[] = {
  2390. /* SCK */
  2391. RCAR_GP_PIN(3, 0),
  2392. };
  2393. static const unsigned int msiof1_clk_e_mux[] = {
  2394. MSIOF1_SCK_E_MARK,
  2395. };
  2396. static const unsigned int msiof1_sync_e_pins[] = {
  2397. /* SYNC */
  2398. RCAR_GP_PIN(3, 1),
  2399. };
  2400. static const unsigned int msiof1_sync_e_mux[] = {
  2401. MSIOF1_SYNC_E_MARK,
  2402. };
  2403. static const unsigned int msiof1_ss1_e_pins[] = {
  2404. /* SS1 */
  2405. RCAR_GP_PIN(3, 4),
  2406. };
  2407. static const unsigned int msiof1_ss1_e_mux[] = {
  2408. MSIOF1_SS1_E_MARK,
  2409. };
  2410. static const unsigned int msiof1_ss2_e_pins[] = {
  2411. /* SS2 */
  2412. RCAR_GP_PIN(3, 5),
  2413. };
  2414. static const unsigned int msiof1_ss2_e_mux[] = {
  2415. MSIOF1_SS2_E_MARK,
  2416. };
  2417. static const unsigned int msiof1_txd_e_pins[] = {
  2418. /* TXD */
  2419. RCAR_GP_PIN(3, 3),
  2420. };
  2421. static const unsigned int msiof1_txd_e_mux[] = {
  2422. MSIOF1_TXD_E_MARK,
  2423. };
  2424. static const unsigned int msiof1_rxd_e_pins[] = {
  2425. /* RXD */
  2426. RCAR_GP_PIN(3, 2),
  2427. };
  2428. static const unsigned int msiof1_rxd_e_mux[] = {
  2429. MSIOF1_RXD_E_MARK,
  2430. };
  2431. static const unsigned int msiof1_clk_f_pins[] = {
  2432. /* SCK */
  2433. RCAR_GP_PIN(5, 23),
  2434. };
  2435. static const unsigned int msiof1_clk_f_mux[] = {
  2436. MSIOF1_SCK_F_MARK,
  2437. };
  2438. static const unsigned int msiof1_sync_f_pins[] = {
  2439. /* SYNC */
  2440. RCAR_GP_PIN(5, 24),
  2441. };
  2442. static const unsigned int msiof1_sync_f_mux[] = {
  2443. MSIOF1_SYNC_F_MARK,
  2444. };
  2445. static const unsigned int msiof1_ss1_f_pins[] = {
  2446. /* SS1 */
  2447. RCAR_GP_PIN(6, 1),
  2448. };
  2449. static const unsigned int msiof1_ss1_f_mux[] = {
  2450. MSIOF1_SS1_F_MARK,
  2451. };
  2452. static const unsigned int msiof1_ss2_f_pins[] = {
  2453. /* SS2 */
  2454. RCAR_GP_PIN(6, 2),
  2455. };
  2456. static const unsigned int msiof1_ss2_f_mux[] = {
  2457. MSIOF1_SS2_F_MARK,
  2458. };
  2459. static const unsigned int msiof1_txd_f_pins[] = {
  2460. /* TXD */
  2461. RCAR_GP_PIN(6, 0),
  2462. };
  2463. static const unsigned int msiof1_txd_f_mux[] = {
  2464. MSIOF1_TXD_F_MARK,
  2465. };
  2466. static const unsigned int msiof1_rxd_f_pins[] = {
  2467. /* RXD */
  2468. RCAR_GP_PIN(5, 25),
  2469. };
  2470. static const unsigned int msiof1_rxd_f_mux[] = {
  2471. MSIOF1_RXD_F_MARK,
  2472. };
  2473. static const unsigned int msiof1_clk_g_pins[] = {
  2474. /* SCK */
  2475. RCAR_GP_PIN(3, 6),
  2476. };
  2477. static const unsigned int msiof1_clk_g_mux[] = {
  2478. MSIOF1_SCK_G_MARK,
  2479. };
  2480. static const unsigned int msiof1_sync_g_pins[] = {
  2481. /* SYNC */
  2482. RCAR_GP_PIN(3, 7),
  2483. };
  2484. static const unsigned int msiof1_sync_g_mux[] = {
  2485. MSIOF1_SYNC_G_MARK,
  2486. };
  2487. static const unsigned int msiof1_ss1_g_pins[] = {
  2488. /* SS1 */
  2489. RCAR_GP_PIN(3, 10),
  2490. };
  2491. static const unsigned int msiof1_ss1_g_mux[] = {
  2492. MSIOF1_SS1_G_MARK,
  2493. };
  2494. static const unsigned int msiof1_ss2_g_pins[] = {
  2495. /* SS2 */
  2496. RCAR_GP_PIN(3, 11),
  2497. };
  2498. static const unsigned int msiof1_ss2_g_mux[] = {
  2499. MSIOF1_SS2_G_MARK,
  2500. };
  2501. static const unsigned int msiof1_txd_g_pins[] = {
  2502. /* TXD */
  2503. RCAR_GP_PIN(3, 9),
  2504. };
  2505. static const unsigned int msiof1_txd_g_mux[] = {
  2506. MSIOF1_TXD_G_MARK,
  2507. };
  2508. static const unsigned int msiof1_rxd_g_pins[] = {
  2509. /* RXD */
  2510. RCAR_GP_PIN(3, 8),
  2511. };
  2512. static const unsigned int msiof1_rxd_g_mux[] = {
  2513. MSIOF1_RXD_G_MARK,
  2514. };
  2515. /* - MSIOF2 ----------------------------------------------------------------- */
  2516. static const unsigned int msiof2_clk_a_pins[] = {
  2517. /* SCK */
  2518. RCAR_GP_PIN(1, 9),
  2519. };
  2520. static const unsigned int msiof2_clk_a_mux[] = {
  2521. MSIOF2_SCK_A_MARK,
  2522. };
  2523. static const unsigned int msiof2_sync_a_pins[] = {
  2524. /* SYNC */
  2525. RCAR_GP_PIN(1, 8),
  2526. };
  2527. static const unsigned int msiof2_sync_a_mux[] = {
  2528. MSIOF2_SYNC_A_MARK,
  2529. };
  2530. static const unsigned int msiof2_ss1_a_pins[] = {
  2531. /* SS1 */
  2532. RCAR_GP_PIN(1, 6),
  2533. };
  2534. static const unsigned int msiof2_ss1_a_mux[] = {
  2535. MSIOF2_SS1_A_MARK,
  2536. };
  2537. static const unsigned int msiof2_ss2_a_pins[] = {
  2538. /* SS2 */
  2539. RCAR_GP_PIN(1, 7),
  2540. };
  2541. static const unsigned int msiof2_ss2_a_mux[] = {
  2542. MSIOF2_SS2_A_MARK,
  2543. };
  2544. static const unsigned int msiof2_txd_a_pins[] = {
  2545. /* TXD */
  2546. RCAR_GP_PIN(1, 11),
  2547. };
  2548. static const unsigned int msiof2_txd_a_mux[] = {
  2549. MSIOF2_TXD_A_MARK,
  2550. };
  2551. static const unsigned int msiof2_rxd_a_pins[] = {
  2552. /* RXD */
  2553. RCAR_GP_PIN(1, 10),
  2554. };
  2555. static const unsigned int msiof2_rxd_a_mux[] = {
  2556. MSIOF2_RXD_A_MARK,
  2557. };
  2558. static const unsigned int msiof2_clk_b_pins[] = {
  2559. /* SCK */
  2560. RCAR_GP_PIN(0, 4),
  2561. };
  2562. static const unsigned int msiof2_clk_b_mux[] = {
  2563. MSIOF2_SCK_B_MARK,
  2564. };
  2565. static const unsigned int msiof2_sync_b_pins[] = {
  2566. /* SYNC */
  2567. RCAR_GP_PIN(0, 5),
  2568. };
  2569. static const unsigned int msiof2_sync_b_mux[] = {
  2570. MSIOF2_SYNC_B_MARK,
  2571. };
  2572. static const unsigned int msiof2_ss1_b_pins[] = {
  2573. /* SS1 */
  2574. RCAR_GP_PIN(0, 0),
  2575. };
  2576. static const unsigned int msiof2_ss1_b_mux[] = {
  2577. MSIOF2_SS1_B_MARK,
  2578. };
  2579. static const unsigned int msiof2_ss2_b_pins[] = {
  2580. /* SS2 */
  2581. RCAR_GP_PIN(0, 1),
  2582. };
  2583. static const unsigned int msiof2_ss2_b_mux[] = {
  2584. MSIOF2_SS2_B_MARK,
  2585. };
  2586. static const unsigned int msiof2_txd_b_pins[] = {
  2587. /* TXD */
  2588. RCAR_GP_PIN(0, 7),
  2589. };
  2590. static const unsigned int msiof2_txd_b_mux[] = {
  2591. MSIOF2_TXD_B_MARK,
  2592. };
  2593. static const unsigned int msiof2_rxd_b_pins[] = {
  2594. /* RXD */
  2595. RCAR_GP_PIN(0, 6),
  2596. };
  2597. static const unsigned int msiof2_rxd_b_mux[] = {
  2598. MSIOF2_RXD_B_MARK,
  2599. };
  2600. static const unsigned int msiof2_clk_c_pins[] = {
  2601. /* SCK */
  2602. RCAR_GP_PIN(2, 12),
  2603. };
  2604. static const unsigned int msiof2_clk_c_mux[] = {
  2605. MSIOF2_SCK_C_MARK,
  2606. };
  2607. static const unsigned int msiof2_sync_c_pins[] = {
  2608. /* SYNC */
  2609. RCAR_GP_PIN(2, 11),
  2610. };
  2611. static const unsigned int msiof2_sync_c_mux[] = {
  2612. MSIOF2_SYNC_C_MARK,
  2613. };
  2614. static const unsigned int msiof2_ss1_c_pins[] = {
  2615. /* SS1 */
  2616. RCAR_GP_PIN(2, 10),
  2617. };
  2618. static const unsigned int msiof2_ss1_c_mux[] = {
  2619. MSIOF2_SS1_C_MARK,
  2620. };
  2621. static const unsigned int msiof2_ss2_c_pins[] = {
  2622. /* SS2 */
  2623. RCAR_GP_PIN(2, 9),
  2624. };
  2625. static const unsigned int msiof2_ss2_c_mux[] = {
  2626. MSIOF2_SS2_C_MARK,
  2627. };
  2628. static const unsigned int msiof2_txd_c_pins[] = {
  2629. /* TXD */
  2630. RCAR_GP_PIN(2, 14),
  2631. };
  2632. static const unsigned int msiof2_txd_c_mux[] = {
  2633. MSIOF2_TXD_C_MARK,
  2634. };
  2635. static const unsigned int msiof2_rxd_c_pins[] = {
  2636. /* RXD */
  2637. RCAR_GP_PIN(2, 13),
  2638. };
  2639. static const unsigned int msiof2_rxd_c_mux[] = {
  2640. MSIOF2_RXD_C_MARK,
  2641. };
  2642. static const unsigned int msiof2_clk_d_pins[] = {
  2643. /* SCK */
  2644. RCAR_GP_PIN(0, 8),
  2645. };
  2646. static const unsigned int msiof2_clk_d_mux[] = {
  2647. MSIOF2_SCK_D_MARK,
  2648. };
  2649. static const unsigned int msiof2_sync_d_pins[] = {
  2650. /* SYNC */
  2651. RCAR_GP_PIN(0, 9),
  2652. };
  2653. static const unsigned int msiof2_sync_d_mux[] = {
  2654. MSIOF2_SYNC_D_MARK,
  2655. };
  2656. static const unsigned int msiof2_ss1_d_pins[] = {
  2657. /* SS1 */
  2658. RCAR_GP_PIN(0, 12),
  2659. };
  2660. static const unsigned int msiof2_ss1_d_mux[] = {
  2661. MSIOF2_SS1_D_MARK,
  2662. };
  2663. static const unsigned int msiof2_ss2_d_pins[] = {
  2664. /* SS2 */
  2665. RCAR_GP_PIN(0, 13),
  2666. };
  2667. static const unsigned int msiof2_ss2_d_mux[] = {
  2668. MSIOF2_SS2_D_MARK,
  2669. };
  2670. static const unsigned int msiof2_txd_d_pins[] = {
  2671. /* TXD */
  2672. RCAR_GP_PIN(0, 11),
  2673. };
  2674. static const unsigned int msiof2_txd_d_mux[] = {
  2675. MSIOF2_TXD_D_MARK,
  2676. };
  2677. static const unsigned int msiof2_rxd_d_pins[] = {
  2678. /* RXD */
  2679. RCAR_GP_PIN(0, 10),
  2680. };
  2681. static const unsigned int msiof2_rxd_d_mux[] = {
  2682. MSIOF2_RXD_D_MARK,
  2683. };
  2684. /* - MSIOF3 ----------------------------------------------------------------- */
  2685. static const unsigned int msiof3_clk_a_pins[] = {
  2686. /* SCK */
  2687. RCAR_GP_PIN(0, 0),
  2688. };
  2689. static const unsigned int msiof3_clk_a_mux[] = {
  2690. MSIOF3_SCK_A_MARK,
  2691. };
  2692. static const unsigned int msiof3_sync_a_pins[] = {
  2693. /* SYNC */
  2694. RCAR_GP_PIN(0, 1),
  2695. };
  2696. static const unsigned int msiof3_sync_a_mux[] = {
  2697. MSIOF3_SYNC_A_MARK,
  2698. };
  2699. static const unsigned int msiof3_ss1_a_pins[] = {
  2700. /* SS1 */
  2701. RCAR_GP_PIN(0, 14),
  2702. };
  2703. static const unsigned int msiof3_ss1_a_mux[] = {
  2704. MSIOF3_SS1_A_MARK,
  2705. };
  2706. static const unsigned int msiof3_ss2_a_pins[] = {
  2707. /* SS2 */
  2708. RCAR_GP_PIN(0, 15),
  2709. };
  2710. static const unsigned int msiof3_ss2_a_mux[] = {
  2711. MSIOF3_SS2_A_MARK,
  2712. };
  2713. static const unsigned int msiof3_txd_a_pins[] = {
  2714. /* TXD */
  2715. RCAR_GP_PIN(0, 3),
  2716. };
  2717. static const unsigned int msiof3_txd_a_mux[] = {
  2718. MSIOF3_TXD_A_MARK,
  2719. };
  2720. static const unsigned int msiof3_rxd_a_pins[] = {
  2721. /* RXD */
  2722. RCAR_GP_PIN(0, 2),
  2723. };
  2724. static const unsigned int msiof3_rxd_a_mux[] = {
  2725. MSIOF3_RXD_A_MARK,
  2726. };
  2727. static const unsigned int msiof3_clk_b_pins[] = {
  2728. /* SCK */
  2729. RCAR_GP_PIN(1, 2),
  2730. };
  2731. static const unsigned int msiof3_clk_b_mux[] = {
  2732. MSIOF3_SCK_B_MARK,
  2733. };
  2734. static const unsigned int msiof3_sync_b_pins[] = {
  2735. /* SYNC */
  2736. RCAR_GP_PIN(1, 0),
  2737. };
  2738. static const unsigned int msiof3_sync_b_mux[] = {
  2739. MSIOF3_SYNC_B_MARK,
  2740. };
  2741. static const unsigned int msiof3_ss1_b_pins[] = {
  2742. /* SS1 */
  2743. RCAR_GP_PIN(1, 4),
  2744. };
  2745. static const unsigned int msiof3_ss1_b_mux[] = {
  2746. MSIOF3_SS1_B_MARK,
  2747. };
  2748. static const unsigned int msiof3_ss2_b_pins[] = {
  2749. /* SS2 */
  2750. RCAR_GP_PIN(1, 5),
  2751. };
  2752. static const unsigned int msiof3_ss2_b_mux[] = {
  2753. MSIOF3_SS2_B_MARK,
  2754. };
  2755. static const unsigned int msiof3_txd_b_pins[] = {
  2756. /* TXD */
  2757. RCAR_GP_PIN(1, 1),
  2758. };
  2759. static const unsigned int msiof3_txd_b_mux[] = {
  2760. MSIOF3_TXD_B_MARK,
  2761. };
  2762. static const unsigned int msiof3_rxd_b_pins[] = {
  2763. /* RXD */
  2764. RCAR_GP_PIN(1, 3),
  2765. };
  2766. static const unsigned int msiof3_rxd_b_mux[] = {
  2767. MSIOF3_RXD_B_MARK,
  2768. };
  2769. static const unsigned int msiof3_clk_c_pins[] = {
  2770. /* SCK */
  2771. RCAR_GP_PIN(1, 12),
  2772. };
  2773. static const unsigned int msiof3_clk_c_mux[] = {
  2774. MSIOF3_SCK_C_MARK,
  2775. };
  2776. static const unsigned int msiof3_sync_c_pins[] = {
  2777. /* SYNC */
  2778. RCAR_GP_PIN(1, 13),
  2779. };
  2780. static const unsigned int msiof3_sync_c_mux[] = {
  2781. MSIOF3_SYNC_C_MARK,
  2782. };
  2783. static const unsigned int msiof3_txd_c_pins[] = {
  2784. /* TXD */
  2785. RCAR_GP_PIN(1, 15),
  2786. };
  2787. static const unsigned int msiof3_txd_c_mux[] = {
  2788. MSIOF3_TXD_C_MARK,
  2789. };
  2790. static const unsigned int msiof3_rxd_c_pins[] = {
  2791. /* RXD */
  2792. RCAR_GP_PIN(1, 14),
  2793. };
  2794. static const unsigned int msiof3_rxd_c_mux[] = {
  2795. MSIOF3_RXD_C_MARK,
  2796. };
  2797. static const unsigned int msiof3_clk_d_pins[] = {
  2798. /* SCK */
  2799. RCAR_GP_PIN(1, 22),
  2800. };
  2801. static const unsigned int msiof3_clk_d_mux[] = {
  2802. MSIOF3_SCK_D_MARK,
  2803. };
  2804. static const unsigned int msiof3_sync_d_pins[] = {
  2805. /* SYNC */
  2806. RCAR_GP_PIN(1, 23),
  2807. };
  2808. static const unsigned int msiof3_sync_d_mux[] = {
  2809. MSIOF3_SYNC_D_MARK,
  2810. };
  2811. static const unsigned int msiof3_ss1_d_pins[] = {
  2812. /* SS1 */
  2813. RCAR_GP_PIN(1, 26),
  2814. };
  2815. static const unsigned int msiof3_ss1_d_mux[] = {
  2816. MSIOF3_SS1_D_MARK,
  2817. };
  2818. static const unsigned int msiof3_txd_d_pins[] = {
  2819. /* TXD */
  2820. RCAR_GP_PIN(1, 25),
  2821. };
  2822. static const unsigned int msiof3_txd_d_mux[] = {
  2823. MSIOF3_TXD_D_MARK,
  2824. };
  2825. static const unsigned int msiof3_rxd_d_pins[] = {
  2826. /* RXD */
  2827. RCAR_GP_PIN(1, 24),
  2828. };
  2829. static const unsigned int msiof3_rxd_d_mux[] = {
  2830. MSIOF3_RXD_D_MARK,
  2831. };
  2832. /* - PWM0 --------------------------------------------------------------------*/
  2833. static const unsigned int pwm0_pins[] = {
  2834. /* PWM */
  2835. RCAR_GP_PIN(2, 6),
  2836. };
  2837. static const unsigned int pwm0_mux[] = {
  2838. PWM0_MARK,
  2839. };
  2840. /* - PWM1 --------------------------------------------------------------------*/
  2841. static const unsigned int pwm1_a_pins[] = {
  2842. /* PWM */
  2843. RCAR_GP_PIN(2, 7),
  2844. };
  2845. static const unsigned int pwm1_a_mux[] = {
  2846. PWM1_A_MARK,
  2847. };
  2848. static const unsigned int pwm1_b_pins[] = {
  2849. /* PWM */
  2850. RCAR_GP_PIN(1, 8),
  2851. };
  2852. static const unsigned int pwm1_b_mux[] = {
  2853. PWM1_B_MARK,
  2854. };
  2855. /* - PWM2 --------------------------------------------------------------------*/
  2856. static const unsigned int pwm2_a_pins[] = {
  2857. /* PWM */
  2858. RCAR_GP_PIN(2, 8),
  2859. };
  2860. static const unsigned int pwm2_a_mux[] = {
  2861. PWM2_A_MARK,
  2862. };
  2863. static const unsigned int pwm2_b_pins[] = {
  2864. /* PWM */
  2865. RCAR_GP_PIN(1, 11),
  2866. };
  2867. static const unsigned int pwm2_b_mux[] = {
  2868. PWM2_B_MARK,
  2869. };
  2870. /* - PWM3 --------------------------------------------------------------------*/
  2871. static const unsigned int pwm3_a_pins[] = {
  2872. /* PWM */
  2873. RCAR_GP_PIN(1, 0),
  2874. };
  2875. static const unsigned int pwm3_a_mux[] = {
  2876. PWM3_A_MARK,
  2877. };
  2878. static const unsigned int pwm3_b_pins[] = {
  2879. /* PWM */
  2880. RCAR_GP_PIN(2, 2),
  2881. };
  2882. static const unsigned int pwm3_b_mux[] = {
  2883. PWM3_B_MARK,
  2884. };
  2885. /* - PWM4 --------------------------------------------------------------------*/
  2886. static const unsigned int pwm4_a_pins[] = {
  2887. /* PWM */
  2888. RCAR_GP_PIN(1, 1),
  2889. };
  2890. static const unsigned int pwm4_a_mux[] = {
  2891. PWM4_A_MARK,
  2892. };
  2893. static const unsigned int pwm4_b_pins[] = {
  2894. /* PWM */
  2895. RCAR_GP_PIN(2, 3),
  2896. };
  2897. static const unsigned int pwm4_b_mux[] = {
  2898. PWM4_B_MARK,
  2899. };
  2900. /* - PWM5 --------------------------------------------------------------------*/
  2901. static const unsigned int pwm5_a_pins[] = {
  2902. /* PWM */
  2903. RCAR_GP_PIN(1, 2),
  2904. };
  2905. static const unsigned int pwm5_a_mux[] = {
  2906. PWM5_A_MARK,
  2907. };
  2908. static const unsigned int pwm5_b_pins[] = {
  2909. /* PWM */
  2910. RCAR_GP_PIN(2, 4),
  2911. };
  2912. static const unsigned int pwm5_b_mux[] = {
  2913. PWM5_B_MARK,
  2914. };
  2915. /* - PWM6 --------------------------------------------------------------------*/
  2916. static const unsigned int pwm6_a_pins[] = {
  2917. /* PWM */
  2918. RCAR_GP_PIN(1, 3),
  2919. };
  2920. static const unsigned int pwm6_a_mux[] = {
  2921. PWM6_A_MARK,
  2922. };
  2923. static const unsigned int pwm6_b_pins[] = {
  2924. /* PWM */
  2925. RCAR_GP_PIN(2, 5),
  2926. };
  2927. static const unsigned int pwm6_b_mux[] = {
  2928. PWM6_B_MARK,
  2929. };
  2930. /* - QSPI0 ------------------------------------------------------------------ */
  2931. static const unsigned int qspi0_ctrl_pins[] = {
  2932. /* QSPI0_SPCLK, QSPI0_SSL */
  2933. PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
  2934. };
  2935. static const unsigned int qspi0_ctrl_mux[] = {
  2936. QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
  2937. };
  2938. static const unsigned int qspi0_data2_pins[] = {
  2939. /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
  2940. PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
  2941. };
  2942. static const unsigned int qspi0_data2_mux[] = {
  2943. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  2944. };
  2945. static const unsigned int qspi0_data4_pins[] = {
  2946. /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
  2947. PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
  2948. };
  2949. static const unsigned int qspi0_data4_mux[] = {
  2950. QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
  2951. QSPI0_IO2_MARK, QSPI0_IO3_MARK,
  2952. };
  2953. /* - QSPI1 ------------------------------------------------------------------ */
  2954. static const unsigned int qspi1_ctrl_pins[] = {
  2955. /* QSPI1_SPCLK, QSPI1_SSL */
  2956. PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
  2957. };
  2958. static const unsigned int qspi1_ctrl_mux[] = {
  2959. QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
  2960. };
  2961. static const unsigned int qspi1_data2_pins[] = {
  2962. /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
  2963. PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
  2964. };
  2965. static const unsigned int qspi1_data2_mux[] = {
  2966. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  2967. };
  2968. static const unsigned int qspi1_data4_pins[] = {
  2969. /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
  2970. PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
  2971. };
  2972. static const unsigned int qspi1_data4_mux[] = {
  2973. QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
  2974. QSPI1_IO2_MARK, QSPI1_IO3_MARK,
  2975. };
  2976. /* - SATA --------------------------------------------------------------------*/
  2977. static const unsigned int sata0_devslp_a_pins[] = {
  2978. /* DEVSLP */
  2979. RCAR_GP_PIN(6, 16),
  2980. };
  2981. static const unsigned int sata0_devslp_a_mux[] = {
  2982. SATA_DEVSLP_A_MARK,
  2983. };
  2984. static const unsigned int sata0_devslp_b_pins[] = {
  2985. /* DEVSLP */
  2986. RCAR_GP_PIN(4, 6),
  2987. };
  2988. static const unsigned int sata0_devslp_b_mux[] = {
  2989. SATA_DEVSLP_B_MARK,
  2990. };
  2991. /* - SCIF0 ------------------------------------------------------------------ */
  2992. static const unsigned int scif0_data_pins[] = {
  2993. /* RX, TX */
  2994. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  2995. };
  2996. static const unsigned int scif0_data_mux[] = {
  2997. RX0_MARK, TX0_MARK,
  2998. };
  2999. static const unsigned int scif0_clk_pins[] = {
  3000. /* SCK */
  3001. RCAR_GP_PIN(5, 0),
  3002. };
  3003. static const unsigned int scif0_clk_mux[] = {
  3004. SCK0_MARK,
  3005. };
  3006. static const unsigned int scif0_ctrl_pins[] = {
  3007. /* RTS, CTS */
  3008. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
  3009. };
  3010. static const unsigned int scif0_ctrl_mux[] = {
  3011. RTS0_N_MARK, CTS0_N_MARK,
  3012. };
  3013. /* - SCIF1 ------------------------------------------------------------------ */
  3014. static const unsigned int scif1_data_a_pins[] = {
  3015. /* RX, TX */
  3016. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  3017. };
  3018. static const unsigned int scif1_data_a_mux[] = {
  3019. RX1_A_MARK, TX1_A_MARK,
  3020. };
  3021. static const unsigned int scif1_clk_pins[] = {
  3022. /* SCK */
  3023. RCAR_GP_PIN(6, 21),
  3024. };
  3025. static const unsigned int scif1_clk_mux[] = {
  3026. SCK1_MARK,
  3027. };
  3028. static const unsigned int scif1_ctrl_pins[] = {
  3029. /* RTS, CTS */
  3030. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
  3031. };
  3032. static const unsigned int scif1_ctrl_mux[] = {
  3033. RTS1_N_MARK, CTS1_N_MARK,
  3034. };
  3035. static const unsigned int scif1_data_b_pins[] = {
  3036. /* RX, TX */
  3037. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
  3038. };
  3039. static const unsigned int scif1_data_b_mux[] = {
  3040. RX1_B_MARK, TX1_B_MARK,
  3041. };
  3042. /* - SCIF2 ------------------------------------------------------------------ */
  3043. static const unsigned int scif2_data_a_pins[] = {
  3044. /* RX, TX */
  3045. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  3046. };
  3047. static const unsigned int scif2_data_a_mux[] = {
  3048. RX2_A_MARK, TX2_A_MARK,
  3049. };
  3050. static const unsigned int scif2_clk_pins[] = {
  3051. /* SCK */
  3052. RCAR_GP_PIN(5, 9),
  3053. };
  3054. static const unsigned int scif2_clk_mux[] = {
  3055. SCK2_MARK,
  3056. };
  3057. static const unsigned int scif2_data_b_pins[] = {
  3058. /* RX, TX */
  3059. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3060. };
  3061. static const unsigned int scif2_data_b_mux[] = {
  3062. RX2_B_MARK, TX2_B_MARK,
  3063. };
  3064. /* - SCIF3 ------------------------------------------------------------------ */
  3065. static const unsigned int scif3_data_a_pins[] = {
  3066. /* RX, TX */
  3067. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
  3068. };
  3069. static const unsigned int scif3_data_a_mux[] = {
  3070. RX3_A_MARK, TX3_A_MARK,
  3071. };
  3072. static const unsigned int scif3_clk_pins[] = {
  3073. /* SCK */
  3074. RCAR_GP_PIN(1, 22),
  3075. };
  3076. static const unsigned int scif3_clk_mux[] = {
  3077. SCK3_MARK,
  3078. };
  3079. static const unsigned int scif3_ctrl_pins[] = {
  3080. /* RTS, CTS */
  3081. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
  3082. };
  3083. static const unsigned int scif3_ctrl_mux[] = {
  3084. RTS3_N_MARK, CTS3_N_MARK,
  3085. };
  3086. static const unsigned int scif3_data_b_pins[] = {
  3087. /* RX, TX */
  3088. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
  3089. };
  3090. static const unsigned int scif3_data_b_mux[] = {
  3091. RX3_B_MARK, TX3_B_MARK,
  3092. };
  3093. /* - SCIF4 ------------------------------------------------------------------ */
  3094. static const unsigned int scif4_data_a_pins[] = {
  3095. /* RX, TX */
  3096. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
  3097. };
  3098. static const unsigned int scif4_data_a_mux[] = {
  3099. RX4_A_MARK, TX4_A_MARK,
  3100. };
  3101. static const unsigned int scif4_clk_a_pins[] = {
  3102. /* SCK */
  3103. RCAR_GP_PIN(2, 10),
  3104. };
  3105. static const unsigned int scif4_clk_a_mux[] = {
  3106. SCK4_A_MARK,
  3107. };
  3108. static const unsigned int scif4_ctrl_a_pins[] = {
  3109. /* RTS, CTS */
  3110. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  3111. };
  3112. static const unsigned int scif4_ctrl_a_mux[] = {
  3113. RTS4_N_A_MARK, CTS4_N_A_MARK,
  3114. };
  3115. static const unsigned int scif4_data_b_pins[] = {
  3116. /* RX, TX */
  3117. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3118. };
  3119. static const unsigned int scif4_data_b_mux[] = {
  3120. RX4_B_MARK, TX4_B_MARK,
  3121. };
  3122. static const unsigned int scif4_clk_b_pins[] = {
  3123. /* SCK */
  3124. RCAR_GP_PIN(1, 5),
  3125. };
  3126. static const unsigned int scif4_clk_b_mux[] = {
  3127. SCK4_B_MARK,
  3128. };
  3129. static const unsigned int scif4_ctrl_b_pins[] = {
  3130. /* RTS, CTS */
  3131. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
  3132. };
  3133. static const unsigned int scif4_ctrl_b_mux[] = {
  3134. RTS4_N_B_MARK, CTS4_N_B_MARK,
  3135. };
  3136. static const unsigned int scif4_data_c_pins[] = {
  3137. /* RX, TX */
  3138. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3139. };
  3140. static const unsigned int scif4_data_c_mux[] = {
  3141. RX4_C_MARK, TX4_C_MARK,
  3142. };
  3143. static const unsigned int scif4_clk_c_pins[] = {
  3144. /* SCK */
  3145. RCAR_GP_PIN(0, 8),
  3146. };
  3147. static const unsigned int scif4_clk_c_mux[] = {
  3148. SCK4_C_MARK,
  3149. };
  3150. static const unsigned int scif4_ctrl_c_pins[] = {
  3151. /* RTS, CTS */
  3152. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
  3153. };
  3154. static const unsigned int scif4_ctrl_c_mux[] = {
  3155. RTS4_N_C_MARK, CTS4_N_C_MARK,
  3156. };
  3157. /* - SCIF5 ------------------------------------------------------------------ */
  3158. static const unsigned int scif5_data_pins[] = {
  3159. /* RX, TX */
  3160. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3161. };
  3162. static const unsigned int scif5_data_mux[] = {
  3163. RX5_MARK, TX5_MARK,
  3164. };
  3165. static const unsigned int scif5_clk_pins[] = {
  3166. /* SCK */
  3167. RCAR_GP_PIN(6, 21),
  3168. };
  3169. static const unsigned int scif5_clk_mux[] = {
  3170. SCK5_MARK,
  3171. };
  3172. /* - SCIF Clock ------------------------------------------------------------- */
  3173. static const unsigned int scif_clk_a_pins[] = {
  3174. /* SCIF_CLK */
  3175. RCAR_GP_PIN(6, 23),
  3176. };
  3177. static const unsigned int scif_clk_a_mux[] = {
  3178. SCIF_CLK_A_MARK,
  3179. };
  3180. static const unsigned int scif_clk_b_pins[] = {
  3181. /* SCIF_CLK */
  3182. RCAR_GP_PIN(5, 9),
  3183. };
  3184. static const unsigned int scif_clk_b_mux[] = {
  3185. SCIF_CLK_B_MARK,
  3186. };
  3187. /* - SDHI0 ------------------------------------------------------------------ */
  3188. static const unsigned int sdhi0_data1_pins[] = {
  3189. /* D0 */
  3190. RCAR_GP_PIN(3, 2),
  3191. };
  3192. static const unsigned int sdhi0_data1_mux[] = {
  3193. SD0_DAT0_MARK,
  3194. };
  3195. static const unsigned int sdhi0_data4_pins[] = {
  3196. /* D[0:3] */
  3197. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  3198. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  3199. };
  3200. static const unsigned int sdhi0_data4_mux[] = {
  3201. SD0_DAT0_MARK, SD0_DAT1_MARK,
  3202. SD0_DAT2_MARK, SD0_DAT3_MARK,
  3203. };
  3204. static const unsigned int sdhi0_ctrl_pins[] = {
  3205. /* CLK, CMD */
  3206. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  3207. };
  3208. static const unsigned int sdhi0_ctrl_mux[] = {
  3209. SD0_CLK_MARK, SD0_CMD_MARK,
  3210. };
  3211. static const unsigned int sdhi0_cd_pins[] = {
  3212. /* CD */
  3213. RCAR_GP_PIN(3, 12),
  3214. };
  3215. static const unsigned int sdhi0_cd_mux[] = {
  3216. SD0_CD_MARK,
  3217. };
  3218. static const unsigned int sdhi0_wp_pins[] = {
  3219. /* WP */
  3220. RCAR_GP_PIN(3, 13),
  3221. };
  3222. static const unsigned int sdhi0_wp_mux[] = {
  3223. SD0_WP_MARK,
  3224. };
  3225. /* - SDHI1 ------------------------------------------------------------------ */
  3226. static const unsigned int sdhi1_data1_pins[] = {
  3227. /* D0 */
  3228. RCAR_GP_PIN(3, 8),
  3229. };
  3230. static const unsigned int sdhi1_data1_mux[] = {
  3231. SD1_DAT0_MARK,
  3232. };
  3233. static const unsigned int sdhi1_data4_pins[] = {
  3234. /* D[0:3] */
  3235. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3236. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3237. };
  3238. static const unsigned int sdhi1_data4_mux[] = {
  3239. SD1_DAT0_MARK, SD1_DAT1_MARK,
  3240. SD1_DAT2_MARK, SD1_DAT3_MARK,
  3241. };
  3242. static const unsigned int sdhi1_ctrl_pins[] = {
  3243. /* CLK, CMD */
  3244. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  3245. };
  3246. static const unsigned int sdhi1_ctrl_mux[] = {
  3247. SD1_CLK_MARK, SD1_CMD_MARK,
  3248. };
  3249. static const unsigned int sdhi1_cd_pins[] = {
  3250. /* CD */
  3251. RCAR_GP_PIN(3, 14),
  3252. };
  3253. static const unsigned int sdhi1_cd_mux[] = {
  3254. SD1_CD_MARK,
  3255. };
  3256. static const unsigned int sdhi1_wp_pins[] = {
  3257. /* WP */
  3258. RCAR_GP_PIN(3, 15),
  3259. };
  3260. static const unsigned int sdhi1_wp_mux[] = {
  3261. SD1_WP_MARK,
  3262. };
  3263. /* - SDHI2 ------------------------------------------------------------------ */
  3264. static const unsigned int sdhi2_data1_pins[] = {
  3265. /* D0 */
  3266. RCAR_GP_PIN(4, 2),
  3267. };
  3268. static const unsigned int sdhi2_data1_mux[] = {
  3269. SD2_DAT0_MARK,
  3270. };
  3271. static const unsigned int sdhi2_data4_pins[] = {
  3272. /* D[0:3] */
  3273. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  3274. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  3275. };
  3276. static const unsigned int sdhi2_data4_mux[] = {
  3277. SD2_DAT0_MARK, SD2_DAT1_MARK,
  3278. SD2_DAT2_MARK, SD2_DAT3_MARK,
  3279. };
  3280. static const unsigned int sdhi2_data8_pins[] = {
  3281. /* D[0:7] */
  3282. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  3283. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  3284. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3285. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3286. };
  3287. static const unsigned int sdhi2_data8_mux[] = {
  3288. SD2_DAT0_MARK, SD2_DAT1_MARK,
  3289. SD2_DAT2_MARK, SD2_DAT3_MARK,
  3290. SD2_DAT4_MARK, SD2_DAT5_MARK,
  3291. SD2_DAT6_MARK, SD2_DAT7_MARK,
  3292. };
  3293. static const unsigned int sdhi2_ctrl_pins[] = {
  3294. /* CLK, CMD */
  3295. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  3296. };
  3297. static const unsigned int sdhi2_ctrl_mux[] = {
  3298. SD2_CLK_MARK, SD2_CMD_MARK,
  3299. };
  3300. static const unsigned int sdhi2_cd_a_pins[] = {
  3301. /* CD */
  3302. RCAR_GP_PIN(4, 13),
  3303. };
  3304. static const unsigned int sdhi2_cd_a_mux[] = {
  3305. SD2_CD_A_MARK,
  3306. };
  3307. static const unsigned int sdhi2_cd_b_pins[] = {
  3308. /* CD */
  3309. RCAR_GP_PIN(5, 10),
  3310. };
  3311. static const unsigned int sdhi2_cd_b_mux[] = {
  3312. SD2_CD_B_MARK,
  3313. };
  3314. static const unsigned int sdhi2_wp_a_pins[] = {
  3315. /* WP */
  3316. RCAR_GP_PIN(4, 14),
  3317. };
  3318. static const unsigned int sdhi2_wp_a_mux[] = {
  3319. SD2_WP_A_MARK,
  3320. };
  3321. static const unsigned int sdhi2_wp_b_pins[] = {
  3322. /* WP */
  3323. RCAR_GP_PIN(5, 11),
  3324. };
  3325. static const unsigned int sdhi2_wp_b_mux[] = {
  3326. SD2_WP_B_MARK,
  3327. };
  3328. static const unsigned int sdhi2_ds_pins[] = {
  3329. /* DS */
  3330. RCAR_GP_PIN(4, 6),
  3331. };
  3332. static const unsigned int sdhi2_ds_mux[] = {
  3333. SD2_DS_MARK,
  3334. };
  3335. /* - SDHI3 ------------------------------------------------------------------ */
  3336. static const unsigned int sdhi3_data1_pins[] = {
  3337. /* D0 */
  3338. RCAR_GP_PIN(4, 9),
  3339. };
  3340. static const unsigned int sdhi3_data1_mux[] = {
  3341. SD3_DAT0_MARK,
  3342. };
  3343. static const unsigned int sdhi3_data4_pins[] = {
  3344. /* D[0:3] */
  3345. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3346. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3347. };
  3348. static const unsigned int sdhi3_data4_mux[] = {
  3349. SD3_DAT0_MARK, SD3_DAT1_MARK,
  3350. SD3_DAT2_MARK, SD3_DAT3_MARK,
  3351. };
  3352. static const unsigned int sdhi3_data8_pins[] = {
  3353. /* D[0:7] */
  3354. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3355. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3356. RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
  3357. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
  3358. };
  3359. static const unsigned int sdhi3_data8_mux[] = {
  3360. SD3_DAT0_MARK, SD3_DAT1_MARK,
  3361. SD3_DAT2_MARK, SD3_DAT3_MARK,
  3362. SD3_DAT4_MARK, SD3_DAT5_MARK,
  3363. SD3_DAT6_MARK, SD3_DAT7_MARK,
  3364. };
  3365. static const unsigned int sdhi3_ctrl_pins[] = {
  3366. /* CLK, CMD */
  3367. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
  3368. };
  3369. static const unsigned int sdhi3_ctrl_mux[] = {
  3370. SD3_CLK_MARK, SD3_CMD_MARK,
  3371. };
  3372. static const unsigned int sdhi3_cd_pins[] = {
  3373. /* CD */
  3374. RCAR_GP_PIN(4, 15),
  3375. };
  3376. static const unsigned int sdhi3_cd_mux[] = {
  3377. SD3_CD_MARK,
  3378. };
  3379. static const unsigned int sdhi3_wp_pins[] = {
  3380. /* WP */
  3381. RCAR_GP_PIN(4, 16),
  3382. };
  3383. static const unsigned int sdhi3_wp_mux[] = {
  3384. SD3_WP_MARK,
  3385. };
  3386. static const unsigned int sdhi3_ds_pins[] = {
  3387. /* DS */
  3388. RCAR_GP_PIN(4, 17),
  3389. };
  3390. static const unsigned int sdhi3_ds_mux[] = {
  3391. SD3_DS_MARK,
  3392. };
  3393. /* - SSI -------------------------------------------------------------------- */
  3394. static const unsigned int ssi0_data_pins[] = {
  3395. /* SDATA */
  3396. RCAR_GP_PIN(6, 2),
  3397. };
  3398. static const unsigned int ssi0_data_mux[] = {
  3399. SSI_SDATA0_MARK,
  3400. };
  3401. static const unsigned int ssi01239_ctrl_pins[] = {
  3402. /* SCK, WS */
  3403. RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
  3404. };
  3405. static const unsigned int ssi01239_ctrl_mux[] = {
  3406. SSI_SCK01239_MARK, SSI_WS01239_MARK,
  3407. };
  3408. static const unsigned int ssi1_data_a_pins[] = {
  3409. /* SDATA */
  3410. RCAR_GP_PIN(6, 3),
  3411. };
  3412. static const unsigned int ssi1_data_a_mux[] = {
  3413. SSI_SDATA1_A_MARK,
  3414. };
  3415. static const unsigned int ssi1_data_b_pins[] = {
  3416. /* SDATA */
  3417. RCAR_GP_PIN(5, 12),
  3418. };
  3419. static const unsigned int ssi1_data_b_mux[] = {
  3420. SSI_SDATA1_B_MARK,
  3421. };
  3422. static const unsigned int ssi1_ctrl_a_pins[] = {
  3423. /* SCK, WS */
  3424. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3425. };
  3426. static const unsigned int ssi1_ctrl_a_mux[] = {
  3427. SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
  3428. };
  3429. static const unsigned int ssi1_ctrl_b_pins[] = {
  3430. /* SCK, WS */
  3431. RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
  3432. };
  3433. static const unsigned int ssi1_ctrl_b_mux[] = {
  3434. SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
  3435. };
  3436. static const unsigned int ssi2_data_a_pins[] = {
  3437. /* SDATA */
  3438. RCAR_GP_PIN(6, 4),
  3439. };
  3440. static const unsigned int ssi2_data_a_mux[] = {
  3441. SSI_SDATA2_A_MARK,
  3442. };
  3443. static const unsigned int ssi2_data_b_pins[] = {
  3444. /* SDATA */
  3445. RCAR_GP_PIN(5, 13),
  3446. };
  3447. static const unsigned int ssi2_data_b_mux[] = {
  3448. SSI_SDATA2_B_MARK,
  3449. };
  3450. static const unsigned int ssi2_ctrl_a_pins[] = {
  3451. /* SCK, WS */
  3452. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
  3453. };
  3454. static const unsigned int ssi2_ctrl_a_mux[] = {
  3455. SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
  3456. };
  3457. static const unsigned int ssi2_ctrl_b_pins[] = {
  3458. /* SCK, WS */
  3459. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3460. };
  3461. static const unsigned int ssi2_ctrl_b_mux[] = {
  3462. SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
  3463. };
  3464. static const unsigned int ssi3_data_pins[] = {
  3465. /* SDATA */
  3466. RCAR_GP_PIN(6, 7),
  3467. };
  3468. static const unsigned int ssi3_data_mux[] = {
  3469. SSI_SDATA3_MARK,
  3470. };
  3471. static const unsigned int ssi349_ctrl_pins[] = {
  3472. /* SCK, WS */
  3473. RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
  3474. };
  3475. static const unsigned int ssi349_ctrl_mux[] = {
  3476. SSI_SCK349_MARK, SSI_WS349_MARK,
  3477. };
  3478. static const unsigned int ssi4_data_pins[] = {
  3479. /* SDATA */
  3480. RCAR_GP_PIN(6, 10),
  3481. };
  3482. static const unsigned int ssi4_data_mux[] = {
  3483. SSI_SDATA4_MARK,
  3484. };
  3485. static const unsigned int ssi4_ctrl_pins[] = {
  3486. /* SCK, WS */
  3487. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  3488. };
  3489. static const unsigned int ssi4_ctrl_mux[] = {
  3490. SSI_SCK4_MARK, SSI_WS4_MARK,
  3491. };
  3492. static const unsigned int ssi5_data_pins[] = {
  3493. /* SDATA */
  3494. RCAR_GP_PIN(6, 13),
  3495. };
  3496. static const unsigned int ssi5_data_mux[] = {
  3497. SSI_SDATA5_MARK,
  3498. };
  3499. static const unsigned int ssi5_ctrl_pins[] = {
  3500. /* SCK, WS */
  3501. RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
  3502. };
  3503. static const unsigned int ssi5_ctrl_mux[] = {
  3504. SSI_SCK5_MARK, SSI_WS5_MARK,
  3505. };
  3506. static const unsigned int ssi6_data_pins[] = {
  3507. /* SDATA */
  3508. RCAR_GP_PIN(6, 16),
  3509. };
  3510. static const unsigned int ssi6_data_mux[] = {
  3511. SSI_SDATA6_MARK,
  3512. };
  3513. static const unsigned int ssi6_ctrl_pins[] = {
  3514. /* SCK, WS */
  3515. RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
  3516. };
  3517. static const unsigned int ssi6_ctrl_mux[] = {
  3518. SSI_SCK6_MARK, SSI_WS6_MARK,
  3519. };
  3520. static const unsigned int ssi7_data_pins[] = {
  3521. /* SDATA */
  3522. RCAR_GP_PIN(6, 19),
  3523. };
  3524. static const unsigned int ssi7_data_mux[] = {
  3525. SSI_SDATA7_MARK,
  3526. };
  3527. static const unsigned int ssi78_ctrl_pins[] = {
  3528. /* SCK, WS */
  3529. RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
  3530. };
  3531. static const unsigned int ssi78_ctrl_mux[] = {
  3532. SSI_SCK78_MARK, SSI_WS78_MARK,
  3533. };
  3534. static const unsigned int ssi8_data_pins[] = {
  3535. /* SDATA */
  3536. RCAR_GP_PIN(6, 20),
  3537. };
  3538. static const unsigned int ssi8_data_mux[] = {
  3539. SSI_SDATA8_MARK,
  3540. };
  3541. static const unsigned int ssi9_data_a_pins[] = {
  3542. /* SDATA */
  3543. RCAR_GP_PIN(6, 21),
  3544. };
  3545. static const unsigned int ssi9_data_a_mux[] = {
  3546. SSI_SDATA9_A_MARK,
  3547. };
  3548. static const unsigned int ssi9_data_b_pins[] = {
  3549. /* SDATA */
  3550. RCAR_GP_PIN(5, 14),
  3551. };
  3552. static const unsigned int ssi9_data_b_mux[] = {
  3553. SSI_SDATA9_B_MARK,
  3554. };
  3555. static const unsigned int ssi9_ctrl_a_pins[] = {
  3556. /* SCK, WS */
  3557. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  3558. };
  3559. static const unsigned int ssi9_ctrl_a_mux[] = {
  3560. SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
  3561. };
  3562. static const unsigned int ssi9_ctrl_b_pins[] = {
  3563. /* SCK, WS */
  3564. RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
  3565. };
  3566. static const unsigned int ssi9_ctrl_b_mux[] = {
  3567. SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
  3568. };
  3569. /* - TMU -------------------------------------------------------------------- */
  3570. static const unsigned int tmu_tclk1_a_pins[] = {
  3571. /* TCLK */
  3572. RCAR_GP_PIN(6, 23),
  3573. };
  3574. static const unsigned int tmu_tclk1_a_mux[] = {
  3575. TCLK1_A_MARK,
  3576. };
  3577. static const unsigned int tmu_tclk1_b_pins[] = {
  3578. /* TCLK */
  3579. RCAR_GP_PIN(5, 19),
  3580. };
  3581. static const unsigned int tmu_tclk1_b_mux[] = {
  3582. TCLK1_B_MARK,
  3583. };
  3584. static const unsigned int tmu_tclk2_a_pins[] = {
  3585. /* TCLK */
  3586. RCAR_GP_PIN(6, 19),
  3587. };
  3588. static const unsigned int tmu_tclk2_a_mux[] = {
  3589. TCLK2_A_MARK,
  3590. };
  3591. static const unsigned int tmu_tclk2_b_pins[] = {
  3592. /* TCLK */
  3593. RCAR_GP_PIN(6, 28),
  3594. };
  3595. static const unsigned int tmu_tclk2_b_mux[] = {
  3596. TCLK2_B_MARK,
  3597. };
  3598. /* - TPU ------------------------------------------------------------------- */
  3599. static const unsigned int tpu_to0_pins[] = {
  3600. /* TPU0TO0 */
  3601. RCAR_GP_PIN(6, 28),
  3602. };
  3603. static const unsigned int tpu_to0_mux[] = {
  3604. TPU0TO0_MARK,
  3605. };
  3606. static const unsigned int tpu_to1_pins[] = {
  3607. /* TPU0TO1 */
  3608. RCAR_GP_PIN(6, 29),
  3609. };
  3610. static const unsigned int tpu_to1_mux[] = {
  3611. TPU0TO1_MARK,
  3612. };
  3613. static const unsigned int tpu_to2_pins[] = {
  3614. /* TPU0TO2 */
  3615. RCAR_GP_PIN(6, 30),
  3616. };
  3617. static const unsigned int tpu_to2_mux[] = {
  3618. TPU0TO2_MARK,
  3619. };
  3620. static const unsigned int tpu_to3_pins[] = {
  3621. /* TPU0TO3 */
  3622. RCAR_GP_PIN(6, 31),
  3623. };
  3624. static const unsigned int tpu_to3_mux[] = {
  3625. TPU0TO3_MARK,
  3626. };
  3627. /* - USB0 ------------------------------------------------------------------- */
  3628. static const unsigned int usb0_pins[] = {
  3629. /* PWEN, OVC */
  3630. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  3631. };
  3632. static const unsigned int usb0_mux[] = {
  3633. USB0_PWEN_MARK, USB0_OVC_MARK,
  3634. };
  3635. /* - USB1 ------------------------------------------------------------------- */
  3636. static const unsigned int usb1_pins[] = {
  3637. /* PWEN, OVC */
  3638. RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
  3639. };
  3640. static const unsigned int usb1_mux[] = {
  3641. USB1_PWEN_MARK, USB1_OVC_MARK,
  3642. };
  3643. /* - USB2 ------------------------------------------------------------------- */
  3644. static const unsigned int usb2_pins[] = {
  3645. /* PWEN, OVC */
  3646. RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
  3647. };
  3648. static const unsigned int usb2_mux[] = {
  3649. USB2_PWEN_MARK, USB2_OVC_MARK,
  3650. };
  3651. /* - USB30 ------------------------------------------------------------------ */
  3652. static const unsigned int usb30_pins[] = {
  3653. /* PWEN, OVC */
  3654. RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
  3655. };
  3656. static const unsigned int usb30_mux[] = {
  3657. USB30_PWEN_MARK, USB30_OVC_MARK,
  3658. };
  3659. /* - USB31 ------------------------------------------------------------------ */
  3660. static const unsigned int usb31_pins[] = {
  3661. /* PWEN, OVC */
  3662. RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
  3663. };
  3664. static const unsigned int usb31_mux[] = {
  3665. USB31_PWEN_MARK, USB31_OVC_MARK,
  3666. };
  3667. static const struct sh_pfc_pin_group pinmux_groups[] = {
  3668. SH_PFC_PIN_GROUP(audio_clk_a_a),
  3669. SH_PFC_PIN_GROUP(audio_clk_a_b),
  3670. SH_PFC_PIN_GROUP(audio_clk_a_c),
  3671. SH_PFC_PIN_GROUP(audio_clk_b_a),
  3672. SH_PFC_PIN_GROUP(audio_clk_b_b),
  3673. SH_PFC_PIN_GROUP(audio_clk_c_a),
  3674. SH_PFC_PIN_GROUP(audio_clk_c_b),
  3675. SH_PFC_PIN_GROUP(audio_clkout_a),
  3676. SH_PFC_PIN_GROUP(audio_clkout_b),
  3677. SH_PFC_PIN_GROUP(audio_clkout_c),
  3678. SH_PFC_PIN_GROUP(audio_clkout_d),
  3679. SH_PFC_PIN_GROUP(audio_clkout1_a),
  3680. SH_PFC_PIN_GROUP(audio_clkout1_b),
  3681. SH_PFC_PIN_GROUP(audio_clkout2_a),
  3682. SH_PFC_PIN_GROUP(audio_clkout2_b),
  3683. SH_PFC_PIN_GROUP(audio_clkout3_a),
  3684. SH_PFC_PIN_GROUP(audio_clkout3_b),
  3685. SH_PFC_PIN_GROUP(avb_link),
  3686. SH_PFC_PIN_GROUP(avb_magic),
  3687. SH_PFC_PIN_GROUP(avb_phy_int),
  3688. SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
  3689. SH_PFC_PIN_GROUP(avb_mdio),
  3690. SH_PFC_PIN_GROUP(avb_mii),
  3691. SH_PFC_PIN_GROUP(avb_avtp_pps),
  3692. SH_PFC_PIN_GROUP(avb_avtp_match_a),
  3693. SH_PFC_PIN_GROUP(avb_avtp_capture_a),
  3694. SH_PFC_PIN_GROUP(avb_avtp_match_b),
  3695. SH_PFC_PIN_GROUP(avb_avtp_capture_b),
  3696. SH_PFC_PIN_GROUP(can0_data_a),
  3697. SH_PFC_PIN_GROUP(can0_data_b),
  3698. SH_PFC_PIN_GROUP(can1_data),
  3699. SH_PFC_PIN_GROUP(can_clk),
  3700. SH_PFC_PIN_GROUP(canfd0_data_a),
  3701. SH_PFC_PIN_GROUP(canfd0_data_b),
  3702. SH_PFC_PIN_GROUP(canfd1_data),
  3703. SH_PFC_PIN_GROUP(drif0_ctrl_a),
  3704. SH_PFC_PIN_GROUP(drif0_data0_a),
  3705. SH_PFC_PIN_GROUP(drif0_data1_a),
  3706. SH_PFC_PIN_GROUP(drif0_ctrl_b),
  3707. SH_PFC_PIN_GROUP(drif0_data0_b),
  3708. SH_PFC_PIN_GROUP(drif0_data1_b),
  3709. SH_PFC_PIN_GROUP(drif0_ctrl_c),
  3710. SH_PFC_PIN_GROUP(drif0_data0_c),
  3711. SH_PFC_PIN_GROUP(drif0_data1_c),
  3712. SH_PFC_PIN_GROUP(drif1_ctrl_a),
  3713. SH_PFC_PIN_GROUP(drif1_data0_a),
  3714. SH_PFC_PIN_GROUP(drif1_data1_a),
  3715. SH_PFC_PIN_GROUP(drif1_ctrl_b),
  3716. SH_PFC_PIN_GROUP(drif1_data0_b),
  3717. SH_PFC_PIN_GROUP(drif1_data1_b),
  3718. SH_PFC_PIN_GROUP(drif1_ctrl_c),
  3719. SH_PFC_PIN_GROUP(drif1_data0_c),
  3720. SH_PFC_PIN_GROUP(drif1_data1_c),
  3721. SH_PFC_PIN_GROUP(drif2_ctrl_a),
  3722. SH_PFC_PIN_GROUP(drif2_data0_a),
  3723. SH_PFC_PIN_GROUP(drif2_data1_a),
  3724. SH_PFC_PIN_GROUP(drif2_ctrl_b),
  3725. SH_PFC_PIN_GROUP(drif2_data0_b),
  3726. SH_PFC_PIN_GROUP(drif2_data1_b),
  3727. SH_PFC_PIN_GROUP(drif3_ctrl_a),
  3728. SH_PFC_PIN_GROUP(drif3_data0_a),
  3729. SH_PFC_PIN_GROUP(drif3_data1_a),
  3730. SH_PFC_PIN_GROUP(drif3_ctrl_b),
  3731. SH_PFC_PIN_GROUP(drif3_data0_b),
  3732. SH_PFC_PIN_GROUP(drif3_data1_b),
  3733. SH_PFC_PIN_GROUP(du_rgb666),
  3734. SH_PFC_PIN_GROUP(du_rgb888),
  3735. SH_PFC_PIN_GROUP(du_clk_out_0),
  3736. SH_PFC_PIN_GROUP(du_clk_out_1),
  3737. SH_PFC_PIN_GROUP(du_sync),
  3738. SH_PFC_PIN_GROUP(du_oddf),
  3739. SH_PFC_PIN_GROUP(du_cde),
  3740. SH_PFC_PIN_GROUP(du_disp),
  3741. SH_PFC_PIN_GROUP(hscif0_data),
  3742. SH_PFC_PIN_GROUP(hscif0_clk),
  3743. SH_PFC_PIN_GROUP(hscif0_ctrl),
  3744. SH_PFC_PIN_GROUP(hscif1_data_a),
  3745. SH_PFC_PIN_GROUP(hscif1_clk_a),
  3746. SH_PFC_PIN_GROUP(hscif1_ctrl_a),
  3747. SH_PFC_PIN_GROUP(hscif1_data_b),
  3748. SH_PFC_PIN_GROUP(hscif1_clk_b),
  3749. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  3750. SH_PFC_PIN_GROUP(hscif2_data_a),
  3751. SH_PFC_PIN_GROUP(hscif2_clk_a),
  3752. SH_PFC_PIN_GROUP(hscif2_ctrl_a),
  3753. SH_PFC_PIN_GROUP(hscif2_data_b),
  3754. SH_PFC_PIN_GROUP(hscif2_clk_b),
  3755. SH_PFC_PIN_GROUP(hscif2_ctrl_b),
  3756. SH_PFC_PIN_GROUP(hscif3_data_a),
  3757. SH_PFC_PIN_GROUP(hscif3_clk),
  3758. SH_PFC_PIN_GROUP(hscif3_ctrl),
  3759. SH_PFC_PIN_GROUP(hscif3_data_b),
  3760. SH_PFC_PIN_GROUP(hscif3_data_c),
  3761. SH_PFC_PIN_GROUP(hscif3_data_d),
  3762. SH_PFC_PIN_GROUP(hscif4_data_a),
  3763. SH_PFC_PIN_GROUP(hscif4_clk),
  3764. SH_PFC_PIN_GROUP(hscif4_ctrl),
  3765. SH_PFC_PIN_GROUP(hscif4_data_b),
  3766. SH_PFC_PIN_GROUP(i2c0),
  3767. SH_PFC_PIN_GROUP(i2c1_a),
  3768. SH_PFC_PIN_GROUP(i2c1_b),
  3769. SH_PFC_PIN_GROUP(i2c2_a),
  3770. SH_PFC_PIN_GROUP(i2c2_b),
  3771. SH_PFC_PIN_GROUP(i2c3),
  3772. SH_PFC_PIN_GROUP(i2c5),
  3773. SH_PFC_PIN_GROUP(i2c6_a),
  3774. SH_PFC_PIN_GROUP(i2c6_b),
  3775. SH_PFC_PIN_GROUP(i2c6_c),
  3776. SH_PFC_PIN_GROUP(intc_ex_irq0),
  3777. SH_PFC_PIN_GROUP(intc_ex_irq1),
  3778. SH_PFC_PIN_GROUP(intc_ex_irq2),
  3779. SH_PFC_PIN_GROUP(intc_ex_irq3),
  3780. SH_PFC_PIN_GROUP(intc_ex_irq4),
  3781. SH_PFC_PIN_GROUP(intc_ex_irq5),
  3782. SH_PFC_PIN_GROUP(msiof0_clk),
  3783. SH_PFC_PIN_GROUP(msiof0_sync),
  3784. SH_PFC_PIN_GROUP(msiof0_ss1),
  3785. SH_PFC_PIN_GROUP(msiof0_ss2),
  3786. SH_PFC_PIN_GROUP(msiof0_txd),
  3787. SH_PFC_PIN_GROUP(msiof0_rxd),
  3788. SH_PFC_PIN_GROUP(msiof1_clk_a),
  3789. SH_PFC_PIN_GROUP(msiof1_sync_a),
  3790. SH_PFC_PIN_GROUP(msiof1_ss1_a),
  3791. SH_PFC_PIN_GROUP(msiof1_ss2_a),
  3792. SH_PFC_PIN_GROUP(msiof1_txd_a),
  3793. SH_PFC_PIN_GROUP(msiof1_rxd_a),
  3794. SH_PFC_PIN_GROUP(msiof1_clk_b),
  3795. SH_PFC_PIN_GROUP(msiof1_sync_b),
  3796. SH_PFC_PIN_GROUP(msiof1_ss1_b),
  3797. SH_PFC_PIN_GROUP(msiof1_ss2_b),
  3798. SH_PFC_PIN_GROUP(msiof1_txd_b),
  3799. SH_PFC_PIN_GROUP(msiof1_rxd_b),
  3800. SH_PFC_PIN_GROUP(msiof1_clk_c),
  3801. SH_PFC_PIN_GROUP(msiof1_sync_c),
  3802. SH_PFC_PIN_GROUP(msiof1_ss1_c),
  3803. SH_PFC_PIN_GROUP(msiof1_ss2_c),
  3804. SH_PFC_PIN_GROUP(msiof1_txd_c),
  3805. SH_PFC_PIN_GROUP(msiof1_rxd_c),
  3806. SH_PFC_PIN_GROUP(msiof1_clk_d),
  3807. SH_PFC_PIN_GROUP(msiof1_sync_d),
  3808. SH_PFC_PIN_GROUP(msiof1_ss1_d),
  3809. SH_PFC_PIN_GROUP(msiof1_ss2_d),
  3810. SH_PFC_PIN_GROUP(msiof1_txd_d),
  3811. SH_PFC_PIN_GROUP(msiof1_rxd_d),
  3812. SH_PFC_PIN_GROUP(msiof1_clk_e),
  3813. SH_PFC_PIN_GROUP(msiof1_sync_e),
  3814. SH_PFC_PIN_GROUP(msiof1_ss1_e),
  3815. SH_PFC_PIN_GROUP(msiof1_ss2_e),
  3816. SH_PFC_PIN_GROUP(msiof1_txd_e),
  3817. SH_PFC_PIN_GROUP(msiof1_rxd_e),
  3818. SH_PFC_PIN_GROUP(msiof1_clk_f),
  3819. SH_PFC_PIN_GROUP(msiof1_sync_f),
  3820. SH_PFC_PIN_GROUP(msiof1_ss1_f),
  3821. SH_PFC_PIN_GROUP(msiof1_ss2_f),
  3822. SH_PFC_PIN_GROUP(msiof1_txd_f),
  3823. SH_PFC_PIN_GROUP(msiof1_rxd_f),
  3824. SH_PFC_PIN_GROUP(msiof1_clk_g),
  3825. SH_PFC_PIN_GROUP(msiof1_sync_g),
  3826. SH_PFC_PIN_GROUP(msiof1_ss1_g),
  3827. SH_PFC_PIN_GROUP(msiof1_ss2_g),
  3828. SH_PFC_PIN_GROUP(msiof1_txd_g),
  3829. SH_PFC_PIN_GROUP(msiof1_rxd_g),
  3830. SH_PFC_PIN_GROUP(msiof2_clk_a),
  3831. SH_PFC_PIN_GROUP(msiof2_sync_a),
  3832. SH_PFC_PIN_GROUP(msiof2_ss1_a),
  3833. SH_PFC_PIN_GROUP(msiof2_ss2_a),
  3834. SH_PFC_PIN_GROUP(msiof2_txd_a),
  3835. SH_PFC_PIN_GROUP(msiof2_rxd_a),
  3836. SH_PFC_PIN_GROUP(msiof2_clk_b),
  3837. SH_PFC_PIN_GROUP(msiof2_sync_b),
  3838. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  3839. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  3840. SH_PFC_PIN_GROUP(msiof2_txd_b),
  3841. SH_PFC_PIN_GROUP(msiof2_rxd_b),
  3842. SH_PFC_PIN_GROUP(msiof2_clk_c),
  3843. SH_PFC_PIN_GROUP(msiof2_sync_c),
  3844. SH_PFC_PIN_GROUP(msiof2_ss1_c),
  3845. SH_PFC_PIN_GROUP(msiof2_ss2_c),
  3846. SH_PFC_PIN_GROUP(msiof2_txd_c),
  3847. SH_PFC_PIN_GROUP(msiof2_rxd_c),
  3848. SH_PFC_PIN_GROUP(msiof2_clk_d),
  3849. SH_PFC_PIN_GROUP(msiof2_sync_d),
  3850. SH_PFC_PIN_GROUP(msiof2_ss1_d),
  3851. SH_PFC_PIN_GROUP(msiof2_ss2_d),
  3852. SH_PFC_PIN_GROUP(msiof2_txd_d),
  3853. SH_PFC_PIN_GROUP(msiof2_rxd_d),
  3854. SH_PFC_PIN_GROUP(msiof3_clk_a),
  3855. SH_PFC_PIN_GROUP(msiof3_sync_a),
  3856. SH_PFC_PIN_GROUP(msiof3_ss1_a),
  3857. SH_PFC_PIN_GROUP(msiof3_ss2_a),
  3858. SH_PFC_PIN_GROUP(msiof3_txd_a),
  3859. SH_PFC_PIN_GROUP(msiof3_rxd_a),
  3860. SH_PFC_PIN_GROUP(msiof3_clk_b),
  3861. SH_PFC_PIN_GROUP(msiof3_sync_b),
  3862. SH_PFC_PIN_GROUP(msiof3_ss1_b),
  3863. SH_PFC_PIN_GROUP(msiof3_ss2_b),
  3864. SH_PFC_PIN_GROUP(msiof3_txd_b),
  3865. SH_PFC_PIN_GROUP(msiof3_rxd_b),
  3866. SH_PFC_PIN_GROUP(msiof3_clk_c),
  3867. SH_PFC_PIN_GROUP(msiof3_sync_c),
  3868. SH_PFC_PIN_GROUP(msiof3_txd_c),
  3869. SH_PFC_PIN_GROUP(msiof3_rxd_c),
  3870. SH_PFC_PIN_GROUP(msiof3_clk_d),
  3871. SH_PFC_PIN_GROUP(msiof3_sync_d),
  3872. SH_PFC_PIN_GROUP(msiof3_ss1_d),
  3873. SH_PFC_PIN_GROUP(msiof3_txd_d),
  3874. SH_PFC_PIN_GROUP(msiof3_rxd_d),
  3875. SH_PFC_PIN_GROUP(pwm0),
  3876. SH_PFC_PIN_GROUP(pwm1_a),
  3877. SH_PFC_PIN_GROUP(pwm1_b),
  3878. SH_PFC_PIN_GROUP(pwm2_a),
  3879. SH_PFC_PIN_GROUP(pwm2_b),
  3880. SH_PFC_PIN_GROUP(pwm3_a),
  3881. SH_PFC_PIN_GROUP(pwm3_b),
  3882. SH_PFC_PIN_GROUP(pwm4_a),
  3883. SH_PFC_PIN_GROUP(pwm4_b),
  3884. SH_PFC_PIN_GROUP(pwm5_a),
  3885. SH_PFC_PIN_GROUP(pwm5_b),
  3886. SH_PFC_PIN_GROUP(pwm6_a),
  3887. SH_PFC_PIN_GROUP(pwm6_b),
  3888. SH_PFC_PIN_GROUP(qspi0_ctrl),
  3889. SH_PFC_PIN_GROUP(qspi0_data2),
  3890. SH_PFC_PIN_GROUP(qspi0_data4),
  3891. SH_PFC_PIN_GROUP(qspi1_ctrl),
  3892. SH_PFC_PIN_GROUP(qspi1_data2),
  3893. SH_PFC_PIN_GROUP(qspi1_data4),
  3894. SH_PFC_PIN_GROUP(sata0_devslp_a),
  3895. SH_PFC_PIN_GROUP(sata0_devslp_b),
  3896. SH_PFC_PIN_GROUP(scif0_data),
  3897. SH_PFC_PIN_GROUP(scif0_clk),
  3898. SH_PFC_PIN_GROUP(scif0_ctrl),
  3899. SH_PFC_PIN_GROUP(scif1_data_a),
  3900. SH_PFC_PIN_GROUP(scif1_clk),
  3901. SH_PFC_PIN_GROUP(scif1_ctrl),
  3902. SH_PFC_PIN_GROUP(scif1_data_b),
  3903. SH_PFC_PIN_GROUP(scif2_data_a),
  3904. SH_PFC_PIN_GROUP(scif2_clk),
  3905. SH_PFC_PIN_GROUP(scif2_data_b),
  3906. SH_PFC_PIN_GROUP(scif3_data_a),
  3907. SH_PFC_PIN_GROUP(scif3_clk),
  3908. SH_PFC_PIN_GROUP(scif3_ctrl),
  3909. SH_PFC_PIN_GROUP(scif3_data_b),
  3910. SH_PFC_PIN_GROUP(scif4_data_a),
  3911. SH_PFC_PIN_GROUP(scif4_clk_a),
  3912. SH_PFC_PIN_GROUP(scif4_ctrl_a),
  3913. SH_PFC_PIN_GROUP(scif4_data_b),
  3914. SH_PFC_PIN_GROUP(scif4_clk_b),
  3915. SH_PFC_PIN_GROUP(scif4_ctrl_b),
  3916. SH_PFC_PIN_GROUP(scif4_data_c),
  3917. SH_PFC_PIN_GROUP(scif4_clk_c),
  3918. SH_PFC_PIN_GROUP(scif4_ctrl_c),
  3919. SH_PFC_PIN_GROUP(scif5_data),
  3920. SH_PFC_PIN_GROUP(scif5_clk),
  3921. SH_PFC_PIN_GROUP(scif_clk_a),
  3922. SH_PFC_PIN_GROUP(scif_clk_b),
  3923. SH_PFC_PIN_GROUP(sdhi0_data1),
  3924. SH_PFC_PIN_GROUP(sdhi0_data4),
  3925. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  3926. SH_PFC_PIN_GROUP(sdhi0_cd),
  3927. SH_PFC_PIN_GROUP(sdhi0_wp),
  3928. SH_PFC_PIN_GROUP(sdhi1_data1),
  3929. SH_PFC_PIN_GROUP(sdhi1_data4),
  3930. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  3931. SH_PFC_PIN_GROUP(sdhi1_cd),
  3932. SH_PFC_PIN_GROUP(sdhi1_wp),
  3933. SH_PFC_PIN_GROUP(sdhi2_data1),
  3934. SH_PFC_PIN_GROUP(sdhi2_data4),
  3935. SH_PFC_PIN_GROUP(sdhi2_data8),
  3936. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  3937. SH_PFC_PIN_GROUP(sdhi2_cd_a),
  3938. SH_PFC_PIN_GROUP(sdhi2_wp_a),
  3939. SH_PFC_PIN_GROUP(sdhi2_cd_b),
  3940. SH_PFC_PIN_GROUP(sdhi2_wp_b),
  3941. SH_PFC_PIN_GROUP(sdhi2_ds),
  3942. SH_PFC_PIN_GROUP(sdhi3_data1),
  3943. SH_PFC_PIN_GROUP(sdhi3_data4),
  3944. SH_PFC_PIN_GROUP(sdhi3_data8),
  3945. SH_PFC_PIN_GROUP(sdhi3_ctrl),
  3946. SH_PFC_PIN_GROUP(sdhi3_cd),
  3947. SH_PFC_PIN_GROUP(sdhi3_wp),
  3948. SH_PFC_PIN_GROUP(sdhi3_ds),
  3949. SH_PFC_PIN_GROUP(ssi0_data),
  3950. SH_PFC_PIN_GROUP(ssi01239_ctrl),
  3951. SH_PFC_PIN_GROUP(ssi1_data_a),
  3952. SH_PFC_PIN_GROUP(ssi1_data_b),
  3953. SH_PFC_PIN_GROUP(ssi1_ctrl_a),
  3954. SH_PFC_PIN_GROUP(ssi1_ctrl_b),
  3955. SH_PFC_PIN_GROUP(ssi2_data_a),
  3956. SH_PFC_PIN_GROUP(ssi2_data_b),
  3957. SH_PFC_PIN_GROUP(ssi2_ctrl_a),
  3958. SH_PFC_PIN_GROUP(ssi2_ctrl_b),
  3959. SH_PFC_PIN_GROUP(ssi3_data),
  3960. SH_PFC_PIN_GROUP(ssi349_ctrl),
  3961. SH_PFC_PIN_GROUP(ssi4_data),
  3962. SH_PFC_PIN_GROUP(ssi4_ctrl),
  3963. SH_PFC_PIN_GROUP(ssi5_data),
  3964. SH_PFC_PIN_GROUP(ssi5_ctrl),
  3965. SH_PFC_PIN_GROUP(ssi6_data),
  3966. SH_PFC_PIN_GROUP(ssi6_ctrl),
  3967. SH_PFC_PIN_GROUP(ssi7_data),
  3968. SH_PFC_PIN_GROUP(ssi78_ctrl),
  3969. SH_PFC_PIN_GROUP(ssi8_data),
  3970. SH_PFC_PIN_GROUP(ssi9_data_a),
  3971. SH_PFC_PIN_GROUP(ssi9_data_b),
  3972. SH_PFC_PIN_GROUP(ssi9_ctrl_a),
  3973. SH_PFC_PIN_GROUP(ssi9_ctrl_b),
  3974. SH_PFC_PIN_GROUP(tmu_tclk1_a),
  3975. SH_PFC_PIN_GROUP(tmu_tclk1_b),
  3976. SH_PFC_PIN_GROUP(tmu_tclk2_a),
  3977. SH_PFC_PIN_GROUP(tmu_tclk2_b),
  3978. SH_PFC_PIN_GROUP(tpu_to0),
  3979. SH_PFC_PIN_GROUP(tpu_to1),
  3980. SH_PFC_PIN_GROUP(tpu_to2),
  3981. SH_PFC_PIN_GROUP(tpu_to3),
  3982. SH_PFC_PIN_GROUP(usb0),
  3983. SH_PFC_PIN_GROUP(usb1),
  3984. SH_PFC_PIN_GROUP(usb2),
  3985. SH_PFC_PIN_GROUP(usb30),
  3986. SH_PFC_PIN_GROUP(usb31),
  3987. };
  3988. static const char * const audio_clk_groups[] = {
  3989. "audio_clk_a_a",
  3990. "audio_clk_a_b",
  3991. "audio_clk_a_c",
  3992. "audio_clk_b_a",
  3993. "audio_clk_b_b",
  3994. "audio_clk_c_a",
  3995. "audio_clk_c_b",
  3996. "audio_clkout_a",
  3997. "audio_clkout_b",
  3998. "audio_clkout_c",
  3999. "audio_clkout_d",
  4000. "audio_clkout1_a",
  4001. "audio_clkout1_b",
  4002. "audio_clkout2_a",
  4003. "audio_clkout2_b",
  4004. "audio_clkout3_a",
  4005. "audio_clkout3_b",
  4006. };
  4007. static const char * const avb_groups[] = {
  4008. "avb_link",
  4009. "avb_magic",
  4010. "avb_phy_int",
  4011. "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
  4012. "avb_mdio",
  4013. "avb_mii",
  4014. "avb_avtp_pps",
  4015. "avb_avtp_match_a",
  4016. "avb_avtp_capture_a",
  4017. "avb_avtp_match_b",
  4018. "avb_avtp_capture_b",
  4019. };
  4020. static const char * const can0_groups[] = {
  4021. "can0_data_a",
  4022. "can0_data_b",
  4023. };
  4024. static const char * const can1_groups[] = {
  4025. "can1_data",
  4026. };
  4027. static const char * const can_clk_groups[] = {
  4028. "can_clk",
  4029. };
  4030. static const char * const canfd0_groups[] = {
  4031. "canfd0_data_a",
  4032. "canfd0_data_b",
  4033. };
  4034. static const char * const canfd1_groups[] = {
  4035. "canfd1_data",
  4036. };
  4037. static const char * const drif0_groups[] = {
  4038. "drif0_ctrl_a",
  4039. "drif0_data0_a",
  4040. "drif0_data1_a",
  4041. "drif0_ctrl_b",
  4042. "drif0_data0_b",
  4043. "drif0_data1_b",
  4044. "drif0_ctrl_c",
  4045. "drif0_data0_c",
  4046. "drif0_data1_c",
  4047. };
  4048. static const char * const drif1_groups[] = {
  4049. "drif1_ctrl_a",
  4050. "drif1_data0_a",
  4051. "drif1_data1_a",
  4052. "drif1_ctrl_b",
  4053. "drif1_data0_b",
  4054. "drif1_data1_b",
  4055. "drif1_ctrl_c",
  4056. "drif1_data0_c",
  4057. "drif1_data1_c",
  4058. };
  4059. static const char * const drif2_groups[] = {
  4060. "drif2_ctrl_a",
  4061. "drif2_data0_a",
  4062. "drif2_data1_a",
  4063. "drif2_ctrl_b",
  4064. "drif2_data0_b",
  4065. "drif2_data1_b",
  4066. };
  4067. static const char * const drif3_groups[] = {
  4068. "drif3_ctrl_a",
  4069. "drif3_data0_a",
  4070. "drif3_data1_a",
  4071. "drif3_ctrl_b",
  4072. "drif3_data0_b",
  4073. "drif3_data1_b",
  4074. };
  4075. static const char * const du_groups[] = {
  4076. "du_rgb666",
  4077. "du_rgb888",
  4078. "du_clk_out_0",
  4079. "du_clk_out_1",
  4080. "du_sync",
  4081. "du_oddf",
  4082. "du_cde",
  4083. "du_disp",
  4084. };
  4085. static const char * const hscif0_groups[] = {
  4086. "hscif0_data",
  4087. "hscif0_clk",
  4088. "hscif0_ctrl",
  4089. };
  4090. static const char * const hscif1_groups[] = {
  4091. "hscif1_data_a",
  4092. "hscif1_clk_a",
  4093. "hscif1_ctrl_a",
  4094. "hscif1_data_b",
  4095. "hscif1_clk_b",
  4096. "hscif1_ctrl_b",
  4097. };
  4098. static const char * const hscif2_groups[] = {
  4099. "hscif2_data_a",
  4100. "hscif2_clk_a",
  4101. "hscif2_ctrl_a",
  4102. "hscif2_data_b",
  4103. "hscif2_clk_b",
  4104. "hscif2_ctrl_b",
  4105. };
  4106. static const char * const hscif3_groups[] = {
  4107. "hscif3_data_a",
  4108. "hscif3_clk",
  4109. "hscif3_ctrl",
  4110. "hscif3_data_b",
  4111. "hscif3_data_c",
  4112. "hscif3_data_d",
  4113. };
  4114. static const char * const hscif4_groups[] = {
  4115. "hscif4_data_a",
  4116. "hscif4_clk",
  4117. "hscif4_ctrl",
  4118. "hscif4_data_b",
  4119. };
  4120. static const char * const i2c0_groups[] = {
  4121. "i2c0",
  4122. };
  4123. static const char * const i2c1_groups[] = {
  4124. "i2c1_a",
  4125. "i2c1_b",
  4126. };
  4127. static const char * const i2c2_groups[] = {
  4128. "i2c2_a",
  4129. "i2c2_b",
  4130. };
  4131. static const char * const i2c3_groups[] = {
  4132. "i2c3",
  4133. };
  4134. static const char * const i2c5_groups[] = {
  4135. "i2c5",
  4136. };
  4137. static const char * const i2c6_groups[] = {
  4138. "i2c6_a",
  4139. "i2c6_b",
  4140. "i2c6_c",
  4141. };
  4142. static const char * const intc_ex_groups[] = {
  4143. "intc_ex_irq0",
  4144. "intc_ex_irq1",
  4145. "intc_ex_irq2",
  4146. "intc_ex_irq3",
  4147. "intc_ex_irq4",
  4148. "intc_ex_irq5",
  4149. };
  4150. static const char * const msiof0_groups[] = {
  4151. "msiof0_clk",
  4152. "msiof0_sync",
  4153. "msiof0_ss1",
  4154. "msiof0_ss2",
  4155. "msiof0_txd",
  4156. "msiof0_rxd",
  4157. };
  4158. static const char * const msiof1_groups[] = {
  4159. "msiof1_clk_a",
  4160. "msiof1_sync_a",
  4161. "msiof1_ss1_a",
  4162. "msiof1_ss2_a",
  4163. "msiof1_txd_a",
  4164. "msiof1_rxd_a",
  4165. "msiof1_clk_b",
  4166. "msiof1_sync_b",
  4167. "msiof1_ss1_b",
  4168. "msiof1_ss2_b",
  4169. "msiof1_txd_b",
  4170. "msiof1_rxd_b",
  4171. "msiof1_clk_c",
  4172. "msiof1_sync_c",
  4173. "msiof1_ss1_c",
  4174. "msiof1_ss2_c",
  4175. "msiof1_txd_c",
  4176. "msiof1_rxd_c",
  4177. "msiof1_clk_d",
  4178. "msiof1_sync_d",
  4179. "msiof1_ss1_d",
  4180. "msiof1_ss2_d",
  4181. "msiof1_txd_d",
  4182. "msiof1_rxd_d",
  4183. "msiof1_clk_e",
  4184. "msiof1_sync_e",
  4185. "msiof1_ss1_e",
  4186. "msiof1_ss2_e",
  4187. "msiof1_txd_e",
  4188. "msiof1_rxd_e",
  4189. "msiof1_clk_f",
  4190. "msiof1_sync_f",
  4191. "msiof1_ss1_f",
  4192. "msiof1_ss2_f",
  4193. "msiof1_txd_f",
  4194. "msiof1_rxd_f",
  4195. "msiof1_clk_g",
  4196. "msiof1_sync_g",
  4197. "msiof1_ss1_g",
  4198. "msiof1_ss2_g",
  4199. "msiof1_txd_g",
  4200. "msiof1_rxd_g",
  4201. };
  4202. static const char * const msiof2_groups[] = {
  4203. "msiof2_clk_a",
  4204. "msiof2_sync_a",
  4205. "msiof2_ss1_a",
  4206. "msiof2_ss2_a",
  4207. "msiof2_txd_a",
  4208. "msiof2_rxd_a",
  4209. "msiof2_clk_b",
  4210. "msiof2_sync_b",
  4211. "msiof2_ss1_b",
  4212. "msiof2_ss2_b",
  4213. "msiof2_txd_b",
  4214. "msiof2_rxd_b",
  4215. "msiof2_clk_c",
  4216. "msiof2_sync_c",
  4217. "msiof2_ss1_c",
  4218. "msiof2_ss2_c",
  4219. "msiof2_txd_c",
  4220. "msiof2_rxd_c",
  4221. "msiof2_clk_d",
  4222. "msiof2_sync_d",
  4223. "msiof2_ss1_d",
  4224. "msiof2_ss2_d",
  4225. "msiof2_txd_d",
  4226. "msiof2_rxd_d",
  4227. };
  4228. static const char * const msiof3_groups[] = {
  4229. "msiof3_clk_a",
  4230. "msiof3_sync_a",
  4231. "msiof3_ss1_a",
  4232. "msiof3_ss2_a",
  4233. "msiof3_txd_a",
  4234. "msiof3_rxd_a",
  4235. "msiof3_clk_b",
  4236. "msiof3_sync_b",
  4237. "msiof3_ss1_b",
  4238. "msiof3_ss2_b",
  4239. "msiof3_txd_b",
  4240. "msiof3_rxd_b",
  4241. "msiof3_clk_c",
  4242. "msiof3_sync_c",
  4243. "msiof3_txd_c",
  4244. "msiof3_rxd_c",
  4245. "msiof3_clk_d",
  4246. "msiof3_sync_d",
  4247. "msiof3_ss1_d",
  4248. "msiof3_txd_d",
  4249. "msiof3_rxd_d",
  4250. };
  4251. static const char * const pwm0_groups[] = {
  4252. "pwm0",
  4253. };
  4254. static const char * const pwm1_groups[] = {
  4255. "pwm1_a",
  4256. "pwm1_b",
  4257. };
  4258. static const char * const pwm2_groups[] = {
  4259. "pwm2_a",
  4260. "pwm2_b",
  4261. };
  4262. static const char * const pwm3_groups[] = {
  4263. "pwm3_a",
  4264. "pwm3_b",
  4265. };
  4266. static const char * const pwm4_groups[] = {
  4267. "pwm4_a",
  4268. "pwm4_b",
  4269. };
  4270. static const char * const pwm5_groups[] = {
  4271. "pwm5_a",
  4272. "pwm5_b",
  4273. };
  4274. static const char * const pwm6_groups[] = {
  4275. "pwm6_a",
  4276. "pwm6_b",
  4277. };
  4278. static const char * const qspi0_groups[] = {
  4279. "qspi0_ctrl",
  4280. "qspi0_data2",
  4281. "qspi0_data4",
  4282. };
  4283. static const char * const qspi1_groups[] = {
  4284. "qspi1_ctrl",
  4285. "qspi1_data2",
  4286. "qspi1_data4",
  4287. };
  4288. static const char * const sata0_groups[] = {
  4289. "sata0_devslp_a",
  4290. "sata0_devslp_b",
  4291. };
  4292. static const char * const scif0_groups[] = {
  4293. "scif0_data",
  4294. "scif0_clk",
  4295. "scif0_ctrl",
  4296. };
  4297. static const char * const scif1_groups[] = {
  4298. "scif1_data_a",
  4299. "scif1_clk",
  4300. "scif1_ctrl",
  4301. "scif1_data_b",
  4302. };
  4303. static const char * const scif2_groups[] = {
  4304. "scif2_data_a",
  4305. "scif2_clk",
  4306. "scif2_data_b",
  4307. };
  4308. static const char * const scif3_groups[] = {
  4309. "scif3_data_a",
  4310. "scif3_clk",
  4311. "scif3_ctrl",
  4312. "scif3_data_b",
  4313. };
  4314. static const char * const scif4_groups[] = {
  4315. "scif4_data_a",
  4316. "scif4_clk_a",
  4317. "scif4_ctrl_a",
  4318. "scif4_data_b",
  4319. "scif4_clk_b",
  4320. "scif4_ctrl_b",
  4321. "scif4_data_c",
  4322. "scif4_clk_c",
  4323. "scif4_ctrl_c",
  4324. };
  4325. static const char * const scif5_groups[] = {
  4326. "scif5_data",
  4327. "scif5_clk",
  4328. };
  4329. static const char * const scif_clk_groups[] = {
  4330. "scif_clk_a",
  4331. "scif_clk_b",
  4332. };
  4333. static const char * const sdhi0_groups[] = {
  4334. "sdhi0_data1",
  4335. "sdhi0_data4",
  4336. "sdhi0_ctrl",
  4337. "sdhi0_cd",
  4338. "sdhi0_wp",
  4339. };
  4340. static const char * const sdhi1_groups[] = {
  4341. "sdhi1_data1",
  4342. "sdhi1_data4",
  4343. "sdhi1_ctrl",
  4344. "sdhi1_cd",
  4345. "sdhi1_wp",
  4346. };
  4347. static const char * const sdhi2_groups[] = {
  4348. "sdhi2_data1",
  4349. "sdhi2_data4",
  4350. "sdhi2_data8",
  4351. "sdhi2_ctrl",
  4352. "sdhi2_cd_a",
  4353. "sdhi2_wp_a",
  4354. "sdhi2_cd_b",
  4355. "sdhi2_wp_b",
  4356. "sdhi2_ds",
  4357. };
  4358. static const char * const sdhi3_groups[] = {
  4359. "sdhi3_data1",
  4360. "sdhi3_data4",
  4361. "sdhi3_data8",
  4362. "sdhi3_ctrl",
  4363. "sdhi3_cd",
  4364. "sdhi3_wp",
  4365. "sdhi3_ds",
  4366. };
  4367. static const char * const ssi_groups[] = {
  4368. "ssi0_data",
  4369. "ssi01239_ctrl",
  4370. "ssi1_data_a",
  4371. "ssi1_data_b",
  4372. "ssi1_ctrl_a",
  4373. "ssi1_ctrl_b",
  4374. "ssi2_data_a",
  4375. "ssi2_data_b",
  4376. "ssi2_ctrl_a",
  4377. "ssi2_ctrl_b",
  4378. "ssi3_data",
  4379. "ssi349_ctrl",
  4380. "ssi4_data",
  4381. "ssi4_ctrl",
  4382. "ssi5_data",
  4383. "ssi5_ctrl",
  4384. "ssi6_data",
  4385. "ssi6_ctrl",
  4386. "ssi7_data",
  4387. "ssi78_ctrl",
  4388. "ssi8_data",
  4389. "ssi9_data_a",
  4390. "ssi9_data_b",
  4391. "ssi9_ctrl_a",
  4392. "ssi9_ctrl_b",
  4393. };
  4394. static const char * const tmu_groups[] = {
  4395. "tmu_tclk1_a",
  4396. "tmu_tclk1_b",
  4397. "tmu_tclk2_a",
  4398. "tmu_tclk2_b",
  4399. };
  4400. static const char * const tpu_groups[] = {
  4401. "tpu_to0",
  4402. "tpu_to1",
  4403. "tpu_to2",
  4404. "tpu_to3",
  4405. };
  4406. static const char * const usb0_groups[] = {
  4407. "usb0",
  4408. };
  4409. static const char * const usb1_groups[] = {
  4410. "usb1",
  4411. };
  4412. static const char * const usb2_groups[] = {
  4413. "usb2",
  4414. };
  4415. static const char * const usb30_groups[] = {
  4416. "usb30",
  4417. };
  4418. static const char * const usb31_groups[] = {
  4419. "usb31",
  4420. };
  4421. static const struct sh_pfc_function pinmux_functions[] = {
  4422. SH_PFC_FUNCTION(audio_clk),
  4423. SH_PFC_FUNCTION(avb),
  4424. SH_PFC_FUNCTION(can0),
  4425. SH_PFC_FUNCTION(can1),
  4426. SH_PFC_FUNCTION(can_clk),
  4427. SH_PFC_FUNCTION(canfd0),
  4428. SH_PFC_FUNCTION(canfd1),
  4429. SH_PFC_FUNCTION(drif0),
  4430. SH_PFC_FUNCTION(drif1),
  4431. SH_PFC_FUNCTION(drif2),
  4432. SH_PFC_FUNCTION(drif3),
  4433. SH_PFC_FUNCTION(du),
  4434. SH_PFC_FUNCTION(hscif0),
  4435. SH_PFC_FUNCTION(hscif1),
  4436. SH_PFC_FUNCTION(hscif2),
  4437. SH_PFC_FUNCTION(hscif3),
  4438. SH_PFC_FUNCTION(hscif4),
  4439. SH_PFC_FUNCTION(i2c0),
  4440. SH_PFC_FUNCTION(i2c1),
  4441. SH_PFC_FUNCTION(i2c2),
  4442. SH_PFC_FUNCTION(i2c3),
  4443. SH_PFC_FUNCTION(i2c5),
  4444. SH_PFC_FUNCTION(i2c6),
  4445. SH_PFC_FUNCTION(intc_ex),
  4446. SH_PFC_FUNCTION(msiof0),
  4447. SH_PFC_FUNCTION(msiof1),
  4448. SH_PFC_FUNCTION(msiof2),
  4449. SH_PFC_FUNCTION(msiof3),
  4450. SH_PFC_FUNCTION(pwm0),
  4451. SH_PFC_FUNCTION(pwm1),
  4452. SH_PFC_FUNCTION(pwm2),
  4453. SH_PFC_FUNCTION(pwm3),
  4454. SH_PFC_FUNCTION(pwm4),
  4455. SH_PFC_FUNCTION(pwm5),
  4456. SH_PFC_FUNCTION(pwm6),
  4457. SH_PFC_FUNCTION(qspi0),
  4458. SH_PFC_FUNCTION(qspi1),
  4459. SH_PFC_FUNCTION(sata0),
  4460. SH_PFC_FUNCTION(scif0),
  4461. SH_PFC_FUNCTION(scif1),
  4462. SH_PFC_FUNCTION(scif2),
  4463. SH_PFC_FUNCTION(scif3),
  4464. SH_PFC_FUNCTION(scif4),
  4465. SH_PFC_FUNCTION(scif5),
  4466. SH_PFC_FUNCTION(scif_clk),
  4467. SH_PFC_FUNCTION(sdhi0),
  4468. SH_PFC_FUNCTION(sdhi1),
  4469. SH_PFC_FUNCTION(sdhi2),
  4470. SH_PFC_FUNCTION(sdhi3),
  4471. SH_PFC_FUNCTION(ssi),
  4472. SH_PFC_FUNCTION(tmu),
  4473. SH_PFC_FUNCTION(tpu),
  4474. SH_PFC_FUNCTION(usb0),
  4475. SH_PFC_FUNCTION(usb1),
  4476. SH_PFC_FUNCTION(usb2),
  4477. SH_PFC_FUNCTION(usb30),
  4478. SH_PFC_FUNCTION(usb31),
  4479. };
  4480. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  4481. #define F_(x, y) FN_##y
  4482. #define FM(x) FN_##x
  4483. { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
  4484. 0, 0,
  4485. 0, 0,
  4486. 0, 0,
  4487. 0, 0,
  4488. 0, 0,
  4489. 0, 0,
  4490. 0, 0,
  4491. 0, 0,
  4492. 0, 0,
  4493. 0, 0,
  4494. 0, 0,
  4495. 0, 0,
  4496. 0, 0,
  4497. 0, 0,
  4498. 0, 0,
  4499. 0, 0,
  4500. GP_0_15_FN, GPSR0_15,
  4501. GP_0_14_FN, GPSR0_14,
  4502. GP_0_13_FN, GPSR0_13,
  4503. GP_0_12_FN, GPSR0_12,
  4504. GP_0_11_FN, GPSR0_11,
  4505. GP_0_10_FN, GPSR0_10,
  4506. GP_0_9_FN, GPSR0_9,
  4507. GP_0_8_FN, GPSR0_8,
  4508. GP_0_7_FN, GPSR0_7,
  4509. GP_0_6_FN, GPSR0_6,
  4510. GP_0_5_FN, GPSR0_5,
  4511. GP_0_4_FN, GPSR0_4,
  4512. GP_0_3_FN, GPSR0_3,
  4513. GP_0_2_FN, GPSR0_2,
  4514. GP_0_1_FN, GPSR0_1,
  4515. GP_0_0_FN, GPSR0_0, ))
  4516. },
  4517. { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
  4518. 0, 0,
  4519. 0, 0,
  4520. 0, 0,
  4521. 0, 0,
  4522. GP_1_27_FN, GPSR1_27,
  4523. GP_1_26_FN, GPSR1_26,
  4524. GP_1_25_FN, GPSR1_25,
  4525. GP_1_24_FN, GPSR1_24,
  4526. GP_1_23_FN, GPSR1_23,
  4527. GP_1_22_FN, GPSR1_22,
  4528. GP_1_21_FN, GPSR1_21,
  4529. GP_1_20_FN, GPSR1_20,
  4530. GP_1_19_FN, GPSR1_19,
  4531. GP_1_18_FN, GPSR1_18,
  4532. GP_1_17_FN, GPSR1_17,
  4533. GP_1_16_FN, GPSR1_16,
  4534. GP_1_15_FN, GPSR1_15,
  4535. GP_1_14_FN, GPSR1_14,
  4536. GP_1_13_FN, GPSR1_13,
  4537. GP_1_12_FN, GPSR1_12,
  4538. GP_1_11_FN, GPSR1_11,
  4539. GP_1_10_FN, GPSR1_10,
  4540. GP_1_9_FN, GPSR1_9,
  4541. GP_1_8_FN, GPSR1_8,
  4542. GP_1_7_FN, GPSR1_7,
  4543. GP_1_6_FN, GPSR1_6,
  4544. GP_1_5_FN, GPSR1_5,
  4545. GP_1_4_FN, GPSR1_4,
  4546. GP_1_3_FN, GPSR1_3,
  4547. GP_1_2_FN, GPSR1_2,
  4548. GP_1_1_FN, GPSR1_1,
  4549. GP_1_0_FN, GPSR1_0, ))
  4550. },
  4551. { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
  4552. 0, 0,
  4553. 0, 0,
  4554. 0, 0,
  4555. 0, 0,
  4556. 0, 0,
  4557. 0, 0,
  4558. 0, 0,
  4559. 0, 0,
  4560. 0, 0,
  4561. 0, 0,
  4562. 0, 0,
  4563. 0, 0,
  4564. 0, 0,
  4565. 0, 0,
  4566. 0, 0,
  4567. 0, 0,
  4568. 0, 0,
  4569. GP_2_14_FN, GPSR2_14,
  4570. GP_2_13_FN, GPSR2_13,
  4571. GP_2_12_FN, GPSR2_12,
  4572. GP_2_11_FN, GPSR2_11,
  4573. GP_2_10_FN, GPSR2_10,
  4574. GP_2_9_FN, GPSR2_9,
  4575. GP_2_8_FN, GPSR2_8,
  4576. GP_2_7_FN, GPSR2_7,
  4577. GP_2_6_FN, GPSR2_6,
  4578. GP_2_5_FN, GPSR2_5,
  4579. GP_2_4_FN, GPSR2_4,
  4580. GP_2_3_FN, GPSR2_3,
  4581. GP_2_2_FN, GPSR2_2,
  4582. GP_2_1_FN, GPSR2_1,
  4583. GP_2_0_FN, GPSR2_0, ))
  4584. },
  4585. { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
  4586. 0, 0,
  4587. 0, 0,
  4588. 0, 0,
  4589. 0, 0,
  4590. 0, 0,
  4591. 0, 0,
  4592. 0, 0,
  4593. 0, 0,
  4594. 0, 0,
  4595. 0, 0,
  4596. 0, 0,
  4597. 0, 0,
  4598. 0, 0,
  4599. 0, 0,
  4600. 0, 0,
  4601. 0, 0,
  4602. GP_3_15_FN, GPSR3_15,
  4603. GP_3_14_FN, GPSR3_14,
  4604. GP_3_13_FN, GPSR3_13,
  4605. GP_3_12_FN, GPSR3_12,
  4606. GP_3_11_FN, GPSR3_11,
  4607. GP_3_10_FN, GPSR3_10,
  4608. GP_3_9_FN, GPSR3_9,
  4609. GP_3_8_FN, GPSR3_8,
  4610. GP_3_7_FN, GPSR3_7,
  4611. GP_3_6_FN, GPSR3_6,
  4612. GP_3_5_FN, GPSR3_5,
  4613. GP_3_4_FN, GPSR3_4,
  4614. GP_3_3_FN, GPSR3_3,
  4615. GP_3_2_FN, GPSR3_2,
  4616. GP_3_1_FN, GPSR3_1,
  4617. GP_3_0_FN, GPSR3_0, ))
  4618. },
  4619. { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
  4620. 0, 0,
  4621. 0, 0,
  4622. 0, 0,
  4623. 0, 0,
  4624. 0, 0,
  4625. 0, 0,
  4626. 0, 0,
  4627. 0, 0,
  4628. 0, 0,
  4629. 0, 0,
  4630. 0, 0,
  4631. 0, 0,
  4632. 0, 0,
  4633. 0, 0,
  4634. GP_4_17_FN, GPSR4_17,
  4635. GP_4_16_FN, GPSR4_16,
  4636. GP_4_15_FN, GPSR4_15,
  4637. GP_4_14_FN, GPSR4_14,
  4638. GP_4_13_FN, GPSR4_13,
  4639. GP_4_12_FN, GPSR4_12,
  4640. GP_4_11_FN, GPSR4_11,
  4641. GP_4_10_FN, GPSR4_10,
  4642. GP_4_9_FN, GPSR4_9,
  4643. GP_4_8_FN, GPSR4_8,
  4644. GP_4_7_FN, GPSR4_7,
  4645. GP_4_6_FN, GPSR4_6,
  4646. GP_4_5_FN, GPSR4_5,
  4647. GP_4_4_FN, GPSR4_4,
  4648. GP_4_3_FN, GPSR4_3,
  4649. GP_4_2_FN, GPSR4_2,
  4650. GP_4_1_FN, GPSR4_1,
  4651. GP_4_0_FN, GPSR4_0, ))
  4652. },
  4653. { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
  4654. 0, 0,
  4655. 0, 0,
  4656. 0, 0,
  4657. 0, 0,
  4658. 0, 0,
  4659. 0, 0,
  4660. GP_5_25_FN, GPSR5_25,
  4661. GP_5_24_FN, GPSR5_24,
  4662. GP_5_23_FN, GPSR5_23,
  4663. GP_5_22_FN, GPSR5_22,
  4664. GP_5_21_FN, GPSR5_21,
  4665. GP_5_20_FN, GPSR5_20,
  4666. GP_5_19_FN, GPSR5_19,
  4667. GP_5_18_FN, GPSR5_18,
  4668. GP_5_17_FN, GPSR5_17,
  4669. GP_5_16_FN, GPSR5_16,
  4670. GP_5_15_FN, GPSR5_15,
  4671. GP_5_14_FN, GPSR5_14,
  4672. GP_5_13_FN, GPSR5_13,
  4673. GP_5_12_FN, GPSR5_12,
  4674. GP_5_11_FN, GPSR5_11,
  4675. GP_5_10_FN, GPSR5_10,
  4676. GP_5_9_FN, GPSR5_9,
  4677. GP_5_8_FN, GPSR5_8,
  4678. GP_5_7_FN, GPSR5_7,
  4679. GP_5_6_FN, GPSR5_6,
  4680. GP_5_5_FN, GPSR5_5,
  4681. GP_5_4_FN, GPSR5_4,
  4682. GP_5_3_FN, GPSR5_3,
  4683. GP_5_2_FN, GPSR5_2,
  4684. GP_5_1_FN, GPSR5_1,
  4685. GP_5_0_FN, GPSR5_0, ))
  4686. },
  4687. { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
  4688. GP_6_31_FN, GPSR6_31,
  4689. GP_6_30_FN, GPSR6_30,
  4690. GP_6_29_FN, GPSR6_29,
  4691. GP_6_28_FN, GPSR6_28,
  4692. GP_6_27_FN, GPSR6_27,
  4693. GP_6_26_FN, GPSR6_26,
  4694. GP_6_25_FN, GPSR6_25,
  4695. GP_6_24_FN, GPSR6_24,
  4696. GP_6_23_FN, GPSR6_23,
  4697. GP_6_22_FN, GPSR6_22,
  4698. GP_6_21_FN, GPSR6_21,
  4699. GP_6_20_FN, GPSR6_20,
  4700. GP_6_19_FN, GPSR6_19,
  4701. GP_6_18_FN, GPSR6_18,
  4702. GP_6_17_FN, GPSR6_17,
  4703. GP_6_16_FN, GPSR6_16,
  4704. GP_6_15_FN, GPSR6_15,
  4705. GP_6_14_FN, GPSR6_14,
  4706. GP_6_13_FN, GPSR6_13,
  4707. GP_6_12_FN, GPSR6_12,
  4708. GP_6_11_FN, GPSR6_11,
  4709. GP_6_10_FN, GPSR6_10,
  4710. GP_6_9_FN, GPSR6_9,
  4711. GP_6_8_FN, GPSR6_8,
  4712. GP_6_7_FN, GPSR6_7,
  4713. GP_6_6_FN, GPSR6_6,
  4714. GP_6_5_FN, GPSR6_5,
  4715. GP_6_4_FN, GPSR6_4,
  4716. GP_6_3_FN, GPSR6_3,
  4717. GP_6_2_FN, GPSR6_2,
  4718. GP_6_1_FN, GPSR6_1,
  4719. GP_6_0_FN, GPSR6_0, ))
  4720. },
  4721. { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
  4722. 0, 0,
  4723. 0, 0,
  4724. 0, 0,
  4725. 0, 0,
  4726. 0, 0,
  4727. 0, 0,
  4728. 0, 0,
  4729. 0, 0,
  4730. 0, 0,
  4731. 0, 0,
  4732. 0, 0,
  4733. 0, 0,
  4734. 0, 0,
  4735. 0, 0,
  4736. 0, 0,
  4737. 0, 0,
  4738. 0, 0,
  4739. 0, 0,
  4740. 0, 0,
  4741. 0, 0,
  4742. 0, 0,
  4743. 0, 0,
  4744. 0, 0,
  4745. 0, 0,
  4746. 0, 0,
  4747. 0, 0,
  4748. 0, 0,
  4749. 0, 0,
  4750. GP_7_3_FN, GPSR7_3,
  4751. GP_7_2_FN, GPSR7_2,
  4752. GP_7_1_FN, GPSR7_1,
  4753. GP_7_0_FN, GPSR7_0, ))
  4754. },
  4755. #undef F_
  4756. #undef FM
  4757. #define F_(x, y) x,
  4758. #define FM(x) FN_##x,
  4759. { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
  4760. IP0_31_28
  4761. IP0_27_24
  4762. IP0_23_20
  4763. IP0_19_16
  4764. IP0_15_12
  4765. IP0_11_8
  4766. IP0_7_4
  4767. IP0_3_0 ))
  4768. },
  4769. { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
  4770. IP1_31_28
  4771. IP1_27_24
  4772. IP1_23_20
  4773. IP1_19_16
  4774. IP1_15_12
  4775. IP1_11_8
  4776. IP1_7_4
  4777. IP1_3_0 ))
  4778. },
  4779. { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
  4780. IP2_31_28
  4781. IP2_27_24
  4782. IP2_23_20
  4783. IP2_19_16
  4784. IP2_15_12
  4785. IP2_11_8
  4786. IP2_7_4
  4787. IP2_3_0 ))
  4788. },
  4789. { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
  4790. IP3_31_28
  4791. IP3_27_24
  4792. IP3_23_20
  4793. IP3_19_16
  4794. IP3_15_12
  4795. IP3_11_8
  4796. IP3_7_4
  4797. IP3_3_0 ))
  4798. },
  4799. { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
  4800. IP4_31_28
  4801. IP4_27_24
  4802. IP4_23_20
  4803. IP4_19_16
  4804. IP4_15_12
  4805. IP4_11_8
  4806. IP4_7_4
  4807. IP4_3_0 ))
  4808. },
  4809. { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
  4810. IP5_31_28
  4811. IP5_27_24
  4812. IP5_23_20
  4813. IP5_19_16
  4814. IP5_15_12
  4815. IP5_11_8
  4816. IP5_7_4
  4817. IP5_3_0 ))
  4818. },
  4819. { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
  4820. IP6_31_28
  4821. IP6_27_24
  4822. IP6_23_20
  4823. IP6_19_16
  4824. IP6_15_12
  4825. IP6_11_8
  4826. IP6_7_4
  4827. IP6_3_0 ))
  4828. },
  4829. { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
  4830. IP7_31_28
  4831. IP7_27_24
  4832. IP7_23_20
  4833. IP7_19_16
  4834. IP7_15_12
  4835. IP7_11_8
  4836. IP7_7_4
  4837. IP7_3_0 ))
  4838. },
  4839. { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
  4840. IP8_31_28
  4841. IP8_27_24
  4842. IP8_23_20
  4843. IP8_19_16
  4844. IP8_15_12
  4845. IP8_11_8
  4846. IP8_7_4
  4847. IP8_3_0 ))
  4848. },
  4849. { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
  4850. IP9_31_28
  4851. IP9_27_24
  4852. IP9_23_20
  4853. IP9_19_16
  4854. IP9_15_12
  4855. IP9_11_8
  4856. IP9_7_4
  4857. IP9_3_0 ))
  4858. },
  4859. { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
  4860. IP10_31_28
  4861. IP10_27_24
  4862. IP10_23_20
  4863. IP10_19_16
  4864. IP10_15_12
  4865. IP10_11_8
  4866. IP10_7_4
  4867. IP10_3_0 ))
  4868. },
  4869. { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
  4870. IP11_31_28
  4871. IP11_27_24
  4872. IP11_23_20
  4873. IP11_19_16
  4874. IP11_15_12
  4875. IP11_11_8
  4876. IP11_7_4
  4877. IP11_3_0 ))
  4878. },
  4879. { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
  4880. IP12_31_28
  4881. IP12_27_24
  4882. IP12_23_20
  4883. IP12_19_16
  4884. IP12_15_12
  4885. IP12_11_8
  4886. IP12_7_4
  4887. IP12_3_0 ))
  4888. },
  4889. { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
  4890. IP13_31_28
  4891. IP13_27_24
  4892. IP13_23_20
  4893. IP13_19_16
  4894. IP13_15_12
  4895. IP13_11_8
  4896. IP13_7_4
  4897. IP13_3_0 ))
  4898. },
  4899. { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
  4900. IP14_31_28
  4901. IP14_27_24
  4902. IP14_23_20
  4903. IP14_19_16
  4904. IP14_15_12
  4905. IP14_11_8
  4906. IP14_7_4
  4907. IP14_3_0 ))
  4908. },
  4909. { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
  4910. IP15_31_28
  4911. IP15_27_24
  4912. IP15_23_20
  4913. IP15_19_16
  4914. IP15_15_12
  4915. IP15_11_8
  4916. IP15_7_4
  4917. IP15_3_0 ))
  4918. },
  4919. { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
  4920. IP16_31_28
  4921. IP16_27_24
  4922. IP16_23_20
  4923. IP16_19_16
  4924. IP16_15_12
  4925. IP16_11_8
  4926. IP16_7_4
  4927. IP16_3_0 ))
  4928. },
  4929. { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
  4930. /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4931. /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4932. /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4933. /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4934. /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4935. /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4936. IP17_7_4
  4937. IP17_3_0 ))
  4938. },
  4939. #undef F_
  4940. #undef FM
  4941. #define F_(x, y) x,
  4942. #define FM(x) FN_##x,
  4943. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
  4944. GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
  4945. 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
  4946. GROUP(
  4947. 0, 0, /* RESERVED 31 */
  4948. MOD_SEL0_30_29
  4949. MOD_SEL0_28_27
  4950. MOD_SEL0_26_25_24
  4951. MOD_SEL0_23
  4952. MOD_SEL0_22
  4953. MOD_SEL0_21_20
  4954. MOD_SEL0_19
  4955. MOD_SEL0_18
  4956. MOD_SEL0_17
  4957. MOD_SEL0_16_15
  4958. MOD_SEL0_14
  4959. MOD_SEL0_13
  4960. MOD_SEL0_12
  4961. MOD_SEL0_11
  4962. MOD_SEL0_10
  4963. MOD_SEL0_9
  4964. MOD_SEL0_8
  4965. MOD_SEL0_7_6
  4966. MOD_SEL0_5_4
  4967. MOD_SEL0_3
  4968. MOD_SEL0_2_1
  4969. 0, 0, /* RESERVED 0 */ ))
  4970. },
  4971. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
  4972. GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
  4973. 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
  4974. GROUP(
  4975. MOD_SEL1_31_30
  4976. MOD_SEL1_29_28_27
  4977. MOD_SEL1_26
  4978. MOD_SEL1_25_24
  4979. MOD_SEL1_23_22_21
  4980. MOD_SEL1_20
  4981. MOD_SEL1_19
  4982. MOD_SEL1_18_17
  4983. MOD_SEL1_16
  4984. MOD_SEL1_15_14
  4985. MOD_SEL1_13
  4986. MOD_SEL1_12
  4987. MOD_SEL1_11
  4988. MOD_SEL1_10
  4989. MOD_SEL1_9
  4990. 0, 0, 0, 0, /* RESERVED 8, 7 */
  4991. MOD_SEL1_6
  4992. MOD_SEL1_5
  4993. MOD_SEL1_4
  4994. MOD_SEL1_3
  4995. MOD_SEL1_2
  4996. MOD_SEL1_1
  4997. MOD_SEL1_0 ))
  4998. },
  4999. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
  5000. GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
  5001. GROUP(
  5002. MOD_SEL2_31
  5003. MOD_SEL2_30
  5004. MOD_SEL2_29
  5005. /* RESERVED 28 */
  5006. 0, 0,
  5007. /* RESERVED 27, 26, 25, 24 */
  5008. 0, 0, 0, 0, 0, 0, 0, 0,
  5009. 0, 0, 0, 0, 0, 0, 0, 0,
  5010. /* RESERVED 23, 22, 21, 20 */
  5011. 0, 0, 0, 0, 0, 0, 0, 0,
  5012. 0, 0, 0, 0, 0, 0, 0, 0,
  5013. /* RESERVED 19, 18, 17, 16 */
  5014. 0, 0, 0, 0, 0, 0, 0, 0,
  5015. 0, 0, 0, 0, 0, 0, 0, 0,
  5016. /* RESERVED 15, 14, 13, 12 */
  5017. 0, 0, 0, 0, 0, 0, 0, 0,
  5018. 0, 0, 0, 0, 0, 0, 0, 0,
  5019. /* RESERVED 11, 10, 9, 8 */
  5020. 0, 0, 0, 0, 0, 0, 0, 0,
  5021. 0, 0, 0, 0, 0, 0, 0, 0,
  5022. /* RESERVED 7, 6, 5, 4 */
  5023. 0, 0, 0, 0, 0, 0, 0, 0,
  5024. 0, 0, 0, 0, 0, 0, 0, 0,
  5025. /* RESERVED 3 */
  5026. 0, 0,
  5027. /* RESERVED 2, 1 */
  5028. 0, 0, 0, 0,
  5029. MOD_SEL2_0 ))
  5030. },
  5031. { },
  5032. };
  5033. static const struct pinmux_drive_reg pinmux_drive_regs[] = {
  5034. { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
  5035. { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
  5036. { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
  5037. { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
  5038. { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
  5039. { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
  5040. { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
  5041. { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
  5042. { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
  5043. } },
  5044. { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
  5045. { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
  5046. { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
  5047. { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
  5048. { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
  5049. { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
  5050. { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
  5051. { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
  5052. { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
  5053. } },
  5054. { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
  5055. { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
  5056. { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
  5057. { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
  5058. { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
  5059. { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
  5060. { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
  5061. { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
  5062. { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
  5063. } },
  5064. { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
  5065. { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
  5066. { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
  5067. { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
  5068. { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
  5069. { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
  5070. { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
  5071. { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
  5072. { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
  5073. } },
  5074. { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
  5075. { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
  5076. { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
  5077. { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
  5078. { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
  5079. { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
  5080. { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
  5081. { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
  5082. { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
  5083. } },
  5084. { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
  5085. { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
  5086. { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
  5087. { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
  5088. { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
  5089. { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
  5090. { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
  5091. { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
  5092. { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
  5093. } },
  5094. { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
  5095. { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
  5096. { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
  5097. { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
  5098. { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
  5099. { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
  5100. { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
  5101. { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
  5102. { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
  5103. } },
  5104. { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
  5105. { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
  5106. { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
  5107. { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
  5108. { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
  5109. { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
  5110. { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
  5111. { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
  5112. { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
  5113. } },
  5114. { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
  5115. { PIN_CLKOUT, 28, 3 }, /* CLKOUT */
  5116. { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
  5117. { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
  5118. { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
  5119. { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
  5120. { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
  5121. { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
  5122. { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
  5123. } },
  5124. { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
  5125. { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
  5126. { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
  5127. { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
  5128. { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
  5129. { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
  5130. { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
  5131. { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
  5132. { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
  5133. } },
  5134. { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
  5135. { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
  5136. { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
  5137. { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
  5138. { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
  5139. { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
  5140. { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
  5141. { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
  5142. { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
  5143. } },
  5144. { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
  5145. { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
  5146. { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
  5147. { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
  5148. { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
  5149. { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
  5150. { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
  5151. { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
  5152. { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
  5153. } },
  5154. { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
  5155. { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
  5156. { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
  5157. { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
  5158. { PIN_TMS, 4, 2 }, /* TMS */
  5159. } },
  5160. { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
  5161. { PIN_TDO, 28, 2 }, /* TDO */
  5162. { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
  5163. { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
  5164. { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
  5165. { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
  5166. { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
  5167. { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
  5168. { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
  5169. } },
  5170. { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
  5171. { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
  5172. { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
  5173. { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
  5174. { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
  5175. { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
  5176. { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
  5177. { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
  5178. { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
  5179. } },
  5180. { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
  5181. { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
  5182. { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
  5183. { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
  5184. { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
  5185. { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
  5186. { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
  5187. { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
  5188. { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
  5189. } },
  5190. { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
  5191. { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
  5192. { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
  5193. { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
  5194. { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
  5195. { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
  5196. { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
  5197. { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
  5198. { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
  5199. } },
  5200. { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
  5201. { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
  5202. { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
  5203. { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
  5204. { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
  5205. { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
  5206. { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
  5207. { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
  5208. { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
  5209. } },
  5210. { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
  5211. { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
  5212. { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
  5213. { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
  5214. { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
  5215. { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
  5216. { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
  5217. { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
  5218. { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
  5219. } },
  5220. { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
  5221. { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
  5222. { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
  5223. { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
  5224. { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
  5225. { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
  5226. { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
  5227. { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
  5228. { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
  5229. } },
  5230. { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
  5231. { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
  5232. { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
  5233. { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
  5234. { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
  5235. { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
  5236. { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
  5237. { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
  5238. { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
  5239. } },
  5240. { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
  5241. { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
  5242. { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
  5243. { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
  5244. { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
  5245. { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
  5246. { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
  5247. { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
  5248. { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
  5249. } },
  5250. { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
  5251. { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
  5252. { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
  5253. { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
  5254. { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
  5255. { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
  5256. { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
  5257. { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
  5258. { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
  5259. } },
  5260. { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
  5261. { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
  5262. { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
  5263. { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
  5264. { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
  5265. { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
  5266. { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
  5267. { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
  5268. { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
  5269. } },
  5270. { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
  5271. { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
  5272. { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
  5273. { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
  5274. { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
  5275. { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
  5276. { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
  5277. { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
  5278. } },
  5279. { },
  5280. };
  5281. enum ioctrl_regs {
  5282. POCCTRL,
  5283. TDSELCTRL,
  5284. };
  5285. static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
  5286. [POCCTRL] = { 0xe6060380, },
  5287. [TDSELCTRL] = { 0xe60603c0, },
  5288. { /* sentinel */ },
  5289. };
  5290. static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
  5291. u32 *pocctrl)
  5292. {
  5293. int bit = -EINVAL;
  5294. *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
  5295. if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
  5296. bit = pin & 0x1f;
  5297. if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
  5298. bit = (pin & 0x1f) + 12;
  5299. return bit;
  5300. }
  5301. static const struct pinmux_bias_reg pinmux_bias_regs[] = {
  5302. { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
  5303. [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
  5304. [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
  5305. [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
  5306. [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
  5307. [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
  5308. [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
  5309. [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
  5310. [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
  5311. [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
  5312. [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
  5313. [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
  5314. [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
  5315. [12] = PIN_RPC_INT_N, /* RPC_INT# */
  5316. [13] = PIN_RPC_WP_N, /* RPC_WP# */
  5317. [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
  5318. [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
  5319. [16] = PIN_AVB_RXC, /* AVB_RXC */
  5320. [17] = PIN_AVB_RD0, /* AVB_RD0 */
  5321. [18] = PIN_AVB_RD1, /* AVB_RD1 */
  5322. [19] = PIN_AVB_RD2, /* AVB_RD2 */
  5323. [20] = PIN_AVB_RD3, /* AVB_RD3 */
  5324. [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
  5325. [22] = PIN_AVB_TXC, /* AVB_TXC */
  5326. [23] = PIN_AVB_TD0, /* AVB_TD0 */
  5327. [24] = PIN_AVB_TD1, /* AVB_TD1 */
  5328. [25] = PIN_AVB_TD2, /* AVB_TD2 */
  5329. [26] = PIN_AVB_TD3, /* AVB_TD3 */
  5330. [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
  5331. [28] = PIN_AVB_MDIO, /* AVB_MDIO */
  5332. [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
  5333. [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
  5334. [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
  5335. } },
  5336. { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
  5337. [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
  5338. [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
  5339. [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
  5340. [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
  5341. [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
  5342. [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
  5343. [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
  5344. [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
  5345. [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
  5346. [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
  5347. [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
  5348. [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
  5349. [12] = RCAR_GP_PIN(1, 0), /* A0 */
  5350. [13] = RCAR_GP_PIN(1, 1), /* A1 */
  5351. [14] = RCAR_GP_PIN(1, 2), /* A2 */
  5352. [15] = RCAR_GP_PIN(1, 3), /* A3 */
  5353. [16] = RCAR_GP_PIN(1, 4), /* A4 */
  5354. [17] = RCAR_GP_PIN(1, 5), /* A5 */
  5355. [18] = RCAR_GP_PIN(1, 6), /* A6 */
  5356. [19] = RCAR_GP_PIN(1, 7), /* A7 */
  5357. [20] = RCAR_GP_PIN(1, 8), /* A8 */
  5358. [21] = RCAR_GP_PIN(1, 9), /* A9 */
  5359. [22] = RCAR_GP_PIN(1, 10), /* A10 */
  5360. [23] = RCAR_GP_PIN(1, 11), /* A11 */
  5361. [24] = RCAR_GP_PIN(1, 12), /* A12 */
  5362. [25] = RCAR_GP_PIN(1, 13), /* A13 */
  5363. [26] = RCAR_GP_PIN(1, 14), /* A14 */
  5364. [27] = RCAR_GP_PIN(1, 15), /* A15 */
  5365. [28] = RCAR_GP_PIN(1, 16), /* A16 */
  5366. [29] = RCAR_GP_PIN(1, 17), /* A17 */
  5367. [30] = RCAR_GP_PIN(1, 18), /* A18 */
  5368. [31] = RCAR_GP_PIN(1, 19), /* A19 */
  5369. } },
  5370. { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
  5371. [ 0] = PIN_CLKOUT, /* CLKOUT */
  5372. [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
  5373. [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
  5374. [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
  5375. [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
  5376. [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
  5377. [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
  5378. [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
  5379. [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
  5380. [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
  5381. [10] = RCAR_GP_PIN(0, 0), /* D0 */
  5382. [11] = RCAR_GP_PIN(0, 1), /* D1 */
  5383. [12] = RCAR_GP_PIN(0, 2), /* D2 */
  5384. [13] = RCAR_GP_PIN(0, 3), /* D3 */
  5385. [14] = RCAR_GP_PIN(0, 4), /* D4 */
  5386. [15] = RCAR_GP_PIN(0, 5), /* D5 */
  5387. [16] = RCAR_GP_PIN(0, 6), /* D6 */
  5388. [17] = RCAR_GP_PIN(0, 7), /* D7 */
  5389. [18] = RCAR_GP_PIN(0, 8), /* D8 */
  5390. [19] = RCAR_GP_PIN(0, 9), /* D9 */
  5391. [20] = RCAR_GP_PIN(0, 10), /* D10 */
  5392. [21] = RCAR_GP_PIN(0, 11), /* D11 */
  5393. [22] = RCAR_GP_PIN(0, 12), /* D12 */
  5394. [23] = RCAR_GP_PIN(0, 13), /* D13 */
  5395. [24] = RCAR_GP_PIN(0, 14), /* D14 */
  5396. [25] = RCAR_GP_PIN(0, 15), /* D15 */
  5397. [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
  5398. [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
  5399. [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
  5400. [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
  5401. [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
  5402. [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
  5403. } },
  5404. { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
  5405. [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
  5406. [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
  5407. [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
  5408. [ 3] = PIN_EXTALR, /* EXTALR*/
  5409. [ 4] = PIN_TRST_N, /* TRST# */
  5410. [ 5] = PIN_TCK, /* TCK */
  5411. [ 6] = PIN_TMS, /* TMS */
  5412. [ 7] = PIN_TDI, /* TDI */
  5413. [ 8] = SH_PFC_PIN_NONE,
  5414. [ 9] = PIN_ASEBRK, /* ASEBRK */
  5415. [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
  5416. [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
  5417. [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
  5418. [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
  5419. [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
  5420. [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
  5421. [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
  5422. [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
  5423. [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
  5424. [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
  5425. [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
  5426. [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
  5427. [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
  5428. [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
  5429. [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
  5430. [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
  5431. [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
  5432. [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
  5433. [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
  5434. [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
  5435. [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
  5436. [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
  5437. } },
  5438. { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
  5439. [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
  5440. [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
  5441. [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
  5442. [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
  5443. [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
  5444. [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
  5445. [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
  5446. [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
  5447. [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
  5448. [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
  5449. [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
  5450. [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
  5451. [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
  5452. [13] = RCAR_GP_PIN(5, 1), /* RX0 */
  5453. [14] = RCAR_GP_PIN(5, 2), /* TX0 */
  5454. [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
  5455. [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
  5456. [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
  5457. [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
  5458. [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
  5459. [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
  5460. [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
  5461. [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
  5462. [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
  5463. [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
  5464. [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
  5465. [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
  5466. [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
  5467. [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
  5468. [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
  5469. [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
  5470. [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
  5471. } },
  5472. { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
  5473. [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
  5474. [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
  5475. [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
  5476. [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
  5477. [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
  5478. [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
  5479. [ 6] = PIN_MLB_REF, /* MLB_REF */
  5480. [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
  5481. [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
  5482. [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
  5483. [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
  5484. [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
  5485. [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
  5486. [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
  5487. [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
  5488. [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
  5489. [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
  5490. [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
  5491. [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
  5492. [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
  5493. [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
  5494. [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
  5495. [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
  5496. [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
  5497. [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
  5498. [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
  5499. [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
  5500. [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
  5501. [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
  5502. [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
  5503. [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
  5504. [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
  5505. } },
  5506. { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
  5507. [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
  5508. [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
  5509. [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
  5510. [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
  5511. [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
  5512. [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
  5513. [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
  5514. [ 7] = SH_PFC_PIN_NONE,
  5515. [ 8] = SH_PFC_PIN_NONE,
  5516. [ 9] = SH_PFC_PIN_NONE,
  5517. [10] = SH_PFC_PIN_NONE,
  5518. [11] = SH_PFC_PIN_NONE,
  5519. [12] = SH_PFC_PIN_NONE,
  5520. [13] = SH_PFC_PIN_NONE,
  5521. [14] = SH_PFC_PIN_NONE,
  5522. [15] = SH_PFC_PIN_NONE,
  5523. [16] = SH_PFC_PIN_NONE,
  5524. [17] = SH_PFC_PIN_NONE,
  5525. [18] = SH_PFC_PIN_NONE,
  5526. [19] = SH_PFC_PIN_NONE,
  5527. [20] = SH_PFC_PIN_NONE,
  5528. [21] = SH_PFC_PIN_NONE,
  5529. [22] = SH_PFC_PIN_NONE,
  5530. [23] = SH_PFC_PIN_NONE,
  5531. [24] = SH_PFC_PIN_NONE,
  5532. [25] = SH_PFC_PIN_NONE,
  5533. [26] = SH_PFC_PIN_NONE,
  5534. [27] = SH_PFC_PIN_NONE,
  5535. [28] = SH_PFC_PIN_NONE,
  5536. [29] = SH_PFC_PIN_NONE,
  5537. [30] = SH_PFC_PIN_NONE,
  5538. [31] = SH_PFC_PIN_NONE,
  5539. } },
  5540. { /* sentinel */ },
  5541. };
  5542. static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
  5543. unsigned int pin)
  5544. {
  5545. const struct pinmux_bias_reg *reg;
  5546. unsigned int bit;
  5547. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  5548. if (!reg)
  5549. return PIN_CONFIG_BIAS_DISABLE;
  5550. if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
  5551. return PIN_CONFIG_BIAS_DISABLE;
  5552. else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
  5553. return PIN_CONFIG_BIAS_PULL_UP;
  5554. else
  5555. return PIN_CONFIG_BIAS_PULL_DOWN;
  5556. }
  5557. static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  5558. unsigned int bias)
  5559. {
  5560. const struct pinmux_bias_reg *reg;
  5561. u32 enable, updown;
  5562. unsigned int bit;
  5563. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  5564. if (!reg)
  5565. return;
  5566. enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
  5567. if (bias != PIN_CONFIG_BIAS_DISABLE)
  5568. enable |= BIT(bit);
  5569. updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
  5570. if (bias == PIN_CONFIG_BIAS_PULL_UP)
  5571. updown |= BIT(bit);
  5572. sh_pfc_write(pfc, reg->pud, updown);
  5573. sh_pfc_write(pfc, reg->puen, enable);
  5574. }
  5575. static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
  5576. .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
  5577. .get_bias = r8a77950_pinmux_get_bias,
  5578. .set_bias = r8a77950_pinmux_set_bias,
  5579. };
  5580. const struct sh_pfc_soc_info r8a77950_pinmux_info = {
  5581. .name = "r8a77950_pfc",
  5582. .ops = &r8a77950_pinmux_ops,
  5583. .unlock_reg = 0xe6060000, /* PMMR */
  5584. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5585. .pins = pinmux_pins,
  5586. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5587. .groups = pinmux_groups,
  5588. .nr_groups = ARRAY_SIZE(pinmux_groups),
  5589. .functions = pinmux_functions,
  5590. .nr_functions = ARRAY_SIZE(pinmux_functions),
  5591. .cfg_regs = pinmux_config_regs,
  5592. .drive_regs = pinmux_drive_regs,
  5593. .bias_regs = pinmux_bias_regs,
  5594. .ioctrl_regs = pinmux_ioctrl_regs,
  5595. .pinmux_data = pinmux_data,
  5596. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5597. };