pfc-r8a7794.c 168 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a7794/r8a7745 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2014-2015 Renesas Electronics Corporation
  6. * Copyright (C) 2015 Renesas Solutions Corp.
  7. * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
  8. */
  9. #include <linux/errno.h>
  10. #include <linux/kernel.h>
  11. #include <linux/sys_soc.h>
  12. #include "core.h"
  13. #include "sh_pfc.h"
  14. #define CPU_ALL_GP(fn, sfx) \
  15. PORT_GP_32(0, fn, sfx), \
  16. PORT_GP_26(1, fn, sfx), \
  17. PORT_GP_32(2, fn, sfx), \
  18. PORT_GP_32(3, fn, sfx), \
  19. PORT_GP_32(4, fn, sfx), \
  20. PORT_GP_28(5, fn, sfx), \
  21. PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  22. PORT_GP_1(6, 24, fn, sfx), \
  23. PORT_GP_1(6, 25, fn, sfx)
  24. enum {
  25. PINMUX_RESERVED = 0,
  26. PINMUX_DATA_BEGIN,
  27. GP_ALL(DATA),
  28. PINMUX_DATA_END,
  29. PINMUX_FUNCTION_BEGIN,
  30. GP_ALL(FN),
  31. /* GPSR0 */
  32. FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  33. FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  34. FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  35. FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  36. FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  37. FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  38. FN_IP2_17_16,
  39. /* GPSR1 */
  40. FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  41. FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  42. FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  43. FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  44. FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  45. /* GPSR2 */
  46. FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  47. FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  48. FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  49. FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  50. FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  51. FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  52. FN_IP6_5_4, FN_IP6_7_6,
  53. /* GPSR3 */
  54. FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  55. FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  56. FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  57. FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  58. FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  59. FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  60. FN_IP8_22_20,
  61. /* GPSR4 */
  62. FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  63. FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  64. FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  65. FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  66. FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  67. FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  68. FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  69. /* GPSR5 */
  70. FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  71. FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  72. FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  73. FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  74. FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  75. FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  76. /* GPSR6 */
  77. FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  78. FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  79. FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  80. FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  81. FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  82. /* IPSR0 */
  83. FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  84. FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
  85. FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
  86. FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
  87. FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
  88. FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
  89. FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
  90. FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
  91. /* IPSR1 */
  92. FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
  93. FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
  94. FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
  95. FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
  96. FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
  97. FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
  98. FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
  99. FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
  100. FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
  101. FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
  102. FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
  103. FN_A1, FN_SCIFB1_TXD,
  104. FN_A3, FN_SCIFB0_SCK,
  105. FN_A4, FN_SCIFB0_TXD,
  106. FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
  107. FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
  108. /* IPSR2 */
  109. FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
  110. FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
  111. FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
  112. FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
  113. FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
  114. FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
  115. FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
  116. FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
  117. FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
  118. FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
  119. FN_TPUTO2_B,
  120. FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
  121. FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
  122. FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
  123. FN_A20, FN_SPCLK,
  124. /* IPSR3 */
  125. FN_A21, FN_MOSI_IO0,
  126. FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
  127. FN_A23, FN_IO2, FN_ATAWR1_N,
  128. FN_A24, FN_IO3, FN_EX_WAIT2,
  129. FN_A25, FN_SSL, FN_ATARD1_N,
  130. FN_CS0_N, FN_VI1_DATA8,
  131. FN_CS1_N_A26, FN_VI1_DATA9,
  132. FN_EX_CS0_N, FN_VI1_DATA10,
  133. FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
  134. FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
  135. FN_SCIFB2_TXD,
  136. FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
  137. FN_SCIFB2_SCK,
  138. FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
  139. FN_SCIFB2_CTS_N,
  140. FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
  141. FN_SCIFB2_RTS_N,
  142. FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
  143. FN_RD_N, FN_ATACS11_N,
  144. FN_RD_WR_N, FN_ATAG1_N,
  145. /* IPSR4 */
  146. FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
  147. FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
  148. FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
  149. FN_DU0_DR2, FN_LCDOUT18,
  150. FN_DU0_DR3, FN_LCDOUT19,
  151. FN_DU0_DR4, FN_LCDOUT20,
  152. FN_DU0_DR5, FN_LCDOUT21,
  153. FN_DU0_DR6, FN_LCDOUT22,
  154. FN_DU0_DR7, FN_LCDOUT23,
  155. FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
  156. FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
  157. FN_DU0_DG2, FN_LCDOUT10,
  158. FN_DU0_DG3, FN_LCDOUT11,
  159. FN_DU0_DG4, FN_LCDOUT12,
  160. /* IPSR5 */
  161. FN_DU0_DG5, FN_LCDOUT13,
  162. FN_DU0_DG6, FN_LCDOUT14,
  163. FN_DU0_DG7, FN_LCDOUT15,
  164. FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
  165. FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
  166. FN_DU0_DB2, FN_LCDOUT2,
  167. FN_DU0_DB3, FN_LCDOUT3,
  168. FN_DU0_DB4, FN_LCDOUT4,
  169. FN_DU0_DB5, FN_LCDOUT5,
  170. FN_DU0_DB6, FN_LCDOUT6,
  171. FN_DU0_DB7, FN_LCDOUT7,
  172. FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
  173. FN_DU0_DOTCLKOUT0, FN_QCLK,
  174. FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
  175. FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
  176. /* IPSR6 */
  177. FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
  178. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
  179. FN_DU0_DISP, FN_QPOLA,
  180. FN_DU0_CDE, FN_QPOLB,
  181. FN_VI0_CLK, FN_AVB_RX_CLK,
  182. FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
  183. FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
  184. FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
  185. FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
  186. FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
  187. FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
  188. FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
  189. FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
  190. FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
  191. FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
  192. FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
  193. FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
  194. FN_AVB_TX_EN,
  195. FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
  196. FN_ADIDATA,
  197. /* IPSR7 */
  198. FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
  199. FN_ADICS_SAMP,
  200. FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
  201. FN_ADICLK,
  202. FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
  203. FN_ADICHS0,
  204. FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
  205. FN_ADICHS1,
  206. FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
  207. FN_ADICHS2,
  208. FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
  209. FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
  210. FN_SSI_WS5_B,
  211. FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
  212. FN_SSI_SDATA5_B,
  213. FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
  214. FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
  215. FN_SSI_WS6_B,
  216. FN_DREQ0_N, FN_SCIFB1_RXD,
  217. /* IPSR8 */
  218. FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
  219. FN_SSI_SDATA6_B,
  220. FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
  221. FN_SSI_SCK78_B,
  222. FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
  223. FN_SSI_WS78_B,
  224. FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
  225. FN_AVB_MAGIC, FN_SSI_SDATA7_B,
  226. FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
  227. FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
  228. FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
  229. FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
  230. FN_CAN1_RX_D, FN_TPUTO0_B,
  231. FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
  232. FN_CAN1_TX_D,
  233. FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
  234. FN_TPUTO1_B,
  235. FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
  236. FN_BPFCLK_C,
  237. FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
  238. FN_FMCLK_C,
  239. /* IPSR9 */
  240. FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
  241. FN_FMIN_C,
  242. FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
  243. FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
  244. FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
  245. FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
  246. FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
  247. FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
  248. FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
  249. FN_SPEEDIN_B,
  250. FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
  251. FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
  252. FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
  253. /* IPSR10 */
  254. FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
  255. FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
  256. FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
  257. FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
  258. FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
  259. FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
  260. FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
  261. FN_SSI_SCK4_B,
  262. FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
  263. FN_SSI_WS4_B,
  264. FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
  265. FN_SSI_SDATA4_B,
  266. FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
  267. FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
  268. /* IPSR11 */
  269. FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
  270. FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
  271. FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
  272. FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
  273. FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
  274. FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
  275. FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
  276. FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
  277. FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
  278. FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
  279. FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
  280. FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
  281. /* IPSR12 */
  282. FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
  283. FN_DREQ1_N_B,
  284. FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
  285. FN_CAN1_RX_C, FN_DACK1_B,
  286. FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
  287. FN_CAN1_TX_C, FN_DREQ2_N,
  288. FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
  289. FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
  290. FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
  291. FN_DACK2, FN_ETH_MDIO_B,
  292. FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
  293. FN_ETH_CRS_DV_B,
  294. FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
  295. FN_ETH_RX_ER_B,
  296. FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
  297. FN_ETH_RXD0_B,
  298. FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
  299. /* IPSR13 */
  300. FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
  301. FN_ATACS00_N, FN_ETH_LINK_B,
  302. FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
  303. FN_ATACS10_N, FN_ETH_REFCLK_B,
  304. FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
  305. FN_ETH_TXD1_B,
  306. FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
  307. FN_ETH_TX_EN_B,
  308. FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
  309. FN_ATADIR0_N, FN_ETH_MAGIC_B,
  310. FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
  311. FN_TS_SDATA_C, FN_ETH_TXD0_B,
  312. FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
  313. FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
  314. FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
  315. FN_TS_SDEN_C, FN_FMCLK_E,
  316. FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
  317. FN_TS_SPSYNC_C, FN_FMIN_E,
  318. /* MOD_SEL */
  319. FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
  320. FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
  321. FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
  322. FN_SEL_DARC_4,
  323. FN_SEL_ETH_0, FN_SEL_ETH_1,
  324. FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
  325. FN_SEL_I2C00_4,
  326. FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
  327. FN_SEL_I2C01_4,
  328. FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
  329. FN_SEL_I2C02_4,
  330. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
  331. FN_SEL_I2C03_4,
  332. FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
  333. FN_SEL_I2C04_4,
  334. FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
  335. /* MOD_SEL2 */
  336. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
  337. FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
  338. FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
  339. FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
  340. FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
  341. FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
  342. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
  343. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
  344. FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
  345. FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
  346. FN_SEL_TMU_0, FN_SEL_TMU_1,
  347. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  348. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  349. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  350. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
  351. /* MOD_SEL3 */
  352. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  353. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
  354. FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
  355. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  356. FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
  357. FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
  358. FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
  359. FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
  360. FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
  361. FN_SEL_SSI9_1,
  362. PINMUX_FUNCTION_END,
  363. PINMUX_MARK_BEGIN,
  364. A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
  365. USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
  366. SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
  367. SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
  368. SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
  369. SD1_DATA2_MARK, SD1_DATA3_MARK,
  370. /* IPSR0 */
  371. SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
  372. MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
  373. SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
  374. SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
  375. MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
  376. CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
  377. CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
  378. SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
  379. SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
  380. SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
  381. /* IPSR1 */
  382. D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
  383. D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
  384. D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
  385. D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
  386. D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
  387. D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
  388. D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
  389. D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
  390. D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
  391. D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
  392. A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
  393. A1_MARK, SCIFB1_TXD_MARK,
  394. A3_MARK, SCIFB0_SCK_MARK,
  395. A4_MARK, SCIFB0_TXD_MARK,
  396. A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
  397. A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
  398. /* IPSR2 */
  399. A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
  400. A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
  401. A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
  402. A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
  403. A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
  404. A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
  405. A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
  406. A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
  407. A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
  408. A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
  409. CAN_CLK_C_MARK, TPUTO2_B_MARK,
  410. A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
  411. A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
  412. A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
  413. A20_MARK, SPCLK_MARK,
  414. /* IPSR3 */
  415. A21_MARK, MOSI_IO0_MARK,
  416. A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
  417. A23_MARK, IO2_MARK, ATAWR1_N_MARK,
  418. A24_MARK, IO3_MARK, EX_WAIT2_MARK,
  419. A25_MARK, SSL_MARK, ATARD1_N_MARK,
  420. CS0_N_MARK, VI1_DATA8_MARK,
  421. CS1_N_A26_MARK, VI1_DATA9_MARK,
  422. EX_CS0_N_MARK, VI1_DATA10_MARK,
  423. EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
  424. EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
  425. TPUTO3_MARK, SCIFB2_TXD_MARK,
  426. EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
  427. BPFCLK_MARK, SCIFB2_SCK_MARK,
  428. EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
  429. FMCLK_MARK, SCIFB2_CTS_N_MARK,
  430. EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
  431. FMIN_MARK, SCIFB2_RTS_N_MARK,
  432. BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
  433. RD_N_MARK, ATACS11_N_MARK,
  434. RD_WR_N_MARK, ATAG1_N_MARK,
  435. /* IPSR4 */
  436. EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
  437. DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
  438. DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
  439. DU0_DR2_MARK, LCDOUT18_MARK,
  440. DU0_DR3_MARK, LCDOUT19_MARK,
  441. DU0_DR4_MARK, LCDOUT20_MARK,
  442. DU0_DR5_MARK, LCDOUT21_MARK,
  443. DU0_DR6_MARK, LCDOUT22_MARK,
  444. DU0_DR7_MARK, LCDOUT23_MARK,
  445. DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
  446. DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
  447. DU0_DG2_MARK, LCDOUT10_MARK,
  448. DU0_DG3_MARK, LCDOUT11_MARK,
  449. DU0_DG4_MARK, LCDOUT12_MARK,
  450. /* IPSR5 */
  451. DU0_DG5_MARK, LCDOUT13_MARK,
  452. DU0_DG6_MARK, LCDOUT14_MARK,
  453. DU0_DG7_MARK, LCDOUT15_MARK,
  454. DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
  455. CAN0_RX_C_MARK,
  456. DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
  457. CAN0_TX_C_MARK,
  458. DU0_DB2_MARK, LCDOUT2_MARK,
  459. DU0_DB3_MARK, LCDOUT3_MARK,
  460. DU0_DB4_MARK, LCDOUT4_MARK,
  461. DU0_DB5_MARK, LCDOUT5_MARK,
  462. DU0_DB6_MARK, LCDOUT6_MARK,
  463. DU0_DB7_MARK, LCDOUT7_MARK,
  464. DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
  465. DU0_DOTCLKOUT0_MARK, QCLK_MARK,
  466. DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
  467. DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
  468. /* IPSR6 */
  469. DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
  470. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
  471. DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
  472. VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
  473. VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
  474. VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
  475. VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
  476. VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
  477. VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
  478. VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
  479. VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
  480. VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
  481. AVB_RXD7_MARK,
  482. VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
  483. AVB_RX_ER_MARK,
  484. VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
  485. AVB_COL_MARK,
  486. VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
  487. AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
  488. ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
  489. AVB_TX_CLK_MARK, ADIDATA_MARK,
  490. /* IPSR7 */
  491. ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
  492. AVB_TXD0_MARK, ADICS_SAMP_MARK,
  493. ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
  494. AVB_TXD1_MARK, ADICLK_MARK,
  495. ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
  496. AVB_TXD2_MARK, ADICHS0_MARK,
  497. ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
  498. AVB_TXD3_MARK, ADICHS1_MARK,
  499. ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
  500. AVB_TXD4_MARK, ADICHS2_MARK,
  501. ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
  502. SSI_SCK5_B_MARK,
  503. ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
  504. AVB_TXD6_MARK, SSI_WS5_B_MARK,
  505. ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
  506. AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
  507. ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
  508. SSI_SCK6_B_MARK,
  509. ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
  510. AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
  511. DREQ0_N_MARK, SCIFB1_RXD_MARK,
  512. /* IPSR8 */
  513. ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
  514. AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
  515. I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
  516. HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
  517. AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
  518. SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
  519. HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
  520. AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
  521. HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
  522. I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
  523. AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
  524. SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
  525. CAN1_TX_D_MARK,
  526. I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
  527. TS_SDATA_D_MARK, TPUTO1_B_MARK,
  528. I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
  529. BPFCLK_C_MARK,
  530. MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
  531. TS_SDEN_D_MARK, FMCLK_C_MARK,
  532. /* IPSR9 */
  533. MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
  534. TS_SPSYNC_D_MARK, FMIN_C_MARK,
  535. MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
  536. MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
  537. MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
  538. FMCLK_B_MARK,
  539. MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
  540. FMIN_B_MARK,
  541. HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
  542. HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
  543. HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
  544. SPEEDIN_B_MARK,
  545. HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
  546. SSI_SCK1_B_MARK,
  547. HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
  548. SSI_WS1_B_MARK,
  549. SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
  550. CAN_TXCLK_MARK,
  551. /* IPSR10 */
  552. SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
  553. SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
  554. SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
  555. SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
  556. SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
  557. SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
  558. SSI_SDATA9_B_MARK,
  559. SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
  560. AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
  561. SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
  562. AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
  563. I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
  564. SSI_SDATA4_B_MARK,
  565. I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
  566. SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
  567. /* IPSR11 */
  568. SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
  569. SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
  570. SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
  571. SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
  572. DU1_EXVSYNC_DU1_VSYNC_MARK,
  573. SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
  574. DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
  575. SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
  576. SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
  577. SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
  578. CAN_CLK_D_MARK,
  579. SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
  580. SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
  581. SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
  582. /* IPSR12 */
  583. SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
  584. DREQ1_N_B_MARK,
  585. SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
  586. CAN1_RX_C_MARK, DACK1_B_MARK,
  587. SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
  588. CAN1_TX_C_MARK, DREQ2_N_MARK,
  589. SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
  590. SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
  591. SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
  592. SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
  593. DACK2_MARK, ETH_MDIO_B_MARK,
  594. SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
  595. CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
  596. SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
  597. CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
  598. SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
  599. ETH_RXD0_B_MARK,
  600. SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
  601. ETH_RXD1_B_MARK,
  602. /* IPSR13 */
  603. SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
  604. ATACS00_N_MARK, ETH_LINK_B_MARK,
  605. SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
  606. VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
  607. SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
  608. EX_WAIT1_MARK, ETH_TXD1_B_MARK,
  609. SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
  610. ATARD0_N_MARK, ETH_TX_EN_B_MARK,
  611. SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
  612. ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
  613. AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
  614. TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
  615. AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
  616. TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
  617. AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
  618. TS_SDEN_C_MARK, FMCLK_E_MARK,
  619. AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
  620. TS_SPSYNC_C_MARK, FMIN_E_MARK,
  621. PINMUX_MARK_END,
  622. };
  623. static const u16 pinmux_data[] = {
  624. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  625. PINMUX_SINGLE(A2),
  626. PINMUX_SINGLE(WE0_N),
  627. PINMUX_SINGLE(WE1_N),
  628. PINMUX_SINGLE(DACK0),
  629. PINMUX_SINGLE(USB0_PWEN),
  630. PINMUX_SINGLE(USB0_OVC),
  631. PINMUX_SINGLE(USB1_PWEN),
  632. PINMUX_SINGLE(USB1_OVC),
  633. PINMUX_SINGLE(SD0_CLK),
  634. PINMUX_SINGLE(SD0_CMD),
  635. PINMUX_SINGLE(SD0_DATA0),
  636. PINMUX_SINGLE(SD0_DATA1),
  637. PINMUX_SINGLE(SD0_DATA2),
  638. PINMUX_SINGLE(SD0_DATA3),
  639. PINMUX_SINGLE(SD0_CD),
  640. PINMUX_SINGLE(SD0_WP),
  641. PINMUX_SINGLE(SD1_CLK),
  642. PINMUX_SINGLE(SD1_CMD),
  643. PINMUX_SINGLE(SD1_DATA0),
  644. PINMUX_SINGLE(SD1_DATA1),
  645. PINMUX_SINGLE(SD1_DATA2),
  646. PINMUX_SINGLE(SD1_DATA3),
  647. /* IPSR0 */
  648. PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
  649. PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
  650. PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
  651. PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
  652. PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
  653. PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
  654. PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
  655. PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
  656. PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
  657. PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
  658. PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
  659. PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
  660. PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
  661. PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
  662. PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
  663. PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
  664. PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
  665. PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
  666. PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
  667. PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
  668. PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
  669. PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
  670. PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
  671. PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
  672. PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
  673. PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
  674. PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
  675. PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
  676. PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
  677. PINMUX_IPSR_GPSR(IP0_23_22, D0),
  678. PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
  679. PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
  680. PINMUX_IPSR_GPSR(IP0_24, D1),
  681. PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
  682. PINMUX_IPSR_GPSR(IP0_25, D2),
  683. PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
  684. PINMUX_IPSR_GPSR(IP0_27_26, D3),
  685. PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
  686. PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
  687. PINMUX_IPSR_GPSR(IP0_29_28, D4),
  688. PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
  689. PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
  690. PINMUX_IPSR_GPSR(IP0_31_30, D5),
  691. PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
  692. PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
  693. /* IPSR1 */
  694. PINMUX_IPSR_GPSR(IP1_1_0, D6),
  695. PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
  696. PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
  697. PINMUX_IPSR_GPSR(IP1_3_2, D7),
  698. PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
  699. PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
  700. PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
  701. PINMUX_IPSR_GPSR(IP1_5_4, D8),
  702. PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
  703. PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
  704. PINMUX_IPSR_GPSR(IP1_7_6, D9),
  705. PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
  706. PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
  707. PINMUX_IPSR_GPSR(IP1_10_8, D10),
  708. PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
  709. PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
  710. PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
  711. PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
  712. PINMUX_IPSR_GPSR(IP1_12_11, D11),
  713. PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
  714. PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
  715. PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
  716. PINMUX_IPSR_GPSR(IP1_14_13, D12),
  717. PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
  718. PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
  719. PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
  720. PINMUX_IPSR_GPSR(IP1_17_15, D13),
  721. PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
  722. PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
  723. PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
  724. PINMUX_IPSR_GPSR(IP1_19_18, D14),
  725. PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
  726. PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
  727. PINMUX_IPSR_GPSR(IP1_21_20, D15),
  728. PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
  729. PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
  730. PINMUX_IPSR_GPSR(IP1_23_22, A0),
  731. PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
  732. PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
  733. PINMUX_IPSR_GPSR(IP1_24, A1),
  734. PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
  735. PINMUX_IPSR_GPSR(IP1_26, A3),
  736. PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
  737. PINMUX_IPSR_GPSR(IP1_27, A4),
  738. PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
  739. PINMUX_IPSR_GPSR(IP1_29_28, A5),
  740. PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
  741. PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
  742. PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
  743. PINMUX_IPSR_GPSR(IP1_31_30, A6),
  744. PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
  745. PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
  746. PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
  747. /* IPSR2 */
  748. PINMUX_IPSR_GPSR(IP2_1_0, A7),
  749. PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
  750. PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
  751. PINMUX_IPSR_GPSR(IP2_3_2, A8),
  752. PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
  753. PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
  754. PINMUX_IPSR_GPSR(IP2_5_4, A9),
  755. PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
  756. PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
  757. PINMUX_IPSR_GPSR(IP2_7_6, A10),
  758. PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
  759. PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
  760. PINMUX_IPSR_GPSR(IP2_9_8, A11),
  761. PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
  762. PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
  763. PINMUX_IPSR_GPSR(IP2_11_10, A12),
  764. PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
  765. PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
  766. PINMUX_IPSR_GPSR(IP2_13_12, A13),
  767. PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
  768. PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
  769. PINMUX_IPSR_GPSR(IP2_15_14, A14),
  770. PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
  771. PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
  772. PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
  773. PINMUX_IPSR_GPSR(IP2_17_16, A15),
  774. PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
  775. PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
  776. PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
  777. PINMUX_IPSR_GPSR(IP2_20_18, A16),
  778. PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
  779. PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
  780. PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
  781. PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
  782. PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
  783. PINMUX_IPSR_GPSR(IP2_23_21, A17),
  784. PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
  785. PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
  786. PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
  787. PINMUX_IPSR_GPSR(IP2_26_24, A18),
  788. PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
  789. PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
  790. PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
  791. PINMUX_IPSR_GPSR(IP2_29_27, A19),
  792. PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
  793. PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
  794. PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
  795. PINMUX_IPSR_GPSR(IP2_31_30, A20),
  796. PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
  797. /* IPSR3 */
  798. PINMUX_IPSR_GPSR(IP3_1_0, A21),
  799. PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
  800. PINMUX_IPSR_GPSR(IP3_3_2, A22),
  801. PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
  802. PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
  803. PINMUX_IPSR_GPSR(IP3_5_4, A23),
  804. PINMUX_IPSR_GPSR(IP3_5_4, IO2),
  805. PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
  806. PINMUX_IPSR_GPSR(IP3_7_6, A24),
  807. PINMUX_IPSR_GPSR(IP3_7_6, IO3),
  808. PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
  809. PINMUX_IPSR_GPSR(IP3_9_8, A25),
  810. PINMUX_IPSR_GPSR(IP3_9_8, SSL),
  811. PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
  812. PINMUX_IPSR_GPSR(IP3_10, CS0_N),
  813. PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
  814. PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
  815. PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
  816. PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
  817. PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
  818. PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
  819. PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
  820. PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
  821. PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
  822. PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
  823. PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
  824. PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
  825. PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
  826. PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
  827. PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
  828. PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
  829. PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
  830. PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
  831. PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
  832. PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
  833. PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
  834. PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
  835. PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
  836. PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
  837. PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
  838. PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
  839. PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
  840. PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
  841. PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
  842. PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
  843. PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
  844. PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
  845. PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
  846. PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
  847. PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
  848. PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
  849. PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
  850. PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
  851. PINMUX_IPSR_GPSR(IP3_30, RD_N),
  852. PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
  853. PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
  854. PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
  855. /* IPSR4 */
  856. PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
  857. PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
  858. PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
  859. PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
  860. PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
  861. PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
  862. PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
  863. PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
  864. PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
  865. PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
  866. PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
  867. PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
  868. PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
  869. PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
  870. PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
  871. PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
  872. PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
  873. PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
  874. PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
  875. PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
  876. PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
  877. PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
  878. PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
  879. PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
  880. PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
  881. PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
  882. PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
  883. PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
  884. PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
  885. PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
  886. PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
  887. PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
  888. PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
  889. PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
  890. PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
  891. PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
  892. PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
  893. /* IPSR5 */
  894. PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
  895. PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
  896. PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
  897. PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
  898. PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
  899. PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
  900. PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
  901. PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
  902. PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
  903. PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
  904. PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
  905. PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
  906. PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
  907. PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
  908. PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
  909. PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
  910. PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
  911. PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
  912. PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
  913. PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
  914. PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
  915. PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
  916. PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
  917. PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
  918. PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
  919. PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
  920. PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
  921. PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
  922. PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
  923. PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
  924. PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
  925. PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
  926. PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
  927. PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
  928. PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
  929. PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
  930. /* IPSR6 */
  931. PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
  932. PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
  933. PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
  934. PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
  935. PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
  936. PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
  937. PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
  938. PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
  939. PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
  940. PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
  941. PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
  942. PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
  943. PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
  944. PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
  945. PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
  946. PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
  947. PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
  948. PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
  949. PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
  950. PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
  951. PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
  952. PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
  953. PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
  954. PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
  955. PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
  956. PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
  957. PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
  958. PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
  959. PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
  960. PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
  961. PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
  962. PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
  963. PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
  964. PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
  965. PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
  966. PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
  967. PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
  968. PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
  969. PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
  970. PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
  971. PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
  972. PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
  973. PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
  974. PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
  975. PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
  976. PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
  977. PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
  978. PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
  979. PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
  980. PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
  981. PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
  982. PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
  983. /* IPSR7 */
  984. PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
  985. PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
  986. PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
  987. PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
  988. PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
  989. PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
  990. PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
  991. PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
  992. PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
  993. PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
  994. PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
  995. PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
  996. PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
  997. PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
  998. PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
  999. PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
  1000. PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
  1001. PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
  1002. PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
  1003. PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
  1004. PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
  1005. PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
  1006. PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
  1007. PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
  1008. PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
  1009. PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
  1010. PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
  1011. PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
  1012. PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
  1013. PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
  1014. PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
  1015. PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
  1016. PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
  1017. PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
  1018. PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
  1019. PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
  1020. PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
  1021. PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
  1022. PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
  1023. PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
  1024. PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
  1025. PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
  1026. PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
  1027. PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
  1028. PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
  1029. PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
  1030. PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
  1031. PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
  1032. PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
  1033. PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
  1034. PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
  1035. PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
  1036. PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
  1037. PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
  1038. PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
  1039. PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
  1040. PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
  1041. PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
  1042. PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
  1043. PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
  1044. /* IPSR8 */
  1045. PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
  1046. PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
  1047. PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
  1048. PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
  1049. PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
  1050. PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
  1051. PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
  1052. PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
  1053. PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
  1054. PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
  1055. PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
  1056. PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
  1057. PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
  1058. PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
  1059. PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
  1060. PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
  1061. PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
  1062. PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
  1063. PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
  1064. PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
  1065. PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
  1066. PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
  1067. PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
  1068. PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
  1069. PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
  1070. PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
  1071. PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
  1072. PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
  1073. PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
  1074. PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
  1075. PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
  1076. PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
  1077. PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
  1078. PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
  1079. PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
  1080. PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
  1081. PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
  1082. PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
  1083. PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
  1084. PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
  1085. PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
  1086. PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
  1087. PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
  1088. PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
  1089. PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
  1090. PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
  1091. PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
  1092. PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
  1093. PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
  1094. PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
  1095. PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
  1096. PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
  1097. PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
  1098. PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
  1099. PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
  1100. PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
  1101. PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
  1102. PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
  1103. PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
  1104. PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
  1105. PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
  1106. PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
  1107. PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
  1108. PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
  1109. PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
  1110. /* IPSR9 */
  1111. PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
  1112. PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
  1113. PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
  1114. PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
  1115. PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
  1116. PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
  1117. PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
  1118. PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
  1119. PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
  1120. PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
  1121. PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
  1122. PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
  1123. PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
  1124. PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
  1125. PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
  1126. PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
  1127. PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
  1128. PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
  1129. PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
  1130. PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
  1131. PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
  1132. PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
  1133. PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
  1134. PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
  1135. PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
  1136. PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
  1137. PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
  1138. PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
  1139. PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
  1140. PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
  1141. PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
  1142. PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
  1143. PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
  1144. PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
  1145. PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
  1146. PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
  1147. PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
  1148. PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
  1149. PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
  1150. PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
  1151. PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
  1152. PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
  1153. PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
  1154. PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
  1155. PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
  1156. PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
  1157. PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
  1158. PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
  1159. PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
  1160. PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
  1161. PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
  1162. PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
  1163. PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
  1164. PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
  1165. PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
  1166. /* IPSR10 */
  1167. PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
  1168. PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
  1169. PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
  1170. PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
  1171. PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
  1172. PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
  1173. PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
  1174. PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
  1175. PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
  1176. PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
  1177. PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
  1178. PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
  1179. PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
  1180. PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
  1181. PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
  1182. PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
  1183. PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
  1184. PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
  1185. PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
  1186. PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
  1187. PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
  1188. PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
  1189. PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
  1190. PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
  1191. PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
  1192. PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
  1193. PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
  1194. PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
  1195. PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
  1196. PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
  1197. PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
  1198. PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
  1199. PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
  1200. PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
  1201. PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
  1202. PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
  1203. PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
  1204. PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
  1205. PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
  1206. PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
  1207. PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
  1208. PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
  1209. PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
  1210. PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
  1211. PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
  1212. PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
  1213. PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
  1214. PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
  1215. PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
  1216. /* IPSR11 */
  1217. PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
  1218. PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
  1219. PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
  1220. PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
  1221. PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
  1222. PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
  1223. PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
  1224. PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
  1225. PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
  1226. PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
  1227. PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
  1228. PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
  1229. PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
  1230. PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
  1231. PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
  1232. PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
  1233. PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
  1234. PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
  1235. PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
  1236. PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
  1237. PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
  1238. PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
  1239. PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
  1240. PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
  1241. PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
  1242. PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
  1243. PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
  1244. PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
  1245. PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
  1246. PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
  1247. PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
  1248. PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
  1249. PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
  1250. PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
  1251. PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
  1252. PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
  1253. PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
  1254. PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
  1255. PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
  1256. PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
  1257. PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
  1258. PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
  1259. PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
  1260. PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
  1261. /* IPSR12 */
  1262. PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
  1263. PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
  1264. PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
  1265. PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
  1266. PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
  1267. PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
  1268. PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
  1269. PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
  1270. PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
  1271. PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
  1272. PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
  1273. PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
  1274. PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
  1275. PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
  1276. PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
  1277. PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
  1278. PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
  1279. PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
  1280. PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
  1281. PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
  1282. PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
  1283. PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
  1284. PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
  1285. PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
  1286. PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
  1287. PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
  1288. PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
  1289. PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
  1290. PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
  1291. PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
  1292. PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
  1293. PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
  1294. PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
  1295. PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
  1296. PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
  1297. PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
  1298. PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
  1299. PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
  1300. PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
  1301. PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
  1302. PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
  1303. PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
  1304. PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
  1305. PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
  1306. PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
  1307. PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
  1308. PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
  1309. PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
  1310. PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
  1311. PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
  1312. PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
  1313. PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
  1314. PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
  1315. PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
  1316. PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
  1317. /* IPSR13 */
  1318. PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
  1319. PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
  1320. PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
  1321. PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
  1322. PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
  1323. PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
  1324. PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
  1325. PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
  1326. PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
  1327. PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
  1328. PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
  1329. PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
  1330. PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
  1331. PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
  1332. PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
  1333. PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
  1334. PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
  1335. PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
  1336. PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
  1337. PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
  1338. PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
  1339. PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
  1340. PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
  1341. PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
  1342. PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
  1343. PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
  1344. PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
  1345. PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
  1346. PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
  1347. PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
  1348. PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
  1349. PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
  1350. PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
  1351. PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
  1352. PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
  1353. PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
  1354. PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
  1355. PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
  1356. PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
  1357. PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
  1358. PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
  1359. PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
  1360. PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
  1361. PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
  1362. PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
  1363. PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
  1364. PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
  1365. PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
  1366. PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
  1367. PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
  1368. PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
  1369. PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
  1370. PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
  1371. PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
  1372. PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
  1373. };
  1374. static const struct sh_pfc_pin pinmux_pins[] = {
  1375. PINMUX_GPIO_GP_ALL(),
  1376. };
  1377. /* - Audio Clock ------------------------------------------------------------ */
  1378. static const unsigned int audio_clka_pins[] = {
  1379. /* CLKA */
  1380. RCAR_GP_PIN(5, 20),
  1381. };
  1382. static const unsigned int audio_clka_mux[] = {
  1383. AUDIO_CLKA_MARK,
  1384. };
  1385. static const unsigned int audio_clka_b_pins[] = {
  1386. /* CLKA */
  1387. RCAR_GP_PIN(3, 25),
  1388. };
  1389. static const unsigned int audio_clka_b_mux[] = {
  1390. AUDIO_CLKA_B_MARK,
  1391. };
  1392. static const unsigned int audio_clka_c_pins[] = {
  1393. /* CLKA */
  1394. RCAR_GP_PIN(4, 20),
  1395. };
  1396. static const unsigned int audio_clka_c_mux[] = {
  1397. AUDIO_CLKA_C_MARK,
  1398. };
  1399. static const unsigned int audio_clka_d_pins[] = {
  1400. /* CLKA */
  1401. RCAR_GP_PIN(5, 0),
  1402. };
  1403. static const unsigned int audio_clka_d_mux[] = {
  1404. AUDIO_CLKA_D_MARK,
  1405. };
  1406. static const unsigned int audio_clkb_pins[] = {
  1407. /* CLKB */
  1408. RCAR_GP_PIN(5, 21),
  1409. };
  1410. static const unsigned int audio_clkb_mux[] = {
  1411. AUDIO_CLKB_MARK,
  1412. };
  1413. static const unsigned int audio_clkb_b_pins[] = {
  1414. /* CLKB */
  1415. RCAR_GP_PIN(3, 26),
  1416. };
  1417. static const unsigned int audio_clkb_b_mux[] = {
  1418. AUDIO_CLKB_B_MARK,
  1419. };
  1420. static const unsigned int audio_clkb_c_pins[] = {
  1421. /* CLKB */
  1422. RCAR_GP_PIN(4, 21),
  1423. };
  1424. static const unsigned int audio_clkb_c_mux[] = {
  1425. AUDIO_CLKB_C_MARK,
  1426. };
  1427. static const unsigned int audio_clkc_pins[] = {
  1428. /* CLKC */
  1429. RCAR_GP_PIN(5, 22),
  1430. };
  1431. static const unsigned int audio_clkc_mux[] = {
  1432. AUDIO_CLKC_MARK,
  1433. };
  1434. static const unsigned int audio_clkc_b_pins[] = {
  1435. /* CLKC */
  1436. RCAR_GP_PIN(3, 29),
  1437. };
  1438. static const unsigned int audio_clkc_b_mux[] = {
  1439. AUDIO_CLKC_B_MARK,
  1440. };
  1441. static const unsigned int audio_clkc_c_pins[] = {
  1442. /* CLKC */
  1443. RCAR_GP_PIN(4, 22),
  1444. };
  1445. static const unsigned int audio_clkc_c_mux[] = {
  1446. AUDIO_CLKC_C_MARK,
  1447. };
  1448. static const unsigned int audio_clkout_pins[] = {
  1449. /* CLKOUT */
  1450. RCAR_GP_PIN(5, 23),
  1451. };
  1452. static const unsigned int audio_clkout_mux[] = {
  1453. AUDIO_CLKOUT_MARK,
  1454. };
  1455. static const unsigned int audio_clkout_b_pins[] = {
  1456. /* CLKOUT */
  1457. RCAR_GP_PIN(3, 12),
  1458. };
  1459. static const unsigned int audio_clkout_b_mux[] = {
  1460. AUDIO_CLKOUT_B_MARK,
  1461. };
  1462. static const unsigned int audio_clkout_c_pins[] = {
  1463. /* CLKOUT */
  1464. RCAR_GP_PIN(4, 23),
  1465. };
  1466. static const unsigned int audio_clkout_c_mux[] = {
  1467. AUDIO_CLKOUT_C_MARK,
  1468. };
  1469. /* - AVB -------------------------------------------------------------------- */
  1470. static const unsigned int avb_link_pins[] = {
  1471. RCAR_GP_PIN(3, 26),
  1472. };
  1473. static const unsigned int avb_link_mux[] = {
  1474. AVB_LINK_MARK,
  1475. };
  1476. static const unsigned int avb_magic_pins[] = {
  1477. RCAR_GP_PIN(3, 27),
  1478. };
  1479. static const unsigned int avb_magic_mux[] = {
  1480. AVB_MAGIC_MARK,
  1481. };
  1482. static const unsigned int avb_phy_int_pins[] = {
  1483. RCAR_GP_PIN(3, 28),
  1484. };
  1485. static const unsigned int avb_phy_int_mux[] = {
  1486. AVB_PHY_INT_MARK,
  1487. };
  1488. static const unsigned int avb_mdio_pins[] = {
  1489. RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
  1490. };
  1491. static const unsigned int avb_mdio_mux[] = {
  1492. AVB_MDC_MARK, AVB_MDIO_MARK,
  1493. };
  1494. static const unsigned int avb_mii_pins[] = {
  1495. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  1496. RCAR_GP_PIN(3, 17),
  1497. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  1498. RCAR_GP_PIN(3, 5),
  1499. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  1500. RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
  1501. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
  1502. };
  1503. static const unsigned int avb_mii_mux[] = {
  1504. AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
  1505. AVB_TXD3_MARK,
  1506. AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1507. AVB_RXD3_MARK,
  1508. AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
  1509. AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
  1510. AVB_TX_CLK_MARK, AVB_COL_MARK,
  1511. };
  1512. static const unsigned int avb_gmii_pins[] = {
  1513. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  1514. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
  1515. RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  1516. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  1517. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  1518. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1519. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  1520. RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
  1521. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
  1522. RCAR_GP_PIN(3, 11),
  1523. };
  1524. static const unsigned int avb_gmii_mux[] = {
  1525. AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
  1526. AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
  1527. AVB_TXD6_MARK, AVB_TXD7_MARK,
  1528. AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1529. AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
  1530. AVB_RXD6_MARK, AVB_RXD7_MARK,
  1531. AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
  1532. AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
  1533. AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
  1534. AVB_COL_MARK,
  1535. };
  1536. /* - CAN -------------------------------------------------------------------- */
  1537. static const unsigned int can0_data_pins[] = {
  1538. /* TX, RX */
  1539. RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
  1540. };
  1541. static const unsigned int can0_data_mux[] = {
  1542. CAN0_TX_MARK, CAN0_RX_MARK,
  1543. };
  1544. static const unsigned int can0_data_b_pins[] = {
  1545. /* TX, RX */
  1546. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
  1547. };
  1548. static const unsigned int can0_data_b_mux[] = {
  1549. CAN0_TX_B_MARK, CAN0_RX_B_MARK,
  1550. };
  1551. static const unsigned int can0_data_c_pins[] = {
  1552. /* TX, RX */
  1553. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
  1554. };
  1555. static const unsigned int can0_data_c_mux[] = {
  1556. CAN0_TX_C_MARK, CAN0_RX_C_MARK,
  1557. };
  1558. static const unsigned int can0_data_d_pins[] = {
  1559. /* TX, RX */
  1560. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
  1561. };
  1562. static const unsigned int can0_data_d_mux[] = {
  1563. CAN0_TX_D_MARK, CAN0_RX_D_MARK,
  1564. };
  1565. static const unsigned int can1_data_pins[] = {
  1566. /* TX, RX */
  1567. RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
  1568. };
  1569. static const unsigned int can1_data_mux[] = {
  1570. CAN1_TX_MARK, CAN1_RX_MARK,
  1571. };
  1572. static const unsigned int can1_data_b_pins[] = {
  1573. /* TX, RX */
  1574. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
  1575. };
  1576. static const unsigned int can1_data_b_mux[] = {
  1577. CAN1_TX_B_MARK, CAN1_RX_B_MARK,
  1578. };
  1579. static const unsigned int can1_data_c_pins[] = {
  1580. /* TX, RX */
  1581. RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
  1582. };
  1583. static const unsigned int can1_data_c_mux[] = {
  1584. CAN1_TX_C_MARK, CAN1_RX_C_MARK,
  1585. };
  1586. static const unsigned int can1_data_d_pins[] = {
  1587. /* TX, RX */
  1588. RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
  1589. };
  1590. static const unsigned int can1_data_d_mux[] = {
  1591. CAN1_TX_D_MARK, CAN1_RX_D_MARK,
  1592. };
  1593. static const unsigned int can_clk_pins[] = {
  1594. /* CLK */
  1595. RCAR_GP_PIN(3, 31),
  1596. };
  1597. static const unsigned int can_clk_mux[] = {
  1598. CAN_CLK_MARK,
  1599. };
  1600. static const unsigned int can_clk_b_pins[] = {
  1601. /* CLK */
  1602. RCAR_GP_PIN(1, 23),
  1603. };
  1604. static const unsigned int can_clk_b_mux[] = {
  1605. CAN_CLK_B_MARK,
  1606. };
  1607. static const unsigned int can_clk_c_pins[] = {
  1608. /* CLK */
  1609. RCAR_GP_PIN(1, 0),
  1610. };
  1611. static const unsigned int can_clk_c_mux[] = {
  1612. CAN_CLK_C_MARK,
  1613. };
  1614. static const unsigned int can_clk_d_pins[] = {
  1615. /* CLK */
  1616. RCAR_GP_PIN(5, 0),
  1617. };
  1618. static const unsigned int can_clk_d_mux[] = {
  1619. CAN_CLK_D_MARK,
  1620. };
  1621. /* - DU --------------------------------------------------------------------- */
  1622. static const unsigned int du0_rgb666_pins[] = {
  1623. /* R[7:2], G[7:2], B[7:2] */
  1624. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
  1625. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
  1626. RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  1627. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1628. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
  1629. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
  1630. };
  1631. static const unsigned int du0_rgb666_mux[] = {
  1632. DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
  1633. DU0_DR3_MARK, DU0_DR2_MARK,
  1634. DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
  1635. DU0_DG3_MARK, DU0_DG2_MARK,
  1636. DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
  1637. DU0_DB3_MARK, DU0_DB2_MARK,
  1638. };
  1639. static const unsigned int du0_rgb888_pins[] = {
  1640. /* R[7:0], G[7:0], B[7:0] */
  1641. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
  1642. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
  1643. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
  1644. RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  1645. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1646. RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
  1647. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
  1648. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
  1649. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
  1650. };
  1651. static const unsigned int du0_rgb888_mux[] = {
  1652. DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
  1653. DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
  1654. DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
  1655. DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
  1656. DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
  1657. DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
  1658. };
  1659. static const unsigned int du0_clk0_out_pins[] = {
  1660. /* DOTCLKOUT0 */
  1661. RCAR_GP_PIN(2, 25),
  1662. };
  1663. static const unsigned int du0_clk0_out_mux[] = {
  1664. DU0_DOTCLKOUT0_MARK
  1665. };
  1666. static const unsigned int du0_clk1_out_pins[] = {
  1667. /* DOTCLKOUT1 */
  1668. RCAR_GP_PIN(2, 26),
  1669. };
  1670. static const unsigned int du0_clk1_out_mux[] = {
  1671. DU0_DOTCLKOUT1_MARK
  1672. };
  1673. static const unsigned int du0_clk_in_pins[] = {
  1674. /* CLKIN */
  1675. RCAR_GP_PIN(2, 24),
  1676. };
  1677. static const unsigned int du0_clk_in_mux[] = {
  1678. DU0_DOTCLKIN_MARK
  1679. };
  1680. static const unsigned int du0_sync_pins[] = {
  1681. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1682. RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
  1683. };
  1684. static const unsigned int du0_sync_mux[] = {
  1685. DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
  1686. };
  1687. static const unsigned int du0_oddf_pins[] = {
  1688. /* EXODDF/ODDF/DISP/CDE */
  1689. RCAR_GP_PIN(2, 29),
  1690. };
  1691. static const unsigned int du0_oddf_mux[] = {
  1692. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
  1693. };
  1694. static const unsigned int du0_cde_pins[] = {
  1695. /* CDE */
  1696. RCAR_GP_PIN(2, 31),
  1697. };
  1698. static const unsigned int du0_cde_mux[] = {
  1699. DU0_CDE_MARK,
  1700. };
  1701. static const unsigned int du0_disp_pins[] = {
  1702. /* DISP */
  1703. RCAR_GP_PIN(2, 30),
  1704. };
  1705. static const unsigned int du0_disp_mux[] = {
  1706. DU0_DISP_MARK
  1707. };
  1708. static const unsigned int du1_rgb666_pins[] = {
  1709. /* R[7:2], G[7:2], B[7:2] */
  1710. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
  1711. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1712. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
  1713. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
  1714. RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
  1715. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
  1716. };
  1717. static const unsigned int du1_rgb666_mux[] = {
  1718. DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
  1719. DU1_DR3_MARK, DU1_DR2_MARK,
  1720. DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
  1721. DU1_DG3_MARK, DU1_DG2_MARK,
  1722. DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
  1723. DU1_DB3_MARK, DU1_DB2_MARK,
  1724. };
  1725. static const unsigned int du1_rgb888_pins[] = {
  1726. /* R[7:0], G[7:0], B[7:0] */
  1727. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
  1728. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1729. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
  1730. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
  1731. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
  1732. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
  1733. RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
  1734. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
  1735. RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
  1736. };
  1737. static const unsigned int du1_rgb888_mux[] = {
  1738. DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
  1739. DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
  1740. DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
  1741. DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
  1742. DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
  1743. DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
  1744. };
  1745. static const unsigned int du1_clk0_out_pins[] = {
  1746. /* DOTCLKOUT0 */
  1747. RCAR_GP_PIN(4, 25),
  1748. };
  1749. static const unsigned int du1_clk0_out_mux[] = {
  1750. DU1_DOTCLKOUT0_MARK
  1751. };
  1752. static const unsigned int du1_clk1_out_pins[] = {
  1753. /* DOTCLKOUT1 */
  1754. RCAR_GP_PIN(4, 26),
  1755. };
  1756. static const unsigned int du1_clk1_out_mux[] = {
  1757. DU1_DOTCLKOUT1_MARK
  1758. };
  1759. static const unsigned int du1_clk_in_pins[] = {
  1760. /* DOTCLKIN */
  1761. RCAR_GP_PIN(4, 24),
  1762. };
  1763. static const unsigned int du1_clk_in_mux[] = {
  1764. DU1_DOTCLKIN_MARK
  1765. };
  1766. static const unsigned int du1_sync_pins[] = {
  1767. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1768. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
  1769. };
  1770. static const unsigned int du1_sync_mux[] = {
  1771. DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
  1772. };
  1773. static const unsigned int du1_oddf_pins[] = {
  1774. /* EXODDF/ODDF/DISP/CDE */
  1775. RCAR_GP_PIN(4, 29),
  1776. };
  1777. static const unsigned int du1_oddf_mux[] = {
  1778. DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
  1779. };
  1780. static const unsigned int du1_cde_pins[] = {
  1781. /* CDE */
  1782. RCAR_GP_PIN(4, 31),
  1783. };
  1784. static const unsigned int du1_cde_mux[] = {
  1785. DU1_CDE_MARK
  1786. };
  1787. static const unsigned int du1_disp_pins[] = {
  1788. /* DISP */
  1789. RCAR_GP_PIN(4, 30),
  1790. };
  1791. static const unsigned int du1_disp_mux[] = {
  1792. DU1_DISP_MARK
  1793. };
  1794. /* - ETH -------------------------------------------------------------------- */
  1795. static const unsigned int eth_link_pins[] = {
  1796. /* LINK */
  1797. RCAR_GP_PIN(3, 18),
  1798. };
  1799. static const unsigned int eth_link_mux[] = {
  1800. ETH_LINK_MARK,
  1801. };
  1802. static const unsigned int eth_magic_pins[] = {
  1803. /* MAGIC */
  1804. RCAR_GP_PIN(3, 22),
  1805. };
  1806. static const unsigned int eth_magic_mux[] = {
  1807. ETH_MAGIC_MARK,
  1808. };
  1809. static const unsigned int eth_mdio_pins[] = {
  1810. /* MDC, MDIO */
  1811. RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
  1812. };
  1813. static const unsigned int eth_mdio_mux[] = {
  1814. ETH_MDC_MARK, ETH_MDIO_MARK,
  1815. };
  1816. static const unsigned int eth_rmii_pins[] = {
  1817. /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
  1818. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
  1819. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
  1820. RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
  1821. };
  1822. static const unsigned int eth_rmii_mux[] = {
  1823. ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
  1824. ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
  1825. };
  1826. static const unsigned int eth_link_b_pins[] = {
  1827. /* LINK */
  1828. RCAR_GP_PIN(5, 15),
  1829. };
  1830. static const unsigned int eth_link_b_mux[] = {
  1831. ETH_LINK_B_MARK,
  1832. };
  1833. static const unsigned int eth_magic_b_pins[] = {
  1834. /* MAGIC */
  1835. RCAR_GP_PIN(5, 19),
  1836. };
  1837. static const unsigned int eth_magic_b_mux[] = {
  1838. ETH_MAGIC_B_MARK,
  1839. };
  1840. static const unsigned int eth_mdio_b_pins[] = {
  1841. /* MDC, MDIO */
  1842. RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
  1843. };
  1844. static const unsigned int eth_mdio_b_mux[] = {
  1845. ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
  1846. };
  1847. static const unsigned int eth_rmii_b_pins[] = {
  1848. /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
  1849. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
  1850. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
  1851. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
  1852. };
  1853. static const unsigned int eth_rmii_b_mux[] = {
  1854. ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
  1855. ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
  1856. };
  1857. /* - HSCIF0 ----------------------------------------------------------------- */
  1858. static const unsigned int hscif0_data_pins[] = {
  1859. /* RX, TX */
  1860. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  1861. };
  1862. static const unsigned int hscif0_data_mux[] = {
  1863. HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
  1864. };
  1865. static const unsigned int hscif0_clk_pins[] = {
  1866. /* SCK */
  1867. RCAR_GP_PIN(3, 29),
  1868. };
  1869. static const unsigned int hscif0_clk_mux[] = {
  1870. HSCIF0_HSCK_MARK,
  1871. };
  1872. static const unsigned int hscif0_ctrl_pins[] = {
  1873. /* RTS, CTS */
  1874. RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
  1875. };
  1876. static const unsigned int hscif0_ctrl_mux[] = {
  1877. HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
  1878. };
  1879. static const unsigned int hscif0_data_b_pins[] = {
  1880. /* RX, TX */
  1881. RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
  1882. };
  1883. static const unsigned int hscif0_data_b_mux[] = {
  1884. HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
  1885. };
  1886. static const unsigned int hscif0_clk_b_pins[] = {
  1887. /* SCK */
  1888. RCAR_GP_PIN(1, 0),
  1889. };
  1890. static const unsigned int hscif0_clk_b_mux[] = {
  1891. HSCIF0_HSCK_B_MARK,
  1892. };
  1893. /* - HSCIF1 ----------------------------------------------------------------- */
  1894. static const unsigned int hscif1_data_pins[] = {
  1895. /* RX, TX */
  1896. RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
  1897. };
  1898. static const unsigned int hscif1_data_mux[] = {
  1899. HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
  1900. };
  1901. static const unsigned int hscif1_clk_pins[] = {
  1902. /* SCK */
  1903. RCAR_GP_PIN(4, 10),
  1904. };
  1905. static const unsigned int hscif1_clk_mux[] = {
  1906. HSCIF1_HSCK_MARK,
  1907. };
  1908. static const unsigned int hscif1_ctrl_pins[] = {
  1909. /* RTS, CTS */
  1910. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
  1911. };
  1912. static const unsigned int hscif1_ctrl_mux[] = {
  1913. HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
  1914. };
  1915. static const unsigned int hscif1_data_b_pins[] = {
  1916. /* RX, TX */
  1917. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  1918. };
  1919. static const unsigned int hscif1_data_b_mux[] = {
  1920. HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
  1921. };
  1922. static const unsigned int hscif1_ctrl_b_pins[] = {
  1923. /* RTS, CTS */
  1924. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
  1925. };
  1926. static const unsigned int hscif1_ctrl_b_mux[] = {
  1927. HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
  1928. };
  1929. /* - HSCIF2 ----------------------------------------------------------------- */
  1930. static const unsigned int hscif2_data_pins[] = {
  1931. /* RX, TX */
  1932. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  1933. };
  1934. static const unsigned int hscif2_data_mux[] = {
  1935. HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
  1936. };
  1937. static const unsigned int hscif2_clk_pins[] = {
  1938. /* SCK */
  1939. RCAR_GP_PIN(0, 10),
  1940. };
  1941. static const unsigned int hscif2_clk_mux[] = {
  1942. HSCIF2_HSCK_MARK,
  1943. };
  1944. static const unsigned int hscif2_ctrl_pins[] = {
  1945. /* RTS, CTS */
  1946. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
  1947. };
  1948. static const unsigned int hscif2_ctrl_mux[] = {
  1949. HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
  1950. };
  1951. /* - I2C0 ------------------------------------------------------------------- */
  1952. static const unsigned int i2c0_pins[] = {
  1953. /* SCL, SDA */
  1954. RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
  1955. };
  1956. static const unsigned int i2c0_mux[] = {
  1957. I2C0_SCL_MARK, I2C0_SDA_MARK,
  1958. };
  1959. static const unsigned int i2c0_b_pins[] = {
  1960. /* SCL, SDA */
  1961. RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
  1962. };
  1963. static const unsigned int i2c0_b_mux[] = {
  1964. I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
  1965. };
  1966. static const unsigned int i2c0_c_pins[] = {
  1967. /* SCL, SDA */
  1968. RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  1969. };
  1970. static const unsigned int i2c0_c_mux[] = {
  1971. I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
  1972. };
  1973. static const unsigned int i2c0_d_pins[] = {
  1974. /* SCL, SDA */
  1975. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  1976. };
  1977. static const unsigned int i2c0_d_mux[] = {
  1978. I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
  1979. };
  1980. static const unsigned int i2c0_e_pins[] = {
  1981. /* SCL, SDA */
  1982. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  1983. };
  1984. static const unsigned int i2c0_e_mux[] = {
  1985. I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
  1986. };
  1987. /* - I2C1 ------------------------------------------------------------------- */
  1988. static const unsigned int i2c1_pins[] = {
  1989. /* SCL, SDA */
  1990. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  1991. };
  1992. static const unsigned int i2c1_mux[] = {
  1993. I2C1_SCL_MARK, I2C1_SDA_MARK,
  1994. };
  1995. static const unsigned int i2c1_b_pins[] = {
  1996. /* SCL, SDA */
  1997. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  1998. };
  1999. static const unsigned int i2c1_b_mux[] = {
  2000. I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
  2001. };
  2002. static const unsigned int i2c1_c_pins[] = {
  2003. /* SCL, SDA */
  2004. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  2005. };
  2006. static const unsigned int i2c1_c_mux[] = {
  2007. I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
  2008. };
  2009. static const unsigned int i2c1_d_pins[] = {
  2010. /* SCL, SDA */
  2011. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
  2012. };
  2013. static const unsigned int i2c1_d_mux[] = {
  2014. I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
  2015. };
  2016. static const unsigned int i2c1_e_pins[] = {
  2017. /* SCL, SDA */
  2018. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
  2019. };
  2020. static const unsigned int i2c1_e_mux[] = {
  2021. I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
  2022. };
  2023. /* - I2C2 ------------------------------------------------------------------- */
  2024. static const unsigned int i2c2_pins[] = {
  2025. /* SCL, SDA */
  2026. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
  2027. };
  2028. static const unsigned int i2c2_mux[] = {
  2029. I2C2_SCL_MARK, I2C2_SDA_MARK,
  2030. };
  2031. static const unsigned int i2c2_b_pins[] = {
  2032. /* SCL, SDA */
  2033. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  2034. };
  2035. static const unsigned int i2c2_b_mux[] = {
  2036. I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
  2037. };
  2038. static const unsigned int i2c2_c_pins[] = {
  2039. /* SCL, SDA */
  2040. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  2041. };
  2042. static const unsigned int i2c2_c_mux[] = {
  2043. I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
  2044. };
  2045. static const unsigned int i2c2_d_pins[] = {
  2046. /* SCL, SDA */
  2047. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  2048. };
  2049. static const unsigned int i2c2_d_mux[] = {
  2050. I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
  2051. };
  2052. static const unsigned int i2c2_e_pins[] = {
  2053. /* SCL, SDA */
  2054. RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
  2055. };
  2056. static const unsigned int i2c2_e_mux[] = {
  2057. I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
  2058. };
  2059. /* - I2C3 ------------------------------------------------------------------- */
  2060. static const unsigned int i2c3_pins[] = {
  2061. /* SCL, SDA */
  2062. RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
  2063. };
  2064. static const unsigned int i2c3_mux[] = {
  2065. I2C3_SCL_MARK, I2C3_SDA_MARK,
  2066. };
  2067. static const unsigned int i2c3_b_pins[] = {
  2068. /* SCL, SDA */
  2069. RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
  2070. };
  2071. static const unsigned int i2c3_b_mux[] = {
  2072. I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
  2073. };
  2074. static const unsigned int i2c3_c_pins[] = {
  2075. /* SCL, SDA */
  2076. RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
  2077. };
  2078. static const unsigned int i2c3_c_mux[] = {
  2079. I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
  2080. };
  2081. static const unsigned int i2c3_d_pins[] = {
  2082. /* SCL, SDA */
  2083. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  2084. };
  2085. static const unsigned int i2c3_d_mux[] = {
  2086. I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
  2087. };
  2088. static const unsigned int i2c3_e_pins[] = {
  2089. /* SCL, SDA */
  2090. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
  2091. };
  2092. static const unsigned int i2c3_e_mux[] = {
  2093. I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
  2094. };
  2095. /* - I2C4 ------------------------------------------------------------------- */
  2096. static const unsigned int i2c4_pins[] = {
  2097. /* SCL, SDA */
  2098. RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
  2099. };
  2100. static const unsigned int i2c4_mux[] = {
  2101. I2C4_SCL_MARK, I2C4_SDA_MARK,
  2102. };
  2103. static const unsigned int i2c4_b_pins[] = {
  2104. /* SCL, SDA */
  2105. RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
  2106. };
  2107. static const unsigned int i2c4_b_mux[] = {
  2108. I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
  2109. };
  2110. static const unsigned int i2c4_c_pins[] = {
  2111. /* SCL, SDA */
  2112. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
  2113. };
  2114. static const unsigned int i2c4_c_mux[] = {
  2115. I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
  2116. };
  2117. static const unsigned int i2c4_d_pins[] = {
  2118. /* SCL, SDA */
  2119. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
  2120. };
  2121. static const unsigned int i2c4_d_mux[] = {
  2122. I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
  2123. };
  2124. static const unsigned int i2c4_e_pins[] = {
  2125. /* SCL, SDA */
  2126. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  2127. };
  2128. static const unsigned int i2c4_e_mux[] = {
  2129. I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
  2130. };
  2131. /* - I2C5 ------------------------------------------------------------------- */
  2132. static const unsigned int i2c5_pins[] = {
  2133. /* SCL, SDA */
  2134. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  2135. };
  2136. static const unsigned int i2c5_mux[] = {
  2137. I2C5_SCL_MARK, I2C5_SDA_MARK,
  2138. };
  2139. static const unsigned int i2c5_b_pins[] = {
  2140. /* SCL, SDA */
  2141. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2142. };
  2143. static const unsigned int i2c5_b_mux[] = {
  2144. I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
  2145. };
  2146. static const unsigned int i2c5_c_pins[] = {
  2147. /* SCL, SDA */
  2148. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
  2149. };
  2150. static const unsigned int i2c5_c_mux[] = {
  2151. I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
  2152. };
  2153. static const unsigned int i2c5_d_pins[] = {
  2154. /* SCL, SDA */
  2155. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  2156. };
  2157. static const unsigned int i2c5_d_mux[] = {
  2158. I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
  2159. };
  2160. /* - INTC ------------------------------------------------------------------- */
  2161. static const unsigned int intc_irq0_pins[] = {
  2162. /* IRQ0 */
  2163. RCAR_GP_PIN(4, 4),
  2164. };
  2165. static const unsigned int intc_irq0_mux[] = {
  2166. IRQ0_MARK,
  2167. };
  2168. static const unsigned int intc_irq1_pins[] = {
  2169. /* IRQ1 */
  2170. RCAR_GP_PIN(4, 18),
  2171. };
  2172. static const unsigned int intc_irq1_mux[] = {
  2173. IRQ1_MARK,
  2174. };
  2175. static const unsigned int intc_irq2_pins[] = {
  2176. /* IRQ2 */
  2177. RCAR_GP_PIN(4, 19),
  2178. };
  2179. static const unsigned int intc_irq2_mux[] = {
  2180. IRQ2_MARK,
  2181. };
  2182. static const unsigned int intc_irq3_pins[] = {
  2183. /* IRQ3 */
  2184. RCAR_GP_PIN(0, 7),
  2185. };
  2186. static const unsigned int intc_irq3_mux[] = {
  2187. IRQ3_MARK,
  2188. };
  2189. static const unsigned int intc_irq4_pins[] = {
  2190. /* IRQ4 */
  2191. RCAR_GP_PIN(0, 0),
  2192. };
  2193. static const unsigned int intc_irq4_mux[] = {
  2194. IRQ4_MARK,
  2195. };
  2196. static const unsigned int intc_irq5_pins[] = {
  2197. /* IRQ5 */
  2198. RCAR_GP_PIN(4, 1),
  2199. };
  2200. static const unsigned int intc_irq5_mux[] = {
  2201. IRQ5_MARK,
  2202. };
  2203. static const unsigned int intc_irq6_pins[] = {
  2204. /* IRQ6 */
  2205. RCAR_GP_PIN(0, 10),
  2206. };
  2207. static const unsigned int intc_irq6_mux[] = {
  2208. IRQ6_MARK,
  2209. };
  2210. static const unsigned int intc_irq7_pins[] = {
  2211. /* IRQ7 */
  2212. RCAR_GP_PIN(6, 15),
  2213. };
  2214. static const unsigned int intc_irq7_mux[] = {
  2215. IRQ7_MARK,
  2216. };
  2217. static const unsigned int intc_irq8_pins[] = {
  2218. /* IRQ8 */
  2219. RCAR_GP_PIN(5, 0),
  2220. };
  2221. static const unsigned int intc_irq8_mux[] = {
  2222. IRQ8_MARK,
  2223. };
  2224. static const unsigned int intc_irq9_pins[] = {
  2225. /* IRQ9 */
  2226. RCAR_GP_PIN(5, 10),
  2227. };
  2228. static const unsigned int intc_irq9_mux[] = {
  2229. IRQ9_MARK,
  2230. };
  2231. /* - MMCIF ------------------------------------------------------------------ */
  2232. static const unsigned int mmc_data1_pins[] = {
  2233. /* D[0] */
  2234. RCAR_GP_PIN(6, 18),
  2235. };
  2236. static const unsigned int mmc_data1_mux[] = {
  2237. MMC_D0_MARK,
  2238. };
  2239. static const unsigned int mmc_data4_pins[] = {
  2240. /* D[0:3] */
  2241. RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
  2242. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
  2243. };
  2244. static const unsigned int mmc_data4_mux[] = {
  2245. MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
  2246. };
  2247. static const unsigned int mmc_data8_pins[] = {
  2248. /* D[0:7] */
  2249. RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
  2250. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
  2251. RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
  2252. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  2253. };
  2254. static const unsigned int mmc_data8_mux[] = {
  2255. MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
  2256. MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
  2257. };
  2258. static const unsigned int mmc_ctrl_pins[] = {
  2259. /* CLK, CMD */
  2260. RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
  2261. };
  2262. static const unsigned int mmc_ctrl_mux[] = {
  2263. MMC_CLK_MARK, MMC_CMD_MARK,
  2264. };
  2265. /* - MSIOF0 ----------------------------------------------------------------- */
  2266. static const unsigned int msiof0_clk_pins[] = {
  2267. /* SCK */
  2268. RCAR_GP_PIN(4, 4),
  2269. };
  2270. static const unsigned int msiof0_clk_mux[] = {
  2271. MSIOF0_SCK_MARK,
  2272. };
  2273. static const unsigned int msiof0_sync_pins[] = {
  2274. /* SYNC */
  2275. RCAR_GP_PIN(4, 5),
  2276. };
  2277. static const unsigned int msiof0_sync_mux[] = {
  2278. MSIOF0_SYNC_MARK,
  2279. };
  2280. static const unsigned int msiof0_ss1_pins[] = {
  2281. /* SS1 */
  2282. RCAR_GP_PIN(4, 6),
  2283. };
  2284. static const unsigned int msiof0_ss1_mux[] = {
  2285. MSIOF0_SS1_MARK,
  2286. };
  2287. static const unsigned int msiof0_ss2_pins[] = {
  2288. /* SS2 */
  2289. RCAR_GP_PIN(4, 7),
  2290. };
  2291. static const unsigned int msiof0_ss2_mux[] = {
  2292. MSIOF0_SS2_MARK,
  2293. };
  2294. static const unsigned int msiof0_rx_pins[] = {
  2295. /* RXD */
  2296. RCAR_GP_PIN(4, 2),
  2297. };
  2298. static const unsigned int msiof0_rx_mux[] = {
  2299. MSIOF0_RXD_MARK,
  2300. };
  2301. static const unsigned int msiof0_tx_pins[] = {
  2302. /* TXD */
  2303. RCAR_GP_PIN(4, 3),
  2304. };
  2305. static const unsigned int msiof0_tx_mux[] = {
  2306. MSIOF0_TXD_MARK,
  2307. };
  2308. /* - MSIOF1 ----------------------------------------------------------------- */
  2309. static const unsigned int msiof1_clk_pins[] = {
  2310. /* SCK */
  2311. RCAR_GP_PIN(0, 26),
  2312. };
  2313. static const unsigned int msiof1_clk_mux[] = {
  2314. MSIOF1_SCK_MARK,
  2315. };
  2316. static const unsigned int msiof1_sync_pins[] = {
  2317. /* SYNC */
  2318. RCAR_GP_PIN(0, 27),
  2319. };
  2320. static const unsigned int msiof1_sync_mux[] = {
  2321. MSIOF1_SYNC_MARK,
  2322. };
  2323. static const unsigned int msiof1_ss1_pins[] = {
  2324. /* SS1 */
  2325. RCAR_GP_PIN(0, 28),
  2326. };
  2327. static const unsigned int msiof1_ss1_mux[] = {
  2328. MSIOF1_SS1_MARK,
  2329. };
  2330. static const unsigned int msiof1_ss2_pins[] = {
  2331. /* SS2 */
  2332. RCAR_GP_PIN(0, 29),
  2333. };
  2334. static const unsigned int msiof1_ss2_mux[] = {
  2335. MSIOF1_SS2_MARK,
  2336. };
  2337. static const unsigned int msiof1_rx_pins[] = {
  2338. /* RXD */
  2339. RCAR_GP_PIN(0, 24),
  2340. };
  2341. static const unsigned int msiof1_rx_mux[] = {
  2342. MSIOF1_RXD_MARK,
  2343. };
  2344. static const unsigned int msiof1_tx_pins[] = {
  2345. /* TXD */
  2346. RCAR_GP_PIN(0, 25),
  2347. };
  2348. static const unsigned int msiof1_tx_mux[] = {
  2349. MSIOF1_TXD_MARK,
  2350. };
  2351. static const unsigned int msiof1_clk_b_pins[] = {
  2352. /* SCK */
  2353. RCAR_GP_PIN(5, 3),
  2354. };
  2355. static const unsigned int msiof1_clk_b_mux[] = {
  2356. MSIOF1_SCK_B_MARK,
  2357. };
  2358. static const unsigned int msiof1_sync_b_pins[] = {
  2359. /* SYNC */
  2360. RCAR_GP_PIN(5, 4),
  2361. };
  2362. static const unsigned int msiof1_sync_b_mux[] = {
  2363. MSIOF1_SYNC_B_MARK,
  2364. };
  2365. static const unsigned int msiof1_ss1_b_pins[] = {
  2366. /* SS1 */
  2367. RCAR_GP_PIN(5, 5),
  2368. };
  2369. static const unsigned int msiof1_ss1_b_mux[] = {
  2370. MSIOF1_SS1_B_MARK,
  2371. };
  2372. static const unsigned int msiof1_ss2_b_pins[] = {
  2373. /* SS2 */
  2374. RCAR_GP_PIN(5, 6),
  2375. };
  2376. static const unsigned int msiof1_ss2_b_mux[] = {
  2377. MSIOF1_SS2_B_MARK,
  2378. };
  2379. static const unsigned int msiof1_rx_b_pins[] = {
  2380. /* RXD */
  2381. RCAR_GP_PIN(5, 1),
  2382. };
  2383. static const unsigned int msiof1_rx_b_mux[] = {
  2384. MSIOF1_RXD_B_MARK,
  2385. };
  2386. static const unsigned int msiof1_tx_b_pins[] = {
  2387. /* TXD */
  2388. RCAR_GP_PIN(5, 2),
  2389. };
  2390. static const unsigned int msiof1_tx_b_mux[] = {
  2391. MSIOF1_TXD_B_MARK,
  2392. };
  2393. /* - MSIOF2 ----------------------------------------------------------------- */
  2394. static const unsigned int msiof2_clk_pins[] = {
  2395. /* SCK */
  2396. RCAR_GP_PIN(1, 0),
  2397. };
  2398. static const unsigned int msiof2_clk_mux[] = {
  2399. MSIOF2_SCK_MARK,
  2400. };
  2401. static const unsigned int msiof2_sync_pins[] = {
  2402. /* SYNC */
  2403. RCAR_GP_PIN(1, 1),
  2404. };
  2405. static const unsigned int msiof2_sync_mux[] = {
  2406. MSIOF2_SYNC_MARK,
  2407. };
  2408. static const unsigned int msiof2_ss1_pins[] = {
  2409. /* SS1 */
  2410. RCAR_GP_PIN(1, 2),
  2411. };
  2412. static const unsigned int msiof2_ss1_mux[] = {
  2413. MSIOF2_SS1_MARK,
  2414. };
  2415. static const unsigned int msiof2_ss2_pins[] = {
  2416. /* SS2 */
  2417. RCAR_GP_PIN(1, 3),
  2418. };
  2419. static const unsigned int msiof2_ss2_mux[] = {
  2420. MSIOF2_SS2_MARK,
  2421. };
  2422. static const unsigned int msiof2_rx_pins[] = {
  2423. /* RXD */
  2424. RCAR_GP_PIN(0, 30),
  2425. };
  2426. static const unsigned int msiof2_rx_mux[] = {
  2427. MSIOF2_RXD_MARK,
  2428. };
  2429. static const unsigned int msiof2_tx_pins[] = {
  2430. /* TXD */
  2431. RCAR_GP_PIN(0, 31),
  2432. };
  2433. static const unsigned int msiof2_tx_mux[] = {
  2434. MSIOF2_TXD_MARK,
  2435. };
  2436. static const unsigned int msiof2_clk_b_pins[] = {
  2437. /* SCK */
  2438. RCAR_GP_PIN(3, 15),
  2439. };
  2440. static const unsigned int msiof2_clk_b_mux[] = {
  2441. MSIOF2_SCK_B_MARK,
  2442. };
  2443. static const unsigned int msiof2_sync_b_pins[] = {
  2444. /* SYNC */
  2445. RCAR_GP_PIN(3, 16),
  2446. };
  2447. static const unsigned int msiof2_sync_b_mux[] = {
  2448. MSIOF2_SYNC_B_MARK,
  2449. };
  2450. static const unsigned int msiof2_ss1_b_pins[] = {
  2451. /* SS1 */
  2452. RCAR_GP_PIN(3, 17),
  2453. };
  2454. static const unsigned int msiof2_ss1_b_mux[] = {
  2455. MSIOF2_SS1_B_MARK,
  2456. };
  2457. static const unsigned int msiof2_ss2_b_pins[] = {
  2458. /* SS2 */
  2459. RCAR_GP_PIN(3, 18),
  2460. };
  2461. static const unsigned int msiof2_ss2_b_mux[] = {
  2462. MSIOF2_SS2_B_MARK,
  2463. };
  2464. static const unsigned int msiof2_rx_b_pins[] = {
  2465. /* RXD */
  2466. RCAR_GP_PIN(3, 13),
  2467. };
  2468. static const unsigned int msiof2_rx_b_mux[] = {
  2469. MSIOF2_RXD_B_MARK,
  2470. };
  2471. static const unsigned int msiof2_tx_b_pins[] = {
  2472. /* TXD */
  2473. RCAR_GP_PIN(3, 14),
  2474. };
  2475. static const unsigned int msiof2_tx_b_mux[] = {
  2476. MSIOF2_TXD_B_MARK,
  2477. };
  2478. /* - PWM -------------------------------------------------------------------- */
  2479. static const unsigned int pwm0_pins[] = {
  2480. RCAR_GP_PIN(1, 14),
  2481. };
  2482. static const unsigned int pwm0_mux[] = {
  2483. PWM0_MARK,
  2484. };
  2485. static const unsigned int pwm0_b_pins[] = {
  2486. RCAR_GP_PIN(5, 3),
  2487. };
  2488. static const unsigned int pwm0_b_mux[] = {
  2489. PWM0_B_MARK,
  2490. };
  2491. static const unsigned int pwm1_pins[] = {
  2492. RCAR_GP_PIN(4, 5),
  2493. };
  2494. static const unsigned int pwm1_mux[] = {
  2495. PWM1_MARK,
  2496. };
  2497. static const unsigned int pwm1_b_pins[] = {
  2498. RCAR_GP_PIN(5, 10),
  2499. };
  2500. static const unsigned int pwm1_b_mux[] = {
  2501. PWM1_B_MARK,
  2502. };
  2503. static const unsigned int pwm1_c_pins[] = {
  2504. RCAR_GP_PIN(1, 18),
  2505. };
  2506. static const unsigned int pwm1_c_mux[] = {
  2507. PWM1_C_MARK,
  2508. };
  2509. static const unsigned int pwm2_pins[] = {
  2510. RCAR_GP_PIN(4, 10),
  2511. };
  2512. static const unsigned int pwm2_mux[] = {
  2513. PWM2_MARK,
  2514. };
  2515. static const unsigned int pwm2_b_pins[] = {
  2516. RCAR_GP_PIN(5, 17),
  2517. };
  2518. static const unsigned int pwm2_b_mux[] = {
  2519. PWM2_B_MARK,
  2520. };
  2521. static const unsigned int pwm2_c_pins[] = {
  2522. RCAR_GP_PIN(0, 13),
  2523. };
  2524. static const unsigned int pwm2_c_mux[] = {
  2525. PWM2_C_MARK,
  2526. };
  2527. static const unsigned int pwm3_pins[] = {
  2528. RCAR_GP_PIN(4, 13),
  2529. };
  2530. static const unsigned int pwm3_mux[] = {
  2531. PWM3_MARK,
  2532. };
  2533. static const unsigned int pwm3_b_pins[] = {
  2534. RCAR_GP_PIN(0, 16),
  2535. };
  2536. static const unsigned int pwm3_b_mux[] = {
  2537. PWM3_B_MARK,
  2538. };
  2539. static const unsigned int pwm4_pins[] = {
  2540. RCAR_GP_PIN(1, 3),
  2541. };
  2542. static const unsigned int pwm4_mux[] = {
  2543. PWM4_MARK,
  2544. };
  2545. static const unsigned int pwm4_b_pins[] = {
  2546. RCAR_GP_PIN(0, 21),
  2547. };
  2548. static const unsigned int pwm4_b_mux[] = {
  2549. PWM4_B_MARK,
  2550. };
  2551. static const unsigned int pwm5_pins[] = {
  2552. RCAR_GP_PIN(3, 30),
  2553. };
  2554. static const unsigned int pwm5_mux[] = {
  2555. PWM5_MARK,
  2556. };
  2557. static const unsigned int pwm5_b_pins[] = {
  2558. RCAR_GP_PIN(4, 0),
  2559. };
  2560. static const unsigned int pwm5_b_mux[] = {
  2561. PWM5_B_MARK,
  2562. };
  2563. static const unsigned int pwm5_c_pins[] = {
  2564. RCAR_GP_PIN(0, 10),
  2565. };
  2566. static const unsigned int pwm5_c_mux[] = {
  2567. PWM5_C_MARK,
  2568. };
  2569. static const unsigned int pwm6_pins[] = {
  2570. RCAR_GP_PIN(4, 8),
  2571. };
  2572. static const unsigned int pwm6_mux[] = {
  2573. PWM6_MARK,
  2574. };
  2575. static const unsigned int pwm6_b_pins[] = {
  2576. RCAR_GP_PIN(0, 7),
  2577. };
  2578. static const unsigned int pwm6_b_mux[] = {
  2579. PWM6_B_MARK,
  2580. };
  2581. /* - QSPI ------------------------------------------------------------------- */
  2582. static const unsigned int qspi_ctrl_pins[] = {
  2583. /* SPCLK, SSL */
  2584. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
  2585. };
  2586. static const unsigned int qspi_ctrl_mux[] = {
  2587. SPCLK_MARK, SSL_MARK,
  2588. };
  2589. static const unsigned int qspi_data2_pins[] = {
  2590. /* MOSI_IO0, MISO_IO1 */
  2591. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  2592. };
  2593. static const unsigned int qspi_data2_mux[] = {
  2594. MOSI_IO0_MARK, MISO_IO1_MARK,
  2595. };
  2596. static const unsigned int qspi_data4_pins[] = {
  2597. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  2598. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  2599. RCAR_GP_PIN(1, 8),
  2600. };
  2601. static const unsigned int qspi_data4_mux[] = {
  2602. MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
  2603. };
  2604. /* - SCIF0 ------------------------------------------------------------------ */
  2605. static const unsigned int scif0_data_pins[] = {
  2606. /* RX, TX */
  2607. RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
  2608. };
  2609. static const unsigned int scif0_data_mux[] = {
  2610. SCIF0_RXD_MARK, SCIF0_TXD_MARK,
  2611. };
  2612. static const unsigned int scif0_data_b_pins[] = {
  2613. /* RX, TX */
  2614. RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  2615. };
  2616. static const unsigned int scif0_data_b_mux[] = {
  2617. SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
  2618. };
  2619. static const unsigned int scif0_data_c_pins[] = {
  2620. /* RX, TX */
  2621. RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
  2622. };
  2623. static const unsigned int scif0_data_c_mux[] = {
  2624. SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
  2625. };
  2626. static const unsigned int scif0_data_d_pins[] = {
  2627. /* RX, TX */
  2628. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  2629. };
  2630. static const unsigned int scif0_data_d_mux[] = {
  2631. SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
  2632. };
  2633. /* - SCIF1 ------------------------------------------------------------------ */
  2634. static const unsigned int scif1_data_pins[] = {
  2635. /* RX, TX */
  2636. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  2637. };
  2638. static const unsigned int scif1_data_mux[] = {
  2639. SCIF1_RXD_MARK, SCIF1_TXD_MARK,
  2640. };
  2641. static const unsigned int scif1_clk_pins[] = {
  2642. /* SCK */
  2643. RCAR_GP_PIN(4, 13),
  2644. };
  2645. static const unsigned int scif1_clk_mux[] = {
  2646. SCIF1_SCK_MARK,
  2647. };
  2648. static const unsigned int scif1_data_b_pins[] = {
  2649. /* RX, TX */
  2650. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
  2651. };
  2652. static const unsigned int scif1_data_b_mux[] = {
  2653. SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
  2654. };
  2655. static const unsigned int scif1_clk_b_pins[] = {
  2656. /* SCK */
  2657. RCAR_GP_PIN(5, 10),
  2658. };
  2659. static const unsigned int scif1_clk_b_mux[] = {
  2660. SCIF1_SCK_B_MARK,
  2661. };
  2662. static const unsigned int scif1_data_c_pins[] = {
  2663. /* RX, TX */
  2664. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
  2665. };
  2666. static const unsigned int scif1_data_c_mux[] = {
  2667. SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
  2668. };
  2669. static const unsigned int scif1_clk_c_pins[] = {
  2670. /* SCK */
  2671. RCAR_GP_PIN(0, 10),
  2672. };
  2673. static const unsigned int scif1_clk_c_mux[] = {
  2674. SCIF1_SCK_C_MARK,
  2675. };
  2676. /* - SCIF2 ------------------------------------------------------------------ */
  2677. static const unsigned int scif2_data_pins[] = {
  2678. /* RX, TX */
  2679. RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
  2680. };
  2681. static const unsigned int scif2_data_mux[] = {
  2682. SCIF2_RXD_MARK, SCIF2_TXD_MARK,
  2683. };
  2684. static const unsigned int scif2_clk_pins[] = {
  2685. /* SCK */
  2686. RCAR_GP_PIN(4, 18),
  2687. };
  2688. static const unsigned int scif2_clk_mux[] = {
  2689. SCIF2_SCK_MARK,
  2690. };
  2691. static const unsigned int scif2_data_b_pins[] = {
  2692. /* RX, TX */
  2693. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
  2694. };
  2695. static const unsigned int scif2_data_b_mux[] = {
  2696. SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
  2697. };
  2698. static const unsigned int scif2_clk_b_pins[] = {
  2699. /* SCK */
  2700. RCAR_GP_PIN(5, 17),
  2701. };
  2702. static const unsigned int scif2_clk_b_mux[] = {
  2703. SCIF2_SCK_B_MARK,
  2704. };
  2705. static const unsigned int scif2_data_c_pins[] = {
  2706. /* RX, TX */
  2707. RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  2708. };
  2709. static const unsigned int scif2_data_c_mux[] = {
  2710. SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
  2711. };
  2712. static const unsigned int scif2_clk_c_pins[] = {
  2713. /* SCK */
  2714. RCAR_GP_PIN(3, 19),
  2715. };
  2716. static const unsigned int scif2_clk_c_mux[] = {
  2717. SCIF2_SCK_C_MARK,
  2718. };
  2719. /* - SCIF3 ------------------------------------------------------------------ */
  2720. static const unsigned int scif3_data_pins[] = {
  2721. /* RX, TX */
  2722. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
  2723. };
  2724. static const unsigned int scif3_data_mux[] = {
  2725. SCIF3_RXD_MARK, SCIF3_TXD_MARK,
  2726. };
  2727. static const unsigned int scif3_clk_pins[] = {
  2728. /* SCK */
  2729. RCAR_GP_PIN(4, 19),
  2730. };
  2731. static const unsigned int scif3_clk_mux[] = {
  2732. SCIF3_SCK_MARK,
  2733. };
  2734. static const unsigned int scif3_data_b_pins[] = {
  2735. /* RX, TX */
  2736. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  2737. };
  2738. static const unsigned int scif3_data_b_mux[] = {
  2739. SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
  2740. };
  2741. static const unsigned int scif3_clk_b_pins[] = {
  2742. /* SCK */
  2743. RCAR_GP_PIN(3, 22),
  2744. };
  2745. static const unsigned int scif3_clk_b_mux[] = {
  2746. SCIF3_SCK_B_MARK,
  2747. };
  2748. /* - SCIF4 ------------------------------------------------------------------ */
  2749. static const unsigned int scif4_data_pins[] = {
  2750. /* RX, TX */
  2751. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  2752. };
  2753. static const unsigned int scif4_data_mux[] = {
  2754. SCIF4_RXD_MARK, SCIF4_TXD_MARK,
  2755. };
  2756. static const unsigned int scif4_data_b_pins[] = {
  2757. /* RX, TX */
  2758. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  2759. };
  2760. static const unsigned int scif4_data_b_mux[] = {
  2761. SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
  2762. };
  2763. static const unsigned int scif4_data_c_pins[] = {
  2764. /* RX, TX */
  2765. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
  2766. };
  2767. static const unsigned int scif4_data_c_mux[] = {
  2768. SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
  2769. };
  2770. static const unsigned int scif4_data_d_pins[] = {
  2771. /* RX, TX */
  2772. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
  2773. };
  2774. static const unsigned int scif4_data_d_mux[] = {
  2775. SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
  2776. };
  2777. static const unsigned int scif4_data_e_pins[] = {
  2778. /* RX, TX */
  2779. RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
  2780. };
  2781. static const unsigned int scif4_data_e_mux[] = {
  2782. SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
  2783. };
  2784. /* - SCIF5 ------------------------------------------------------------------ */
  2785. static const unsigned int scif5_data_pins[] = {
  2786. /* RX, TX */
  2787. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  2788. };
  2789. static const unsigned int scif5_data_mux[] = {
  2790. SCIF5_RXD_MARK, SCIF5_TXD_MARK,
  2791. };
  2792. static const unsigned int scif5_data_b_pins[] = {
  2793. /* RX, TX */
  2794. RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
  2795. };
  2796. static const unsigned int scif5_data_b_mux[] = {
  2797. SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
  2798. };
  2799. static const unsigned int scif5_data_c_pins[] = {
  2800. /* RX, TX */
  2801. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
  2802. };
  2803. static const unsigned int scif5_data_c_mux[] = {
  2804. SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
  2805. };
  2806. static const unsigned int scif5_data_d_pins[] = {
  2807. /* RX, TX */
  2808. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  2809. };
  2810. static const unsigned int scif5_data_d_mux[] = {
  2811. SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
  2812. };
  2813. /* - SCIFA0 ----------------------------------------------------------------- */
  2814. static const unsigned int scifa0_data_pins[] = {
  2815. /* RXD, TXD */
  2816. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
  2817. };
  2818. static const unsigned int scifa0_data_mux[] = {
  2819. SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
  2820. };
  2821. static const unsigned int scifa0_data_b_pins[] = {
  2822. /* RXD, TXD */
  2823. RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
  2824. };
  2825. static const unsigned int scifa0_data_b_mux[] = {
  2826. SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
  2827. };
  2828. static const unsigned int scifa0_data_c_pins[] = {
  2829. /* RXD, TXD */
  2830. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  2831. };
  2832. static const unsigned int scifa0_data_c_mux[] = {
  2833. SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
  2834. };
  2835. static const unsigned int scifa0_data_d_pins[] = {
  2836. /* RXD, TXD */
  2837. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  2838. };
  2839. static const unsigned int scifa0_data_d_mux[] = {
  2840. SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
  2841. };
  2842. /* - SCIFA1 ----------------------------------------------------------------- */
  2843. static const unsigned int scifa1_data_pins[] = {
  2844. /* RXD, TXD */
  2845. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2846. };
  2847. static const unsigned int scifa1_data_mux[] = {
  2848. SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
  2849. };
  2850. static const unsigned int scifa1_clk_pins[] = {
  2851. /* SCK */
  2852. RCAR_GP_PIN(0, 13),
  2853. };
  2854. static const unsigned int scifa1_clk_mux[] = {
  2855. SCIFA1_SCK_MARK,
  2856. };
  2857. static const unsigned int scifa1_data_b_pins[] = {
  2858. /* RXD, TXD */
  2859. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
  2860. };
  2861. static const unsigned int scifa1_data_b_mux[] = {
  2862. SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
  2863. };
  2864. static const unsigned int scifa1_clk_b_pins[] = {
  2865. /* SCK */
  2866. RCAR_GP_PIN(4, 27),
  2867. };
  2868. static const unsigned int scifa1_clk_b_mux[] = {
  2869. SCIFA1_SCK_B_MARK,
  2870. };
  2871. static const unsigned int scifa1_data_c_pins[] = {
  2872. /* RXD, TXD */
  2873. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  2874. };
  2875. static const unsigned int scifa1_data_c_mux[] = {
  2876. SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
  2877. };
  2878. static const unsigned int scifa1_clk_c_pins[] = {
  2879. /* SCK */
  2880. RCAR_GP_PIN(5, 4),
  2881. };
  2882. static const unsigned int scifa1_clk_c_mux[] = {
  2883. SCIFA1_SCK_C_MARK,
  2884. };
  2885. /* - SCIFA2 ----------------------------------------------------------------- */
  2886. static const unsigned int scifa2_data_pins[] = {
  2887. /* RXD, TXD */
  2888. RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
  2889. };
  2890. static const unsigned int scifa2_data_mux[] = {
  2891. SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
  2892. };
  2893. static const unsigned int scifa2_clk_pins[] = {
  2894. /* SCK */
  2895. RCAR_GP_PIN(1, 15),
  2896. };
  2897. static const unsigned int scifa2_clk_mux[] = {
  2898. SCIFA2_SCK_MARK,
  2899. };
  2900. static const unsigned int scifa2_data_b_pins[] = {
  2901. /* RXD, TXD */
  2902. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
  2903. };
  2904. static const unsigned int scifa2_data_b_mux[] = {
  2905. SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
  2906. };
  2907. static const unsigned int scifa2_clk_b_pins[] = {
  2908. /* SCK */
  2909. RCAR_GP_PIN(4, 30),
  2910. };
  2911. static const unsigned int scifa2_clk_b_mux[] = {
  2912. SCIFA2_SCK_B_MARK,
  2913. };
  2914. /* - SCIFA3 ----------------------------------------------------------------- */
  2915. static const unsigned int scifa3_data_pins[] = {
  2916. /* RXD, TXD */
  2917. RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
  2918. };
  2919. static const unsigned int scifa3_data_mux[] = {
  2920. SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
  2921. };
  2922. static const unsigned int scifa3_clk_pins[] = {
  2923. /* SCK */
  2924. RCAR_GP_PIN(4, 24),
  2925. };
  2926. static const unsigned int scifa3_clk_mux[] = {
  2927. SCIFA3_SCK_MARK,
  2928. };
  2929. static const unsigned int scifa3_data_b_pins[] = {
  2930. /* RXD, TXD */
  2931. RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
  2932. };
  2933. static const unsigned int scifa3_data_b_mux[] = {
  2934. SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
  2935. };
  2936. static const unsigned int scifa3_clk_b_pins[] = {
  2937. /* SCK */
  2938. RCAR_GP_PIN(0, 0),
  2939. };
  2940. static const unsigned int scifa3_clk_b_mux[] = {
  2941. SCIFA3_SCK_B_MARK,
  2942. };
  2943. /* - SCIFA4 ----------------------------------------------------------------- */
  2944. static const unsigned int scifa4_data_pins[] = {
  2945. /* RXD, TXD */
  2946. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
  2947. };
  2948. static const unsigned int scifa4_data_mux[] = {
  2949. SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
  2950. };
  2951. static const unsigned int scifa4_data_b_pins[] = {
  2952. /* RXD, TXD */
  2953. RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
  2954. };
  2955. static const unsigned int scifa4_data_b_mux[] = {
  2956. SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
  2957. };
  2958. static const unsigned int scifa4_data_c_pins[] = {
  2959. /* RXD, TXD */
  2960. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
  2961. };
  2962. static const unsigned int scifa4_data_c_mux[] = {
  2963. SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
  2964. };
  2965. static const unsigned int scifa4_data_d_pins[] = {
  2966. /* RXD, TXD */
  2967. RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
  2968. };
  2969. static const unsigned int scifa4_data_d_mux[] = {
  2970. SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
  2971. };
  2972. /* - SCIFA5 ----------------------------------------------------------------- */
  2973. static const unsigned int scifa5_data_pins[] = {
  2974. /* RXD, TXD */
  2975. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
  2976. };
  2977. static const unsigned int scifa5_data_mux[] = {
  2978. SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
  2979. };
  2980. static const unsigned int scifa5_data_b_pins[] = {
  2981. /* RXD, TXD */
  2982. RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
  2983. };
  2984. static const unsigned int scifa5_data_b_mux[] = {
  2985. SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
  2986. };
  2987. static const unsigned int scifa5_data_c_pins[] = {
  2988. /* RXD, TXD */
  2989. RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
  2990. };
  2991. static const unsigned int scifa5_data_c_mux[] = {
  2992. SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
  2993. };
  2994. static const unsigned int scifa5_data_d_pins[] = {
  2995. /* RXD, TXD */
  2996. RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
  2997. };
  2998. static const unsigned int scifa5_data_d_mux[] = {
  2999. SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
  3000. };
  3001. /* - SCIFB0 ----------------------------------------------------------------- */
  3002. static const unsigned int scifb0_data_pins[] = {
  3003. /* RXD, TXD */
  3004. RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
  3005. };
  3006. static const unsigned int scifb0_data_mux[] = {
  3007. SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
  3008. };
  3009. static const unsigned int scifb0_clk_pins[] = {
  3010. /* SCK */
  3011. RCAR_GP_PIN(0, 19),
  3012. };
  3013. static const unsigned int scifb0_clk_mux[] = {
  3014. SCIFB0_SCK_MARK,
  3015. };
  3016. static const unsigned int scifb0_ctrl_pins[] = {
  3017. /* RTS, CTS */
  3018. RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
  3019. };
  3020. static const unsigned int scifb0_ctrl_mux[] = {
  3021. SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
  3022. };
  3023. /* - SCIFB1 ----------------------------------------------------------------- */
  3024. static const unsigned int scifb1_data_pins[] = {
  3025. /* RXD, TXD */
  3026. RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
  3027. };
  3028. static const unsigned int scifb1_data_mux[] = {
  3029. SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
  3030. };
  3031. static const unsigned int scifb1_clk_pins[] = {
  3032. /* SCK */
  3033. RCAR_GP_PIN(0, 16),
  3034. };
  3035. static const unsigned int scifb1_clk_mux[] = {
  3036. SCIFB1_SCK_MARK,
  3037. };
  3038. /* - SCIFB2 ----------------------------------------------------------------- */
  3039. static const unsigned int scifb2_data_pins[] = {
  3040. /* RXD, TXD */
  3041. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  3042. };
  3043. static const unsigned int scifb2_data_mux[] = {
  3044. SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
  3045. };
  3046. static const unsigned int scifb2_clk_pins[] = {
  3047. /* SCK */
  3048. RCAR_GP_PIN(1, 15),
  3049. };
  3050. static const unsigned int scifb2_clk_mux[] = {
  3051. SCIFB2_SCK_MARK,
  3052. };
  3053. static const unsigned int scifb2_ctrl_pins[] = {
  3054. /* RTS, CTS */
  3055. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
  3056. };
  3057. static const unsigned int scifb2_ctrl_mux[] = {
  3058. SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
  3059. };
  3060. /* - SCIF Clock ------------------------------------------------------------- */
  3061. static const unsigned int scif_clk_pins[] = {
  3062. /* SCIF_CLK */
  3063. RCAR_GP_PIN(1, 23),
  3064. };
  3065. static const unsigned int scif_clk_mux[] = {
  3066. SCIF_CLK_MARK,
  3067. };
  3068. static const unsigned int scif_clk_b_pins[] = {
  3069. /* SCIF_CLK */
  3070. RCAR_GP_PIN(3, 29),
  3071. };
  3072. static const unsigned int scif_clk_b_mux[] = {
  3073. SCIF_CLK_B_MARK,
  3074. };
  3075. /* - SDHI0 ------------------------------------------------------------------ */
  3076. static const unsigned int sdhi0_data1_pins[] = {
  3077. /* D0 */
  3078. RCAR_GP_PIN(6, 2),
  3079. };
  3080. static const unsigned int sdhi0_data1_mux[] = {
  3081. SD0_DATA0_MARK,
  3082. };
  3083. static const unsigned int sdhi0_data4_pins[] = {
  3084. /* D[0:3] */
  3085. RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
  3086. RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
  3087. };
  3088. static const unsigned int sdhi0_data4_mux[] = {
  3089. SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
  3090. };
  3091. static const unsigned int sdhi0_ctrl_pins[] = {
  3092. /* CLK, CMD */
  3093. RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
  3094. };
  3095. static const unsigned int sdhi0_ctrl_mux[] = {
  3096. SD0_CLK_MARK, SD0_CMD_MARK,
  3097. };
  3098. static const unsigned int sdhi0_cd_pins[] = {
  3099. /* CD */
  3100. RCAR_GP_PIN(6, 6),
  3101. };
  3102. static const unsigned int sdhi0_cd_mux[] = {
  3103. SD0_CD_MARK,
  3104. };
  3105. static const unsigned int sdhi0_wp_pins[] = {
  3106. /* WP */
  3107. RCAR_GP_PIN(6, 7),
  3108. };
  3109. static const unsigned int sdhi0_wp_mux[] = {
  3110. SD0_WP_MARK,
  3111. };
  3112. /* - SDHI1 ------------------------------------------------------------------ */
  3113. static const unsigned int sdhi1_data1_pins[] = {
  3114. /* D0 */
  3115. RCAR_GP_PIN(6, 10),
  3116. };
  3117. static const unsigned int sdhi1_data1_mux[] = {
  3118. SD1_DATA0_MARK,
  3119. };
  3120. static const unsigned int sdhi1_data4_pins[] = {
  3121. /* D[0:3] */
  3122. RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
  3123. RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
  3124. };
  3125. static const unsigned int sdhi1_data4_mux[] = {
  3126. SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
  3127. };
  3128. static const unsigned int sdhi1_ctrl_pins[] = {
  3129. /* CLK, CMD */
  3130. RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
  3131. };
  3132. static const unsigned int sdhi1_ctrl_mux[] = {
  3133. SD1_CLK_MARK, SD1_CMD_MARK,
  3134. };
  3135. static const unsigned int sdhi1_cd_pins[] = {
  3136. /* CD */
  3137. RCAR_GP_PIN(6, 14),
  3138. };
  3139. static const unsigned int sdhi1_cd_mux[] = {
  3140. SD1_CD_MARK,
  3141. };
  3142. static const unsigned int sdhi1_wp_pins[] = {
  3143. /* WP */
  3144. RCAR_GP_PIN(6, 15),
  3145. };
  3146. static const unsigned int sdhi1_wp_mux[] = {
  3147. SD1_WP_MARK,
  3148. };
  3149. /* - SDHI2 ------------------------------------------------------------------ */
  3150. static const unsigned int sdhi2_data1_pins[] = {
  3151. /* D0 */
  3152. RCAR_GP_PIN(6, 18),
  3153. };
  3154. static const unsigned int sdhi2_data1_mux[] = {
  3155. SD2_DATA0_MARK,
  3156. };
  3157. static const unsigned int sdhi2_data4_pins[] = {
  3158. /* D[0:3] */
  3159. RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
  3160. RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
  3161. };
  3162. static const unsigned int sdhi2_data4_mux[] = {
  3163. SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
  3164. };
  3165. static const unsigned int sdhi2_ctrl_pins[] = {
  3166. /* CLK, CMD */
  3167. RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
  3168. };
  3169. static const unsigned int sdhi2_ctrl_mux[] = {
  3170. SD2_CLK_MARK, SD2_CMD_MARK,
  3171. };
  3172. static const unsigned int sdhi2_cd_pins[] = {
  3173. /* CD */
  3174. RCAR_GP_PIN(6, 22),
  3175. };
  3176. static const unsigned int sdhi2_cd_mux[] = {
  3177. SD2_CD_MARK,
  3178. };
  3179. static const unsigned int sdhi2_wp_pins[] = {
  3180. /* WP */
  3181. RCAR_GP_PIN(6, 23),
  3182. };
  3183. static const unsigned int sdhi2_wp_mux[] = {
  3184. SD2_WP_MARK,
  3185. };
  3186. /* - SSI -------------------------------------------------------------------- */
  3187. static const unsigned int ssi0_data_pins[] = {
  3188. /* SDATA0 */
  3189. RCAR_GP_PIN(5, 3),
  3190. };
  3191. static const unsigned int ssi0_data_mux[] = {
  3192. SSI_SDATA0_MARK,
  3193. };
  3194. static const unsigned int ssi0129_ctrl_pins[] = {
  3195. /* SCK0129, WS0129 */
  3196. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  3197. };
  3198. static const unsigned int ssi0129_ctrl_mux[] = {
  3199. SSI_SCK0129_MARK, SSI_WS0129_MARK,
  3200. };
  3201. static const unsigned int ssi1_data_pins[] = {
  3202. /* SDATA1 */
  3203. RCAR_GP_PIN(5, 13),
  3204. };
  3205. static const unsigned int ssi1_data_mux[] = {
  3206. SSI_SDATA1_MARK,
  3207. };
  3208. static const unsigned int ssi1_ctrl_pins[] = {
  3209. /* SCK1, WS1 */
  3210. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
  3211. };
  3212. static const unsigned int ssi1_ctrl_mux[] = {
  3213. SSI_SCK1_MARK, SSI_WS1_MARK,
  3214. };
  3215. static const unsigned int ssi1_data_b_pins[] = {
  3216. /* SDATA1 */
  3217. RCAR_GP_PIN(4, 13),
  3218. };
  3219. static const unsigned int ssi1_data_b_mux[] = {
  3220. SSI_SDATA1_B_MARK,
  3221. };
  3222. static const unsigned int ssi1_ctrl_b_pins[] = {
  3223. /* SCK1, WS1 */
  3224. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3225. };
  3226. static const unsigned int ssi1_ctrl_b_mux[] = {
  3227. SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
  3228. };
  3229. static const unsigned int ssi2_data_pins[] = {
  3230. /* SDATA2 */
  3231. RCAR_GP_PIN(5, 16),
  3232. };
  3233. static const unsigned int ssi2_data_mux[] = {
  3234. SSI_SDATA2_MARK,
  3235. };
  3236. static const unsigned int ssi2_ctrl_pins[] = {
  3237. /* SCK2, WS2 */
  3238. RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
  3239. };
  3240. static const unsigned int ssi2_ctrl_mux[] = {
  3241. SSI_SCK2_MARK, SSI_WS2_MARK,
  3242. };
  3243. static const unsigned int ssi2_data_b_pins[] = {
  3244. /* SDATA2 */
  3245. RCAR_GP_PIN(4, 16),
  3246. };
  3247. static const unsigned int ssi2_data_b_mux[] = {
  3248. SSI_SDATA2_B_MARK,
  3249. };
  3250. static const unsigned int ssi2_ctrl_b_pins[] = {
  3251. /* SCK2, WS2 */
  3252. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  3253. };
  3254. static const unsigned int ssi2_ctrl_b_mux[] = {
  3255. SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
  3256. };
  3257. static const unsigned int ssi3_data_pins[] = {
  3258. /* SDATA3 */
  3259. RCAR_GP_PIN(5, 6),
  3260. };
  3261. static const unsigned int ssi3_data_mux[] = {
  3262. SSI_SDATA3_MARK
  3263. };
  3264. static const unsigned int ssi34_ctrl_pins[] = {
  3265. /* SCK34, WS34 */
  3266. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
  3267. };
  3268. static const unsigned int ssi34_ctrl_mux[] = {
  3269. SSI_SCK34_MARK, SSI_WS34_MARK,
  3270. };
  3271. static const unsigned int ssi4_data_pins[] = {
  3272. /* SDATA4 */
  3273. RCAR_GP_PIN(5, 9),
  3274. };
  3275. static const unsigned int ssi4_data_mux[] = {
  3276. SSI_SDATA4_MARK,
  3277. };
  3278. static const unsigned int ssi4_ctrl_pins[] = {
  3279. /* SCK4, WS4 */
  3280. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
  3281. };
  3282. static const unsigned int ssi4_ctrl_mux[] = {
  3283. SSI_SCK4_MARK, SSI_WS4_MARK,
  3284. };
  3285. static const unsigned int ssi4_data_b_pins[] = {
  3286. /* SDATA4 */
  3287. RCAR_GP_PIN(4, 22),
  3288. };
  3289. static const unsigned int ssi4_data_b_mux[] = {
  3290. SSI_SDATA4_B_MARK,
  3291. };
  3292. static const unsigned int ssi4_ctrl_b_pins[] = {
  3293. /* SCK4, WS4 */
  3294. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
  3295. };
  3296. static const unsigned int ssi4_ctrl_b_mux[] = {
  3297. SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
  3298. };
  3299. static const unsigned int ssi5_data_pins[] = {
  3300. /* SDATA5 */
  3301. RCAR_GP_PIN(4, 26),
  3302. };
  3303. static const unsigned int ssi5_data_mux[] = {
  3304. SSI_SDATA5_MARK,
  3305. };
  3306. static const unsigned int ssi5_ctrl_pins[] = {
  3307. /* SCK5, WS5 */
  3308. RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
  3309. };
  3310. static const unsigned int ssi5_ctrl_mux[] = {
  3311. SSI_SCK5_MARK, SSI_WS5_MARK,
  3312. };
  3313. static const unsigned int ssi5_data_b_pins[] = {
  3314. /* SDATA5 */
  3315. RCAR_GP_PIN(3, 21),
  3316. };
  3317. static const unsigned int ssi5_data_b_mux[] = {
  3318. SSI_SDATA5_B_MARK,
  3319. };
  3320. static const unsigned int ssi5_ctrl_b_pins[] = {
  3321. /* SCK5, WS5 */
  3322. RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
  3323. };
  3324. static const unsigned int ssi5_ctrl_b_mux[] = {
  3325. SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
  3326. };
  3327. static const unsigned int ssi6_data_pins[] = {
  3328. /* SDATA6 */
  3329. RCAR_GP_PIN(4, 29),
  3330. };
  3331. static const unsigned int ssi6_data_mux[] = {
  3332. SSI_SDATA6_MARK,
  3333. };
  3334. static const unsigned int ssi6_ctrl_pins[] = {
  3335. /* SCK6, WS6 */
  3336. RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
  3337. };
  3338. static const unsigned int ssi6_ctrl_mux[] = {
  3339. SSI_SCK6_MARK, SSI_WS6_MARK,
  3340. };
  3341. static const unsigned int ssi6_data_b_pins[] = {
  3342. /* SDATA6 */
  3343. RCAR_GP_PIN(3, 24),
  3344. };
  3345. static const unsigned int ssi6_data_b_mux[] = {
  3346. SSI_SDATA6_B_MARK,
  3347. };
  3348. static const unsigned int ssi6_ctrl_b_pins[] = {
  3349. /* SCK6, WS6 */
  3350. RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
  3351. };
  3352. static const unsigned int ssi6_ctrl_b_mux[] = {
  3353. SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
  3354. };
  3355. static const unsigned int ssi7_data_pins[] = {
  3356. /* SDATA7 */
  3357. RCAR_GP_PIN(5, 0),
  3358. };
  3359. static const unsigned int ssi7_data_mux[] = {
  3360. SSI_SDATA7_MARK,
  3361. };
  3362. static const unsigned int ssi78_ctrl_pins[] = {
  3363. /* SCK78, WS78 */
  3364. RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
  3365. };
  3366. static const unsigned int ssi78_ctrl_mux[] = {
  3367. SSI_SCK78_MARK, SSI_WS78_MARK,
  3368. };
  3369. static const unsigned int ssi7_data_b_pins[] = {
  3370. /* SDATA7 */
  3371. RCAR_GP_PIN(3, 27),
  3372. };
  3373. static const unsigned int ssi7_data_b_mux[] = {
  3374. SSI_SDATA7_B_MARK,
  3375. };
  3376. static const unsigned int ssi78_ctrl_b_pins[] = {
  3377. /* SCK78, WS78 */
  3378. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  3379. };
  3380. static const unsigned int ssi78_ctrl_b_mux[] = {
  3381. SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
  3382. };
  3383. static const unsigned int ssi8_data_pins[] = {
  3384. /* SDATA8 */
  3385. RCAR_GP_PIN(5, 10),
  3386. };
  3387. static const unsigned int ssi8_data_mux[] = {
  3388. SSI_SDATA8_MARK,
  3389. };
  3390. static const unsigned int ssi8_data_b_pins[] = {
  3391. /* SDATA8 */
  3392. RCAR_GP_PIN(3, 28),
  3393. };
  3394. static const unsigned int ssi8_data_b_mux[] = {
  3395. SSI_SDATA8_B_MARK,
  3396. };
  3397. static const unsigned int ssi9_data_pins[] = {
  3398. /* SDATA9 */
  3399. RCAR_GP_PIN(5, 19),
  3400. };
  3401. static const unsigned int ssi9_data_mux[] = {
  3402. SSI_SDATA9_MARK,
  3403. };
  3404. static const unsigned int ssi9_ctrl_pins[] = {
  3405. /* SCK9, WS9 */
  3406. RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
  3407. };
  3408. static const unsigned int ssi9_ctrl_mux[] = {
  3409. SSI_SCK9_MARK, SSI_WS9_MARK,
  3410. };
  3411. static const unsigned int ssi9_data_b_pins[] = {
  3412. /* SDATA9 */
  3413. RCAR_GP_PIN(4, 19),
  3414. };
  3415. static const unsigned int ssi9_data_b_mux[] = {
  3416. SSI_SDATA9_B_MARK,
  3417. };
  3418. static const unsigned int ssi9_ctrl_b_pins[] = {
  3419. /* SCK9, WS9 */
  3420. RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
  3421. };
  3422. static const unsigned int ssi9_ctrl_b_mux[] = {
  3423. SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
  3424. };
  3425. /* - TPU -------------------------------------------------------------------- */
  3426. static const unsigned int tpu_to0_pins[] = {
  3427. RCAR_GP_PIN(3, 31),
  3428. };
  3429. static const unsigned int tpu_to0_mux[] = {
  3430. TPUTO0_MARK,
  3431. };
  3432. static const unsigned int tpu_to0_b_pins[] = {
  3433. RCAR_GP_PIN(3, 30),
  3434. };
  3435. static const unsigned int tpu_to0_b_mux[] = {
  3436. TPUTO0_B_MARK,
  3437. };
  3438. static const unsigned int tpu_to0_c_pins[] = {
  3439. RCAR_GP_PIN(1, 18),
  3440. };
  3441. static const unsigned int tpu_to0_c_mux[] = {
  3442. TPUTO0_C_MARK,
  3443. };
  3444. static const unsigned int tpu_to1_pins[] = {
  3445. RCAR_GP_PIN(4, 9),
  3446. };
  3447. static const unsigned int tpu_to1_mux[] = {
  3448. TPUTO1_MARK,
  3449. };
  3450. static const unsigned int tpu_to1_b_pins[] = {
  3451. RCAR_GP_PIN(4, 0),
  3452. };
  3453. static const unsigned int tpu_to1_b_mux[] = {
  3454. TPUTO1_B_MARK,
  3455. };
  3456. static const unsigned int tpu_to1_c_pins[] = {
  3457. RCAR_GP_PIN(4, 4),
  3458. };
  3459. static const unsigned int tpu_to1_c_mux[] = {
  3460. TPUTO1_C_MARK,
  3461. };
  3462. static const unsigned int tpu_to2_pins[] = {
  3463. RCAR_GP_PIN(1, 3),
  3464. };
  3465. static const unsigned int tpu_to2_mux[] = {
  3466. TPUTO2_MARK,
  3467. };
  3468. static const unsigned int tpu_to2_b_pins[] = {
  3469. RCAR_GP_PIN(1, 0),
  3470. };
  3471. static const unsigned int tpu_to2_b_mux[] = {
  3472. TPUTO2_B_MARK,
  3473. };
  3474. static const unsigned int tpu_to2_c_pins[] = {
  3475. RCAR_GP_PIN(0, 22),
  3476. };
  3477. static const unsigned int tpu_to2_c_mux[] = {
  3478. TPUTO2_C_MARK,
  3479. };
  3480. static const unsigned int tpu_to3_pins[] = {
  3481. RCAR_GP_PIN(1, 14),
  3482. };
  3483. static const unsigned int tpu_to3_mux[] = {
  3484. TPUTO3_MARK,
  3485. };
  3486. static const unsigned int tpu_to3_b_pins[] = {
  3487. RCAR_GP_PIN(1, 13),
  3488. };
  3489. static const unsigned int tpu_to3_b_mux[] = {
  3490. TPUTO3_B_MARK,
  3491. };
  3492. static const unsigned int tpu_to3_c_pins[] = {
  3493. RCAR_GP_PIN(0, 21),
  3494. };
  3495. static const unsigned int tpu_to3_c_mux[] = {
  3496. TPUTO3_C_MARK,
  3497. };
  3498. /* - USB0 ------------------------------------------------------------------- */
  3499. static const unsigned int usb0_pins[] = {
  3500. RCAR_GP_PIN(5, 24), /* PWEN */
  3501. RCAR_GP_PIN(5, 25), /* OVC */
  3502. };
  3503. static const unsigned int usb0_mux[] = {
  3504. USB0_PWEN_MARK,
  3505. USB0_OVC_MARK,
  3506. };
  3507. /* - USB1 ------------------------------------------------------------------- */
  3508. static const unsigned int usb1_pins[] = {
  3509. RCAR_GP_PIN(5, 26), /* PWEN */
  3510. RCAR_GP_PIN(5, 27), /* OVC */
  3511. };
  3512. static const unsigned int usb1_mux[] = {
  3513. USB1_PWEN_MARK,
  3514. USB1_OVC_MARK,
  3515. };
  3516. /* - VIN0 ------------------------------------------------------------------- */
  3517. static const union vin_data vin0_data_pins = {
  3518. .data24 = {
  3519. /* B */
  3520. RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
  3521. RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  3522. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
  3523. RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
  3524. /* G */
  3525. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  3526. RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  3527. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
  3528. RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
  3529. /* R */
  3530. RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
  3531. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  3532. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  3533. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  3534. },
  3535. };
  3536. static const union vin_data vin0_data_mux = {
  3537. .data24 = {
  3538. /* B */
  3539. VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
  3540. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  3541. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  3542. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  3543. /* G */
  3544. VI0_G0_MARK, VI0_G1_MARK,
  3545. VI0_G2_MARK, VI0_G3_MARK,
  3546. VI0_G4_MARK, VI0_G5_MARK,
  3547. VI0_G6_MARK, VI0_G7_MARK,
  3548. /* R */
  3549. VI0_R0_MARK, VI0_R1_MARK,
  3550. VI0_R2_MARK, VI0_R3_MARK,
  3551. VI0_R4_MARK, VI0_R5_MARK,
  3552. VI0_R6_MARK, VI0_R7_MARK,
  3553. },
  3554. };
  3555. static const unsigned int vin0_data18_pins[] = {
  3556. /* B */
  3557. RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  3558. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
  3559. RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
  3560. /* G */
  3561. RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  3562. RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
  3563. RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
  3564. /* R */
  3565. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
  3566. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  3567. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  3568. };
  3569. static const unsigned int vin0_data18_mux[] = {
  3570. /* B */
  3571. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  3572. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  3573. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  3574. /* G */
  3575. VI0_G2_MARK, VI0_G3_MARK,
  3576. VI0_G4_MARK, VI0_G5_MARK,
  3577. VI0_G6_MARK, VI0_G7_MARK,
  3578. /* R */
  3579. VI0_R2_MARK, VI0_R3_MARK,
  3580. VI0_R4_MARK, VI0_R5_MARK,
  3581. VI0_R6_MARK, VI0_R7_MARK,
  3582. };
  3583. static const unsigned int vin0_sync_pins[] = {
  3584. RCAR_GP_PIN(3, 11), /* HSYNC */
  3585. RCAR_GP_PIN(3, 12), /* VSYNC */
  3586. };
  3587. static const unsigned int vin0_sync_mux[] = {
  3588. VI0_HSYNC_N_MARK,
  3589. VI0_VSYNC_N_MARK,
  3590. };
  3591. static const unsigned int vin0_field_pins[] = {
  3592. RCAR_GP_PIN(3, 10),
  3593. };
  3594. static const unsigned int vin0_field_mux[] = {
  3595. VI0_FIELD_MARK,
  3596. };
  3597. static const unsigned int vin0_clkenb_pins[] = {
  3598. RCAR_GP_PIN(3, 9),
  3599. };
  3600. static const unsigned int vin0_clkenb_mux[] = {
  3601. VI0_CLKENB_MARK,
  3602. };
  3603. static const unsigned int vin0_clk_pins[] = {
  3604. RCAR_GP_PIN(3, 0),
  3605. };
  3606. static const unsigned int vin0_clk_mux[] = {
  3607. VI0_CLK_MARK,
  3608. };
  3609. /* - VIN1 ------------------------------------------------------------------- */
  3610. static const union vin_data12 vin1_data_pins = {
  3611. .data12 = {
  3612. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
  3613. RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
  3614. RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
  3615. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
  3616. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
  3617. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  3618. },
  3619. };
  3620. static const union vin_data12 vin1_data_mux = {
  3621. .data12 = {
  3622. VI1_DATA0_MARK, VI1_DATA1_MARK,
  3623. VI1_DATA2_MARK, VI1_DATA3_MARK,
  3624. VI1_DATA4_MARK, VI1_DATA5_MARK,
  3625. VI1_DATA6_MARK, VI1_DATA7_MARK,
  3626. VI1_DATA8_MARK, VI1_DATA9_MARK,
  3627. VI1_DATA10_MARK, VI1_DATA11_MARK,
  3628. },
  3629. };
  3630. static const unsigned int vin1_sync_pins[] = {
  3631. RCAR_GP_PIN(5, 22), /* HSYNC */
  3632. RCAR_GP_PIN(5, 23), /* VSYNC */
  3633. };
  3634. static const unsigned int vin1_sync_mux[] = {
  3635. VI1_HSYNC_N_MARK,
  3636. VI1_VSYNC_N_MARK,
  3637. };
  3638. static const unsigned int vin1_field_pins[] = {
  3639. RCAR_GP_PIN(5, 21),
  3640. };
  3641. static const unsigned int vin1_field_mux[] = {
  3642. VI1_FIELD_MARK,
  3643. };
  3644. static const unsigned int vin1_clkenb_pins[] = {
  3645. RCAR_GP_PIN(5, 20),
  3646. };
  3647. static const unsigned int vin1_clkenb_mux[] = {
  3648. VI1_CLKENB_MARK,
  3649. };
  3650. static const unsigned int vin1_clk_pins[] = {
  3651. RCAR_GP_PIN(5, 11),
  3652. };
  3653. static const unsigned int vin1_clk_mux[] = {
  3654. VI1_CLK_MARK,
  3655. };
  3656. static const struct sh_pfc_pin_group pinmux_groups[] = {
  3657. SH_PFC_PIN_GROUP(audio_clka),
  3658. SH_PFC_PIN_GROUP(audio_clka_b),
  3659. SH_PFC_PIN_GROUP(audio_clka_c),
  3660. SH_PFC_PIN_GROUP(audio_clka_d),
  3661. SH_PFC_PIN_GROUP(audio_clkb),
  3662. SH_PFC_PIN_GROUP(audio_clkb_b),
  3663. SH_PFC_PIN_GROUP(audio_clkb_c),
  3664. SH_PFC_PIN_GROUP(audio_clkc),
  3665. SH_PFC_PIN_GROUP(audio_clkc_b),
  3666. SH_PFC_PIN_GROUP(audio_clkc_c),
  3667. SH_PFC_PIN_GROUP(audio_clkout),
  3668. SH_PFC_PIN_GROUP(audio_clkout_b),
  3669. SH_PFC_PIN_GROUP(audio_clkout_c),
  3670. SH_PFC_PIN_GROUP(avb_link),
  3671. SH_PFC_PIN_GROUP(avb_magic),
  3672. SH_PFC_PIN_GROUP(avb_phy_int),
  3673. SH_PFC_PIN_GROUP(avb_mdio),
  3674. SH_PFC_PIN_GROUP(avb_mii),
  3675. SH_PFC_PIN_GROUP(avb_gmii),
  3676. SH_PFC_PIN_GROUP(can0_data),
  3677. SH_PFC_PIN_GROUP(can0_data_b),
  3678. SH_PFC_PIN_GROUP(can0_data_c),
  3679. SH_PFC_PIN_GROUP(can0_data_d),
  3680. SH_PFC_PIN_GROUP(can1_data),
  3681. SH_PFC_PIN_GROUP(can1_data_b),
  3682. SH_PFC_PIN_GROUP(can1_data_c),
  3683. SH_PFC_PIN_GROUP(can1_data_d),
  3684. SH_PFC_PIN_GROUP(can_clk),
  3685. SH_PFC_PIN_GROUP(can_clk_b),
  3686. SH_PFC_PIN_GROUP(can_clk_c),
  3687. SH_PFC_PIN_GROUP(can_clk_d),
  3688. SH_PFC_PIN_GROUP(du0_rgb666),
  3689. SH_PFC_PIN_GROUP(du0_rgb888),
  3690. SH_PFC_PIN_GROUP(du0_clk0_out),
  3691. SH_PFC_PIN_GROUP(du0_clk1_out),
  3692. SH_PFC_PIN_GROUP(du0_clk_in),
  3693. SH_PFC_PIN_GROUP(du0_sync),
  3694. SH_PFC_PIN_GROUP(du0_oddf),
  3695. SH_PFC_PIN_GROUP(du0_cde),
  3696. SH_PFC_PIN_GROUP(du0_disp),
  3697. SH_PFC_PIN_GROUP(du1_rgb666),
  3698. SH_PFC_PIN_GROUP(du1_rgb888),
  3699. SH_PFC_PIN_GROUP(du1_clk0_out),
  3700. SH_PFC_PIN_GROUP(du1_clk1_out),
  3701. SH_PFC_PIN_GROUP(du1_clk_in),
  3702. SH_PFC_PIN_GROUP(du1_sync),
  3703. SH_PFC_PIN_GROUP(du1_oddf),
  3704. SH_PFC_PIN_GROUP(du1_cde),
  3705. SH_PFC_PIN_GROUP(du1_disp),
  3706. SH_PFC_PIN_GROUP(eth_link),
  3707. SH_PFC_PIN_GROUP(eth_magic),
  3708. SH_PFC_PIN_GROUP(eth_mdio),
  3709. SH_PFC_PIN_GROUP(eth_rmii),
  3710. SH_PFC_PIN_GROUP(eth_link_b),
  3711. SH_PFC_PIN_GROUP(eth_magic_b),
  3712. SH_PFC_PIN_GROUP(eth_mdio_b),
  3713. SH_PFC_PIN_GROUP(eth_rmii_b),
  3714. SH_PFC_PIN_GROUP(hscif0_data),
  3715. SH_PFC_PIN_GROUP(hscif0_clk),
  3716. SH_PFC_PIN_GROUP(hscif0_ctrl),
  3717. SH_PFC_PIN_GROUP(hscif0_data_b),
  3718. SH_PFC_PIN_GROUP(hscif0_clk_b),
  3719. SH_PFC_PIN_GROUP(hscif1_data),
  3720. SH_PFC_PIN_GROUP(hscif1_clk),
  3721. SH_PFC_PIN_GROUP(hscif1_ctrl),
  3722. SH_PFC_PIN_GROUP(hscif1_data_b),
  3723. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  3724. SH_PFC_PIN_GROUP(hscif2_data),
  3725. SH_PFC_PIN_GROUP(hscif2_clk),
  3726. SH_PFC_PIN_GROUP(hscif2_ctrl),
  3727. SH_PFC_PIN_GROUP(i2c0),
  3728. SH_PFC_PIN_GROUP(i2c0_b),
  3729. SH_PFC_PIN_GROUP(i2c0_c),
  3730. SH_PFC_PIN_GROUP(i2c0_d),
  3731. SH_PFC_PIN_GROUP(i2c0_e),
  3732. SH_PFC_PIN_GROUP(i2c1),
  3733. SH_PFC_PIN_GROUP(i2c1_b),
  3734. SH_PFC_PIN_GROUP(i2c1_c),
  3735. SH_PFC_PIN_GROUP(i2c1_d),
  3736. SH_PFC_PIN_GROUP(i2c1_e),
  3737. SH_PFC_PIN_GROUP(i2c2),
  3738. SH_PFC_PIN_GROUP(i2c2_b),
  3739. SH_PFC_PIN_GROUP(i2c2_c),
  3740. SH_PFC_PIN_GROUP(i2c2_d),
  3741. SH_PFC_PIN_GROUP(i2c2_e),
  3742. SH_PFC_PIN_GROUP(i2c3),
  3743. SH_PFC_PIN_GROUP(i2c3_b),
  3744. SH_PFC_PIN_GROUP(i2c3_c),
  3745. SH_PFC_PIN_GROUP(i2c3_d),
  3746. SH_PFC_PIN_GROUP(i2c3_e),
  3747. SH_PFC_PIN_GROUP(i2c4),
  3748. SH_PFC_PIN_GROUP(i2c4_b),
  3749. SH_PFC_PIN_GROUP(i2c4_c),
  3750. SH_PFC_PIN_GROUP(i2c4_d),
  3751. SH_PFC_PIN_GROUP(i2c4_e),
  3752. SH_PFC_PIN_GROUP(i2c5),
  3753. SH_PFC_PIN_GROUP(i2c5_b),
  3754. SH_PFC_PIN_GROUP(i2c5_c),
  3755. SH_PFC_PIN_GROUP(i2c5_d),
  3756. SH_PFC_PIN_GROUP(intc_irq0),
  3757. SH_PFC_PIN_GROUP(intc_irq1),
  3758. SH_PFC_PIN_GROUP(intc_irq2),
  3759. SH_PFC_PIN_GROUP(intc_irq3),
  3760. SH_PFC_PIN_GROUP(intc_irq4),
  3761. SH_PFC_PIN_GROUP(intc_irq5),
  3762. SH_PFC_PIN_GROUP(intc_irq6),
  3763. SH_PFC_PIN_GROUP(intc_irq7),
  3764. SH_PFC_PIN_GROUP(intc_irq8),
  3765. SH_PFC_PIN_GROUP(intc_irq9),
  3766. SH_PFC_PIN_GROUP(mmc_data1),
  3767. SH_PFC_PIN_GROUP(mmc_data4),
  3768. SH_PFC_PIN_GROUP(mmc_data8),
  3769. SH_PFC_PIN_GROUP(mmc_ctrl),
  3770. SH_PFC_PIN_GROUP(msiof0_clk),
  3771. SH_PFC_PIN_GROUP(msiof0_sync),
  3772. SH_PFC_PIN_GROUP(msiof0_ss1),
  3773. SH_PFC_PIN_GROUP(msiof0_ss2),
  3774. SH_PFC_PIN_GROUP(msiof0_rx),
  3775. SH_PFC_PIN_GROUP(msiof0_tx),
  3776. SH_PFC_PIN_GROUP(msiof1_clk),
  3777. SH_PFC_PIN_GROUP(msiof1_sync),
  3778. SH_PFC_PIN_GROUP(msiof1_ss1),
  3779. SH_PFC_PIN_GROUP(msiof1_ss2),
  3780. SH_PFC_PIN_GROUP(msiof1_rx),
  3781. SH_PFC_PIN_GROUP(msiof1_tx),
  3782. SH_PFC_PIN_GROUP(msiof1_clk_b),
  3783. SH_PFC_PIN_GROUP(msiof1_sync_b),
  3784. SH_PFC_PIN_GROUP(msiof1_ss1_b),
  3785. SH_PFC_PIN_GROUP(msiof1_ss2_b),
  3786. SH_PFC_PIN_GROUP(msiof1_rx_b),
  3787. SH_PFC_PIN_GROUP(msiof1_tx_b),
  3788. SH_PFC_PIN_GROUP(msiof2_clk),
  3789. SH_PFC_PIN_GROUP(msiof2_sync),
  3790. SH_PFC_PIN_GROUP(msiof2_ss1),
  3791. SH_PFC_PIN_GROUP(msiof2_ss2),
  3792. SH_PFC_PIN_GROUP(msiof2_rx),
  3793. SH_PFC_PIN_GROUP(msiof2_tx),
  3794. SH_PFC_PIN_GROUP(msiof2_clk_b),
  3795. SH_PFC_PIN_GROUP(msiof2_sync_b),
  3796. SH_PFC_PIN_GROUP(msiof2_ss1_b),
  3797. SH_PFC_PIN_GROUP(msiof2_ss2_b),
  3798. SH_PFC_PIN_GROUP(msiof2_rx_b),
  3799. SH_PFC_PIN_GROUP(msiof2_tx_b),
  3800. SH_PFC_PIN_GROUP(pwm0),
  3801. SH_PFC_PIN_GROUP(pwm0_b),
  3802. SH_PFC_PIN_GROUP(pwm1),
  3803. SH_PFC_PIN_GROUP(pwm1_b),
  3804. SH_PFC_PIN_GROUP(pwm1_c),
  3805. SH_PFC_PIN_GROUP(pwm2),
  3806. SH_PFC_PIN_GROUP(pwm2_b),
  3807. SH_PFC_PIN_GROUP(pwm2_c),
  3808. SH_PFC_PIN_GROUP(pwm3),
  3809. SH_PFC_PIN_GROUP(pwm3_b),
  3810. SH_PFC_PIN_GROUP(pwm4),
  3811. SH_PFC_PIN_GROUP(pwm4_b),
  3812. SH_PFC_PIN_GROUP(pwm5),
  3813. SH_PFC_PIN_GROUP(pwm5_b),
  3814. SH_PFC_PIN_GROUP(pwm5_c),
  3815. SH_PFC_PIN_GROUP(pwm6),
  3816. SH_PFC_PIN_GROUP(pwm6_b),
  3817. SH_PFC_PIN_GROUP(qspi_ctrl),
  3818. SH_PFC_PIN_GROUP(qspi_data2),
  3819. SH_PFC_PIN_GROUP(qspi_data4),
  3820. SH_PFC_PIN_GROUP(scif0_data),
  3821. SH_PFC_PIN_GROUP(scif0_data_b),
  3822. SH_PFC_PIN_GROUP(scif0_data_c),
  3823. SH_PFC_PIN_GROUP(scif0_data_d),
  3824. SH_PFC_PIN_GROUP(scif1_data),
  3825. SH_PFC_PIN_GROUP(scif1_clk),
  3826. SH_PFC_PIN_GROUP(scif1_data_b),
  3827. SH_PFC_PIN_GROUP(scif1_clk_b),
  3828. SH_PFC_PIN_GROUP(scif1_data_c),
  3829. SH_PFC_PIN_GROUP(scif1_clk_c),
  3830. SH_PFC_PIN_GROUP(scif2_data),
  3831. SH_PFC_PIN_GROUP(scif2_clk),
  3832. SH_PFC_PIN_GROUP(scif2_data_b),
  3833. SH_PFC_PIN_GROUP(scif2_clk_b),
  3834. SH_PFC_PIN_GROUP(scif2_data_c),
  3835. SH_PFC_PIN_GROUP(scif2_clk_c),
  3836. SH_PFC_PIN_GROUP(scif3_data),
  3837. SH_PFC_PIN_GROUP(scif3_clk),
  3838. SH_PFC_PIN_GROUP(scif3_data_b),
  3839. SH_PFC_PIN_GROUP(scif3_clk_b),
  3840. SH_PFC_PIN_GROUP(scif4_data),
  3841. SH_PFC_PIN_GROUP(scif4_data_b),
  3842. SH_PFC_PIN_GROUP(scif4_data_c),
  3843. SH_PFC_PIN_GROUP(scif4_data_d),
  3844. SH_PFC_PIN_GROUP(scif4_data_e),
  3845. SH_PFC_PIN_GROUP(scif5_data),
  3846. SH_PFC_PIN_GROUP(scif5_data_b),
  3847. SH_PFC_PIN_GROUP(scif5_data_c),
  3848. SH_PFC_PIN_GROUP(scif5_data_d),
  3849. SH_PFC_PIN_GROUP(scifa0_data),
  3850. SH_PFC_PIN_GROUP(scifa0_data_b),
  3851. SH_PFC_PIN_GROUP(scifa0_data_c),
  3852. SH_PFC_PIN_GROUP(scifa0_data_d),
  3853. SH_PFC_PIN_GROUP(scifa1_data),
  3854. SH_PFC_PIN_GROUP(scifa1_clk),
  3855. SH_PFC_PIN_GROUP(scifa1_data_b),
  3856. SH_PFC_PIN_GROUP(scifa1_clk_b),
  3857. SH_PFC_PIN_GROUP(scifa1_data_c),
  3858. SH_PFC_PIN_GROUP(scifa1_clk_c),
  3859. SH_PFC_PIN_GROUP(scifa2_data),
  3860. SH_PFC_PIN_GROUP(scifa2_clk),
  3861. SH_PFC_PIN_GROUP(scifa2_data_b),
  3862. SH_PFC_PIN_GROUP(scifa2_clk_b),
  3863. SH_PFC_PIN_GROUP(scifa3_data),
  3864. SH_PFC_PIN_GROUP(scifa3_clk),
  3865. SH_PFC_PIN_GROUP(scifa3_data_b),
  3866. SH_PFC_PIN_GROUP(scifa3_clk_b),
  3867. SH_PFC_PIN_GROUP(scifa4_data),
  3868. SH_PFC_PIN_GROUP(scifa4_data_b),
  3869. SH_PFC_PIN_GROUP(scifa4_data_c),
  3870. SH_PFC_PIN_GROUP(scifa4_data_d),
  3871. SH_PFC_PIN_GROUP(scifa5_data),
  3872. SH_PFC_PIN_GROUP(scifa5_data_b),
  3873. SH_PFC_PIN_GROUP(scifa5_data_c),
  3874. SH_PFC_PIN_GROUP(scifa5_data_d),
  3875. SH_PFC_PIN_GROUP(scifb0_data),
  3876. SH_PFC_PIN_GROUP(scifb0_clk),
  3877. SH_PFC_PIN_GROUP(scifb0_ctrl),
  3878. SH_PFC_PIN_GROUP(scifb1_data),
  3879. SH_PFC_PIN_GROUP(scifb1_clk),
  3880. SH_PFC_PIN_GROUP(scifb2_data),
  3881. SH_PFC_PIN_GROUP(scifb2_clk),
  3882. SH_PFC_PIN_GROUP(scifb2_ctrl),
  3883. SH_PFC_PIN_GROUP(scif_clk),
  3884. SH_PFC_PIN_GROUP(scif_clk_b),
  3885. SH_PFC_PIN_GROUP(sdhi0_data1),
  3886. SH_PFC_PIN_GROUP(sdhi0_data4),
  3887. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  3888. SH_PFC_PIN_GROUP(sdhi0_cd),
  3889. SH_PFC_PIN_GROUP(sdhi0_wp),
  3890. SH_PFC_PIN_GROUP(sdhi1_data1),
  3891. SH_PFC_PIN_GROUP(sdhi1_data4),
  3892. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  3893. SH_PFC_PIN_GROUP(sdhi1_cd),
  3894. SH_PFC_PIN_GROUP(sdhi1_wp),
  3895. SH_PFC_PIN_GROUP(sdhi2_data1),
  3896. SH_PFC_PIN_GROUP(sdhi2_data4),
  3897. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  3898. SH_PFC_PIN_GROUP(sdhi2_cd),
  3899. SH_PFC_PIN_GROUP(sdhi2_wp),
  3900. SH_PFC_PIN_GROUP(ssi0_data),
  3901. SH_PFC_PIN_GROUP(ssi0129_ctrl),
  3902. SH_PFC_PIN_GROUP(ssi1_data),
  3903. SH_PFC_PIN_GROUP(ssi1_ctrl),
  3904. SH_PFC_PIN_GROUP(ssi1_data_b),
  3905. SH_PFC_PIN_GROUP(ssi1_ctrl_b),
  3906. SH_PFC_PIN_GROUP(ssi2_data),
  3907. SH_PFC_PIN_GROUP(ssi2_ctrl),
  3908. SH_PFC_PIN_GROUP(ssi2_data_b),
  3909. SH_PFC_PIN_GROUP(ssi2_ctrl_b),
  3910. SH_PFC_PIN_GROUP(ssi3_data),
  3911. SH_PFC_PIN_GROUP(ssi34_ctrl),
  3912. SH_PFC_PIN_GROUP(ssi4_data),
  3913. SH_PFC_PIN_GROUP(ssi4_ctrl),
  3914. SH_PFC_PIN_GROUP(ssi4_data_b),
  3915. SH_PFC_PIN_GROUP(ssi4_ctrl_b),
  3916. SH_PFC_PIN_GROUP(ssi5_data),
  3917. SH_PFC_PIN_GROUP(ssi5_ctrl),
  3918. SH_PFC_PIN_GROUP(ssi5_data_b),
  3919. SH_PFC_PIN_GROUP(ssi5_ctrl_b),
  3920. SH_PFC_PIN_GROUP(ssi6_data),
  3921. SH_PFC_PIN_GROUP(ssi6_ctrl),
  3922. SH_PFC_PIN_GROUP(ssi6_data_b),
  3923. SH_PFC_PIN_GROUP(ssi6_ctrl_b),
  3924. SH_PFC_PIN_GROUP(ssi7_data),
  3925. SH_PFC_PIN_GROUP(ssi78_ctrl),
  3926. SH_PFC_PIN_GROUP(ssi7_data_b),
  3927. SH_PFC_PIN_GROUP(ssi78_ctrl_b),
  3928. SH_PFC_PIN_GROUP(ssi8_data),
  3929. SH_PFC_PIN_GROUP(ssi8_data_b),
  3930. SH_PFC_PIN_GROUP(ssi9_data),
  3931. SH_PFC_PIN_GROUP(ssi9_ctrl),
  3932. SH_PFC_PIN_GROUP(ssi9_data_b),
  3933. SH_PFC_PIN_GROUP(ssi9_ctrl_b),
  3934. SH_PFC_PIN_GROUP(tpu_to0),
  3935. SH_PFC_PIN_GROUP(tpu_to0_b),
  3936. SH_PFC_PIN_GROUP(tpu_to0_c),
  3937. SH_PFC_PIN_GROUP(tpu_to1),
  3938. SH_PFC_PIN_GROUP(tpu_to1_b),
  3939. SH_PFC_PIN_GROUP(tpu_to1_c),
  3940. SH_PFC_PIN_GROUP(tpu_to2),
  3941. SH_PFC_PIN_GROUP(tpu_to2_b),
  3942. SH_PFC_PIN_GROUP(tpu_to2_c),
  3943. SH_PFC_PIN_GROUP(tpu_to3),
  3944. SH_PFC_PIN_GROUP(tpu_to3_b),
  3945. SH_PFC_PIN_GROUP(tpu_to3_c),
  3946. SH_PFC_PIN_GROUP(usb0),
  3947. SH_PFC_PIN_GROUP(usb1),
  3948. VIN_DATA_PIN_GROUP(vin0_data, 24),
  3949. VIN_DATA_PIN_GROUP(vin0_data, 20),
  3950. SH_PFC_PIN_GROUP(vin0_data18),
  3951. VIN_DATA_PIN_GROUP(vin0_data, 16),
  3952. VIN_DATA_PIN_GROUP(vin0_data, 12),
  3953. VIN_DATA_PIN_GROUP(vin0_data, 10),
  3954. VIN_DATA_PIN_GROUP(vin0_data, 8),
  3955. SH_PFC_PIN_GROUP(vin0_sync),
  3956. SH_PFC_PIN_GROUP(vin0_field),
  3957. SH_PFC_PIN_GROUP(vin0_clkenb),
  3958. SH_PFC_PIN_GROUP(vin0_clk),
  3959. VIN_DATA_PIN_GROUP(vin1_data, 12),
  3960. VIN_DATA_PIN_GROUP(vin1_data, 10),
  3961. VIN_DATA_PIN_GROUP(vin1_data, 8),
  3962. SH_PFC_PIN_GROUP(vin1_sync),
  3963. SH_PFC_PIN_GROUP(vin1_field),
  3964. SH_PFC_PIN_GROUP(vin1_clkenb),
  3965. SH_PFC_PIN_GROUP(vin1_clk),
  3966. };
  3967. static const char * const audio_clk_groups[] = {
  3968. "audio_clka",
  3969. "audio_clka_b",
  3970. "audio_clka_c",
  3971. "audio_clka_d",
  3972. "audio_clkb",
  3973. "audio_clkb_b",
  3974. "audio_clkb_c",
  3975. "audio_clkc",
  3976. "audio_clkc_b",
  3977. "audio_clkc_c",
  3978. "audio_clkout",
  3979. "audio_clkout_b",
  3980. "audio_clkout_c",
  3981. };
  3982. static const char * const avb_groups[] = {
  3983. "avb_link",
  3984. "avb_magic",
  3985. "avb_phy_int",
  3986. "avb_mdio",
  3987. "avb_mii",
  3988. "avb_gmii",
  3989. };
  3990. static const char * const can0_groups[] = {
  3991. "can0_data",
  3992. "can0_data_b",
  3993. "can0_data_c",
  3994. "can0_data_d",
  3995. /*
  3996. * Retained for backwards compatibility, use can_clk_groups in new
  3997. * designs.
  3998. */
  3999. "can_clk",
  4000. "can_clk_b",
  4001. "can_clk_c",
  4002. "can_clk_d",
  4003. };
  4004. static const char * const can1_groups[] = {
  4005. "can1_data",
  4006. "can1_data_b",
  4007. "can1_data_c",
  4008. "can1_data_d",
  4009. /*
  4010. * Retained for backwards compatibility, use can_clk_groups in new
  4011. * designs.
  4012. */
  4013. "can_clk",
  4014. "can_clk_b",
  4015. "can_clk_c",
  4016. "can_clk_d",
  4017. };
  4018. /*
  4019. * can_clk_groups allows for independent configuration, use can_clk function
  4020. * in new designs.
  4021. */
  4022. static const char * const can_clk_groups[] = {
  4023. "can_clk",
  4024. "can_clk_b",
  4025. "can_clk_c",
  4026. "can_clk_d",
  4027. };
  4028. static const char * const du0_groups[] = {
  4029. "du0_rgb666",
  4030. "du0_rgb888",
  4031. "du0_clk0_out",
  4032. "du0_clk1_out",
  4033. "du0_clk_in",
  4034. "du0_sync",
  4035. "du0_oddf",
  4036. "du0_cde",
  4037. "du0_disp",
  4038. };
  4039. static const char * const du1_groups[] = {
  4040. "du1_rgb666",
  4041. "du1_rgb888",
  4042. "du1_clk0_out",
  4043. "du1_clk1_out",
  4044. "du1_clk_in",
  4045. "du1_sync",
  4046. "du1_oddf",
  4047. "du1_cde",
  4048. "du1_disp",
  4049. };
  4050. static const char * const eth_groups[] = {
  4051. "eth_link",
  4052. "eth_magic",
  4053. "eth_mdio",
  4054. "eth_rmii",
  4055. "eth_link_b",
  4056. "eth_magic_b",
  4057. "eth_mdio_b",
  4058. "eth_rmii_b",
  4059. };
  4060. static const char * const hscif0_groups[] = {
  4061. "hscif0_data",
  4062. "hscif0_clk",
  4063. "hscif0_ctrl",
  4064. "hscif0_data_b",
  4065. "hscif0_clk_b",
  4066. };
  4067. static const char * const hscif1_groups[] = {
  4068. "hscif1_data",
  4069. "hscif1_clk",
  4070. "hscif1_ctrl",
  4071. "hscif1_data_b",
  4072. "hscif1_ctrl_b",
  4073. };
  4074. static const char * const hscif2_groups[] = {
  4075. "hscif2_data",
  4076. "hscif2_clk",
  4077. "hscif2_ctrl",
  4078. };
  4079. static const char * const i2c0_groups[] = {
  4080. "i2c0",
  4081. "i2c0_b",
  4082. "i2c0_c",
  4083. "i2c0_d",
  4084. "i2c0_e",
  4085. };
  4086. static const char * const i2c1_groups[] = {
  4087. "i2c1",
  4088. "i2c1_b",
  4089. "i2c1_c",
  4090. "i2c1_d",
  4091. "i2c1_e",
  4092. };
  4093. static const char * const i2c2_groups[] = {
  4094. "i2c2",
  4095. "i2c2_b",
  4096. "i2c2_c",
  4097. "i2c2_d",
  4098. "i2c2_e",
  4099. };
  4100. static const char * const i2c3_groups[] = {
  4101. "i2c3",
  4102. "i2c3_b",
  4103. "i2c3_c",
  4104. "i2c3_d",
  4105. "i2c3_e",
  4106. };
  4107. static const char * const i2c4_groups[] = {
  4108. "i2c4",
  4109. "i2c4_b",
  4110. "i2c4_c",
  4111. "i2c4_d",
  4112. "i2c4_e",
  4113. };
  4114. static const char * const i2c5_groups[] = {
  4115. "i2c5",
  4116. "i2c5_b",
  4117. "i2c5_c",
  4118. "i2c5_d",
  4119. };
  4120. static const char * const intc_groups[] = {
  4121. "intc_irq0",
  4122. "intc_irq1",
  4123. "intc_irq2",
  4124. "intc_irq3",
  4125. "intc_irq4",
  4126. "intc_irq5",
  4127. "intc_irq6",
  4128. "intc_irq7",
  4129. "intc_irq8",
  4130. "intc_irq9",
  4131. };
  4132. static const char * const mmc_groups[] = {
  4133. "mmc_data1",
  4134. "mmc_data4",
  4135. "mmc_data8",
  4136. "mmc_ctrl",
  4137. };
  4138. static const char * const msiof0_groups[] = {
  4139. "msiof0_clk",
  4140. "msiof0_sync",
  4141. "msiof0_ss1",
  4142. "msiof0_ss2",
  4143. "msiof0_rx",
  4144. "msiof0_tx",
  4145. };
  4146. static const char * const msiof1_groups[] = {
  4147. "msiof1_clk",
  4148. "msiof1_sync",
  4149. "msiof1_ss1",
  4150. "msiof1_ss2",
  4151. "msiof1_rx",
  4152. "msiof1_tx",
  4153. "msiof1_clk_b",
  4154. "msiof1_sync_b",
  4155. "msiof1_ss1_b",
  4156. "msiof1_ss2_b",
  4157. "msiof1_rx_b",
  4158. "msiof1_tx_b",
  4159. };
  4160. static const char * const msiof2_groups[] = {
  4161. "msiof2_clk",
  4162. "msiof2_sync",
  4163. "msiof2_ss1",
  4164. "msiof2_ss2",
  4165. "msiof2_rx",
  4166. "msiof2_tx",
  4167. "msiof2_clk_b",
  4168. "msiof2_sync_b",
  4169. "msiof2_ss1_b",
  4170. "msiof2_ss2_b",
  4171. "msiof2_rx_b",
  4172. "msiof2_tx_b",
  4173. };
  4174. static const char * const pwm0_groups[] = {
  4175. "pwm0",
  4176. "pwm0_b",
  4177. };
  4178. static const char * const pwm1_groups[] = {
  4179. "pwm1",
  4180. "pwm1_b",
  4181. "pwm1_c",
  4182. };
  4183. static const char * const pwm2_groups[] = {
  4184. "pwm2",
  4185. "pwm2_b",
  4186. "pwm2_c",
  4187. };
  4188. static const char * const pwm3_groups[] = {
  4189. "pwm3",
  4190. "pwm3_b",
  4191. };
  4192. static const char * const pwm4_groups[] = {
  4193. "pwm4",
  4194. "pwm4_b",
  4195. };
  4196. static const char * const pwm5_groups[] = {
  4197. "pwm5",
  4198. "pwm5_b",
  4199. "pwm5_c",
  4200. };
  4201. static const char * const pwm6_groups[] = {
  4202. "pwm6",
  4203. "pwm6_b",
  4204. };
  4205. static const char * const qspi_groups[] = {
  4206. "qspi_ctrl",
  4207. "qspi_data2",
  4208. "qspi_data4",
  4209. };
  4210. static const char * const scif0_groups[] = {
  4211. "scif0_data",
  4212. "scif0_data_b",
  4213. "scif0_data_c",
  4214. "scif0_data_d",
  4215. };
  4216. static const char * const scif1_groups[] = {
  4217. "scif1_data",
  4218. "scif1_clk",
  4219. "scif1_data_b",
  4220. "scif1_clk_b",
  4221. "scif1_data_c",
  4222. "scif1_clk_c",
  4223. };
  4224. static const char * const scif2_groups[] = {
  4225. "scif2_data",
  4226. "scif2_clk",
  4227. "scif2_data_b",
  4228. "scif2_clk_b",
  4229. "scif2_data_c",
  4230. "scif2_clk_c",
  4231. };
  4232. static const char * const scif3_groups[] = {
  4233. "scif3_data",
  4234. "scif3_clk",
  4235. "scif3_data_b",
  4236. "scif3_clk_b",
  4237. };
  4238. static const char * const scif4_groups[] = {
  4239. "scif4_data",
  4240. "scif4_data_b",
  4241. "scif4_data_c",
  4242. "scif4_data_d",
  4243. "scif4_data_e",
  4244. };
  4245. static const char * const scif5_groups[] = {
  4246. "scif5_data",
  4247. "scif5_data_b",
  4248. "scif5_data_c",
  4249. "scif5_data_d",
  4250. };
  4251. static const char * const scifa0_groups[] = {
  4252. "scifa0_data",
  4253. "scifa0_data_b",
  4254. "scifa0_data_c",
  4255. "scifa0_data_d",
  4256. };
  4257. static const char * const scifa1_groups[] = {
  4258. "scifa1_data",
  4259. "scifa1_clk",
  4260. "scifa1_data_b",
  4261. "scifa1_clk_b",
  4262. "scifa1_data_c",
  4263. "scifa1_clk_c",
  4264. };
  4265. static const char * const scifa2_groups[] = {
  4266. "scifa2_data",
  4267. "scifa2_clk",
  4268. "scifa2_data_b",
  4269. "scifa2_clk_b",
  4270. };
  4271. static const char * const scifa3_groups[] = {
  4272. "scifa3_data",
  4273. "scifa3_clk",
  4274. "scifa3_data_b",
  4275. "scifa3_clk_b",
  4276. };
  4277. static const char * const scifa4_groups[] = {
  4278. "scifa4_data",
  4279. "scifa4_data_b",
  4280. "scifa4_data_c",
  4281. "scifa4_data_d",
  4282. };
  4283. static const char * const scifa5_groups[] = {
  4284. "scifa5_data",
  4285. "scifa5_data_b",
  4286. "scifa5_data_c",
  4287. "scifa5_data_d",
  4288. };
  4289. static const char * const scifb0_groups[] = {
  4290. "scifb0_data",
  4291. "scifb0_clk",
  4292. "scifb0_ctrl",
  4293. };
  4294. static const char * const scifb1_groups[] = {
  4295. "scifb1_data",
  4296. "scifb1_clk",
  4297. };
  4298. static const char * const scifb2_groups[] = {
  4299. "scifb2_data",
  4300. "scifb2_clk",
  4301. "scifb2_ctrl",
  4302. };
  4303. static const char * const scif_clk_groups[] = {
  4304. "scif_clk",
  4305. "scif_clk_b",
  4306. };
  4307. static const char * const sdhi0_groups[] = {
  4308. "sdhi0_data1",
  4309. "sdhi0_data4",
  4310. "sdhi0_ctrl",
  4311. "sdhi0_cd",
  4312. "sdhi0_wp",
  4313. };
  4314. static const char * const sdhi1_groups[] = {
  4315. "sdhi1_data1",
  4316. "sdhi1_data4",
  4317. "sdhi1_ctrl",
  4318. "sdhi1_cd",
  4319. "sdhi1_wp",
  4320. };
  4321. static const char * const sdhi2_groups[] = {
  4322. "sdhi2_data1",
  4323. "sdhi2_data4",
  4324. "sdhi2_ctrl",
  4325. "sdhi2_cd",
  4326. "sdhi2_wp",
  4327. };
  4328. static const char * const ssi_groups[] = {
  4329. "ssi0_data",
  4330. "ssi0129_ctrl",
  4331. "ssi1_data",
  4332. "ssi1_ctrl",
  4333. "ssi1_data_b",
  4334. "ssi1_ctrl_b",
  4335. "ssi2_data",
  4336. "ssi2_ctrl",
  4337. "ssi2_data_b",
  4338. "ssi2_ctrl_b",
  4339. "ssi3_data",
  4340. "ssi34_ctrl",
  4341. "ssi4_data",
  4342. "ssi4_ctrl",
  4343. "ssi4_data_b",
  4344. "ssi4_ctrl_b",
  4345. "ssi5_data",
  4346. "ssi5_ctrl",
  4347. "ssi5_data_b",
  4348. "ssi5_ctrl_b",
  4349. "ssi6_data",
  4350. "ssi6_ctrl",
  4351. "ssi6_data_b",
  4352. "ssi6_ctrl_b",
  4353. "ssi7_data",
  4354. "ssi78_ctrl",
  4355. "ssi7_data_b",
  4356. "ssi78_ctrl_b",
  4357. "ssi8_data",
  4358. "ssi8_data_b",
  4359. "ssi9_data",
  4360. "ssi9_ctrl",
  4361. "ssi9_data_b",
  4362. "ssi9_ctrl_b",
  4363. };
  4364. static const char * const tpu_groups[] = {
  4365. "tpu_to0",
  4366. "tpu_to0_b",
  4367. "tpu_to0_c",
  4368. "tpu_to1",
  4369. "tpu_to1_b",
  4370. "tpu_to1_c",
  4371. "tpu_to2",
  4372. "tpu_to2_b",
  4373. "tpu_to2_c",
  4374. "tpu_to3",
  4375. "tpu_to3_b",
  4376. "tpu_to3_c",
  4377. };
  4378. static const char * const usb0_groups[] = {
  4379. "usb0",
  4380. };
  4381. static const char * const usb1_groups[] = {
  4382. "usb1",
  4383. };
  4384. static const char * const vin0_groups[] = {
  4385. "vin0_data24",
  4386. "vin0_data20",
  4387. "vin0_data18",
  4388. "vin0_data16",
  4389. "vin0_data12",
  4390. "vin0_data10",
  4391. "vin0_data8",
  4392. "vin0_sync",
  4393. "vin0_field",
  4394. "vin0_clkenb",
  4395. "vin0_clk",
  4396. };
  4397. static const char * const vin1_groups[] = {
  4398. "vin1_data12",
  4399. "vin1_data10",
  4400. "vin1_data8",
  4401. "vin1_sync",
  4402. "vin1_field",
  4403. "vin1_clkenb",
  4404. "vin1_clk",
  4405. };
  4406. static const struct sh_pfc_function pinmux_functions[] = {
  4407. SH_PFC_FUNCTION(audio_clk),
  4408. SH_PFC_FUNCTION(avb),
  4409. SH_PFC_FUNCTION(can0),
  4410. SH_PFC_FUNCTION(can1),
  4411. SH_PFC_FUNCTION(can_clk),
  4412. SH_PFC_FUNCTION(du0),
  4413. SH_PFC_FUNCTION(du1),
  4414. SH_PFC_FUNCTION(eth),
  4415. SH_PFC_FUNCTION(hscif0),
  4416. SH_PFC_FUNCTION(hscif1),
  4417. SH_PFC_FUNCTION(hscif2),
  4418. SH_PFC_FUNCTION(i2c0),
  4419. SH_PFC_FUNCTION(i2c1),
  4420. SH_PFC_FUNCTION(i2c2),
  4421. SH_PFC_FUNCTION(i2c3),
  4422. SH_PFC_FUNCTION(i2c4),
  4423. SH_PFC_FUNCTION(i2c5),
  4424. SH_PFC_FUNCTION(intc),
  4425. SH_PFC_FUNCTION(mmc),
  4426. SH_PFC_FUNCTION(msiof0),
  4427. SH_PFC_FUNCTION(msiof1),
  4428. SH_PFC_FUNCTION(msiof2),
  4429. SH_PFC_FUNCTION(pwm0),
  4430. SH_PFC_FUNCTION(pwm1),
  4431. SH_PFC_FUNCTION(pwm2),
  4432. SH_PFC_FUNCTION(pwm3),
  4433. SH_PFC_FUNCTION(pwm4),
  4434. SH_PFC_FUNCTION(pwm5),
  4435. SH_PFC_FUNCTION(pwm6),
  4436. SH_PFC_FUNCTION(qspi),
  4437. SH_PFC_FUNCTION(scif0),
  4438. SH_PFC_FUNCTION(scif1),
  4439. SH_PFC_FUNCTION(scif2),
  4440. SH_PFC_FUNCTION(scif3),
  4441. SH_PFC_FUNCTION(scif4),
  4442. SH_PFC_FUNCTION(scif5),
  4443. SH_PFC_FUNCTION(scifa0),
  4444. SH_PFC_FUNCTION(scifa1),
  4445. SH_PFC_FUNCTION(scifa2),
  4446. SH_PFC_FUNCTION(scifa3),
  4447. SH_PFC_FUNCTION(scifa4),
  4448. SH_PFC_FUNCTION(scifa5),
  4449. SH_PFC_FUNCTION(scifb0),
  4450. SH_PFC_FUNCTION(scifb1),
  4451. SH_PFC_FUNCTION(scifb2),
  4452. SH_PFC_FUNCTION(scif_clk),
  4453. SH_PFC_FUNCTION(sdhi0),
  4454. SH_PFC_FUNCTION(sdhi1),
  4455. SH_PFC_FUNCTION(sdhi2),
  4456. SH_PFC_FUNCTION(ssi),
  4457. SH_PFC_FUNCTION(tpu),
  4458. SH_PFC_FUNCTION(usb0),
  4459. SH_PFC_FUNCTION(usb1),
  4460. SH_PFC_FUNCTION(vin0),
  4461. SH_PFC_FUNCTION(vin1),
  4462. };
  4463. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  4464. { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
  4465. GP_0_31_FN, FN_IP2_17_16,
  4466. GP_0_30_FN, FN_IP2_15_14,
  4467. GP_0_29_FN, FN_IP2_13_12,
  4468. GP_0_28_FN, FN_IP2_11_10,
  4469. GP_0_27_FN, FN_IP2_9_8,
  4470. GP_0_26_FN, FN_IP2_7_6,
  4471. GP_0_25_FN, FN_IP2_5_4,
  4472. GP_0_24_FN, FN_IP2_3_2,
  4473. GP_0_23_FN, FN_IP2_1_0,
  4474. GP_0_22_FN, FN_IP1_31_30,
  4475. GP_0_21_FN, FN_IP1_29_28,
  4476. GP_0_20_FN, FN_IP1_27,
  4477. GP_0_19_FN, FN_IP1_26,
  4478. GP_0_18_FN, FN_A2,
  4479. GP_0_17_FN, FN_IP1_24,
  4480. GP_0_16_FN, FN_IP1_23_22,
  4481. GP_0_15_FN, FN_IP1_21_20,
  4482. GP_0_14_FN, FN_IP1_19_18,
  4483. GP_0_13_FN, FN_IP1_17_15,
  4484. GP_0_12_FN, FN_IP1_14_13,
  4485. GP_0_11_FN, FN_IP1_12_11,
  4486. GP_0_10_FN, FN_IP1_10_8,
  4487. GP_0_9_FN, FN_IP1_7_6,
  4488. GP_0_8_FN, FN_IP1_5_4,
  4489. GP_0_7_FN, FN_IP1_3_2,
  4490. GP_0_6_FN, FN_IP1_1_0,
  4491. GP_0_5_FN, FN_IP0_31_30,
  4492. GP_0_4_FN, FN_IP0_29_28,
  4493. GP_0_3_FN, FN_IP0_27_26,
  4494. GP_0_2_FN, FN_IP0_25,
  4495. GP_0_1_FN, FN_IP0_24,
  4496. GP_0_0_FN, FN_IP0_23_22, ))
  4497. },
  4498. { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
  4499. 0, 0,
  4500. 0, 0,
  4501. 0, 0,
  4502. 0, 0,
  4503. 0, 0,
  4504. 0, 0,
  4505. GP_1_25_FN, FN_DACK0,
  4506. GP_1_24_FN, FN_IP7_31,
  4507. GP_1_23_FN, FN_IP4_1_0,
  4508. GP_1_22_FN, FN_WE1_N,
  4509. GP_1_21_FN, FN_WE0_N,
  4510. GP_1_20_FN, FN_IP3_31,
  4511. GP_1_19_FN, FN_IP3_30,
  4512. GP_1_18_FN, FN_IP3_29_27,
  4513. GP_1_17_FN, FN_IP3_26_24,
  4514. GP_1_16_FN, FN_IP3_23_21,
  4515. GP_1_15_FN, FN_IP3_20_18,
  4516. GP_1_14_FN, FN_IP3_17_15,
  4517. GP_1_13_FN, FN_IP3_14_13,
  4518. GP_1_12_FN, FN_IP3_12,
  4519. GP_1_11_FN, FN_IP3_11,
  4520. GP_1_10_FN, FN_IP3_10,
  4521. GP_1_9_FN, FN_IP3_9_8,
  4522. GP_1_8_FN, FN_IP3_7_6,
  4523. GP_1_7_FN, FN_IP3_5_4,
  4524. GP_1_6_FN, FN_IP3_3_2,
  4525. GP_1_5_FN, FN_IP3_1_0,
  4526. GP_1_4_FN, FN_IP2_31_30,
  4527. GP_1_3_FN, FN_IP2_29_27,
  4528. GP_1_2_FN, FN_IP2_26_24,
  4529. GP_1_1_FN, FN_IP2_23_21,
  4530. GP_1_0_FN, FN_IP2_20_18, ))
  4531. },
  4532. { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
  4533. GP_2_31_FN, FN_IP6_7_6,
  4534. GP_2_30_FN, FN_IP6_5_4,
  4535. GP_2_29_FN, FN_IP6_3_2,
  4536. GP_2_28_FN, FN_IP6_1_0,
  4537. GP_2_27_FN, FN_IP5_31_30,
  4538. GP_2_26_FN, FN_IP5_29_28,
  4539. GP_2_25_FN, FN_IP5_27_26,
  4540. GP_2_24_FN, FN_IP5_25_24,
  4541. GP_2_23_FN, FN_IP5_23_22,
  4542. GP_2_22_FN, FN_IP5_21_20,
  4543. GP_2_21_FN, FN_IP5_19_18,
  4544. GP_2_20_FN, FN_IP5_17_16,
  4545. GP_2_19_FN, FN_IP5_15_14,
  4546. GP_2_18_FN, FN_IP5_13_12,
  4547. GP_2_17_FN, FN_IP5_11_9,
  4548. GP_2_16_FN, FN_IP5_8_6,
  4549. GP_2_15_FN, FN_IP5_5_4,
  4550. GP_2_14_FN, FN_IP5_3_2,
  4551. GP_2_13_FN, FN_IP5_1_0,
  4552. GP_2_12_FN, FN_IP4_31_30,
  4553. GP_2_11_FN, FN_IP4_29_28,
  4554. GP_2_10_FN, FN_IP4_27_26,
  4555. GP_2_9_FN, FN_IP4_25_23,
  4556. GP_2_8_FN, FN_IP4_22_20,
  4557. GP_2_7_FN, FN_IP4_19_18,
  4558. GP_2_6_FN, FN_IP4_17_16,
  4559. GP_2_5_FN, FN_IP4_15_14,
  4560. GP_2_4_FN, FN_IP4_13_12,
  4561. GP_2_3_FN, FN_IP4_11_10,
  4562. GP_2_2_FN, FN_IP4_9_8,
  4563. GP_2_1_FN, FN_IP4_7_5,
  4564. GP_2_0_FN, FN_IP4_4_2 ))
  4565. },
  4566. { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
  4567. GP_3_31_FN, FN_IP8_22_20,
  4568. GP_3_30_FN, FN_IP8_19_17,
  4569. GP_3_29_FN, FN_IP8_16_15,
  4570. GP_3_28_FN, FN_IP8_14_12,
  4571. GP_3_27_FN, FN_IP8_11_9,
  4572. GP_3_26_FN, FN_IP8_8_6,
  4573. GP_3_25_FN, FN_IP8_5_3,
  4574. GP_3_24_FN, FN_IP8_2_0,
  4575. GP_3_23_FN, FN_IP7_29_27,
  4576. GP_3_22_FN, FN_IP7_26_24,
  4577. GP_3_21_FN, FN_IP7_23_21,
  4578. GP_3_20_FN, FN_IP7_20_18,
  4579. GP_3_19_FN, FN_IP7_17_15,
  4580. GP_3_18_FN, FN_IP7_14_12,
  4581. GP_3_17_FN, FN_IP7_11_9,
  4582. GP_3_16_FN, FN_IP7_8_6,
  4583. GP_3_15_FN, FN_IP7_5_3,
  4584. GP_3_14_FN, FN_IP7_2_0,
  4585. GP_3_13_FN, FN_IP6_31_29,
  4586. GP_3_12_FN, FN_IP6_28_26,
  4587. GP_3_11_FN, FN_IP6_25_23,
  4588. GP_3_10_FN, FN_IP6_22_20,
  4589. GP_3_9_FN, FN_IP6_19_17,
  4590. GP_3_8_FN, FN_IP6_16,
  4591. GP_3_7_FN, FN_IP6_15,
  4592. GP_3_6_FN, FN_IP6_14,
  4593. GP_3_5_FN, FN_IP6_13,
  4594. GP_3_4_FN, FN_IP6_12,
  4595. GP_3_3_FN, FN_IP6_11,
  4596. GP_3_2_FN, FN_IP6_10,
  4597. GP_3_1_FN, FN_IP6_9,
  4598. GP_3_0_FN, FN_IP6_8 ))
  4599. },
  4600. { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
  4601. GP_4_31_FN, FN_IP11_17_16,
  4602. GP_4_30_FN, FN_IP11_15_14,
  4603. GP_4_29_FN, FN_IP11_13_11,
  4604. GP_4_28_FN, FN_IP11_10_8,
  4605. GP_4_27_FN, FN_IP11_7_6,
  4606. GP_4_26_FN, FN_IP11_5_3,
  4607. GP_4_25_FN, FN_IP11_2_0,
  4608. GP_4_24_FN, FN_IP10_31_30,
  4609. GP_4_23_FN, FN_IP10_29_27,
  4610. GP_4_22_FN, FN_IP10_26_24,
  4611. GP_4_21_FN, FN_IP10_23_21,
  4612. GP_4_20_FN, FN_IP10_20_18,
  4613. GP_4_19_FN, FN_IP10_17_15,
  4614. GP_4_18_FN, FN_IP10_14_12,
  4615. GP_4_17_FN, FN_IP10_11_9,
  4616. GP_4_16_FN, FN_IP10_8_6,
  4617. GP_4_15_FN, FN_IP10_5_3,
  4618. GP_4_14_FN, FN_IP10_2_0,
  4619. GP_4_13_FN, FN_IP9_30_28,
  4620. GP_4_12_FN, FN_IP9_27_25,
  4621. GP_4_11_FN, FN_IP9_24_22,
  4622. GP_4_10_FN, FN_IP9_21_19,
  4623. GP_4_9_FN, FN_IP9_18_17,
  4624. GP_4_8_FN, FN_IP9_16_15,
  4625. GP_4_7_FN, FN_IP9_14_12,
  4626. GP_4_6_FN, FN_IP9_11_9,
  4627. GP_4_5_FN, FN_IP9_8_6,
  4628. GP_4_4_FN, FN_IP9_5_3,
  4629. GP_4_3_FN, FN_IP9_2_0,
  4630. GP_4_2_FN, FN_IP8_31_29,
  4631. GP_4_1_FN, FN_IP8_28_26,
  4632. GP_4_0_FN, FN_IP8_25_23 ))
  4633. },
  4634. { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
  4635. 0, 0,
  4636. 0, 0,
  4637. 0, 0,
  4638. 0, 0,
  4639. GP_5_27_FN, FN_USB1_OVC,
  4640. GP_5_26_FN, FN_USB1_PWEN,
  4641. GP_5_25_FN, FN_USB0_OVC,
  4642. GP_5_24_FN, FN_USB0_PWEN,
  4643. GP_5_23_FN, FN_IP13_26_24,
  4644. GP_5_22_FN, FN_IP13_23_21,
  4645. GP_5_21_FN, FN_IP13_20_18,
  4646. GP_5_20_FN, FN_IP13_17_15,
  4647. GP_5_19_FN, FN_IP13_14_12,
  4648. GP_5_18_FN, FN_IP13_11_9,
  4649. GP_5_17_FN, FN_IP13_8_6,
  4650. GP_5_16_FN, FN_IP13_5_3,
  4651. GP_5_15_FN, FN_IP13_2_0,
  4652. GP_5_14_FN, FN_IP12_29_27,
  4653. GP_5_13_FN, FN_IP12_26_24,
  4654. GP_5_12_FN, FN_IP12_23_21,
  4655. GP_5_11_FN, FN_IP12_20_18,
  4656. GP_5_10_FN, FN_IP12_17_15,
  4657. GP_5_9_FN, FN_IP12_14_13,
  4658. GP_5_8_FN, FN_IP12_12_11,
  4659. GP_5_7_FN, FN_IP12_10_9,
  4660. GP_5_6_FN, FN_IP12_8_6,
  4661. GP_5_5_FN, FN_IP12_5_3,
  4662. GP_5_4_FN, FN_IP12_2_0,
  4663. GP_5_3_FN, FN_IP11_29_27,
  4664. GP_5_2_FN, FN_IP11_26_24,
  4665. GP_5_1_FN, FN_IP11_23_21,
  4666. GP_5_0_FN, FN_IP11_20_18 ))
  4667. },
  4668. { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
  4669. 0, 0,
  4670. 0, 0,
  4671. 0, 0,
  4672. 0, 0,
  4673. 0, 0,
  4674. 0, 0,
  4675. GP_6_25_FN, FN_IP0_21_20,
  4676. GP_6_24_FN, FN_IP0_19_18,
  4677. GP_6_23_FN, FN_IP0_17,
  4678. GP_6_22_FN, FN_IP0_16,
  4679. GP_6_21_FN, FN_IP0_15,
  4680. GP_6_20_FN, FN_IP0_14,
  4681. GP_6_19_FN, FN_IP0_13,
  4682. GP_6_18_FN, FN_IP0_12,
  4683. GP_6_17_FN, FN_IP0_11,
  4684. GP_6_16_FN, FN_IP0_10,
  4685. GP_6_15_FN, FN_IP0_9_8,
  4686. GP_6_14_FN, FN_IP0_0,
  4687. GP_6_13_FN, FN_SD1_DATA3,
  4688. GP_6_12_FN, FN_SD1_DATA2,
  4689. GP_6_11_FN, FN_SD1_DATA1,
  4690. GP_6_10_FN, FN_SD1_DATA0,
  4691. GP_6_9_FN, FN_SD1_CMD,
  4692. GP_6_8_FN, FN_SD1_CLK,
  4693. GP_6_7_FN, FN_SD0_WP,
  4694. GP_6_6_FN, FN_SD0_CD,
  4695. GP_6_5_FN, FN_SD0_DATA3,
  4696. GP_6_4_FN, FN_SD0_DATA2,
  4697. GP_6_3_FN, FN_SD0_DATA1,
  4698. GP_6_2_FN, FN_SD0_DATA0,
  4699. GP_6_1_FN, FN_SD0_CMD,
  4700. GP_6_0_FN, FN_SD0_CLK ))
  4701. },
  4702. { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
  4703. GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
  4704. 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
  4705. GROUP(
  4706. /* IP0_31_30 [2] */
  4707. FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
  4708. /* IP0_29_28 [2] */
  4709. FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
  4710. /* IP0_27_26 [2] */
  4711. FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
  4712. /* IP0_25 [1] */
  4713. FN_D2, FN_SCIFA3_TXD_B,
  4714. /* IP0_24 [1] */
  4715. FN_D1, FN_SCIFA3_RXD_B,
  4716. /* IP0_23_22 [2] */
  4717. FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
  4718. /* IP0_21_20 [2] */
  4719. FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
  4720. /* IP0_19_18 [2] */
  4721. FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
  4722. /* IP0_17 [1] */
  4723. FN_MMC_D5, FN_SD2_WP,
  4724. /* IP0_16 [1] */
  4725. FN_MMC_D4, FN_SD2_CD,
  4726. /* IP0_15 [1] */
  4727. FN_MMC_D3, FN_SD2_DATA3,
  4728. /* IP0_14 [1] */
  4729. FN_MMC_D2, FN_SD2_DATA2,
  4730. /* IP0_13 [1] */
  4731. FN_MMC_D1, FN_SD2_DATA1,
  4732. /* IP0_12 [1] */
  4733. FN_MMC_D0, FN_SD2_DATA0,
  4734. /* IP0_11 [1] */
  4735. FN_MMC_CMD, FN_SD2_CMD,
  4736. /* IP0_10 [1] */
  4737. FN_MMC_CLK, FN_SD2_CLK,
  4738. /* IP0_9_8 [2] */
  4739. FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
  4740. /* IP0_7 [1] */
  4741. 0, 0,
  4742. /* IP0_6 [1] */
  4743. 0, 0,
  4744. /* IP0_5 [1] */
  4745. 0, 0,
  4746. /* IP0_4 [1] */
  4747. 0, 0,
  4748. /* IP0_3 [1] */
  4749. 0, 0,
  4750. /* IP0_2 [1] */
  4751. 0, 0,
  4752. /* IP0_1 [1] */
  4753. 0, 0,
  4754. /* IP0_0 [1] */
  4755. FN_SD1_CD, FN_CAN0_RX, ))
  4756. },
  4757. { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
  4758. GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
  4759. 3, 2, 2, 2, 2),
  4760. GROUP(
  4761. /* IP1_31_30 [2] */
  4762. FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
  4763. /* IP1_29_28 [2] */
  4764. FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
  4765. /* IP1_27 [1] */
  4766. FN_A4, FN_SCIFB0_TXD,
  4767. /* IP1_26 [1] */
  4768. FN_A3, FN_SCIFB0_SCK,
  4769. /* IP1_25 [1] */
  4770. 0, 0,
  4771. /* IP1_24 [1] */
  4772. FN_A1, FN_SCIFB1_TXD,
  4773. /* IP1_23_22 [2] */
  4774. FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
  4775. /* IP1_21_20 [2] */
  4776. FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
  4777. /* IP1_19_18 [2] */
  4778. FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
  4779. /* IP1_17_15 [3] */
  4780. FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
  4781. 0, 0, 0,
  4782. /* IP1_14_13 [2] */
  4783. FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
  4784. /* IP1_12_11 [2] */
  4785. FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
  4786. /* IP1_10_8 [3] */
  4787. FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
  4788. 0, 0, 0,
  4789. /* IP1_7_6 [2] */
  4790. FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
  4791. /* IP1_5_4 [2] */
  4792. FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
  4793. /* IP1_3_2 [2] */
  4794. FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
  4795. /* IP1_1_0 [2] */
  4796. FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
  4797. },
  4798. { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
  4799. GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
  4800. GROUP(
  4801. /* IP2_31_30 [2] */
  4802. FN_A20, FN_SPCLK, 0, 0,
  4803. /* IP2_29_27 [3] */
  4804. FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
  4805. 0, 0, 0, 0,
  4806. /* IP2_26_24 [3] */
  4807. FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
  4808. 0, 0, 0, 0,
  4809. /* IP2_23_21 [3] */
  4810. FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
  4811. 0, 0, 0, 0,
  4812. /* IP2_20_18 [3] */
  4813. FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
  4814. 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
  4815. /* IP2_17_16 [2] */
  4816. FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
  4817. /* IP2_15_14 [2] */
  4818. FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
  4819. /* IP2_13_12 [2] */
  4820. FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
  4821. /* IP2_11_10 [2] */
  4822. FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
  4823. /* IP2_9_8 [2] */
  4824. FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
  4825. /* IP2_7_6 [2] */
  4826. FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
  4827. /* IP2_5_4 [2] */
  4828. FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
  4829. /* IP2_3_2 [2] */
  4830. FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
  4831. /* IP2_1_0 [2] */
  4832. FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
  4833. },
  4834. { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
  4835. GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
  4836. 2, 2, 2, 2),
  4837. GROUP(
  4838. /* IP3_31 [1] */
  4839. FN_RD_WR_N, FN_ATAG1_N,
  4840. /* IP3_30 [1] */
  4841. FN_RD_N, FN_ATACS11_N,
  4842. /* IP3_29_27 [3] */
  4843. FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
  4844. 0, 0, 0,
  4845. /* IP3_26_24 [3] */
  4846. FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
  4847. 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
  4848. /* IP3_23_21 [3] */
  4849. FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
  4850. 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
  4851. /* IP3_20_18 [3] */
  4852. FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
  4853. 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
  4854. /* IP3_17_15 [3] */
  4855. FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
  4856. 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
  4857. /* IP3_14_13 [2] */
  4858. FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
  4859. /* IP3_12 [1] */
  4860. FN_EX_CS0_N, FN_VI1_DATA10,
  4861. /* IP3_11 [1] */
  4862. FN_CS1_N_A26, FN_VI1_DATA9,
  4863. /* IP3_10 [1] */
  4864. FN_CS0_N, FN_VI1_DATA8,
  4865. /* IP3_9_8 [2] */
  4866. FN_A25, FN_SSL, FN_ATARD1_N, 0,
  4867. /* IP3_7_6 [2] */
  4868. FN_A24, FN_IO3, FN_EX_WAIT2, 0,
  4869. /* IP3_5_4 [2] */
  4870. FN_A23, FN_IO2, 0, FN_ATAWR1_N,
  4871. /* IP3_3_2 [2] */
  4872. FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
  4873. /* IP3_1_0 [2] */
  4874. FN_A21, FN_MOSI_IO0, 0, 0, ))
  4875. },
  4876. { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
  4877. GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
  4878. GROUP(
  4879. /* IP4_31_30 [2] */
  4880. FN_DU0_DG4, FN_LCDOUT12, 0, 0,
  4881. /* IP4_29_28 [2] */
  4882. FN_DU0_DG3, FN_LCDOUT11, 0, 0,
  4883. /* IP4_27_26 [2] */
  4884. FN_DU0_DG2, FN_LCDOUT10, 0, 0,
  4885. /* IP4_25_23 [3] */
  4886. FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
  4887. 0, 0, 0, 0,
  4888. /* IP4_22_20 [3] */
  4889. FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
  4890. 0, 0, 0, 0,
  4891. /* IP4_19_18 [2] */
  4892. FN_DU0_DR7, FN_LCDOUT23, 0, 0,
  4893. /* IP4_17_16 [2] */
  4894. FN_DU0_DR6, FN_LCDOUT22, 0, 0,
  4895. /* IP4_15_14 [2] */
  4896. FN_DU0_DR5, FN_LCDOUT21, 0, 0,
  4897. /* IP4_13_12 [2] */
  4898. FN_DU0_DR4, FN_LCDOUT20, 0, 0,
  4899. /* IP4_11_10 [2] */
  4900. FN_DU0_DR3, FN_LCDOUT19, 0, 0,
  4901. /* IP4_9_8 [2] */
  4902. FN_DU0_DR2, FN_LCDOUT18, 0, 0,
  4903. /* IP4_7_5 [3] */
  4904. FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
  4905. 0, 0, 0, 0,
  4906. /* IP4_4_2 [3] */
  4907. FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
  4908. 0, 0, 0, 0,
  4909. /* IP4_1_0 [2] */
  4910. FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
  4911. },
  4912. { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
  4913. GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
  4914. 2, 2, 2),
  4915. GROUP(
  4916. /* IP5_31_30 [2] */
  4917. FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
  4918. /* IP5_29_28 [2] */
  4919. FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
  4920. /* IP5_27_26 [2] */
  4921. FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
  4922. /* IP5_25_24 [2] */
  4923. FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
  4924. /* IP5_23_22 [2] */
  4925. FN_DU0_DB7, FN_LCDOUT7, 0, 0,
  4926. /* IP5_21_20 [2] */
  4927. FN_DU0_DB6, FN_LCDOUT6, 0, 0,
  4928. /* IP5_19_18 [2] */
  4929. FN_DU0_DB5, FN_LCDOUT5, 0, 0,
  4930. /* IP5_17_16 [2] */
  4931. FN_DU0_DB4, FN_LCDOUT4, 0, 0,
  4932. /* IP5_15_14 [2] */
  4933. FN_DU0_DB3, FN_LCDOUT3, 0, 0,
  4934. /* IP5_13_12 [2] */
  4935. FN_DU0_DB2, FN_LCDOUT2, 0, 0,
  4936. /* IP5_11_9 [3] */
  4937. FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
  4938. FN_CAN0_TX_C, 0, 0, 0,
  4939. /* IP5_8_6 [3] */
  4940. FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
  4941. FN_CAN0_RX_C, 0, 0, 0,
  4942. /* IP5_5_4 [2] */
  4943. FN_DU0_DG7, FN_LCDOUT15, 0, 0,
  4944. /* IP5_3_2 [2] */
  4945. FN_DU0_DG6, FN_LCDOUT14, 0, 0,
  4946. /* IP5_1_0 [2] */
  4947. FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
  4948. },
  4949. { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
  4950. GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
  4951. 1, 1, 2, 2, 2, 2),
  4952. GROUP(
  4953. /* IP6_31_29 [3] */
  4954. FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
  4955. FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
  4956. /* IP6_28_26 [3] */
  4957. FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
  4958. FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
  4959. /* IP6_25_23 [3] */
  4960. FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
  4961. FN_AVB_COL, 0, 0, 0,
  4962. /* IP6_22_20 [3] */
  4963. FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
  4964. FN_AVB_RX_ER, 0, 0, 0,
  4965. /* IP6_19_17 [3] */
  4966. FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
  4967. FN_AVB_RXD7, 0, 0, 0,
  4968. /* IP6_16 [1] */
  4969. FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
  4970. /* IP6_15 [1] */
  4971. FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
  4972. /* IP6_14 [1] */
  4973. FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
  4974. /* IP6_13 [1] */
  4975. FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
  4976. /* IP6_12 [1] */
  4977. FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
  4978. /* IP6_11 [1] */
  4979. FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
  4980. /* IP6_10 [1] */
  4981. FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
  4982. /* IP6_9 [1] */
  4983. FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
  4984. /* IP6_8 [1] */
  4985. FN_VI0_CLK, FN_AVB_RX_CLK,
  4986. /* IP6_7_6 [2] */
  4987. FN_DU0_CDE, FN_QPOLB, 0, 0,
  4988. /* IP6_5_4 [2] */
  4989. FN_DU0_DISP, FN_QPOLA, 0, 0,
  4990. /* IP6_3_2 [2] */
  4991. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
  4992. 0,
  4993. /* IP6_1_0 [2] */
  4994. FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
  4995. },
  4996. { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
  4997. GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  4998. GROUP(
  4999. /* IP7_31 [1] */
  5000. FN_DREQ0_N, FN_SCIFB1_RXD,
  5001. /* IP7_30 [1] */
  5002. 0, 0,
  5003. /* IP7_29_27 [3] */
  5004. FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
  5005. FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
  5006. /* IP7_26_24 [3] */
  5007. FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
  5008. FN_SSI_SCK6_B, 0, 0, 0,
  5009. /* IP7_23_21 [3] */
  5010. FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
  5011. FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
  5012. /* IP7_20_18 [3] */
  5013. FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
  5014. FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
  5015. /* IP7_17_15 [3] */
  5016. FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
  5017. FN_SSI_SCK5_B, 0, 0, 0,
  5018. /* IP7_14_12 [3] */
  5019. FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
  5020. FN_AVB_TXD4, FN_ADICHS2, 0, 0,
  5021. /* IP7_11_9 [3] */
  5022. FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
  5023. FN_AVB_TXD3, FN_ADICHS1, 0, 0,
  5024. /* IP7_8_6 [3] */
  5025. FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
  5026. FN_AVB_TXD2, FN_ADICHS0, 0, 0,
  5027. /* IP7_5_3 [3] */
  5028. FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
  5029. FN_AVB_TXD1, FN_ADICLK, 0, 0,
  5030. /* IP7_2_0 [3] */
  5031. FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
  5032. FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
  5033. },
  5034. { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
  5035. GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
  5036. GROUP(
  5037. /* IP8_31_29 [3] */
  5038. FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
  5039. 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
  5040. /* IP8_28_26 [3] */
  5041. FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
  5042. 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
  5043. /* IP8_25_23 [3] */
  5044. FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
  5045. 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
  5046. /* IP8_22_20 [3] */
  5047. FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
  5048. FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
  5049. /* IP8_19_17 [3] */
  5050. FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
  5051. FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
  5052. /* IP8_16_15 [2] */
  5053. FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
  5054. /* IP8_14_12 [3] */
  5055. FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
  5056. FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
  5057. /* IP8_11_9 [3] */
  5058. FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
  5059. FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
  5060. /* IP8_8_6 [3] */
  5061. FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
  5062. FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
  5063. /* IP8_5_3 [3] */
  5064. FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
  5065. FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
  5066. /* IP8_2_0 [3] */
  5067. FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
  5068. FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
  5069. },
  5070. { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
  5071. GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
  5072. GROUP(
  5073. /* IP9_31 [1] */
  5074. 0, 0,
  5075. /* IP9_30_28 [3] */
  5076. FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
  5077. FN_SSI_SDATA1_B, 0, 0, 0,
  5078. /* IP9_27_25 [3] */
  5079. FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
  5080. FN_SSI_WS1_B, 0, 0, 0,
  5081. /* IP9_24_22 [3] */
  5082. FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
  5083. FN_SSI_SCK1_B, 0, 0, 0,
  5084. /* IP9_21_19 [3] */
  5085. FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
  5086. FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
  5087. /* IP9_18_17 [2] */
  5088. FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
  5089. /* IP9_16_15 [2] */
  5090. FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
  5091. /* IP9_14_12 [3] */
  5092. FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
  5093. 0, FN_FMIN_B, 0, 0,
  5094. /* IP9_11_9 [3] */
  5095. FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
  5096. 0, FN_FMCLK_B, 0, 0,
  5097. /* IP9_8_6 [3] */
  5098. FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
  5099. 0, FN_BPFCLK_B, 0, 0,
  5100. /* IP9_5_3 [3] */
  5101. FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
  5102. 0, FN_TPUTO1_C, 0, 0,
  5103. /* IP9_2_0 [3] */
  5104. FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
  5105. 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
  5106. },
  5107. { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
  5108. GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  5109. GROUP(
  5110. /* IP10_31_30 [2] */
  5111. FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
  5112. /* IP10_29_27 [3] */
  5113. FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
  5114. 0, 0, 0, 0,
  5115. /* IP10_26_24 [3] */
  5116. FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
  5117. FN_SSI_SDATA4_B, 0, 0, 0,
  5118. /* IP10_23_21 [3] */
  5119. FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
  5120. FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
  5121. /* IP10_20_18 [3] */
  5122. FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
  5123. FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
  5124. /* IP10_17_15 [3] */
  5125. FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
  5126. FN_SSI_SDATA9_B, 0, 0, 0,
  5127. /* IP10_14_12 [3] */
  5128. FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
  5129. 0, 0, 0, 0,
  5130. /* IP10_11_9 [3] */
  5131. FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
  5132. 0, 0, 0, 0,
  5133. /* IP10_8_6 [3] */
  5134. FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
  5135. 0, 0, 0, 0,
  5136. /* IP10_5_3 [3] */
  5137. FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
  5138. 0, 0, 0, 0,
  5139. /* IP10_2_0 [3] */
  5140. FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
  5141. 0, 0, 0, 0, ))
  5142. },
  5143. { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
  5144. GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
  5145. GROUP(
  5146. /* IP11_31_30 [2] */
  5147. 0, 0, 0, 0,
  5148. /* IP11_29_27 [3] */
  5149. FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
  5150. 0, 0, 0, 0,
  5151. /* IP11_26_24 [3] */
  5152. FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
  5153. 0, 0, 0, 0,
  5154. /* IP11_23_21 [3] */
  5155. FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
  5156. 0, 0, 0, 0,
  5157. /* IP11_20_18 [3] */
  5158. FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
  5159. FN_CAN_CLK_D, 0, 0, 0,
  5160. /* IP11_17_16 [2] */
  5161. FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
  5162. /* IP11_15_14 [2] */
  5163. FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
  5164. /* IP11_13_11 [3] */
  5165. FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
  5166. FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
  5167. /* IP11_10_8 [3] */
  5168. FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
  5169. FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
  5170. /* IP11_7_6 [2] */
  5171. FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
  5172. /* IP11_5_3 [3] */
  5173. FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
  5174. 0, 0, 0, 0,
  5175. /* IP11_2_0 [3] */
  5176. FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
  5177. 0, 0, 0, 0, ))
  5178. },
  5179. { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
  5180. GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
  5181. GROUP(
  5182. /* IP12_31_30 [2] */
  5183. 0, 0, 0, 0,
  5184. /* IP12_29_27 [3] */
  5185. FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
  5186. FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
  5187. /* IP12_26_24 [3] */
  5188. FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
  5189. FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
  5190. /* IP12_23_21 [3] */
  5191. FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
  5192. FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
  5193. /* IP12_20_18 [3] */
  5194. FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
  5195. FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
  5196. /* IP12_17_15 [3] */
  5197. FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
  5198. FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
  5199. /* IP12_14_13 [2] */
  5200. FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
  5201. /* IP12_12_11 [2] */
  5202. FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
  5203. /* IP12_10_9 [2] */
  5204. FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
  5205. /* IP12_8_6 [3] */
  5206. FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
  5207. FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
  5208. /* IP12_5_3 [3] */
  5209. FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
  5210. FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
  5211. /* IP12_2_0 [3] */
  5212. FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
  5213. 0, FN_DREQ1_N_B, 0, 0, ))
  5214. },
  5215. { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
  5216. GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  5217. GROUP(
  5218. /* IP13_31 [1] */
  5219. 0, 0,
  5220. /* IP13_30 [1] */
  5221. 0, 0,
  5222. /* IP13_29 [1] */
  5223. 0, 0,
  5224. /* IP13_28 [1] */
  5225. 0, 0,
  5226. /* IP13_27 [1] */
  5227. 0, 0,
  5228. /* IP13_26_24 [3] */
  5229. FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
  5230. FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
  5231. /* IP13_23_21 [3] */
  5232. FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
  5233. FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
  5234. /* IP13_20_18 [3] */
  5235. FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
  5236. FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
  5237. /* IP13_17_15 [3] */
  5238. FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
  5239. FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
  5240. /* IP13_14_12 [3] */
  5241. FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
  5242. FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
  5243. /* IP13_11_9 [3] */
  5244. FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
  5245. FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
  5246. /* IP13_8_6 [3] */
  5247. FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
  5248. 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
  5249. /* IP13_5_3 [2] */
  5250. FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
  5251. FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
  5252. /* IP13_2_0 [3] */
  5253. FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
  5254. 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
  5255. },
  5256. { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
  5257. GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
  5258. GROUP(
  5259. /* SEL_ADG [2] */
  5260. FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
  5261. /* RESERVED [1] */
  5262. 0, 0,
  5263. /* SEL_CAN [2] */
  5264. FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
  5265. /* SEL_DARC [3] */
  5266. FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
  5267. FN_SEL_DARC_4, 0, 0, 0,
  5268. /* RESERVED [4] */
  5269. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5270. /* SEL_ETH [1] */
  5271. FN_SEL_ETH_0, FN_SEL_ETH_1,
  5272. /* RESERVED [1] */
  5273. 0, 0,
  5274. /* SEL_IC200 [3] */
  5275. FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
  5276. FN_SEL_I2C00_4, 0, 0, 0,
  5277. /* SEL_I2C01 [3] */
  5278. FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
  5279. FN_SEL_I2C01_4, 0, 0, 0,
  5280. /* SEL_I2C02 [3] */
  5281. FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
  5282. FN_SEL_I2C02_4, 0, 0, 0,
  5283. /* SEL_I2C03 [3] */
  5284. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
  5285. FN_SEL_I2C03_4, 0, 0, 0,
  5286. /* SEL_I2C04 [3] */
  5287. FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
  5288. FN_SEL_I2C04_4, 0, 0, 0,
  5289. /* SEL_I2C05 [2] */
  5290. FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
  5291. /* RESERVED [1] */
  5292. 0, 0, ))
  5293. },
  5294. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
  5295. GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
  5296. 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
  5297. GROUP(
  5298. /* SEL_IEB [2] */
  5299. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
  5300. /* SEL_IIC0 [2] */
  5301. FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
  5302. /* SEL_LBS [1] */
  5303. FN_SEL_LBS_0, FN_SEL_LBS_1,
  5304. /* SEL_MSI1 [1] */
  5305. FN_SEL_MSI1_0, FN_SEL_MSI1_1,
  5306. /* SEL_MSI2 [1] */
  5307. FN_SEL_MSI2_0, FN_SEL_MSI2_1,
  5308. /* SEL_RAD [1] */
  5309. FN_SEL_RAD_0, FN_SEL_RAD_1,
  5310. /* SEL_RCN [1] */
  5311. FN_SEL_RCN_0, FN_SEL_RCN_1,
  5312. /* SEL_RSP [1] */
  5313. FN_SEL_RSP_0, FN_SEL_RSP_1,
  5314. /* SEL_SCIFA0 [2] */
  5315. FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
  5316. FN_SEL_SCIFA0_3,
  5317. /* SEL_SCIFA1 [2] */
  5318. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
  5319. /* SEL_SCIFA2 [1] */
  5320. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
  5321. /* SEL_SCIFA3 [1] */
  5322. FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
  5323. /* SEL_SCIFA4 [2] */
  5324. FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
  5325. FN_SEL_SCIFA4_3,
  5326. /* SEL_SCIFA5 [2] */
  5327. FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
  5328. FN_SEL_SCIFA5_3,
  5329. /* RESERVED [1] */
  5330. 0, 0,
  5331. /* SEL_TMU [1] */
  5332. FN_SEL_TMU_0, FN_SEL_TMU_1,
  5333. /* SEL_TSIF0 [2] */
  5334. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  5335. /* SEL_CAN0 [2] */
  5336. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  5337. /* SEL_CAN1 [2] */
  5338. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  5339. /* SEL_HSCIF0 [1] */
  5340. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
  5341. /* SEL_HSCIF1 [1] */
  5342. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
  5343. /* RESERVED [2] */
  5344. 0, 0, 0, 0, ))
  5345. },
  5346. { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
  5347. GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
  5348. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
  5349. GROUP(
  5350. /* SEL_SCIF0 [2] */
  5351. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  5352. /* SEL_SCIF1 [2] */
  5353. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
  5354. /* SEL_SCIF2 [2] */
  5355. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
  5356. /* SEL_SCIF3 [1] */
  5357. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
  5358. /* SEL_SCIF4 [3] */
  5359. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  5360. FN_SEL_SCIF4_4, 0, 0, 0,
  5361. /* SEL_SCIF5 [2] */
  5362. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
  5363. /* SEL_SSI1 [1] */
  5364. FN_SEL_SSI1_0, FN_SEL_SSI1_1,
  5365. /* SEL_SSI2 [1] */
  5366. FN_SEL_SSI2_0, FN_SEL_SSI2_1,
  5367. /* SEL_SSI4 [1] */
  5368. FN_SEL_SSI4_0, FN_SEL_SSI4_1,
  5369. /* SEL_SSI5 [1] */
  5370. FN_SEL_SSI5_0, FN_SEL_SSI5_1,
  5371. /* SEL_SSI6 [1] */
  5372. FN_SEL_SSI6_0, FN_SEL_SSI6_1,
  5373. /* SEL_SSI7 [1] */
  5374. FN_SEL_SSI7_0, FN_SEL_SSI7_1,
  5375. /* SEL_SSI8 [1] */
  5376. FN_SEL_SSI8_0, FN_SEL_SSI8_1,
  5377. /* SEL_SSI9 [1] */
  5378. FN_SEL_SSI9_0, FN_SEL_SSI9_1,
  5379. /* RESERVED [1] */
  5380. 0, 0,
  5381. /* RESERVED [1] */
  5382. 0, 0,
  5383. /* RESERVED [1] */
  5384. 0, 0,
  5385. /* RESERVED [1] */
  5386. 0, 0,
  5387. /* RESERVED [1] */
  5388. 0, 0,
  5389. /* RESERVED [1] */
  5390. 0, 0,
  5391. /* RESERVED [1] */
  5392. 0, 0,
  5393. /* RESERVED [1] */
  5394. 0, 0,
  5395. /* RESERVED [1] */
  5396. 0, 0,
  5397. /* RESERVED [1] */
  5398. 0, 0,
  5399. /* RESERVED [1] */
  5400. 0, 0,
  5401. /* RESERVED [1] */
  5402. 0, 0, ))
  5403. },
  5404. { },
  5405. };
  5406. static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
  5407. {
  5408. *pocctrl = 0xe606006c;
  5409. switch (pin & 0x1f) {
  5410. case 6: return 23;
  5411. case 7: return 16;
  5412. case 14: return 15;
  5413. case 15: return 8;
  5414. case 0 ... 5:
  5415. case 8 ... 13:
  5416. return 22 - (pin & 0x1f);
  5417. case 16 ... 23:
  5418. return 47 - (pin & 0x1f);
  5419. }
  5420. return -EINVAL;
  5421. }
  5422. static const struct soc_device_attribute r8a7794_tdsel[] = {
  5423. { .soc_id = "r8a7794", .revision = "ES1.0" },
  5424. { /* sentinel */ }
  5425. };
  5426. static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
  5427. {
  5428. /* Initialize TDSEL on old revisions */
  5429. if (soc_device_match(r8a7794_tdsel))
  5430. sh_pfc_write(pfc, 0xe6060068, 0x55555500);
  5431. return 0;
  5432. }
  5433. static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
  5434. .init = r8a7794_pinmux_soc_init,
  5435. .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
  5436. };
  5437. #ifdef CONFIG_PINCTRL_PFC_R8A7745
  5438. const struct sh_pfc_soc_info r8a7745_pinmux_info = {
  5439. .name = "r8a77450_pfc",
  5440. .ops = &r8a7794_pinmux_ops,
  5441. .unlock_reg = 0xe6060000, /* PMMR */
  5442. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5443. .pins = pinmux_pins,
  5444. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5445. .groups = pinmux_groups,
  5446. .nr_groups = ARRAY_SIZE(pinmux_groups),
  5447. .functions = pinmux_functions,
  5448. .nr_functions = ARRAY_SIZE(pinmux_functions),
  5449. .cfg_regs = pinmux_config_regs,
  5450. .pinmux_data = pinmux_data,
  5451. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5452. };
  5453. #endif
  5454. #ifdef CONFIG_PINCTRL_PFC_R8A7794
  5455. const struct sh_pfc_soc_info r8a7794_pinmux_info = {
  5456. .name = "r8a77940_pfc",
  5457. .ops = &r8a7794_pinmux_ops,
  5458. .unlock_reg = 0xe6060000, /* PMMR */
  5459. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5460. .pins = pinmux_pins,
  5461. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5462. .groups = pinmux_groups,
  5463. .nr_groups = ARRAY_SIZE(pinmux_groups),
  5464. .functions = pinmux_functions,
  5465. .nr_functions = ARRAY_SIZE(pinmux_functions),
  5466. .cfg_regs = pinmux_config_regs,
  5467. .pinmux_data = pinmux_data,
  5468. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5469. };
  5470. #endif