pfc-r8a7790.c 186 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A7790 processor support
  4. *
  5. * Copyright (C) 2013 Renesas Electronics Corporation
  6. * Copyright (C) 2013 Magnus Damm
  7. * Copyright (C) 2012 Renesas Solutions Corp.
  8. * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  9. */
  10. #include <linux/errno.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/sys_soc.h>
  14. #include "core.h"
  15. #include "sh_pfc.h"
  16. /*
  17. * All pins assigned to GPIO bank 3 can be used for SD interfaces in
  18. * which case they support both 3.3V and 1.8V signalling.
  19. */
  20. #define CPU_ALL_GP(fn, sfx) \
  21. PORT_GP_32(0, fn, sfx), \
  22. PORT_GP_30(1, fn, sfx), \
  23. PORT_GP_30(2, fn, sfx), \
  24. PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  25. PORT_GP_32(4, fn, sfx), \
  26. PORT_GP_32(5, fn, sfx)
  27. #define CPU_ALL_NOGP(fn) \
  28. PIN_NOGP(IIC0_SDA, "AF15", fn), \
  29. PIN_NOGP(IIC0_SCL, "AG15", fn), \
  30. PIN_NOGP(IIC3_SDA, "AH15", fn), \
  31. PIN_NOGP(IIC3_SCL, "AJ15", fn)
  32. enum {
  33. PINMUX_RESERVED = 0,
  34. PINMUX_DATA_BEGIN,
  35. GP_ALL(DATA),
  36. PINMUX_DATA_END,
  37. PINMUX_FUNCTION_BEGIN,
  38. GP_ALL(FN),
  39. /* GPSR0 */
  40. FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
  41. FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
  42. FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
  43. FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
  44. FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
  45. FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
  46. FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
  47. FN_IP3_14_12, FN_IP3_17_15,
  48. /* GPSR1 */
  49. FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
  50. FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
  51. FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
  52. FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
  53. FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
  54. FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
  55. FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
  56. /* GPSR2 */
  57. FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  58. FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
  59. FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
  60. FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
  61. FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
  62. FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
  63. FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
  64. /* GPSR3 */
  65. FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
  66. FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
  67. FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
  68. FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
  69. FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
  70. FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
  71. FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
  72. /* GPSR4 */
  73. FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
  74. FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
  75. FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
  76. FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
  77. FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
  78. FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
  79. FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
  80. FN_IP14_15_12, FN_IP14_18_16,
  81. /* GPSR5 */
  82. FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
  83. FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
  84. FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
  85. FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
  86. FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
  87. FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
  88. FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
  89. /* IPSR0 */
  90. FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
  91. FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
  92. FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
  93. FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
  94. FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
  95. FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
  96. FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
  97. FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
  98. FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
  99. FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
  100. FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
  101. FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
  102. FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
  103. FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
  104. /* IPSR1 */
  105. FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
  106. FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
  107. FN_SCIFA1_TXD_C, FN_AVB_TXD2,
  108. FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
  109. FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
  110. FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
  111. FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
  112. FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
  113. FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
  114. FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
  115. FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
  116. FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
  117. FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
  118. FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
  119. FN_A0, FN_PWM3, FN_A1, FN_PWM4,
  120. /* IPSR2 */
  121. FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
  122. FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
  123. FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
  124. FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
  125. FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
  126. FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
  127. FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
  128. FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
  129. FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
  130. FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
  131. FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
  132. /* IPSR3 */
  133. FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
  134. FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
  135. FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
  136. FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
  137. FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
  138. FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
  139. FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
  140. FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
  141. FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
  142. FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
  143. FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
  144. FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
  145. FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
  146. /* IPSR4 */
  147. FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
  148. FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
  149. FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
  150. FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
  151. FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
  152. FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
  153. FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
  154. FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
  155. FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
  156. FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
  157. FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
  158. FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
  159. FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
  160. FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
  161. FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
  162. /* IPSR5 */
  163. FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
  164. FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
  165. FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
  166. FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
  167. FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
  168. FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
  169. FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
  170. FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
  171. FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
  172. FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
  173. FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
  174. FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
  175. FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
  176. FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
  177. FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
  178. FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
  179. FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
  180. FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
  181. FN_SSI_WS78_B,
  182. /* IPSR6 */
  183. FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
  184. FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
  185. FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
  186. FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
  187. FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
  188. FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
  189. FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
  190. FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
  191. FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
  192. FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
  193. FN_I2C2_SCL_E, FN_ETH_RX_ER,
  194. FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
  195. FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
  196. FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
  197. FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
  198. FN_HRX0_E, FN_STP_ISSYNC_0_B,
  199. FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
  200. FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
  201. FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
  202. FN_ETH_REF_CLK, FN_HCTS0_N_E,
  203. FN_STP_IVCXO27_1_B, FN_HRX0_F,
  204. /* IPSR7 */
  205. FN_ETH_MDIO, FN_HRTS0_N_E,
  206. FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
  207. FN_HTX0_F, FN_BPFCLK_G,
  208. FN_ETH_TX_EN, FN_SIM0_CLK_C,
  209. FN_HRTS0_N_F, FN_ETH_MAGIC,
  210. FN_SIM0_RST_C, FN_ETH_TXD0,
  211. FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
  212. FN_ETH_MDC, FN_STP_ISD_1_B,
  213. FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
  214. FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
  215. FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
  216. FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
  217. FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
  218. FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
  219. FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
  220. FN_ATACS00_N, FN_AVB_RXD1,
  221. FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
  222. /* IPSR8 */
  223. FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
  224. FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
  225. FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
  226. FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
  227. FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
  228. FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
  229. FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
  230. FN_VI1_CLK, FN_AVB_RX_DV,
  231. FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
  232. FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
  233. FN_SCIFA1_RXD_D, FN_AVB_MDC,
  234. FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
  235. FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
  236. FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
  237. FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
  238. FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
  239. FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
  240. FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
  241. /* IPSR9 */
  242. FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
  243. FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
  244. FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
  245. FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
  246. FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
  247. FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
  248. FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
  249. FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
  250. FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
  251. FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
  252. FN_AVB_TX_EN, FN_SD1_CMD,
  253. FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
  254. FN_SD1_DAT0, FN_AVB_TX_CLK,
  255. FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
  256. FN_SCIFB0_TXD_B, FN_SD1_DAT2,
  257. FN_AVB_COL, FN_SCIFB0_CTS_N_B,
  258. FN_SD1_DAT3, FN_AVB_RXD0,
  259. FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
  260. FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
  261. FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
  262. FN_VI3_CLK_B,
  263. /* IPSR10 */
  264. FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
  265. FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
  266. FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
  267. FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
  268. FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
  269. FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
  270. FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
  271. FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
  272. FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
  273. FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
  274. FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
  275. FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
  276. FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
  277. FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
  278. FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
  279. FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
  280. FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
  281. FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
  282. FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
  283. FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
  284. FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
  285. FN_GLO_I0_B, FN_VI3_DATA6_B,
  286. /* IPSR11 */
  287. FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
  288. FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
  289. FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
  290. FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
  291. FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
  292. FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
  293. FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
  294. FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
  295. FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
  296. FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
  297. FN_FMIN_E, FN_FMIN_F,
  298. FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
  299. FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
  300. FN_I2C2_SDA_B, FN_MLB_DAT,
  301. FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
  302. FN_SSI_SCK0129, FN_CAN_CLK_B,
  303. FN_MOUT0,
  304. /* IPSR12 */
  305. FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
  306. FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
  307. FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
  308. FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
  309. FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
  310. FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
  311. FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
  312. FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
  313. FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
  314. FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
  315. FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
  316. FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
  317. FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
  318. FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
  319. FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
  320. FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
  321. FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
  322. FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
  323. FN_CAN_DEBUGOUT4,
  324. /* IPSR13 */
  325. FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
  326. FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
  327. FN_SCIFB1_CTS_N, FN_BPFCLK_D,
  328. FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
  329. FN_BPFCLK_F, FN_SSI_WS6,
  330. FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
  331. FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
  332. FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
  333. FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
  334. FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
  335. FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
  336. FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
  337. FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
  338. FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
  339. FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
  340. FN_BPFCLK_E, FN_SSI_SDATA7_B,
  341. FN_FMIN_G, FN_SSI_SDATA8,
  342. FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
  343. FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
  344. FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
  345. FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
  346. FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
  347. /* IPSR14 */
  348. FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
  349. FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
  350. FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
  351. FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
  352. FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
  353. FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
  354. FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
  355. FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
  356. FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
  357. FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
  358. FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
  359. FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
  360. FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
  361. FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
  362. FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
  363. FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
  364. FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
  365. FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
  366. FN_HRTS0_N_C,
  367. /* IPSR15 */
  368. FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
  369. FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
  370. FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
  371. FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
  372. FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
  373. FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
  374. FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
  375. FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
  376. FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
  377. FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
  378. FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
  379. FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
  380. FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
  381. FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
  382. FN_DU2_DG6, FN_LCDOUT14,
  383. /* IPSR16 */
  384. FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
  385. FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
  386. FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
  387. FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
  388. FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
  389. FN_TCLK1_B,
  390. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
  391. FN_SEL_SCIF1_4,
  392. FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
  393. FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
  394. FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
  395. FN_SEL_SCIFB1_4,
  396. FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
  397. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
  398. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
  399. FN_SEL_SCFA_0, FN_SEL_SCFA_1,
  400. FN_SEL_SOF1_0, FN_SEL_SOF1_1,
  401. FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
  402. FN_SEL_SSI6_0, FN_SEL_SSI6_1,
  403. FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
  404. FN_SEL_VI3_0, FN_SEL_VI3_1,
  405. FN_SEL_VI2_0, FN_SEL_VI2_1,
  406. FN_SEL_VI1_0, FN_SEL_VI1_1,
  407. FN_SEL_VI0_0, FN_SEL_VI0_1,
  408. FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
  409. FN_SEL_LBS_0, FN_SEL_LBS_1,
  410. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  411. FN_SEL_SOF3_0, FN_SEL_SOF3_1,
  412. FN_SEL_SOF0_0, FN_SEL_SOF0_1,
  413. FN_SEL_TMU1_0, FN_SEL_TMU1_1,
  414. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
  415. FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
  416. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  417. FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
  418. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
  419. FN_SEL_CAN1_0, FN_SEL_CAN1_1,
  420. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
  421. FN_SEL_ADI_0, FN_SEL_ADI_1,
  422. FN_SEL_SSP_0, FN_SEL_SSP_1,
  423. FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
  424. FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
  425. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
  426. FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
  427. FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
  428. FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
  429. FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
  430. FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
  431. FN_SEL_IIC0_0, FN_SEL_IIC0_1,
  432. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
  433. FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
  434. FN_SEL_IIC2_4,
  435. FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
  436. FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
  437. FN_SEL_I2C2_4,
  438. FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
  439. PINMUX_FUNCTION_END,
  440. PINMUX_MARK_BEGIN,
  441. VI1_DATA7_VI1_B7_MARK,
  442. USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
  443. USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
  444. DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
  445. D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
  446. D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
  447. VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
  448. VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
  449. VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
  450. SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
  451. VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
  452. SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
  453. VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
  454. IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
  455. I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
  456. VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
  457. D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
  458. VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
  459. D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
  460. VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
  461. SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
  462. VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
  463. SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
  464. VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
  465. D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
  466. VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
  467. D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
  468. VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
  469. SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
  470. VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
  471. D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
  472. VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
  473. A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
  474. A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
  475. PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
  476. TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
  477. A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
  478. SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
  479. A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
  480. VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
  481. A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
  482. VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
  483. A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
  484. VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
  485. A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
  486. VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
  487. A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
  488. VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
  489. A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
  490. MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
  491. VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
  492. ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
  493. ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
  494. A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
  495. AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
  496. ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
  497. VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
  498. A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
  499. A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
  500. VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
  501. VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
  502. VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
  503. VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
  504. VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
  505. VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
  506. CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
  507. VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
  508. VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
  509. MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
  510. HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
  511. VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
  512. VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
  513. EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
  514. VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
  515. EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
  516. VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
  517. INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
  518. MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
  519. VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
  520. I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
  521. CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
  522. CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
  523. VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
  524. INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
  525. VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
  526. WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
  527. VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
  528. IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
  529. VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
  530. MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
  531. VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
  532. SSI_WS78_B_MARK,
  533. DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
  534. VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
  535. DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
  536. SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
  537. INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
  538. DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
  539. MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
  540. SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
  541. ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
  542. TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
  543. I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
  544. STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
  545. IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
  546. STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
  547. SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
  548. HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
  549. TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
  550. RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
  551. STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
  552. ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
  553. STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
  554. ETH_MDIO_MARK, HRTS0_N_E_MARK,
  555. SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
  556. HTX0_F_MARK, BPFCLK_G_MARK,
  557. ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
  558. HRTS0_N_F_MARK, ETH_MAGIC_MARK,
  559. SIM0_RST_C_MARK, ETH_TXD0_MARK,
  560. STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
  561. ETH_MDC_MARK, STP_ISD_1_B_MARK,
  562. TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
  563. SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
  564. GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
  565. STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
  566. PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
  567. PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
  568. AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
  569. ATACS00_N_MARK, AVB_RXD1_MARK,
  570. VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
  571. VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
  572. VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
  573. AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
  574. AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
  575. AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
  576. AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
  577. VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
  578. VI1_CLK_MARK, AVB_RX_DV_MARK,
  579. VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
  580. AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
  581. SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
  582. VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
  583. VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
  584. AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
  585. AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
  586. AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
  587. SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
  588. SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
  589. SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
  590. SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
  591. SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
  592. SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
  593. SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
  594. GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
  595. I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
  596. MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
  597. GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
  598. I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
  599. AVB_TX_EN_MARK, SD1_CMD_MARK,
  600. AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
  601. SD1_DAT0_MARK, AVB_TX_CLK_MARK,
  602. SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
  603. SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
  604. AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
  605. SD1_DAT3_MARK, AVB_RXD0_MARK,
  606. SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
  607. TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
  608. IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
  609. VI3_CLK_B_MARK,
  610. SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
  611. GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
  612. SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
  613. VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
  614. VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
  615. VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
  616. TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
  617. SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
  618. VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
  619. TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
  620. SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
  621. VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
  622. TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
  623. SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
  624. VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
  625. GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
  626. MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
  627. HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
  628. VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
  629. TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
  630. VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
  631. GLO_I0_B_MARK, VI3_DATA6_B_MARK,
  632. SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
  633. GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
  634. TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
  635. SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
  636. MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
  637. SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
  638. MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
  639. SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
  640. VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
  641. MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
  642. FMIN_E_MARK, FMIN_F_MARK,
  643. MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
  644. MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
  645. I2C2_SDA_B_MARK, MLB_DAT_MARK,
  646. SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
  647. SSI_SCK0129_MARK, CAN_CLK_B_MARK,
  648. MOUT0_MARK,
  649. SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
  650. SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
  651. SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
  652. SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
  653. SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
  654. MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
  655. STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
  656. CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
  657. SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
  658. SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
  659. MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
  660. SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
  661. MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
  662. SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
  663. CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
  664. IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
  665. CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
  666. IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
  667. CAN_DEBUGOUT4_MARK,
  668. SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
  669. LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
  670. SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
  671. DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
  672. BPFCLK_F_MARK, SSI_WS6_MARK,
  673. SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
  674. LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
  675. FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
  676. CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
  677. SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
  678. CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
  679. SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
  680. LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
  681. STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
  682. TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
  683. BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
  684. FMIN_G_MARK, SSI_SDATA8_MARK,
  685. STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
  686. CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
  687. STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
  688. SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
  689. SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
  690. AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
  691. DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
  692. REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
  693. MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
  694. I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
  695. DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
  696. TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
  697. HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
  698. LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
  699. SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
  700. MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
  701. SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
  702. DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
  703. SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
  704. LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
  705. CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
  706. SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
  707. MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
  708. HRTS0_N_C_MARK,
  709. SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
  710. LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
  711. TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
  712. SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
  713. IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
  714. DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
  715. DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
  716. LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
  717. LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
  718. LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
  719. DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
  720. SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
  721. HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
  722. DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
  723. DU2_DG6_MARK, LCDOUT14_MARK,
  724. MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
  725. DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
  726. MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
  727. ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
  728. USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
  729. TCLK1_B_MARK,
  730. IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
  731. IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
  732. PINMUX_MARK_END,
  733. };
  734. static const u16 pinmux_data[] = {
  735. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  736. PINMUX_SINGLE(VI1_DATA7_VI1_B7),
  737. PINMUX_SINGLE(USB0_PWEN),
  738. PINMUX_SINGLE(USB0_OVC_VBUS),
  739. PINMUX_SINGLE(USB2_PWEN),
  740. PINMUX_SINGLE(USB2_OVC),
  741. PINMUX_SINGLE(AVS1),
  742. PINMUX_SINGLE(AVS2),
  743. PINMUX_SINGLE(DU_DOTCLKIN0),
  744. PINMUX_SINGLE(DU_DOTCLKIN2),
  745. PINMUX_IPSR_GPSR(IP0_2_0, D0),
  746. PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
  747. PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
  748. PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
  749. PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
  750. PINMUX_IPSR_GPSR(IP0_5_3, D1),
  751. PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
  752. PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
  753. PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
  754. PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
  755. PINMUX_IPSR_GPSR(IP0_8_6, D2),
  756. PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
  757. PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
  758. PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
  759. PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
  760. PINMUX_IPSR_GPSR(IP0_11_9, D3),
  761. PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
  762. PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
  763. PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
  764. PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
  765. PINMUX_IPSR_GPSR(IP0_15_12, D4),
  766. PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
  767. PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
  768. PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
  769. PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
  770. PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
  771. PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
  772. PINMUX_IPSR_GPSR(IP0_19_16, D5),
  773. PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
  774. PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
  775. PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
  776. PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
  777. PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
  778. PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
  779. PINMUX_IPSR_GPSR(IP0_22_20, D6),
  780. PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
  781. PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
  782. PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
  783. PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
  784. PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
  785. PINMUX_IPSR_GPSR(IP0_26_23, D7),
  786. PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
  787. PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
  788. PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
  789. PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
  790. PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
  791. PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
  792. PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
  793. PINMUX_IPSR_GPSR(IP0_30_27, D8),
  794. PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
  795. PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
  796. PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
  797. PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
  798. PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
  799. PINMUX_IPSR_GPSR(IP1_3_0, D9),
  800. PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
  801. PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
  802. PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
  803. PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
  804. PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
  805. PINMUX_IPSR_GPSR(IP1_7_4, D10),
  806. PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
  807. PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
  808. PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
  809. PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
  810. PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
  811. PINMUX_IPSR_GPSR(IP1_11_8, D11),
  812. PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
  813. PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
  814. PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
  815. PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
  816. PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
  817. PINMUX_IPSR_GPSR(IP1_14_12, D12),
  818. PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
  819. PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
  820. PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
  821. PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
  822. PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
  823. PINMUX_IPSR_GPSR(IP1_17_15, D13),
  824. PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
  825. PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
  826. PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
  827. PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
  828. PINMUX_IPSR_GPSR(IP1_21_18, D14),
  829. PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
  830. PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
  831. PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
  832. PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
  833. PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
  834. PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
  835. PINMUX_IPSR_GPSR(IP1_25_22, D15),
  836. PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
  837. PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
  838. PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
  839. PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
  840. PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
  841. PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
  842. PINMUX_IPSR_GPSR(IP1_27_26, A0),
  843. PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
  844. PINMUX_IPSR_GPSR(IP1_29_28, A1),
  845. PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
  846. PINMUX_IPSR_GPSR(IP2_2_0, A2),
  847. PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
  848. PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
  849. PINMUX_IPSR_GPSR(IP2_5_3, A3),
  850. PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
  851. PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
  852. PINMUX_IPSR_GPSR(IP2_8_6, A4),
  853. PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
  854. PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
  855. PINMUX_IPSR_GPSR(IP2_11_9, A5),
  856. PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
  857. PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
  858. PINMUX_IPSR_GPSR(IP2_14_12, A6),
  859. PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
  860. PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
  861. PINMUX_IPSR_GPSR(IP2_17_15, A7),
  862. PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
  863. PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
  864. PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
  865. PINMUX_IPSR_GPSR(IP2_21_18, A8),
  866. PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
  867. PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
  868. PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
  869. PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
  870. PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
  871. PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
  872. PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
  873. PINMUX_IPSR_GPSR(IP2_25_22, A9),
  874. PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
  875. PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
  876. PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
  877. PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
  878. PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
  879. PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
  880. PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
  881. PINMUX_IPSR_GPSR(IP2_28_26, A10),
  882. PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
  883. PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
  884. PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
  885. PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
  886. PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
  887. PINMUX_IPSR_GPSR(IP3_3_0, A11),
  888. PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
  889. PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
  890. PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
  891. PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
  892. PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
  893. PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
  894. PINMUX_IPSR_GPSR(IP3_7_4, A12),
  895. PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
  896. PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
  897. PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
  898. PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
  899. PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
  900. PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
  901. PINMUX_IPSR_GPSR(IP3_11_8, A13),
  902. PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
  903. PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
  904. PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
  905. PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
  906. PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
  907. PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
  908. PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
  909. PINMUX_IPSR_GPSR(IP3_14_12, A14),
  910. PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
  911. PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
  912. PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
  913. PINMUX_IPSR_GPSR(IP3_17_15, A15),
  914. PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
  915. PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
  916. PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
  917. PINMUX_IPSR_GPSR(IP3_19_18, A16),
  918. PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
  919. PINMUX_IPSR_GPSR(IP3_22_20, A17),
  920. PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
  921. PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
  922. PINMUX_IPSR_GPSR(IP3_25_23, A18),
  923. PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
  924. PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
  925. PINMUX_IPSR_GPSR(IP3_28_26, A19),
  926. PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
  927. PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
  928. PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
  929. PINMUX_IPSR_GPSR(IP3_31_29, A20),
  930. PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
  931. PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
  932. PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
  933. PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
  934. PINMUX_IPSR_GPSR(IP4_2_0, A21),
  935. PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
  936. PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
  937. PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
  938. PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
  939. PINMUX_IPSR_GPSR(IP4_5_3, A22),
  940. PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
  941. PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
  942. PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
  943. PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
  944. PINMUX_IPSR_GPSR(IP4_8_6, A23),
  945. PINMUX_IPSR_GPSR(IP4_8_6, IO2),
  946. PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
  947. PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
  948. PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
  949. PINMUX_IPSR_GPSR(IP4_11_9, A24),
  950. PINMUX_IPSR_GPSR(IP4_11_9, IO3),
  951. PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
  952. PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
  953. PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
  954. PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
  955. PINMUX_IPSR_GPSR(IP4_14_12, A25),
  956. PINMUX_IPSR_GPSR(IP4_14_12, SSL),
  957. PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
  958. PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
  959. PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
  960. PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
  961. PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
  962. PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
  963. PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
  964. PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
  965. PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
  966. PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
  967. PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
  968. PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
  969. PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
  970. PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
  971. PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
  972. PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
  973. PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
  974. PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
  975. PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
  976. PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
  977. PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
  978. PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
  979. PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
  980. PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
  981. PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
  982. PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
  983. PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
  984. PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
  985. PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
  986. PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
  987. PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
  988. PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
  989. PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
  990. PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
  991. PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
  992. PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
  993. PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
  994. PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
  995. PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
  996. PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
  997. PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
  998. PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
  999. PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
  1000. PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
  1001. PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
  1002. PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
  1003. PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
  1004. PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
  1005. PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
  1006. PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
  1007. PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
  1008. PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
  1009. PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
  1010. PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
  1011. PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
  1012. PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
  1013. PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
  1014. PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
  1015. PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
  1016. PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
  1017. PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
  1018. PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
  1019. PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
  1020. PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
  1021. PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
  1022. PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
  1023. PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
  1024. PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
  1025. PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
  1026. PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
  1027. PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
  1028. PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
  1029. PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
  1030. PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
  1031. PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
  1032. PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
  1033. PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
  1034. PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
  1035. PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
  1036. PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
  1037. PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
  1038. PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
  1039. PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
  1040. PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
  1041. PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
  1042. PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
  1043. PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
  1044. PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
  1045. PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
  1046. PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
  1047. PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
  1048. PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
  1049. PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
  1050. PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
  1051. PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
  1052. PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
  1053. PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
  1054. PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
  1055. PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
  1056. PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
  1057. PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
  1058. PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
  1059. PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
  1060. PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
  1061. PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
  1062. PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
  1063. PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
  1064. PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
  1065. PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
  1066. PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
  1067. PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
  1068. PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
  1069. PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
  1070. PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
  1071. PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
  1072. PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
  1073. PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
  1074. PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
  1075. PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
  1076. PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
  1077. PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
  1078. PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
  1079. PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
  1080. PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
  1081. PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
  1082. PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
  1083. PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
  1084. PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
  1085. PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
  1086. PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
  1087. PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
  1088. PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
  1089. PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
  1090. PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
  1091. PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
  1092. PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
  1093. PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
  1094. PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
  1095. PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
  1096. PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
  1097. PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
  1098. PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
  1099. PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
  1100. PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
  1101. PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
  1102. PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
  1103. PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
  1104. PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
  1105. PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
  1106. PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
  1107. PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
  1108. PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
  1109. PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
  1110. PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
  1111. PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
  1112. PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
  1113. PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
  1114. PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
  1115. PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
  1116. PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
  1117. PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
  1118. PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
  1119. PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
  1120. PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
  1121. PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
  1122. PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
  1123. PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
  1124. PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
  1125. PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
  1126. PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
  1127. PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
  1128. PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
  1129. PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
  1130. PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
  1131. PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
  1132. PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
  1133. PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
  1134. PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
  1135. PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
  1136. PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
  1137. PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
  1138. PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
  1139. PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
  1140. PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
  1141. PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
  1142. PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
  1143. PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
  1144. PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
  1145. PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
  1146. PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
  1147. PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
  1148. PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
  1149. PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
  1150. PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
  1151. PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
  1152. PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
  1153. PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
  1154. PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
  1155. PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
  1156. PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
  1157. PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
  1158. PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
  1159. PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
  1160. PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
  1161. PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
  1162. PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
  1163. PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
  1164. PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
  1165. PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
  1166. PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
  1167. PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
  1168. PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
  1169. PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
  1170. PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
  1171. PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
  1172. PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
  1173. PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
  1174. PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
  1175. PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
  1176. PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
  1177. PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
  1178. PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
  1179. PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
  1180. PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
  1181. PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
  1182. PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
  1183. PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
  1184. PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
  1185. PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
  1186. PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
  1187. PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
  1188. PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
  1189. PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
  1190. PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
  1191. PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
  1192. PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
  1193. PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
  1194. PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
  1195. PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
  1196. PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
  1197. PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
  1198. PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
  1199. PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
  1200. PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
  1201. PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
  1202. PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
  1203. PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
  1204. PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
  1205. PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
  1206. PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
  1207. PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
  1208. PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
  1209. PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
  1210. PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
  1211. PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
  1212. PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
  1213. PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
  1214. PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
  1215. PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
  1216. PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
  1217. PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
  1218. PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
  1219. PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
  1220. PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
  1221. PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
  1222. PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
  1223. PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
  1224. PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
  1225. PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
  1226. PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
  1227. PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
  1228. PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
  1229. PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
  1230. PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
  1231. PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
  1232. PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
  1233. PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
  1234. PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
  1235. PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
  1236. PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
  1237. PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
  1238. PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
  1239. PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
  1240. PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
  1241. PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
  1242. PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
  1243. PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
  1244. PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
  1245. PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
  1246. PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
  1247. PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
  1248. PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
  1249. PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
  1250. PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
  1251. PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
  1252. PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
  1253. PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
  1254. PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
  1255. PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
  1256. PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
  1257. PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
  1258. PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
  1259. PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
  1260. PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
  1261. PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
  1262. PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
  1263. PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
  1264. PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
  1265. PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
  1266. PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
  1267. PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
  1268. PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
  1269. PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
  1270. PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
  1271. PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
  1272. PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
  1273. PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
  1274. PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
  1275. PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
  1276. PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
  1277. PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
  1278. PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
  1279. PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
  1280. PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
  1281. PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
  1282. PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
  1283. PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
  1284. PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
  1285. PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
  1286. PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
  1287. PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
  1288. PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
  1289. PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
  1290. PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
  1291. PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
  1292. PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
  1293. PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
  1294. PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
  1295. PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
  1296. PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
  1297. PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
  1298. PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
  1299. PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
  1300. PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
  1301. PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
  1302. PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
  1303. PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
  1304. PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
  1305. PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
  1306. PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
  1307. PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
  1308. PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
  1309. PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
  1310. PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
  1311. PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
  1312. PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
  1313. PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
  1314. PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
  1315. PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
  1316. PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
  1317. PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
  1318. PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
  1319. PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
  1320. PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
  1321. PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
  1322. PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
  1323. PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
  1324. PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
  1325. PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
  1326. PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
  1327. PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
  1328. PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
  1329. PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
  1330. PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
  1331. PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
  1332. PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
  1333. PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
  1334. PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
  1335. PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
  1336. PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
  1337. PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
  1338. PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
  1339. PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
  1340. PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
  1341. PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
  1342. PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
  1343. PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
  1344. PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
  1345. PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
  1346. PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
  1347. PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
  1348. PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
  1349. PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
  1350. PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
  1351. PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
  1352. PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
  1353. PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
  1354. PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
  1355. PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
  1356. PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
  1357. PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
  1358. PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
  1359. PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
  1360. PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
  1361. PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
  1362. PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
  1363. PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
  1364. PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
  1365. PINMUX_IPSR_GPSR(IP11_17_15, VSP),
  1366. PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
  1367. PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
  1368. PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
  1369. PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
  1370. PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
  1371. PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
  1372. PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
  1373. PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
  1374. PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
  1375. PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
  1376. PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
  1377. PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
  1378. PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
  1379. PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
  1380. PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
  1381. PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
  1382. PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
  1383. PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
  1384. PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
  1385. PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
  1386. PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
  1387. PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
  1388. PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
  1389. PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
  1390. PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
  1391. PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
  1392. PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
  1393. PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
  1394. PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
  1395. PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
  1396. PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
  1397. PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
  1398. PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
  1399. PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
  1400. PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
  1401. PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
  1402. PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
  1403. PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
  1404. PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
  1405. PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
  1406. PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
  1407. PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
  1408. PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
  1409. PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
  1410. PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
  1411. PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
  1412. PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
  1413. PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
  1414. PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
  1415. PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
  1416. PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
  1417. PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
  1418. PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
  1419. PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
  1420. PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
  1421. PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
  1422. PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
  1423. PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
  1424. PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
  1425. PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
  1426. PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
  1427. PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
  1428. PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
  1429. PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
  1430. PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
  1431. PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
  1432. PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
  1433. PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
  1434. PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
  1435. PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
  1436. PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
  1437. PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
  1438. PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
  1439. PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
  1440. PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
  1441. PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
  1442. PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
  1443. PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
  1444. PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
  1445. PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
  1446. PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
  1447. PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
  1448. PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
  1449. PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
  1450. PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
  1451. PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
  1452. PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
  1453. PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
  1454. PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
  1455. PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
  1456. PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
  1457. PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
  1458. PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
  1459. PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
  1460. PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
  1461. PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
  1462. PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
  1463. PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
  1464. PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
  1465. PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
  1466. PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
  1467. PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
  1468. PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
  1469. PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
  1470. PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
  1471. PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
  1472. PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
  1473. PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
  1474. PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
  1475. PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
  1476. PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
  1477. PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
  1478. PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
  1479. PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
  1480. PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
  1481. PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
  1482. PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
  1483. PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
  1484. PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
  1485. PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
  1486. PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
  1487. PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
  1488. PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
  1489. PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
  1490. PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
  1491. PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
  1492. PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
  1493. PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
  1494. PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
  1495. PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
  1496. PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
  1497. PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
  1498. PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
  1499. PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
  1500. PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
  1501. PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
  1502. PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
  1503. PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
  1504. PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
  1505. PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
  1506. PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
  1507. PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
  1508. PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
  1509. PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
  1510. PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
  1511. PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
  1512. PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
  1513. PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
  1514. PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
  1515. PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
  1516. PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
  1517. PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
  1518. PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
  1519. PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
  1520. PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
  1521. PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
  1522. PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
  1523. PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
  1524. PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
  1525. PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
  1526. PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
  1527. PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
  1528. PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
  1529. PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
  1530. PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
  1531. PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
  1532. PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
  1533. PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
  1534. PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
  1535. PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
  1536. PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
  1537. PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
  1538. PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
  1539. PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
  1540. PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
  1541. PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
  1542. PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
  1543. PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
  1544. PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
  1545. PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
  1546. PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
  1547. PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
  1548. PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
  1549. PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
  1550. PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
  1551. PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
  1552. PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
  1553. PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
  1554. PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
  1555. PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
  1556. PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
  1557. PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
  1558. PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
  1559. PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
  1560. PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
  1561. PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
  1562. PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
  1563. PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
  1564. PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
  1565. PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
  1566. PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
  1567. PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
  1568. PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
  1569. PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
  1570. PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
  1571. PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
  1572. PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
  1573. PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
  1574. PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
  1575. PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
  1576. PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
  1577. PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
  1578. PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
  1579. PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
  1580. PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
  1581. PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
  1582. PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
  1583. PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
  1584. PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
  1585. PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
  1586. PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
  1587. PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
  1588. PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
  1589. PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
  1590. PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
  1591. PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
  1592. PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
  1593. PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
  1594. PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
  1595. PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
  1596. PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
  1597. PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
  1598. PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
  1599. PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
  1600. PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
  1601. PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
  1602. PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
  1603. PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
  1604. PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
  1605. PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
  1606. PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
  1607. PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
  1608. PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
  1609. PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
  1610. PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
  1611. PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
  1612. PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
  1613. PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
  1614. PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
  1615. PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
  1616. PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
  1617. PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
  1618. PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
  1619. PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
  1620. PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
  1621. PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
  1622. PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
  1623. PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
  1624. PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
  1625. PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
  1626. PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
  1627. PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
  1628. PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
  1629. PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
  1630. PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
  1631. PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
  1632. PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
  1633. PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
  1634. PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
  1635. PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
  1636. PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
  1637. PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
  1638. PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
  1639. PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
  1640. PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
  1641. PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
  1642. PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
  1643. PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
  1644. PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
  1645. PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
  1646. PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
  1647. PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
  1648. PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
  1649. PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
  1650. PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
  1651. PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
  1652. PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
  1653. PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
  1654. PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
  1655. PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
  1656. PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
  1657. PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
  1658. PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
  1659. };
  1660. /*
  1661. * Pins not associated with a GPIO port.
  1662. */
  1663. enum {
  1664. GP_ASSIGN_LAST(),
  1665. NOGP_ALL(),
  1666. };
  1667. static const struct sh_pfc_pin pinmux_pins[] = {
  1668. PINMUX_GPIO_GP_ALL(),
  1669. PINMUX_NOGP_ALL(),
  1670. };
  1671. /* - AUDIO CLOCK ------------------------------------------------------------ */
  1672. static const unsigned int audio_clk_a_pins[] = {
  1673. /* CLK A */
  1674. RCAR_GP_PIN(4, 25),
  1675. };
  1676. static const unsigned int audio_clk_a_mux[] = {
  1677. AUDIO_CLKA_MARK,
  1678. };
  1679. static const unsigned int audio_clk_b_pins[] = {
  1680. /* CLK B */
  1681. RCAR_GP_PIN(4, 26),
  1682. };
  1683. static const unsigned int audio_clk_b_mux[] = {
  1684. AUDIO_CLKB_MARK,
  1685. };
  1686. static const unsigned int audio_clk_c_pins[] = {
  1687. /* CLK C */
  1688. RCAR_GP_PIN(5, 27),
  1689. };
  1690. static const unsigned int audio_clk_c_mux[] = {
  1691. AUDIO_CLKC_MARK,
  1692. };
  1693. static const unsigned int audio_clkout_pins[] = {
  1694. /* CLK OUT */
  1695. RCAR_GP_PIN(5, 16),
  1696. };
  1697. static const unsigned int audio_clkout_mux[] = {
  1698. AUDIO_CLKOUT_MARK,
  1699. };
  1700. static const unsigned int audio_clkout_b_pins[] = {
  1701. /* CLK OUT B */
  1702. RCAR_GP_PIN(0, 23),
  1703. };
  1704. static const unsigned int audio_clkout_b_mux[] = {
  1705. AUDIO_CLKOUT_B_MARK,
  1706. };
  1707. static const unsigned int audio_clkout_c_pins[] = {
  1708. /* CLK OUT C */
  1709. RCAR_GP_PIN(5, 27),
  1710. };
  1711. static const unsigned int audio_clkout_c_mux[] = {
  1712. AUDIO_CLKOUT_C_MARK,
  1713. };
  1714. static const unsigned int audio_clkout_d_pins[] = {
  1715. /* CLK OUT D */
  1716. RCAR_GP_PIN(5, 20),
  1717. };
  1718. static const unsigned int audio_clkout_d_mux[] = {
  1719. AUDIO_CLKOUT_D_MARK,
  1720. };
  1721. /* - AVB -------------------------------------------------------------------- */
  1722. static const unsigned int avb_link_pins[] = {
  1723. RCAR_GP_PIN(3, 11),
  1724. };
  1725. static const unsigned int avb_link_mux[] = {
  1726. AVB_LINK_MARK,
  1727. };
  1728. static const unsigned int avb_magic_pins[] = {
  1729. RCAR_GP_PIN(2, 14),
  1730. };
  1731. static const unsigned int avb_magic_mux[] = {
  1732. AVB_MAGIC_MARK,
  1733. };
  1734. static const unsigned int avb_phy_int_pins[] = {
  1735. RCAR_GP_PIN(2, 15),
  1736. };
  1737. static const unsigned int avb_phy_int_mux[] = {
  1738. AVB_PHY_INT_MARK,
  1739. };
  1740. static const unsigned int avb_mdio_pins[] = {
  1741. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
  1742. };
  1743. static const unsigned int avb_mdio_mux[] = {
  1744. AVB_MDC_MARK, AVB_MDIO_MARK,
  1745. };
  1746. static const unsigned int avb_mii_pins[] = {
  1747. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
  1748. RCAR_GP_PIN(0, 11),
  1749. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1750. RCAR_GP_PIN(2, 2),
  1751. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1752. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1753. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
  1754. };
  1755. static const unsigned int avb_mii_mux[] = {
  1756. AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
  1757. AVB_TXD3_MARK,
  1758. AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1759. AVB_RXD3_MARK,
  1760. AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
  1761. AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
  1762. AVB_TX_CLK_MARK, AVB_COL_MARK,
  1763. };
  1764. static const unsigned int avb_gmii_pins[] = {
  1765. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
  1766. RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  1767. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  1768. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1769. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
  1770. RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
  1771. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1772. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
  1773. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
  1774. RCAR_GP_PIN(3, 12),
  1775. };
  1776. static const unsigned int avb_gmii_mux[] = {
  1777. AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
  1778. AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
  1779. AVB_TXD6_MARK, AVB_TXD7_MARK,
  1780. AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1781. AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
  1782. AVB_RXD6_MARK, AVB_RXD7_MARK,
  1783. AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
  1784. AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
  1785. AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
  1786. AVB_COL_MARK,
  1787. };
  1788. /* - CAN0 ----------------------------------------------------------------- */
  1789. static const unsigned int can0_data_pins[] = {
  1790. /* CAN0 RX */
  1791. RCAR_GP_PIN(1, 17),
  1792. /* CAN0 TX */
  1793. RCAR_GP_PIN(1, 19),
  1794. };
  1795. static const unsigned int can0_data_mux[] = {
  1796. CAN0_RX_MARK,
  1797. CAN0_TX_MARK,
  1798. };
  1799. static const unsigned int can0_data_b_pins[] = {
  1800. /* CAN0 RXB */
  1801. RCAR_GP_PIN(4, 5),
  1802. /* CAN0 TXB */
  1803. RCAR_GP_PIN(4, 4),
  1804. };
  1805. static const unsigned int can0_data_b_mux[] = {
  1806. CAN0_RX_B_MARK,
  1807. CAN0_TX_B_MARK,
  1808. };
  1809. static const unsigned int can0_data_c_pins[] = {
  1810. /* CAN0 RXC */
  1811. RCAR_GP_PIN(4, 26),
  1812. /* CAN0 TXC */
  1813. RCAR_GP_PIN(4, 23),
  1814. };
  1815. static const unsigned int can0_data_c_mux[] = {
  1816. CAN0_RX_C_MARK,
  1817. CAN0_TX_C_MARK,
  1818. };
  1819. static const unsigned int can0_data_d_pins[] = {
  1820. /* CAN0 RXD */
  1821. RCAR_GP_PIN(4, 26),
  1822. /* CAN0 TXD */
  1823. RCAR_GP_PIN(4, 18),
  1824. };
  1825. static const unsigned int can0_data_d_mux[] = {
  1826. CAN0_RX_D_MARK,
  1827. CAN0_TX_D_MARK,
  1828. };
  1829. /* - CAN1 ----------------------------------------------------------------- */
  1830. static const unsigned int can1_data_pins[] = {
  1831. /* CAN1 RX */
  1832. RCAR_GP_PIN(1, 22),
  1833. /* CAN1 TX */
  1834. RCAR_GP_PIN(1, 18),
  1835. };
  1836. static const unsigned int can1_data_mux[] = {
  1837. CAN1_RX_MARK,
  1838. CAN1_TX_MARK,
  1839. };
  1840. static const unsigned int can1_data_b_pins[] = {
  1841. /* CAN1 RXB */
  1842. RCAR_GP_PIN(4, 7),
  1843. /* CAN1 TXB */
  1844. RCAR_GP_PIN(4, 6),
  1845. };
  1846. static const unsigned int can1_data_b_mux[] = {
  1847. CAN1_RX_B_MARK,
  1848. CAN1_TX_B_MARK,
  1849. };
  1850. /* - CAN Clock -------------------------------------------------------------- */
  1851. static const unsigned int can_clk_pins[] = {
  1852. /* CLK */
  1853. RCAR_GP_PIN(1, 21),
  1854. };
  1855. static const unsigned int can_clk_mux[] = {
  1856. CAN_CLK_MARK,
  1857. };
  1858. static const unsigned int can_clk_b_pins[] = {
  1859. /* CLK */
  1860. RCAR_GP_PIN(4, 3),
  1861. };
  1862. static const unsigned int can_clk_b_mux[] = {
  1863. CAN_CLK_B_MARK,
  1864. };
  1865. /* - DU RGB ----------------------------------------------------------------- */
  1866. static const unsigned int du_rgb666_pins[] = {
  1867. /* R[7:2], G[7:2], B[7:2] */
  1868. RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
  1869. RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
  1870. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
  1871. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
  1872. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
  1873. RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
  1874. };
  1875. static const unsigned int du_rgb666_mux[] = {
  1876. DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
  1877. DU2_DR3_MARK, DU2_DR2_MARK,
  1878. DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
  1879. DU2_DG3_MARK, DU2_DG2_MARK,
  1880. DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
  1881. DU2_DB3_MARK, DU2_DB2_MARK,
  1882. };
  1883. static const unsigned int du_rgb888_pins[] = {
  1884. /* R[7:0], G[7:0], B[7:0] */
  1885. RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
  1886. RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
  1887. RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
  1888. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
  1889. RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
  1890. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
  1891. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
  1892. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
  1893. };
  1894. static const unsigned int du_rgb888_mux[] = {
  1895. DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
  1896. DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
  1897. DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
  1898. DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
  1899. DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
  1900. DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
  1901. };
  1902. static const unsigned int du_clk_out_0_pins[] = {
  1903. /* CLKOUT */
  1904. RCAR_GP_PIN(5, 2),
  1905. };
  1906. static const unsigned int du_clk_out_0_mux[] = {
  1907. DU0_DOTCLKOUT_MARK
  1908. };
  1909. static const unsigned int du_clk_out_1_pins[] = {
  1910. /* CLKOUT */
  1911. RCAR_GP_PIN(5, 3),
  1912. };
  1913. static const unsigned int du_clk_out_1_mux[] = {
  1914. DU1_DOTCLKOUT_MARK
  1915. };
  1916. static const unsigned int du_sync_0_pins[] = {
  1917. /* VSYNC, HSYNC, DISP */
  1918. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
  1919. };
  1920. static const unsigned int du_sync_0_mux[] = {
  1921. DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
  1922. DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
  1923. };
  1924. static const unsigned int du_sync_1_pins[] = {
  1925. /* VSYNC, HSYNC, DISP */
  1926. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
  1927. };
  1928. static const unsigned int du_sync_1_mux[] = {
  1929. DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
  1930. DU2_DISP_MARK
  1931. };
  1932. static const unsigned int du_cde_pins[] = {
  1933. /* CDE */
  1934. RCAR_GP_PIN(5, 17),
  1935. };
  1936. static const unsigned int du_cde_mux[] = {
  1937. DU2_CDE_MARK,
  1938. };
  1939. /* - DU0 -------------------------------------------------------------------- */
  1940. static const unsigned int du0_clk_in_pins[] = {
  1941. /* CLKIN */
  1942. RCAR_GP_PIN(5, 26),
  1943. };
  1944. static const unsigned int du0_clk_in_mux[] = {
  1945. DU_DOTCLKIN0_MARK
  1946. };
  1947. /* - DU1 -------------------------------------------------------------------- */
  1948. static const unsigned int du1_clk_in_pins[] = {
  1949. /* CLKIN */
  1950. RCAR_GP_PIN(5, 27),
  1951. };
  1952. static const unsigned int du1_clk_in_mux[] = {
  1953. DU_DOTCLKIN1_MARK,
  1954. };
  1955. /* - DU2 -------------------------------------------------------------------- */
  1956. static const unsigned int du2_clk_in_pins[] = {
  1957. /* CLKIN */
  1958. RCAR_GP_PIN(5, 28),
  1959. };
  1960. static const unsigned int du2_clk_in_mux[] = {
  1961. DU_DOTCLKIN2_MARK,
  1962. };
  1963. /* - ETH -------------------------------------------------------------------- */
  1964. static const unsigned int eth_link_pins[] = {
  1965. /* LINK */
  1966. RCAR_GP_PIN(2, 22),
  1967. };
  1968. static const unsigned int eth_link_mux[] = {
  1969. ETH_LINK_MARK,
  1970. };
  1971. static const unsigned int eth_magic_pins[] = {
  1972. /* MAGIC */
  1973. RCAR_GP_PIN(2, 27),
  1974. };
  1975. static const unsigned int eth_magic_mux[] = {
  1976. ETH_MAGIC_MARK,
  1977. };
  1978. static const unsigned int eth_mdio_pins[] = {
  1979. /* MDC, MDIO */
  1980. RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
  1981. };
  1982. static const unsigned int eth_mdio_mux[] = {
  1983. ETH_MDC_MARK, ETH_MDIO_MARK,
  1984. };
  1985. static const unsigned int eth_rmii_pins[] = {
  1986. /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
  1987. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
  1988. RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
  1989. RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
  1990. };
  1991. static const unsigned int eth_rmii_mux[] = {
  1992. ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
  1993. ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
  1994. };
  1995. /* - HSCIF0 ----------------------------------------------------------------- */
  1996. static const unsigned int hscif0_data_pins[] = {
  1997. /* RX, TX */
  1998. RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
  1999. };
  2000. static const unsigned int hscif0_data_mux[] = {
  2001. HRX0_MARK, HTX0_MARK,
  2002. };
  2003. static const unsigned int hscif0_clk_pins[] = {
  2004. /* SCK */
  2005. RCAR_GP_PIN(5, 7),
  2006. };
  2007. static const unsigned int hscif0_clk_mux[] = {
  2008. HSCK0_MARK,
  2009. };
  2010. static const unsigned int hscif0_ctrl_pins[] = {
  2011. /* RTS, CTS */
  2012. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
  2013. };
  2014. static const unsigned int hscif0_ctrl_mux[] = {
  2015. HRTS0_N_MARK, HCTS0_N_MARK,
  2016. };
  2017. static const unsigned int hscif0_data_b_pins[] = {
  2018. /* RX, TX */
  2019. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
  2020. };
  2021. static const unsigned int hscif0_data_b_mux[] = {
  2022. HRX0_B_MARK, HTX0_B_MARK,
  2023. };
  2024. static const unsigned int hscif0_ctrl_b_pins[] = {
  2025. /* RTS, CTS */
  2026. RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
  2027. };
  2028. static const unsigned int hscif0_ctrl_b_mux[] = {
  2029. HRTS0_N_B_MARK, HCTS0_N_B_MARK,
  2030. };
  2031. static const unsigned int hscif0_data_c_pins[] = {
  2032. /* RX, TX */
  2033. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
  2034. };
  2035. static const unsigned int hscif0_data_c_mux[] = {
  2036. HRX0_C_MARK, HTX0_C_MARK,
  2037. };
  2038. static const unsigned int hscif0_ctrl_c_pins[] = {
  2039. /* RTS, CTS */
  2040. RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
  2041. };
  2042. static const unsigned int hscif0_ctrl_c_mux[] = {
  2043. HRTS0_N_C_MARK, HCTS0_N_C_MARK,
  2044. };
  2045. static const unsigned int hscif0_data_d_pins[] = {
  2046. /* RX, TX */
  2047. RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  2048. };
  2049. static const unsigned int hscif0_data_d_mux[] = {
  2050. HRX0_D_MARK, HTX0_D_MARK,
  2051. };
  2052. static const unsigned int hscif0_ctrl_d_pins[] = {
  2053. /* RTS, CTS */
  2054. RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
  2055. };
  2056. static const unsigned int hscif0_ctrl_d_mux[] = {
  2057. HRTS0_N_D_MARK, HCTS0_N_D_MARK,
  2058. };
  2059. static const unsigned int hscif0_data_e_pins[] = {
  2060. /* RX, TX */
  2061. RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
  2062. };
  2063. static const unsigned int hscif0_data_e_mux[] = {
  2064. HRX0_E_MARK, HTX0_E_MARK,
  2065. };
  2066. static const unsigned int hscif0_ctrl_e_pins[] = {
  2067. /* RTS, CTS */
  2068. RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
  2069. };
  2070. static const unsigned int hscif0_ctrl_e_mux[] = {
  2071. HRTS0_N_E_MARK, HCTS0_N_E_MARK,
  2072. };
  2073. static const unsigned int hscif0_data_f_pins[] = {
  2074. /* RX, TX */
  2075. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
  2076. };
  2077. static const unsigned int hscif0_data_f_mux[] = {
  2078. HRX0_F_MARK, HTX0_F_MARK,
  2079. };
  2080. static const unsigned int hscif0_ctrl_f_pins[] = {
  2081. /* RTS, CTS */
  2082. RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
  2083. };
  2084. static const unsigned int hscif0_ctrl_f_mux[] = {
  2085. HRTS0_N_F_MARK, HCTS0_N_F_MARK,
  2086. };
  2087. /* - HSCIF1 ----------------------------------------------------------------- */
  2088. static const unsigned int hscif1_data_pins[] = {
  2089. /* RX, TX */
  2090. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
  2091. };
  2092. static const unsigned int hscif1_data_mux[] = {
  2093. HRX1_MARK, HTX1_MARK,
  2094. };
  2095. static const unsigned int hscif1_clk_pins[] = {
  2096. /* SCK */
  2097. RCAR_GP_PIN(4, 27),
  2098. };
  2099. static const unsigned int hscif1_clk_mux[] = {
  2100. HSCK1_MARK,
  2101. };
  2102. static const unsigned int hscif1_ctrl_pins[] = {
  2103. /* RTS, CTS */
  2104. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
  2105. };
  2106. static const unsigned int hscif1_ctrl_mux[] = {
  2107. HRTS1_N_MARK, HCTS1_N_MARK,
  2108. };
  2109. static const unsigned int hscif1_data_b_pins[] = {
  2110. /* RX, TX */
  2111. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
  2112. };
  2113. static const unsigned int hscif1_data_b_mux[] = {
  2114. HRX1_B_MARK, HTX1_B_MARK,
  2115. };
  2116. static const unsigned int hscif1_clk_b_pins[] = {
  2117. /* SCK */
  2118. RCAR_GP_PIN(1, 28),
  2119. };
  2120. static const unsigned int hscif1_clk_b_mux[] = {
  2121. HSCK1_B_MARK,
  2122. };
  2123. static const unsigned int hscif1_ctrl_b_pins[] = {
  2124. /* RTS, CTS */
  2125. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
  2126. };
  2127. static const unsigned int hscif1_ctrl_b_mux[] = {
  2128. HRTS1_N_B_MARK, HCTS1_N_B_MARK,
  2129. };
  2130. /* - I2C0 ------------------------------------------------------------------- */
  2131. static const unsigned int i2c0_pins[] = {
  2132. /* SCL, SDA */
  2133. PIN_IIC0_SCL, PIN_IIC0_SDA,
  2134. };
  2135. static const unsigned int i2c0_mux[] = {
  2136. I2C0_SCL_MARK, I2C0_SDA_MARK,
  2137. };
  2138. /* - I2C1 ------------------------------------------------------------------- */
  2139. static const unsigned int i2c1_pins[] = {
  2140. /* SCL, SDA */
  2141. RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
  2142. };
  2143. static const unsigned int i2c1_mux[] = {
  2144. I2C1_SCL_MARK, I2C1_SDA_MARK,
  2145. };
  2146. static const unsigned int i2c1_b_pins[] = {
  2147. /* SCL, SDA */
  2148. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  2149. };
  2150. static const unsigned int i2c1_b_mux[] = {
  2151. I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
  2152. };
  2153. static const unsigned int i2c1_c_pins[] = {
  2154. /* SCL, SDA */
  2155. RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
  2156. };
  2157. static const unsigned int i2c1_c_mux[] = {
  2158. I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
  2159. };
  2160. /* - I2C2 ------------------------------------------------------------------- */
  2161. static const unsigned int i2c2_pins[] = {
  2162. /* SCL, SDA */
  2163. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  2164. };
  2165. static const unsigned int i2c2_mux[] = {
  2166. I2C2_SCL_MARK, I2C2_SDA_MARK,
  2167. };
  2168. static const unsigned int i2c2_b_pins[] = {
  2169. /* SCL, SDA */
  2170. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  2171. };
  2172. static const unsigned int i2c2_b_mux[] = {
  2173. I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
  2174. };
  2175. static const unsigned int i2c2_c_pins[] = {
  2176. /* SCL, SDA */
  2177. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  2178. };
  2179. static const unsigned int i2c2_c_mux[] = {
  2180. I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
  2181. };
  2182. static const unsigned int i2c2_d_pins[] = {
  2183. /* SCL, SDA */
  2184. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2185. };
  2186. static const unsigned int i2c2_d_mux[] = {
  2187. I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
  2188. };
  2189. static const unsigned int i2c2_e_pins[] = {
  2190. /* SCL, SDA */
  2191. RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
  2192. };
  2193. static const unsigned int i2c2_e_mux[] = {
  2194. I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
  2195. };
  2196. /* - I2C3 ------------------------------------------------------------------- */
  2197. static const unsigned int i2c3_pins[] = {
  2198. /* SCL, SDA */
  2199. PIN_IIC3_SCL, PIN_IIC3_SDA,
  2200. };
  2201. static const unsigned int i2c3_mux[] = {
  2202. I2C3_SCL_MARK, I2C3_SDA_MARK,
  2203. };
  2204. /* - IIC0 (I2C4) ------------------------------------------------------------ */
  2205. static const unsigned int iic0_pins[] = {
  2206. /* SCL, SDA */
  2207. PIN_IIC0_SCL, PIN_IIC0_SDA,
  2208. };
  2209. static const unsigned int iic0_mux[] = {
  2210. IIC0_SCL_MARK, IIC0_SDA_MARK,
  2211. };
  2212. /* - IIC1 (I2C5) ------------------------------------------------------------ */
  2213. static const unsigned int iic1_pins[] = {
  2214. /* SCL, SDA */
  2215. RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
  2216. };
  2217. static const unsigned int iic1_mux[] = {
  2218. IIC1_SCL_MARK, IIC1_SDA_MARK,
  2219. };
  2220. static const unsigned int iic1_b_pins[] = {
  2221. /* SCL, SDA */
  2222. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  2223. };
  2224. static const unsigned int iic1_b_mux[] = {
  2225. IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
  2226. };
  2227. static const unsigned int iic1_c_pins[] = {
  2228. /* SCL, SDA */
  2229. RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
  2230. };
  2231. static const unsigned int iic1_c_mux[] = {
  2232. IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
  2233. };
  2234. /* - IIC2 (I2C6) ------------------------------------------------------------ */
  2235. static const unsigned int iic2_pins[] = {
  2236. /* SCL, SDA */
  2237. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  2238. };
  2239. static const unsigned int iic2_mux[] = {
  2240. IIC2_SCL_MARK, IIC2_SDA_MARK,
  2241. };
  2242. static const unsigned int iic2_b_pins[] = {
  2243. /* SCL, SDA */
  2244. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  2245. };
  2246. static const unsigned int iic2_b_mux[] = {
  2247. IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
  2248. };
  2249. static const unsigned int iic2_c_pins[] = {
  2250. /* SCL, SDA */
  2251. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  2252. };
  2253. static const unsigned int iic2_c_mux[] = {
  2254. IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
  2255. };
  2256. static const unsigned int iic2_d_pins[] = {
  2257. /* SCL, SDA */
  2258. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2259. };
  2260. static const unsigned int iic2_d_mux[] = {
  2261. IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
  2262. };
  2263. static const unsigned int iic2_e_pins[] = {
  2264. /* SCL, SDA */
  2265. RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
  2266. };
  2267. static const unsigned int iic2_e_mux[] = {
  2268. IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
  2269. };
  2270. /* - IIC3 (I2C7) ------------------------------------------------------------ */
  2271. static const unsigned int iic3_pins[] = {
  2272. /* SCL, SDA */
  2273. PIN_IIC3_SCL, PIN_IIC3_SDA,
  2274. };
  2275. static const unsigned int iic3_mux[] = {
  2276. IIC3_SCL_MARK, IIC3_SDA_MARK,
  2277. };
  2278. /* - INTC ------------------------------------------------------------------- */
  2279. static const unsigned int intc_irq0_pins[] = {
  2280. /* IRQ */
  2281. RCAR_GP_PIN(1, 25),
  2282. };
  2283. static const unsigned int intc_irq0_mux[] = {
  2284. IRQ0_MARK,
  2285. };
  2286. static const unsigned int intc_irq1_pins[] = {
  2287. /* IRQ */
  2288. RCAR_GP_PIN(1, 27),
  2289. };
  2290. static const unsigned int intc_irq1_mux[] = {
  2291. IRQ1_MARK,
  2292. };
  2293. static const unsigned int intc_irq2_pins[] = {
  2294. /* IRQ */
  2295. RCAR_GP_PIN(1, 29),
  2296. };
  2297. static const unsigned int intc_irq2_mux[] = {
  2298. IRQ2_MARK,
  2299. };
  2300. static const unsigned int intc_irq3_pins[] = {
  2301. /* IRQ */
  2302. RCAR_GP_PIN(1, 23),
  2303. };
  2304. static const unsigned int intc_irq3_mux[] = {
  2305. IRQ3_MARK,
  2306. };
  2307. /* - MLB+ ------------------------------------------------------------------- */
  2308. static const unsigned int mlb_3pin_pins[] = {
  2309. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
  2310. };
  2311. static const unsigned int mlb_3pin_mux[] = {
  2312. MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
  2313. };
  2314. /* - MMCIF0 ----------------------------------------------------------------- */
  2315. static const unsigned int mmc0_data1_pins[] = {
  2316. /* D[0] */
  2317. RCAR_GP_PIN(3, 18),
  2318. };
  2319. static const unsigned int mmc0_data1_mux[] = {
  2320. MMC0_D0_MARK,
  2321. };
  2322. static const unsigned int mmc0_data4_pins[] = {
  2323. /* D[0:3] */
  2324. RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
  2325. RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  2326. };
  2327. static const unsigned int mmc0_data4_mux[] = {
  2328. MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
  2329. };
  2330. static const unsigned int mmc0_data8_pins[] = {
  2331. /* D[0:7] */
  2332. RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
  2333. RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  2334. RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
  2335. RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
  2336. };
  2337. static const unsigned int mmc0_data8_mux[] = {
  2338. MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
  2339. MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
  2340. };
  2341. static const unsigned int mmc0_ctrl_pins[] = {
  2342. /* CLK, CMD */
  2343. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
  2344. };
  2345. static const unsigned int mmc0_ctrl_mux[] = {
  2346. MMC0_CLK_MARK, MMC0_CMD_MARK,
  2347. };
  2348. /* - MMCIF1 ----------------------------------------------------------------- */
  2349. static const unsigned int mmc1_data1_pins[] = {
  2350. /* D[0] */
  2351. RCAR_GP_PIN(3, 26),
  2352. };
  2353. static const unsigned int mmc1_data1_mux[] = {
  2354. MMC1_D0_MARK,
  2355. };
  2356. static const unsigned int mmc1_data4_pins[] = {
  2357. /* D[0:3] */
  2358. RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
  2359. RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
  2360. };
  2361. static const unsigned int mmc1_data4_mux[] = {
  2362. MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
  2363. };
  2364. static const unsigned int mmc1_data8_pins[] = {
  2365. /* D[0:7] */
  2366. RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
  2367. RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
  2368. RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
  2369. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  2370. };
  2371. static const unsigned int mmc1_data8_mux[] = {
  2372. MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
  2373. MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
  2374. };
  2375. static const unsigned int mmc1_ctrl_pins[] = {
  2376. /* CLK, CMD */
  2377. RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
  2378. };
  2379. static const unsigned int mmc1_ctrl_mux[] = {
  2380. MMC1_CLK_MARK, MMC1_CMD_MARK,
  2381. };
  2382. /* - MSIOF0 ----------------------------------------------------------------- */
  2383. static const unsigned int msiof0_clk_pins[] = {
  2384. /* SCK */
  2385. RCAR_GP_PIN(5, 12),
  2386. };
  2387. static const unsigned int msiof0_clk_mux[] = {
  2388. MSIOF0_SCK_MARK,
  2389. };
  2390. static const unsigned int msiof0_sync_pins[] = {
  2391. /* SYNC */
  2392. RCAR_GP_PIN(5, 13),
  2393. };
  2394. static const unsigned int msiof0_sync_mux[] = {
  2395. MSIOF0_SYNC_MARK,
  2396. };
  2397. static const unsigned int msiof0_ss1_pins[] = {
  2398. /* SS1 */
  2399. RCAR_GP_PIN(5, 14),
  2400. };
  2401. static const unsigned int msiof0_ss1_mux[] = {
  2402. MSIOF0_SS1_MARK,
  2403. };
  2404. static const unsigned int msiof0_ss2_pins[] = {
  2405. /* SS2 */
  2406. RCAR_GP_PIN(5, 16),
  2407. };
  2408. static const unsigned int msiof0_ss2_mux[] = {
  2409. MSIOF0_SS2_MARK,
  2410. };
  2411. static const unsigned int msiof0_rx_pins[] = {
  2412. /* RXD */
  2413. RCAR_GP_PIN(5, 17),
  2414. };
  2415. static const unsigned int msiof0_rx_mux[] = {
  2416. MSIOF0_RXD_MARK,
  2417. };
  2418. static const unsigned int msiof0_tx_pins[] = {
  2419. /* TXD */
  2420. RCAR_GP_PIN(5, 15),
  2421. };
  2422. static const unsigned int msiof0_tx_mux[] = {
  2423. MSIOF0_TXD_MARK,
  2424. };
  2425. static const unsigned int msiof0_clk_b_pins[] = {
  2426. /* SCK */
  2427. RCAR_GP_PIN(1, 23),
  2428. };
  2429. static const unsigned int msiof0_clk_b_mux[] = {
  2430. MSIOF0_SCK_B_MARK,
  2431. };
  2432. static const unsigned int msiof0_ss1_b_pins[] = {
  2433. /* SS1 */
  2434. RCAR_GP_PIN(1, 12),
  2435. };
  2436. static const unsigned int msiof0_ss1_b_mux[] = {
  2437. MSIOF0_SS1_B_MARK,
  2438. };
  2439. static const unsigned int msiof0_ss2_b_pins[] = {
  2440. /* SS2 */
  2441. RCAR_GP_PIN(1, 10),
  2442. };
  2443. static const unsigned int msiof0_ss2_b_mux[] = {
  2444. MSIOF0_SS2_B_MARK,
  2445. };
  2446. static const unsigned int msiof0_rx_b_pins[] = {
  2447. /* RXD */
  2448. RCAR_GP_PIN(1, 29),
  2449. };
  2450. static const unsigned int msiof0_rx_b_mux[] = {
  2451. MSIOF0_RXD_B_MARK,
  2452. };
  2453. static const unsigned int msiof0_tx_b_pins[] = {
  2454. /* TXD */
  2455. RCAR_GP_PIN(1, 28),
  2456. };
  2457. static const unsigned int msiof0_tx_b_mux[] = {
  2458. MSIOF0_TXD_B_MARK,
  2459. };
  2460. /* - MSIOF1 ----------------------------------------------------------------- */
  2461. static const unsigned int msiof1_clk_pins[] = {
  2462. /* SCK */
  2463. RCAR_GP_PIN(4, 8),
  2464. };
  2465. static const unsigned int msiof1_clk_mux[] = {
  2466. MSIOF1_SCK_MARK,
  2467. };
  2468. static const unsigned int msiof1_sync_pins[] = {
  2469. /* SYNC */
  2470. RCAR_GP_PIN(4, 9),
  2471. };
  2472. static const unsigned int msiof1_sync_mux[] = {
  2473. MSIOF1_SYNC_MARK,
  2474. };
  2475. static const unsigned int msiof1_ss1_pins[] = {
  2476. /* SS1 */
  2477. RCAR_GP_PIN(4, 10),
  2478. };
  2479. static const unsigned int msiof1_ss1_mux[] = {
  2480. MSIOF1_SS1_MARK,
  2481. };
  2482. static const unsigned int msiof1_ss2_pins[] = {
  2483. /* SS2 */
  2484. RCAR_GP_PIN(4, 11),
  2485. };
  2486. static const unsigned int msiof1_ss2_mux[] = {
  2487. MSIOF1_SS2_MARK,
  2488. };
  2489. static const unsigned int msiof1_rx_pins[] = {
  2490. /* RXD */
  2491. RCAR_GP_PIN(4, 13),
  2492. };
  2493. static const unsigned int msiof1_rx_mux[] = {
  2494. MSIOF1_RXD_MARK,
  2495. };
  2496. static const unsigned int msiof1_tx_pins[] = {
  2497. /* TXD */
  2498. RCAR_GP_PIN(4, 12),
  2499. };
  2500. static const unsigned int msiof1_tx_mux[] = {
  2501. MSIOF1_TXD_MARK,
  2502. };
  2503. static const unsigned int msiof1_clk_b_pins[] = {
  2504. /* SCK */
  2505. RCAR_GP_PIN(1, 16),
  2506. };
  2507. static const unsigned int msiof1_clk_b_mux[] = {
  2508. MSIOF1_SCK_B_MARK,
  2509. };
  2510. static const unsigned int msiof1_ss1_b_pins[] = {
  2511. /* SS1 */
  2512. RCAR_GP_PIN(0, 18),
  2513. };
  2514. static const unsigned int msiof1_ss1_b_mux[] = {
  2515. MSIOF1_SS1_B_MARK,
  2516. };
  2517. static const unsigned int msiof1_ss2_b_pins[] = {
  2518. /* SS2 */
  2519. RCAR_GP_PIN(0, 19),
  2520. };
  2521. static const unsigned int msiof1_ss2_b_mux[] = {
  2522. MSIOF1_SS2_B_MARK,
  2523. };
  2524. static const unsigned int msiof1_rx_b_pins[] = {
  2525. /* RXD */
  2526. RCAR_GP_PIN(1, 17),
  2527. };
  2528. static const unsigned int msiof1_rx_b_mux[] = {
  2529. MSIOF1_RXD_B_MARK,
  2530. };
  2531. static const unsigned int msiof1_tx_b_pins[] = {
  2532. /* TXD */
  2533. RCAR_GP_PIN(0, 20),
  2534. };
  2535. static const unsigned int msiof1_tx_b_mux[] = {
  2536. MSIOF1_TXD_B_MARK,
  2537. };
  2538. /* - MSIOF2 ----------------------------------------------------------------- */
  2539. static const unsigned int msiof2_clk_pins[] = {
  2540. /* SCK */
  2541. RCAR_GP_PIN(0, 27),
  2542. };
  2543. static const unsigned int msiof2_clk_mux[] = {
  2544. MSIOF2_SCK_MARK,
  2545. };
  2546. static const unsigned int msiof2_sync_pins[] = {
  2547. /* SYNC */
  2548. RCAR_GP_PIN(0, 26),
  2549. };
  2550. static const unsigned int msiof2_sync_mux[] = {
  2551. MSIOF2_SYNC_MARK,
  2552. };
  2553. static const unsigned int msiof2_ss1_pins[] = {
  2554. /* SS1 */
  2555. RCAR_GP_PIN(0, 30),
  2556. };
  2557. static const unsigned int msiof2_ss1_mux[] = {
  2558. MSIOF2_SS1_MARK,
  2559. };
  2560. static const unsigned int msiof2_ss2_pins[] = {
  2561. /* SS2 */
  2562. RCAR_GP_PIN(0, 31),
  2563. };
  2564. static const unsigned int msiof2_ss2_mux[] = {
  2565. MSIOF2_SS2_MARK,
  2566. };
  2567. static const unsigned int msiof2_rx_pins[] = {
  2568. /* RXD */
  2569. RCAR_GP_PIN(0, 29),
  2570. };
  2571. static const unsigned int msiof2_rx_mux[] = {
  2572. MSIOF2_RXD_MARK,
  2573. };
  2574. static const unsigned int msiof2_tx_pins[] = {
  2575. /* TXD */
  2576. RCAR_GP_PIN(0, 28),
  2577. };
  2578. static const unsigned int msiof2_tx_mux[] = {
  2579. MSIOF2_TXD_MARK,
  2580. };
  2581. /* - MSIOF3 ----------------------------------------------------------------- */
  2582. static const unsigned int msiof3_clk_pins[] = {
  2583. /* SCK */
  2584. RCAR_GP_PIN(5, 4),
  2585. };
  2586. static const unsigned int msiof3_clk_mux[] = {
  2587. MSIOF3_SCK_MARK,
  2588. };
  2589. static const unsigned int msiof3_sync_pins[] = {
  2590. /* SYNC */
  2591. RCAR_GP_PIN(4, 30),
  2592. };
  2593. static const unsigned int msiof3_sync_mux[] = {
  2594. MSIOF3_SYNC_MARK,
  2595. };
  2596. static const unsigned int msiof3_ss1_pins[] = {
  2597. /* SS1 */
  2598. RCAR_GP_PIN(4, 31),
  2599. };
  2600. static const unsigned int msiof3_ss1_mux[] = {
  2601. MSIOF3_SS1_MARK,
  2602. };
  2603. static const unsigned int msiof3_ss2_pins[] = {
  2604. /* SS2 */
  2605. RCAR_GP_PIN(4, 27),
  2606. };
  2607. static const unsigned int msiof3_ss2_mux[] = {
  2608. MSIOF3_SS2_MARK,
  2609. };
  2610. static const unsigned int msiof3_rx_pins[] = {
  2611. /* RXD */
  2612. RCAR_GP_PIN(5, 2),
  2613. };
  2614. static const unsigned int msiof3_rx_mux[] = {
  2615. MSIOF3_RXD_MARK,
  2616. };
  2617. static const unsigned int msiof3_tx_pins[] = {
  2618. /* TXD */
  2619. RCAR_GP_PIN(5, 3),
  2620. };
  2621. static const unsigned int msiof3_tx_mux[] = {
  2622. MSIOF3_TXD_MARK,
  2623. };
  2624. static const unsigned int msiof3_clk_b_pins[] = {
  2625. /* SCK */
  2626. RCAR_GP_PIN(0, 0),
  2627. };
  2628. static const unsigned int msiof3_clk_b_mux[] = {
  2629. MSIOF3_SCK_B_MARK,
  2630. };
  2631. static const unsigned int msiof3_sync_b_pins[] = {
  2632. /* SYNC */
  2633. RCAR_GP_PIN(0, 1),
  2634. };
  2635. static const unsigned int msiof3_sync_b_mux[] = {
  2636. MSIOF3_SYNC_B_MARK,
  2637. };
  2638. static const unsigned int msiof3_rx_b_pins[] = {
  2639. /* RXD */
  2640. RCAR_GP_PIN(0, 2),
  2641. };
  2642. static const unsigned int msiof3_rx_b_mux[] = {
  2643. MSIOF3_RXD_B_MARK,
  2644. };
  2645. static const unsigned int msiof3_tx_b_pins[] = {
  2646. /* TXD */
  2647. RCAR_GP_PIN(0, 3),
  2648. };
  2649. static const unsigned int msiof3_tx_b_mux[] = {
  2650. MSIOF3_TXD_B_MARK,
  2651. };
  2652. /* - PWM -------------------------------------------------------------------- */
  2653. static const unsigned int pwm0_pins[] = {
  2654. RCAR_GP_PIN(5, 29),
  2655. };
  2656. static const unsigned int pwm0_mux[] = {
  2657. PWM0_MARK,
  2658. };
  2659. static const unsigned int pwm0_b_pins[] = {
  2660. RCAR_GP_PIN(4, 30),
  2661. };
  2662. static const unsigned int pwm0_b_mux[] = {
  2663. PWM0_B_MARK,
  2664. };
  2665. static const unsigned int pwm1_pins[] = {
  2666. RCAR_GP_PIN(5, 30),
  2667. };
  2668. static const unsigned int pwm1_mux[] = {
  2669. PWM1_MARK,
  2670. };
  2671. static const unsigned int pwm1_b_pins[] = {
  2672. RCAR_GP_PIN(4, 31),
  2673. };
  2674. static const unsigned int pwm1_b_mux[] = {
  2675. PWM1_B_MARK,
  2676. };
  2677. static const unsigned int pwm2_pins[] = {
  2678. RCAR_GP_PIN(5, 31),
  2679. };
  2680. static const unsigned int pwm2_mux[] = {
  2681. PWM2_MARK,
  2682. };
  2683. static const unsigned int pwm3_pins[] = {
  2684. RCAR_GP_PIN(0, 16),
  2685. };
  2686. static const unsigned int pwm3_mux[] = {
  2687. PWM3_MARK,
  2688. };
  2689. static const unsigned int pwm4_pins[] = {
  2690. RCAR_GP_PIN(0, 17),
  2691. };
  2692. static const unsigned int pwm4_mux[] = {
  2693. PWM4_MARK,
  2694. };
  2695. static const unsigned int pwm5_pins[] = {
  2696. RCAR_GP_PIN(0, 18),
  2697. };
  2698. static const unsigned int pwm5_mux[] = {
  2699. PWM5_MARK,
  2700. };
  2701. static const unsigned int pwm6_pins[] = {
  2702. RCAR_GP_PIN(0, 19),
  2703. };
  2704. static const unsigned int pwm6_mux[] = {
  2705. PWM6_MARK,
  2706. };
  2707. /* - QSPI ------------------------------------------------------------------- */
  2708. static const unsigned int qspi_ctrl_pins[] = {
  2709. /* SPCLK, SSL */
  2710. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
  2711. };
  2712. static const unsigned int qspi_ctrl_mux[] = {
  2713. SPCLK_MARK, SSL_MARK,
  2714. };
  2715. static const unsigned int qspi_data2_pins[] = {
  2716. /* MOSI_IO0, MISO_IO1 */
  2717. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  2718. };
  2719. static const unsigned int qspi_data2_mux[] = {
  2720. MOSI_IO0_MARK, MISO_IO1_MARK,
  2721. };
  2722. static const unsigned int qspi_data4_pins[] = {
  2723. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  2724. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  2725. RCAR_GP_PIN(1, 8),
  2726. };
  2727. static const unsigned int qspi_data4_mux[] = {
  2728. MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
  2729. };
  2730. /* - SCIF0 ------------------------------------------------------------------ */
  2731. static const unsigned int scif0_data_pins[] = {
  2732. /* RX, TX */
  2733. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
  2734. };
  2735. static const unsigned int scif0_data_mux[] = {
  2736. RX0_MARK, TX0_MARK,
  2737. };
  2738. static const unsigned int scif0_clk_pins[] = {
  2739. /* SCK */
  2740. RCAR_GP_PIN(4, 27),
  2741. };
  2742. static const unsigned int scif0_clk_mux[] = {
  2743. SCK0_MARK,
  2744. };
  2745. static const unsigned int scif0_ctrl_pins[] = {
  2746. /* RTS, CTS */
  2747. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
  2748. };
  2749. static const unsigned int scif0_ctrl_mux[] = {
  2750. RTS0_N_MARK, CTS0_N_MARK,
  2751. };
  2752. static const unsigned int scif0_data_b_pins[] = {
  2753. /* RX, TX */
  2754. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  2755. };
  2756. static const unsigned int scif0_data_b_mux[] = {
  2757. RX0_B_MARK, TX0_B_MARK,
  2758. };
  2759. /* - SCIF1 ------------------------------------------------------------------ */
  2760. static const unsigned int scif1_data_pins[] = {
  2761. /* RX, TX */
  2762. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
  2763. };
  2764. static const unsigned int scif1_data_mux[] = {
  2765. RX1_MARK, TX1_MARK,
  2766. };
  2767. static const unsigned int scif1_clk_pins[] = {
  2768. /* SCK */
  2769. RCAR_GP_PIN(4, 20),
  2770. };
  2771. static const unsigned int scif1_clk_mux[] = {
  2772. SCK1_MARK,
  2773. };
  2774. static const unsigned int scif1_ctrl_pins[] = {
  2775. /* RTS, CTS */
  2776. RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
  2777. };
  2778. static const unsigned int scif1_ctrl_mux[] = {
  2779. RTS1_N_MARK, CTS1_N_MARK,
  2780. };
  2781. static const unsigned int scif1_data_b_pins[] = {
  2782. /* RX, TX */
  2783. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  2784. };
  2785. static const unsigned int scif1_data_b_mux[] = {
  2786. RX1_B_MARK, TX1_B_MARK,
  2787. };
  2788. static const unsigned int scif1_data_c_pins[] = {
  2789. /* RX, TX */
  2790. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
  2791. };
  2792. static const unsigned int scif1_data_c_mux[] = {
  2793. RX1_C_MARK, TX1_C_MARK,
  2794. };
  2795. static const unsigned int scif1_data_d_pins[] = {
  2796. /* RX, TX */
  2797. RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
  2798. };
  2799. static const unsigned int scif1_data_d_mux[] = {
  2800. RX1_D_MARK, TX1_D_MARK,
  2801. };
  2802. static const unsigned int scif1_clk_d_pins[] = {
  2803. /* SCK */
  2804. RCAR_GP_PIN(3, 17),
  2805. };
  2806. static const unsigned int scif1_clk_d_mux[] = {
  2807. SCK1_D_MARK,
  2808. };
  2809. static const unsigned int scif1_data_e_pins[] = {
  2810. /* RX, TX */
  2811. RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
  2812. };
  2813. static const unsigned int scif1_data_e_mux[] = {
  2814. RX1_E_MARK, TX1_E_MARK,
  2815. };
  2816. static const unsigned int scif1_clk_e_pins[] = {
  2817. /* SCK */
  2818. RCAR_GP_PIN(2, 20),
  2819. };
  2820. static const unsigned int scif1_clk_e_mux[] = {
  2821. SCK1_E_MARK,
  2822. };
  2823. /* - SCIF2 ------------------------------------------------------------------ */
  2824. static const unsigned int scif2_data_pins[] = {
  2825. /* RX, TX */
  2826. RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
  2827. };
  2828. static const unsigned int scif2_data_mux[] = {
  2829. RX2_MARK, TX2_MARK,
  2830. };
  2831. static const unsigned int scif2_clk_pins[] = {
  2832. /* SCK */
  2833. RCAR_GP_PIN(5, 4),
  2834. };
  2835. static const unsigned int scif2_clk_mux[] = {
  2836. SCK2_MARK,
  2837. };
  2838. static const unsigned int scif2_data_b_pins[] = {
  2839. /* RX, TX */
  2840. RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
  2841. };
  2842. static const unsigned int scif2_data_b_mux[] = {
  2843. RX2_B_MARK, TX2_B_MARK,
  2844. };
  2845. /* - SCIFA0 ----------------------------------------------------------------- */
  2846. static const unsigned int scifa0_data_pins[] = {
  2847. /* RXD, TXD */
  2848. RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
  2849. };
  2850. static const unsigned int scifa0_data_mux[] = {
  2851. SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
  2852. };
  2853. static const unsigned int scifa0_clk_pins[] = {
  2854. /* SCK */
  2855. RCAR_GP_PIN(4, 27),
  2856. };
  2857. static const unsigned int scifa0_clk_mux[] = {
  2858. SCIFA0_SCK_MARK,
  2859. };
  2860. static const unsigned int scifa0_ctrl_pins[] = {
  2861. /* RTS, CTS */
  2862. RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
  2863. };
  2864. static const unsigned int scifa0_ctrl_mux[] = {
  2865. SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
  2866. };
  2867. static const unsigned int scifa0_data_b_pins[] = {
  2868. /* RXD, TXD */
  2869. RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
  2870. };
  2871. static const unsigned int scifa0_data_b_mux[] = {
  2872. SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
  2873. };
  2874. static const unsigned int scifa0_clk_b_pins[] = {
  2875. /* SCK */
  2876. RCAR_GP_PIN(1, 19),
  2877. };
  2878. static const unsigned int scifa0_clk_b_mux[] = {
  2879. SCIFA0_SCK_B_MARK,
  2880. };
  2881. static const unsigned int scifa0_ctrl_b_pins[] = {
  2882. /* RTS, CTS */
  2883. RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
  2884. };
  2885. static const unsigned int scifa0_ctrl_b_mux[] = {
  2886. SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
  2887. };
  2888. /* - SCIFA1 ----------------------------------------------------------------- */
  2889. static const unsigned int scifa1_data_pins[] = {
  2890. /* RXD, TXD */
  2891. RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
  2892. };
  2893. static const unsigned int scifa1_data_mux[] = {
  2894. SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
  2895. };
  2896. static const unsigned int scifa1_clk_pins[] = {
  2897. /* SCK */
  2898. RCAR_GP_PIN(4, 20),
  2899. };
  2900. static const unsigned int scifa1_clk_mux[] = {
  2901. SCIFA1_SCK_MARK,
  2902. };
  2903. static const unsigned int scifa1_ctrl_pins[] = {
  2904. /* RTS, CTS */
  2905. RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
  2906. };
  2907. static const unsigned int scifa1_ctrl_mux[] = {
  2908. SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
  2909. };
  2910. static const unsigned int scifa1_data_b_pins[] = {
  2911. /* RXD, TXD */
  2912. RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
  2913. };
  2914. static const unsigned int scifa1_data_b_mux[] = {
  2915. SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
  2916. };
  2917. static const unsigned int scifa1_clk_b_pins[] = {
  2918. /* SCK */
  2919. RCAR_GP_PIN(0, 23),
  2920. };
  2921. static const unsigned int scifa1_clk_b_mux[] = {
  2922. SCIFA1_SCK_B_MARK,
  2923. };
  2924. static const unsigned int scifa1_ctrl_b_pins[] = {
  2925. /* RTS, CTS */
  2926. RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
  2927. };
  2928. static const unsigned int scifa1_ctrl_b_mux[] = {
  2929. SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
  2930. };
  2931. static const unsigned int scifa1_data_c_pins[] = {
  2932. /* RXD, TXD */
  2933. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
  2934. };
  2935. static const unsigned int scifa1_data_c_mux[] = {
  2936. SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
  2937. };
  2938. static const unsigned int scifa1_clk_c_pins[] = {
  2939. /* SCK */
  2940. RCAR_GP_PIN(0, 8),
  2941. };
  2942. static const unsigned int scifa1_clk_c_mux[] = {
  2943. SCIFA1_SCK_C_MARK,
  2944. };
  2945. static const unsigned int scifa1_ctrl_c_pins[] = {
  2946. /* RTS, CTS */
  2947. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
  2948. };
  2949. static const unsigned int scifa1_ctrl_c_mux[] = {
  2950. SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
  2951. };
  2952. static const unsigned int scifa1_data_d_pins[] = {
  2953. /* RXD, TXD */
  2954. RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
  2955. };
  2956. static const unsigned int scifa1_data_d_mux[] = {
  2957. SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
  2958. };
  2959. static const unsigned int scifa1_clk_d_pins[] = {
  2960. /* SCK */
  2961. RCAR_GP_PIN(2, 10),
  2962. };
  2963. static const unsigned int scifa1_clk_d_mux[] = {
  2964. SCIFA1_SCK_D_MARK,
  2965. };
  2966. static const unsigned int scifa1_ctrl_d_pins[] = {
  2967. /* RTS, CTS */
  2968. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  2969. };
  2970. static const unsigned int scifa1_ctrl_d_mux[] = {
  2971. SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
  2972. };
  2973. /* - SCIFA2 ----------------------------------------------------------------- */
  2974. static const unsigned int scifa2_data_pins[] = {
  2975. /* RXD, TXD */
  2976. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
  2977. };
  2978. static const unsigned int scifa2_data_mux[] = {
  2979. SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
  2980. };
  2981. static const unsigned int scifa2_clk_pins[] = {
  2982. /* SCK */
  2983. RCAR_GP_PIN(5, 4),
  2984. };
  2985. static const unsigned int scifa2_clk_mux[] = {
  2986. SCIFA2_SCK_MARK,
  2987. };
  2988. static const unsigned int scifa2_ctrl_pins[] = {
  2989. /* RTS, CTS */
  2990. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
  2991. };
  2992. static const unsigned int scifa2_ctrl_mux[] = {
  2993. SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
  2994. };
  2995. static const unsigned int scifa2_data_b_pins[] = {
  2996. /* RXD, TXD */
  2997. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
  2998. };
  2999. static const unsigned int scifa2_data_b_mux[] = {
  3000. SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
  3001. };
  3002. static const unsigned int scifa2_data_c_pins[] = {
  3003. /* RXD, TXD */
  3004. RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
  3005. };
  3006. static const unsigned int scifa2_data_c_mux[] = {
  3007. SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
  3008. };
  3009. static const unsigned int scifa2_clk_c_pins[] = {
  3010. /* SCK */
  3011. RCAR_GP_PIN(5, 29),
  3012. };
  3013. static const unsigned int scifa2_clk_c_mux[] = {
  3014. SCIFA2_SCK_C_MARK,
  3015. };
  3016. /* - SCIFB0 ----------------------------------------------------------------- */
  3017. static const unsigned int scifb0_data_pins[] = {
  3018. /* RXD, TXD */
  3019. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
  3020. };
  3021. static const unsigned int scifb0_data_mux[] = {
  3022. SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
  3023. };
  3024. static const unsigned int scifb0_clk_pins[] = {
  3025. /* SCK */
  3026. RCAR_GP_PIN(4, 8),
  3027. };
  3028. static const unsigned int scifb0_clk_mux[] = {
  3029. SCIFB0_SCK_MARK,
  3030. };
  3031. static const unsigned int scifb0_ctrl_pins[] = {
  3032. /* RTS, CTS */
  3033. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
  3034. };
  3035. static const unsigned int scifb0_ctrl_mux[] = {
  3036. SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
  3037. };
  3038. static const unsigned int scifb0_data_b_pins[] = {
  3039. /* RXD, TXD */
  3040. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
  3041. };
  3042. static const unsigned int scifb0_data_b_mux[] = {
  3043. SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
  3044. };
  3045. static const unsigned int scifb0_clk_b_pins[] = {
  3046. /* SCK */
  3047. RCAR_GP_PIN(3, 9),
  3048. };
  3049. static const unsigned int scifb0_clk_b_mux[] = {
  3050. SCIFB0_SCK_B_MARK,
  3051. };
  3052. static const unsigned int scifb0_ctrl_b_pins[] = {
  3053. /* RTS, CTS */
  3054. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
  3055. };
  3056. static const unsigned int scifb0_ctrl_b_mux[] = {
  3057. SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
  3058. };
  3059. static const unsigned int scifb0_data_c_pins[] = {
  3060. /* RXD, TXD */
  3061. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3062. };
  3063. static const unsigned int scifb0_data_c_mux[] = {
  3064. SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
  3065. };
  3066. /* - SCIFB1 ----------------------------------------------------------------- */
  3067. static const unsigned int scifb1_data_pins[] = {
  3068. /* RXD, TXD */
  3069. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
  3070. };
  3071. static const unsigned int scifb1_data_mux[] = {
  3072. SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
  3073. };
  3074. static const unsigned int scifb1_clk_pins[] = {
  3075. /* SCK */
  3076. RCAR_GP_PIN(4, 14),
  3077. };
  3078. static const unsigned int scifb1_clk_mux[] = {
  3079. SCIFB1_SCK_MARK,
  3080. };
  3081. static const unsigned int scifb1_ctrl_pins[] = {
  3082. /* RTS, CTS */
  3083. RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
  3084. };
  3085. static const unsigned int scifb1_ctrl_mux[] = {
  3086. SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
  3087. };
  3088. static const unsigned int scifb1_data_b_pins[] = {
  3089. /* RXD, TXD */
  3090. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  3091. };
  3092. static const unsigned int scifb1_data_b_mux[] = {
  3093. SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
  3094. };
  3095. static const unsigned int scifb1_clk_b_pins[] = {
  3096. /* SCK */
  3097. RCAR_GP_PIN(3, 1),
  3098. };
  3099. static const unsigned int scifb1_clk_b_mux[] = {
  3100. SCIFB1_SCK_B_MARK,
  3101. };
  3102. static const unsigned int scifb1_ctrl_b_pins[] = {
  3103. /* RTS, CTS */
  3104. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
  3105. };
  3106. static const unsigned int scifb1_ctrl_b_mux[] = {
  3107. SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
  3108. };
  3109. static const unsigned int scifb1_data_c_pins[] = {
  3110. /* RXD, TXD */
  3111. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  3112. };
  3113. static const unsigned int scifb1_data_c_mux[] = {
  3114. SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
  3115. };
  3116. static const unsigned int scifb1_data_d_pins[] = {
  3117. /* RXD, TXD */
  3118. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
  3119. };
  3120. static const unsigned int scifb1_data_d_mux[] = {
  3121. SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
  3122. };
  3123. static const unsigned int scifb1_data_e_pins[] = {
  3124. /* RXD, TXD */
  3125. RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
  3126. };
  3127. static const unsigned int scifb1_data_e_mux[] = {
  3128. SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
  3129. };
  3130. static const unsigned int scifb1_clk_e_pins[] = {
  3131. /* SCK */
  3132. RCAR_GP_PIN(3, 17),
  3133. };
  3134. static const unsigned int scifb1_clk_e_mux[] = {
  3135. SCIFB1_SCK_E_MARK,
  3136. };
  3137. static const unsigned int scifb1_data_f_pins[] = {
  3138. /* RXD, TXD */
  3139. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3140. };
  3141. static const unsigned int scifb1_data_f_mux[] = {
  3142. SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
  3143. };
  3144. static const unsigned int scifb1_data_g_pins[] = {
  3145. /* RXD, TXD */
  3146. RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
  3147. };
  3148. static const unsigned int scifb1_data_g_mux[] = {
  3149. SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
  3150. };
  3151. static const unsigned int scifb1_clk_g_pins[] = {
  3152. /* SCK */
  3153. RCAR_GP_PIN(2, 20),
  3154. };
  3155. static const unsigned int scifb1_clk_g_mux[] = {
  3156. SCIFB1_SCK_G_MARK,
  3157. };
  3158. /* - SCIFB2 ----------------------------------------------------------------- */
  3159. static const unsigned int scifb2_data_pins[] = {
  3160. /* RXD, TXD */
  3161. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
  3162. };
  3163. static const unsigned int scifb2_data_mux[] = {
  3164. SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
  3165. };
  3166. static const unsigned int scifb2_clk_pins[] = {
  3167. /* SCK */
  3168. RCAR_GP_PIN(4, 21),
  3169. };
  3170. static const unsigned int scifb2_clk_mux[] = {
  3171. SCIFB2_SCK_MARK,
  3172. };
  3173. static const unsigned int scifb2_ctrl_pins[] = {
  3174. /* RTS, CTS */
  3175. RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
  3176. };
  3177. static const unsigned int scifb2_ctrl_mux[] = {
  3178. SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
  3179. };
  3180. static const unsigned int scifb2_data_b_pins[] = {
  3181. /* RXD, TXD */
  3182. RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
  3183. };
  3184. static const unsigned int scifb2_data_b_mux[] = {
  3185. SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
  3186. };
  3187. static const unsigned int scifb2_clk_b_pins[] = {
  3188. /* SCK */
  3189. RCAR_GP_PIN(0, 31),
  3190. };
  3191. static const unsigned int scifb2_clk_b_mux[] = {
  3192. SCIFB2_SCK_B_MARK,
  3193. };
  3194. static const unsigned int scifb2_ctrl_b_pins[] = {
  3195. /* RTS, CTS */
  3196. RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
  3197. };
  3198. static const unsigned int scifb2_ctrl_b_mux[] = {
  3199. SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
  3200. };
  3201. static const unsigned int scifb2_data_c_pins[] = {
  3202. /* RXD, TXD */
  3203. RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
  3204. };
  3205. static const unsigned int scifb2_data_c_mux[] = {
  3206. SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
  3207. };
  3208. /* - SCIF Clock ------------------------------------------------------------- */
  3209. static const unsigned int scif_clk_pins[] = {
  3210. /* SCIF_CLK */
  3211. RCAR_GP_PIN(4, 26),
  3212. };
  3213. static const unsigned int scif_clk_mux[] = {
  3214. SCIF_CLK_MARK,
  3215. };
  3216. static const unsigned int scif_clk_b_pins[] = {
  3217. /* SCIF_CLK */
  3218. RCAR_GP_PIN(5, 4),
  3219. };
  3220. static const unsigned int scif_clk_b_mux[] = {
  3221. SCIF_CLK_B_MARK,
  3222. };
  3223. /* - SDHI0 ------------------------------------------------------------------ */
  3224. static const unsigned int sdhi0_data1_pins[] = {
  3225. /* D0 */
  3226. RCAR_GP_PIN(3, 2),
  3227. };
  3228. static const unsigned int sdhi0_data1_mux[] = {
  3229. SD0_DAT0_MARK,
  3230. };
  3231. static const unsigned int sdhi0_data4_pins[] = {
  3232. /* D[0:3] */
  3233. RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
  3234. };
  3235. static const unsigned int sdhi0_data4_mux[] = {
  3236. SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
  3237. };
  3238. static const unsigned int sdhi0_ctrl_pins[] = {
  3239. /* CLK, CMD */
  3240. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
  3241. };
  3242. static const unsigned int sdhi0_ctrl_mux[] = {
  3243. SD0_CLK_MARK, SD0_CMD_MARK,
  3244. };
  3245. static const unsigned int sdhi0_cd_pins[] = {
  3246. /* CD */
  3247. RCAR_GP_PIN(3, 6),
  3248. };
  3249. static const unsigned int sdhi0_cd_mux[] = {
  3250. SD0_CD_MARK,
  3251. };
  3252. static const unsigned int sdhi0_wp_pins[] = {
  3253. /* WP */
  3254. RCAR_GP_PIN(3, 7),
  3255. };
  3256. static const unsigned int sdhi0_wp_mux[] = {
  3257. SD0_WP_MARK,
  3258. };
  3259. /* - SDHI1 ------------------------------------------------------------------ */
  3260. static const unsigned int sdhi1_data1_pins[] = {
  3261. /* D0 */
  3262. RCAR_GP_PIN(3, 10),
  3263. };
  3264. static const unsigned int sdhi1_data1_mux[] = {
  3265. SD1_DAT0_MARK,
  3266. };
  3267. static const unsigned int sdhi1_data4_pins[] = {
  3268. /* D[0:3] */
  3269. RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
  3270. };
  3271. static const unsigned int sdhi1_data4_mux[] = {
  3272. SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
  3273. };
  3274. static const unsigned int sdhi1_ctrl_pins[] = {
  3275. /* CLK, CMD */
  3276. RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  3277. };
  3278. static const unsigned int sdhi1_ctrl_mux[] = {
  3279. SD1_CLK_MARK, SD1_CMD_MARK,
  3280. };
  3281. static const unsigned int sdhi1_cd_pins[] = {
  3282. /* CD */
  3283. RCAR_GP_PIN(3, 14),
  3284. };
  3285. static const unsigned int sdhi1_cd_mux[] = {
  3286. SD1_CD_MARK,
  3287. };
  3288. static const unsigned int sdhi1_wp_pins[] = {
  3289. /* WP */
  3290. RCAR_GP_PIN(3, 15),
  3291. };
  3292. static const unsigned int sdhi1_wp_mux[] = {
  3293. SD1_WP_MARK,
  3294. };
  3295. /* - SDHI2 ------------------------------------------------------------------ */
  3296. static const unsigned int sdhi2_data1_pins[] = {
  3297. /* D0 */
  3298. RCAR_GP_PIN(3, 18),
  3299. };
  3300. static const unsigned int sdhi2_data1_mux[] = {
  3301. SD2_DAT0_MARK,
  3302. };
  3303. static const unsigned int sdhi2_data4_pins[] = {
  3304. /* D[0:3] */
  3305. RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
  3306. };
  3307. static const unsigned int sdhi2_data4_mux[] = {
  3308. SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
  3309. };
  3310. static const unsigned int sdhi2_ctrl_pins[] = {
  3311. /* CLK, CMD */
  3312. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
  3313. };
  3314. static const unsigned int sdhi2_ctrl_mux[] = {
  3315. SD2_CLK_MARK, SD2_CMD_MARK,
  3316. };
  3317. static const unsigned int sdhi2_cd_pins[] = {
  3318. /* CD */
  3319. RCAR_GP_PIN(3, 22),
  3320. };
  3321. static const unsigned int sdhi2_cd_mux[] = {
  3322. SD2_CD_MARK,
  3323. };
  3324. static const unsigned int sdhi2_wp_pins[] = {
  3325. /* WP */
  3326. RCAR_GP_PIN(3, 23),
  3327. };
  3328. static const unsigned int sdhi2_wp_mux[] = {
  3329. SD2_WP_MARK,
  3330. };
  3331. /* - SDHI3 ------------------------------------------------------------------ */
  3332. static const unsigned int sdhi3_data1_pins[] = {
  3333. /* D0 */
  3334. RCAR_GP_PIN(3, 26),
  3335. };
  3336. static const unsigned int sdhi3_data1_mux[] = {
  3337. SD3_DAT0_MARK,
  3338. };
  3339. static const unsigned int sdhi3_data4_pins[] = {
  3340. /* D[0:3] */
  3341. RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
  3342. };
  3343. static const unsigned int sdhi3_data4_mux[] = {
  3344. SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
  3345. };
  3346. static const unsigned int sdhi3_ctrl_pins[] = {
  3347. /* CLK, CMD */
  3348. RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
  3349. };
  3350. static const unsigned int sdhi3_ctrl_mux[] = {
  3351. SD3_CLK_MARK, SD3_CMD_MARK,
  3352. };
  3353. static const unsigned int sdhi3_cd_pins[] = {
  3354. /* CD */
  3355. RCAR_GP_PIN(3, 30),
  3356. };
  3357. static const unsigned int sdhi3_cd_mux[] = {
  3358. SD3_CD_MARK,
  3359. };
  3360. static const unsigned int sdhi3_wp_pins[] = {
  3361. /* WP */
  3362. RCAR_GP_PIN(3, 31),
  3363. };
  3364. static const unsigned int sdhi3_wp_mux[] = {
  3365. SD3_WP_MARK,
  3366. };
  3367. /* - SSI -------------------------------------------------------------------- */
  3368. static const unsigned int ssi0_data_pins[] = {
  3369. /* SDATA0 */
  3370. RCAR_GP_PIN(4, 5),
  3371. };
  3372. static const unsigned int ssi0_data_mux[] = {
  3373. SSI_SDATA0_MARK,
  3374. };
  3375. static const unsigned int ssi0129_ctrl_pins[] = {
  3376. /* SCK, WS */
  3377. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
  3378. };
  3379. static const unsigned int ssi0129_ctrl_mux[] = {
  3380. SSI_SCK0129_MARK, SSI_WS0129_MARK,
  3381. };
  3382. static const unsigned int ssi1_data_pins[] = {
  3383. /* SDATA1 */
  3384. RCAR_GP_PIN(4, 6),
  3385. };
  3386. static const unsigned int ssi1_data_mux[] = {
  3387. SSI_SDATA1_MARK,
  3388. };
  3389. static const unsigned int ssi1_ctrl_pins[] = {
  3390. /* SCK, WS */
  3391. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
  3392. };
  3393. static const unsigned int ssi1_ctrl_mux[] = {
  3394. SSI_SCK1_MARK, SSI_WS1_MARK,
  3395. };
  3396. static const unsigned int ssi2_data_pins[] = {
  3397. /* SDATA2 */
  3398. RCAR_GP_PIN(4, 7),
  3399. };
  3400. static const unsigned int ssi2_data_mux[] = {
  3401. SSI_SDATA2_MARK,
  3402. };
  3403. static const unsigned int ssi2_ctrl_pins[] = {
  3404. /* SCK, WS */
  3405. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
  3406. };
  3407. static const unsigned int ssi2_ctrl_mux[] = {
  3408. SSI_SCK2_MARK, SSI_WS2_MARK,
  3409. };
  3410. static const unsigned int ssi3_data_pins[] = {
  3411. /* SDATA3 */
  3412. RCAR_GP_PIN(4, 10),
  3413. };
  3414. static const unsigned int ssi3_data_mux[] = {
  3415. SSI_SDATA3_MARK
  3416. };
  3417. static const unsigned int ssi34_ctrl_pins[] = {
  3418. /* SCK, WS */
  3419. RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
  3420. };
  3421. static const unsigned int ssi34_ctrl_mux[] = {
  3422. SSI_SCK34_MARK, SSI_WS34_MARK,
  3423. };
  3424. static const unsigned int ssi4_data_pins[] = {
  3425. /* SDATA4 */
  3426. RCAR_GP_PIN(4, 13),
  3427. };
  3428. static const unsigned int ssi4_data_mux[] = {
  3429. SSI_SDATA4_MARK,
  3430. };
  3431. static const unsigned int ssi4_ctrl_pins[] = {
  3432. /* SCK, WS */
  3433. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3434. };
  3435. static const unsigned int ssi4_ctrl_mux[] = {
  3436. SSI_SCK4_MARK, SSI_WS4_MARK,
  3437. };
  3438. static const unsigned int ssi5_pins[] = {
  3439. /* SDATA5, SCK, WS */
  3440. RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  3441. };
  3442. static const unsigned int ssi5_mux[] = {
  3443. SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
  3444. };
  3445. static const unsigned int ssi5_b_pins[] = {
  3446. /* SDATA5, SCK, WS */
  3447. RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
  3448. };
  3449. static const unsigned int ssi5_b_mux[] = {
  3450. SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
  3451. };
  3452. static const unsigned int ssi5_c_pins[] = {
  3453. /* SDATA5, SCK, WS */
  3454. RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
  3455. };
  3456. static const unsigned int ssi5_c_mux[] = {
  3457. SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
  3458. };
  3459. static const unsigned int ssi6_pins[] = {
  3460. /* SDATA6, SCK, WS */
  3461. RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
  3462. };
  3463. static const unsigned int ssi6_mux[] = {
  3464. SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
  3465. };
  3466. static const unsigned int ssi6_b_pins[] = {
  3467. /* SDATA6, SCK, WS */
  3468. RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
  3469. };
  3470. static const unsigned int ssi6_b_mux[] = {
  3471. SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
  3472. };
  3473. static const unsigned int ssi7_data_pins[] = {
  3474. /* SDATA7 */
  3475. RCAR_GP_PIN(4, 22),
  3476. };
  3477. static const unsigned int ssi7_data_mux[] = {
  3478. SSI_SDATA7_MARK,
  3479. };
  3480. static const unsigned int ssi7_b_data_pins[] = {
  3481. /* SDATA7 */
  3482. RCAR_GP_PIN(4, 22),
  3483. };
  3484. static const unsigned int ssi7_b_data_mux[] = {
  3485. SSI_SDATA7_B_MARK,
  3486. };
  3487. static const unsigned int ssi7_c_data_pins[] = {
  3488. /* SDATA7 */
  3489. RCAR_GP_PIN(1, 26),
  3490. };
  3491. static const unsigned int ssi7_c_data_mux[] = {
  3492. SSI_SDATA7_C_MARK,
  3493. };
  3494. static const unsigned int ssi78_ctrl_pins[] = {
  3495. /* SCK, WS */
  3496. RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
  3497. };
  3498. static const unsigned int ssi78_ctrl_mux[] = {
  3499. SSI_SCK78_MARK, SSI_WS78_MARK,
  3500. };
  3501. static const unsigned int ssi78_b_ctrl_pins[] = {
  3502. /* SCK, WS */
  3503. RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
  3504. };
  3505. static const unsigned int ssi78_b_ctrl_mux[] = {
  3506. SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
  3507. };
  3508. static const unsigned int ssi78_c_ctrl_pins[] = {
  3509. /* SCK, WS */
  3510. RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
  3511. };
  3512. static const unsigned int ssi78_c_ctrl_mux[] = {
  3513. SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
  3514. };
  3515. static const unsigned int ssi8_data_pins[] = {
  3516. /* SDATA8 */
  3517. RCAR_GP_PIN(4, 23),
  3518. };
  3519. static const unsigned int ssi8_data_mux[] = {
  3520. SSI_SDATA8_MARK,
  3521. };
  3522. static const unsigned int ssi8_b_data_pins[] = {
  3523. /* SDATA8 */
  3524. RCAR_GP_PIN(4, 23),
  3525. };
  3526. static const unsigned int ssi8_b_data_mux[] = {
  3527. SSI_SDATA8_B_MARK,
  3528. };
  3529. static const unsigned int ssi8_c_data_pins[] = {
  3530. /* SDATA8 */
  3531. RCAR_GP_PIN(1, 27),
  3532. };
  3533. static const unsigned int ssi8_c_data_mux[] = {
  3534. SSI_SDATA8_C_MARK,
  3535. };
  3536. static const unsigned int ssi9_data_pins[] = {
  3537. /* SDATA9 */
  3538. RCAR_GP_PIN(4, 24),
  3539. };
  3540. static const unsigned int ssi9_data_mux[] = {
  3541. SSI_SDATA9_MARK,
  3542. };
  3543. static const unsigned int ssi9_ctrl_pins[] = {
  3544. /* SCK, WS */
  3545. RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
  3546. };
  3547. static const unsigned int ssi9_ctrl_mux[] = {
  3548. SSI_SCK9_MARK, SSI_WS9_MARK,
  3549. };
  3550. /* - TPU0 ------------------------------------------------------------------- */
  3551. static const unsigned int tpu0_to0_pins[] = {
  3552. /* TO */
  3553. RCAR_GP_PIN(0, 20),
  3554. };
  3555. static const unsigned int tpu0_to0_mux[] = {
  3556. TPU0TO0_MARK,
  3557. };
  3558. static const unsigned int tpu0_to1_pins[] = {
  3559. /* TO */
  3560. RCAR_GP_PIN(0, 21),
  3561. };
  3562. static const unsigned int tpu0_to1_mux[] = {
  3563. TPU0TO1_MARK,
  3564. };
  3565. static const unsigned int tpu0_to2_pins[] = {
  3566. /* TO */
  3567. RCAR_GP_PIN(0, 22),
  3568. };
  3569. static const unsigned int tpu0_to2_mux[] = {
  3570. TPU0TO2_MARK,
  3571. };
  3572. static const unsigned int tpu0_to3_pins[] = {
  3573. /* TO */
  3574. RCAR_GP_PIN(0, 23),
  3575. };
  3576. static const unsigned int tpu0_to3_mux[] = {
  3577. TPU0TO3_MARK,
  3578. };
  3579. /* - USB0 ------------------------------------------------------------------- */
  3580. static const unsigned int usb0_pins[] = {
  3581. /* PWEN, OVC/VBUS */
  3582. RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
  3583. };
  3584. static const unsigned int usb0_mux[] = {
  3585. USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
  3586. };
  3587. static const unsigned int usb0_ovc_vbus_pins[] = {
  3588. /* OVC/VBUS */
  3589. RCAR_GP_PIN(5, 19),
  3590. };
  3591. static const unsigned int usb0_ovc_vbus_mux[] = {
  3592. USB0_OVC_VBUS_MARK,
  3593. };
  3594. /* - USB1 ------------------------------------------------------------------- */
  3595. static const unsigned int usb1_pins[] = {
  3596. /* PWEN, OVC */
  3597. RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
  3598. };
  3599. static const unsigned int usb1_mux[] = {
  3600. USB1_PWEN_MARK, USB1_OVC_MARK,
  3601. };
  3602. static const unsigned int usb1_pwen_pins[] = {
  3603. /* PWEN */
  3604. RCAR_GP_PIN(5, 20),
  3605. };
  3606. static const unsigned int usb1_pwen_mux[] = {
  3607. USB1_PWEN_MARK,
  3608. };
  3609. /* - USB2 ------------------------------------------------------------------- */
  3610. static const unsigned int usb2_pins[] = {
  3611. /* PWEN, OVC */
  3612. RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
  3613. };
  3614. static const unsigned int usb2_mux[] = {
  3615. USB2_PWEN_MARK, USB2_OVC_MARK,
  3616. };
  3617. /* - VIN0 ------------------------------------------------------------------- */
  3618. static const union vin_data vin0_data_pins = {
  3619. .data24 = {
  3620. /* B */
  3621. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
  3622. RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
  3623. RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
  3624. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  3625. /* G */
  3626. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  3627. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3628. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3629. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3630. /* R */
  3631. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3632. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3633. RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
  3634. RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
  3635. },
  3636. };
  3637. static const union vin_data vin0_data_mux = {
  3638. .data24 = {
  3639. /* B */
  3640. VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
  3641. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  3642. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  3643. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  3644. /* G */
  3645. VI0_G0_MARK, VI0_G1_MARK,
  3646. VI0_G2_MARK, VI0_G3_MARK,
  3647. VI0_G4_MARK, VI0_G5_MARK,
  3648. VI0_G6_MARK, VI0_G7_MARK,
  3649. /* R */
  3650. VI0_R0_MARK, VI0_R1_MARK,
  3651. VI0_R2_MARK, VI0_R3_MARK,
  3652. VI0_R4_MARK, VI0_R5_MARK,
  3653. VI0_R6_MARK, VI0_R7_MARK,
  3654. },
  3655. };
  3656. static const unsigned int vin0_data18_pins[] = {
  3657. /* B */
  3658. RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
  3659. RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
  3660. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
  3661. /* G */
  3662. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3663. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3664. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3665. /* R */
  3666. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3667. RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
  3668. RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
  3669. };
  3670. static const unsigned int vin0_data18_mux[] = {
  3671. /* B */
  3672. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  3673. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  3674. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  3675. /* G */
  3676. VI0_G2_MARK, VI0_G3_MARK,
  3677. VI0_G4_MARK, VI0_G5_MARK,
  3678. VI0_G6_MARK, VI0_G7_MARK,
  3679. /* R */
  3680. VI0_R2_MARK, VI0_R3_MARK,
  3681. VI0_R4_MARK, VI0_R5_MARK,
  3682. VI0_R6_MARK, VI0_R7_MARK,
  3683. };
  3684. static const unsigned int vin0_sync_pins[] = {
  3685. RCAR_GP_PIN(0, 12), /* HSYNC */
  3686. RCAR_GP_PIN(0, 13), /* VSYNC */
  3687. };
  3688. static const unsigned int vin0_sync_mux[] = {
  3689. VI0_HSYNC_N_MARK,
  3690. VI0_VSYNC_N_MARK,
  3691. };
  3692. static const unsigned int vin0_field_pins[] = {
  3693. RCAR_GP_PIN(0, 15),
  3694. };
  3695. static const unsigned int vin0_field_mux[] = {
  3696. VI0_FIELD_MARK,
  3697. };
  3698. static const unsigned int vin0_clkenb_pins[] = {
  3699. RCAR_GP_PIN(0, 14),
  3700. };
  3701. static const unsigned int vin0_clkenb_mux[] = {
  3702. VI0_CLKENB_MARK,
  3703. };
  3704. static const unsigned int vin0_clk_pins[] = {
  3705. RCAR_GP_PIN(2, 0),
  3706. };
  3707. static const unsigned int vin0_clk_mux[] = {
  3708. VI0_CLK_MARK,
  3709. };
  3710. /* - VIN1 ------------------------------------------------------------------- */
  3711. static const union vin_data vin1_data_pins = {
  3712. .data24 = {
  3713. /* B */
  3714. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  3715. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
  3716. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
  3717. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
  3718. /* G */
  3719. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
  3720. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
  3721. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
  3722. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
  3723. /* R */
  3724. RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
  3725. RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
  3726. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  3727. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
  3728. },
  3729. };
  3730. static const union vin_data vin1_data_mux = {
  3731. .data24 = {
  3732. /* B */
  3733. VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
  3734. VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
  3735. VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
  3736. VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
  3737. /* G */
  3738. VI1_G0_MARK, VI1_G1_MARK,
  3739. VI1_G2_MARK, VI1_G3_MARK,
  3740. VI1_G4_MARK, VI1_G5_MARK,
  3741. VI1_G6_MARK, VI1_G7_MARK,
  3742. /* R */
  3743. VI1_R0_MARK, VI1_R1_MARK,
  3744. VI1_R2_MARK, VI1_R3_MARK,
  3745. VI1_R4_MARK, VI1_R5_MARK,
  3746. VI1_R6_MARK, VI1_R7_MARK,
  3747. },
  3748. };
  3749. static const unsigned int vin1_data18_pins[] = {
  3750. /* B */
  3751. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
  3752. RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
  3753. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
  3754. /* G */
  3755. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
  3756. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
  3757. RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
  3758. /* R */
  3759. RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
  3760. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  3761. RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
  3762. };
  3763. static const unsigned int vin1_data18_mux[] = {
  3764. /* B */
  3765. VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
  3766. VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
  3767. VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
  3768. /* G */
  3769. VI1_G2_MARK, VI1_G3_MARK,
  3770. VI1_G4_MARK, VI1_G5_MARK,
  3771. VI1_G6_MARK, VI1_G7_MARK,
  3772. /* R */
  3773. VI1_R2_MARK, VI1_R3_MARK,
  3774. VI1_R4_MARK, VI1_R5_MARK,
  3775. VI1_R6_MARK, VI1_R7_MARK,
  3776. };
  3777. static const unsigned int vin1_sync_pins[] = {
  3778. RCAR_GP_PIN(1, 24), /* HSYNC */
  3779. RCAR_GP_PIN(1, 25), /* VSYNC */
  3780. };
  3781. static const unsigned int vin1_sync_mux[] = {
  3782. VI1_HSYNC_N_MARK,
  3783. VI1_VSYNC_N_MARK,
  3784. };
  3785. static const unsigned int vin1_field_pins[] = {
  3786. RCAR_GP_PIN(1, 13),
  3787. };
  3788. static const unsigned int vin1_field_mux[] = {
  3789. VI1_FIELD_MARK,
  3790. };
  3791. static const unsigned int vin1_clkenb_pins[] = {
  3792. RCAR_GP_PIN(1, 26),
  3793. };
  3794. static const unsigned int vin1_clkenb_mux[] = {
  3795. VI1_CLKENB_MARK,
  3796. };
  3797. static const unsigned int vin1_clk_pins[] = {
  3798. RCAR_GP_PIN(2, 9),
  3799. };
  3800. static const unsigned int vin1_clk_mux[] = {
  3801. VI1_CLK_MARK,
  3802. };
  3803. /* - VIN2 ----------------------------------------------------------------- */
  3804. static const union vin_data vin2_data_pins = {
  3805. .data24 = {
  3806. /* B */
  3807. RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
  3808. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3809. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3810. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  3811. /* G */
  3812. RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
  3813. RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
  3814. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3815. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3816. /* R */
  3817. RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
  3818. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
  3819. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
  3820. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
  3821. },
  3822. };
  3823. static const union vin_data vin2_data_mux = {
  3824. .data24 = {
  3825. /* B */
  3826. VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
  3827. VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
  3828. VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
  3829. VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
  3830. /* G */
  3831. VI2_G0_MARK, VI2_G1_MARK,
  3832. VI2_G2_MARK, VI2_G3_MARK,
  3833. VI2_G4_MARK, VI2_G5_MARK,
  3834. VI2_G6_MARK, VI2_G7_MARK,
  3835. /* R */
  3836. VI2_R0_MARK, VI2_R1_MARK,
  3837. VI2_R2_MARK, VI2_R3_MARK,
  3838. VI2_R4_MARK, VI2_R5_MARK,
  3839. VI2_R6_MARK, VI2_R7_MARK,
  3840. },
  3841. };
  3842. static const unsigned int vin2_data18_pins[] = {
  3843. /* B */
  3844. RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
  3845. RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
  3846. RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
  3847. /* G */
  3848. RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
  3849. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
  3850. RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
  3851. /* R */
  3852. RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
  3853. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
  3854. RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
  3855. };
  3856. static const unsigned int vin2_data18_mux[] = {
  3857. /* B */
  3858. VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
  3859. VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
  3860. VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
  3861. /* G */
  3862. VI2_G2_MARK, VI2_G3_MARK,
  3863. VI2_G4_MARK, VI2_G5_MARK,
  3864. VI2_G6_MARK, VI2_G7_MARK,
  3865. /* R */
  3866. VI2_R2_MARK, VI2_R3_MARK,
  3867. VI2_R4_MARK, VI2_R5_MARK,
  3868. VI2_R6_MARK, VI2_R7_MARK,
  3869. };
  3870. static const unsigned int vin2_sync_pins[] = {
  3871. RCAR_GP_PIN(1, 16), /* HSYNC */
  3872. RCAR_GP_PIN(1, 21), /* VSYNC */
  3873. };
  3874. static const unsigned int vin2_sync_mux[] = {
  3875. VI2_HSYNC_N_MARK,
  3876. VI2_VSYNC_N_MARK,
  3877. };
  3878. static const unsigned int vin2_field_pins[] = {
  3879. RCAR_GP_PIN(1, 9),
  3880. };
  3881. static const unsigned int vin2_field_mux[] = {
  3882. VI2_FIELD_MARK,
  3883. };
  3884. static const unsigned int vin2_clkenb_pins[] = {
  3885. RCAR_GP_PIN(1, 8),
  3886. };
  3887. static const unsigned int vin2_clkenb_mux[] = {
  3888. VI2_CLKENB_MARK,
  3889. };
  3890. static const unsigned int vin2_clk_pins[] = {
  3891. RCAR_GP_PIN(1, 11),
  3892. };
  3893. static const unsigned int vin2_clk_mux[] = {
  3894. VI2_CLK_MARK,
  3895. };
  3896. /* - VIN3 ----------------------------------------------------------------- */
  3897. static const unsigned int vin3_data8_pins[] = {
  3898. RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
  3899. RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
  3900. RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
  3901. RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
  3902. };
  3903. static const unsigned int vin3_data8_mux[] = {
  3904. VI3_DATA0_MARK, VI3_DATA1_MARK,
  3905. VI3_DATA2_MARK, VI3_DATA3_MARK,
  3906. VI3_DATA4_MARK, VI3_DATA5_MARK,
  3907. VI3_DATA6_MARK, VI3_DATA7_MARK,
  3908. };
  3909. static const unsigned int vin3_sync_pins[] = {
  3910. RCAR_GP_PIN(1, 16), /* HSYNC */
  3911. RCAR_GP_PIN(1, 17), /* VSYNC */
  3912. };
  3913. static const unsigned int vin3_sync_mux[] = {
  3914. VI3_HSYNC_N_MARK,
  3915. VI3_VSYNC_N_MARK,
  3916. };
  3917. static const unsigned int vin3_field_pins[] = {
  3918. RCAR_GP_PIN(1, 15),
  3919. };
  3920. static const unsigned int vin3_field_mux[] = {
  3921. VI3_FIELD_MARK,
  3922. };
  3923. static const unsigned int vin3_clkenb_pins[] = {
  3924. RCAR_GP_PIN(1, 14),
  3925. };
  3926. static const unsigned int vin3_clkenb_mux[] = {
  3927. VI3_CLKENB_MARK,
  3928. };
  3929. static const unsigned int vin3_clk_pins[] = {
  3930. RCAR_GP_PIN(1, 23),
  3931. };
  3932. static const unsigned int vin3_clk_mux[] = {
  3933. VI3_CLK_MARK,
  3934. };
  3935. static const struct {
  3936. struct sh_pfc_pin_group common[298];
  3937. struct sh_pfc_pin_group automotive[1];
  3938. } pinmux_groups = {
  3939. .common = {
  3940. SH_PFC_PIN_GROUP(audio_clk_a),
  3941. SH_PFC_PIN_GROUP(audio_clk_b),
  3942. SH_PFC_PIN_GROUP(audio_clk_c),
  3943. SH_PFC_PIN_GROUP(audio_clkout),
  3944. SH_PFC_PIN_GROUP(audio_clkout_b),
  3945. SH_PFC_PIN_GROUP(audio_clkout_c),
  3946. SH_PFC_PIN_GROUP(audio_clkout_d),
  3947. SH_PFC_PIN_GROUP(avb_link),
  3948. SH_PFC_PIN_GROUP(avb_magic),
  3949. SH_PFC_PIN_GROUP(avb_phy_int),
  3950. SH_PFC_PIN_GROUP(avb_mdio),
  3951. SH_PFC_PIN_GROUP(avb_mii),
  3952. SH_PFC_PIN_GROUP(avb_gmii),
  3953. SH_PFC_PIN_GROUP(can0_data),
  3954. SH_PFC_PIN_GROUP(can0_data_b),
  3955. SH_PFC_PIN_GROUP(can0_data_c),
  3956. SH_PFC_PIN_GROUP(can0_data_d),
  3957. SH_PFC_PIN_GROUP(can1_data),
  3958. SH_PFC_PIN_GROUP(can1_data_b),
  3959. SH_PFC_PIN_GROUP(can_clk),
  3960. SH_PFC_PIN_GROUP(can_clk_b),
  3961. SH_PFC_PIN_GROUP(du_rgb666),
  3962. SH_PFC_PIN_GROUP(du_rgb888),
  3963. SH_PFC_PIN_GROUP(du_clk_out_0),
  3964. SH_PFC_PIN_GROUP(du_clk_out_1),
  3965. SH_PFC_PIN_GROUP(du_sync_0),
  3966. SH_PFC_PIN_GROUP(du_sync_1),
  3967. SH_PFC_PIN_GROUP(du_cde),
  3968. SH_PFC_PIN_GROUP(du0_clk_in),
  3969. SH_PFC_PIN_GROUP(du1_clk_in),
  3970. SH_PFC_PIN_GROUP(du2_clk_in),
  3971. SH_PFC_PIN_GROUP(eth_link),
  3972. SH_PFC_PIN_GROUP(eth_magic),
  3973. SH_PFC_PIN_GROUP(eth_mdio),
  3974. SH_PFC_PIN_GROUP(eth_rmii),
  3975. SH_PFC_PIN_GROUP(hscif0_data),
  3976. SH_PFC_PIN_GROUP(hscif0_clk),
  3977. SH_PFC_PIN_GROUP(hscif0_ctrl),
  3978. SH_PFC_PIN_GROUP(hscif0_data_b),
  3979. SH_PFC_PIN_GROUP(hscif0_ctrl_b),
  3980. SH_PFC_PIN_GROUP(hscif0_data_c),
  3981. SH_PFC_PIN_GROUP(hscif0_ctrl_c),
  3982. SH_PFC_PIN_GROUP(hscif0_data_d),
  3983. SH_PFC_PIN_GROUP(hscif0_ctrl_d),
  3984. SH_PFC_PIN_GROUP(hscif0_data_e),
  3985. SH_PFC_PIN_GROUP(hscif0_ctrl_e),
  3986. SH_PFC_PIN_GROUP(hscif0_data_f),
  3987. SH_PFC_PIN_GROUP(hscif0_ctrl_f),
  3988. SH_PFC_PIN_GROUP(hscif1_data),
  3989. SH_PFC_PIN_GROUP(hscif1_clk),
  3990. SH_PFC_PIN_GROUP(hscif1_ctrl),
  3991. SH_PFC_PIN_GROUP(hscif1_data_b),
  3992. SH_PFC_PIN_GROUP(hscif1_clk_b),
  3993. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  3994. SH_PFC_PIN_GROUP(i2c0),
  3995. SH_PFC_PIN_GROUP(i2c1),
  3996. SH_PFC_PIN_GROUP(i2c1_b),
  3997. SH_PFC_PIN_GROUP(i2c1_c),
  3998. SH_PFC_PIN_GROUP(i2c2),
  3999. SH_PFC_PIN_GROUP(i2c2_b),
  4000. SH_PFC_PIN_GROUP(i2c2_c),
  4001. SH_PFC_PIN_GROUP(i2c2_d),
  4002. SH_PFC_PIN_GROUP(i2c2_e),
  4003. SH_PFC_PIN_GROUP(i2c3),
  4004. SH_PFC_PIN_GROUP(iic0),
  4005. SH_PFC_PIN_GROUP(iic1),
  4006. SH_PFC_PIN_GROUP(iic1_b),
  4007. SH_PFC_PIN_GROUP(iic1_c),
  4008. SH_PFC_PIN_GROUP(iic2),
  4009. SH_PFC_PIN_GROUP(iic2_b),
  4010. SH_PFC_PIN_GROUP(iic2_c),
  4011. SH_PFC_PIN_GROUP(iic2_d),
  4012. SH_PFC_PIN_GROUP(iic2_e),
  4013. SH_PFC_PIN_GROUP(iic3),
  4014. SH_PFC_PIN_GROUP(intc_irq0),
  4015. SH_PFC_PIN_GROUP(intc_irq1),
  4016. SH_PFC_PIN_GROUP(intc_irq2),
  4017. SH_PFC_PIN_GROUP(intc_irq3),
  4018. SH_PFC_PIN_GROUP(mmc0_data1),
  4019. SH_PFC_PIN_GROUP(mmc0_data4),
  4020. SH_PFC_PIN_GROUP(mmc0_data8),
  4021. SH_PFC_PIN_GROUP(mmc0_ctrl),
  4022. SH_PFC_PIN_GROUP(mmc1_data1),
  4023. SH_PFC_PIN_GROUP(mmc1_data4),
  4024. SH_PFC_PIN_GROUP(mmc1_data8),
  4025. SH_PFC_PIN_GROUP(mmc1_ctrl),
  4026. SH_PFC_PIN_GROUP(msiof0_clk),
  4027. SH_PFC_PIN_GROUP(msiof0_sync),
  4028. SH_PFC_PIN_GROUP(msiof0_ss1),
  4029. SH_PFC_PIN_GROUP(msiof0_ss2),
  4030. SH_PFC_PIN_GROUP(msiof0_rx),
  4031. SH_PFC_PIN_GROUP(msiof0_tx),
  4032. SH_PFC_PIN_GROUP(msiof0_clk_b),
  4033. SH_PFC_PIN_GROUP(msiof0_ss1_b),
  4034. SH_PFC_PIN_GROUP(msiof0_ss2_b),
  4035. SH_PFC_PIN_GROUP(msiof0_rx_b),
  4036. SH_PFC_PIN_GROUP(msiof0_tx_b),
  4037. SH_PFC_PIN_GROUP(msiof1_clk),
  4038. SH_PFC_PIN_GROUP(msiof1_sync),
  4039. SH_PFC_PIN_GROUP(msiof1_ss1),
  4040. SH_PFC_PIN_GROUP(msiof1_ss2),
  4041. SH_PFC_PIN_GROUP(msiof1_rx),
  4042. SH_PFC_PIN_GROUP(msiof1_tx),
  4043. SH_PFC_PIN_GROUP(msiof1_clk_b),
  4044. SH_PFC_PIN_GROUP(msiof1_ss1_b),
  4045. SH_PFC_PIN_GROUP(msiof1_ss2_b),
  4046. SH_PFC_PIN_GROUP(msiof1_rx_b),
  4047. SH_PFC_PIN_GROUP(msiof1_tx_b),
  4048. SH_PFC_PIN_GROUP(msiof2_clk),
  4049. SH_PFC_PIN_GROUP(msiof2_sync),
  4050. SH_PFC_PIN_GROUP(msiof2_ss1),
  4051. SH_PFC_PIN_GROUP(msiof2_ss2),
  4052. SH_PFC_PIN_GROUP(msiof2_rx),
  4053. SH_PFC_PIN_GROUP(msiof2_tx),
  4054. SH_PFC_PIN_GROUP(msiof3_clk),
  4055. SH_PFC_PIN_GROUP(msiof3_sync),
  4056. SH_PFC_PIN_GROUP(msiof3_ss1),
  4057. SH_PFC_PIN_GROUP(msiof3_ss2),
  4058. SH_PFC_PIN_GROUP(msiof3_rx),
  4059. SH_PFC_PIN_GROUP(msiof3_tx),
  4060. SH_PFC_PIN_GROUP(msiof3_clk_b),
  4061. SH_PFC_PIN_GROUP(msiof3_sync_b),
  4062. SH_PFC_PIN_GROUP(msiof3_rx_b),
  4063. SH_PFC_PIN_GROUP(msiof3_tx_b),
  4064. SH_PFC_PIN_GROUP(pwm0),
  4065. SH_PFC_PIN_GROUP(pwm0_b),
  4066. SH_PFC_PIN_GROUP(pwm1),
  4067. SH_PFC_PIN_GROUP(pwm1_b),
  4068. SH_PFC_PIN_GROUP(pwm2),
  4069. SH_PFC_PIN_GROUP(pwm3),
  4070. SH_PFC_PIN_GROUP(pwm4),
  4071. SH_PFC_PIN_GROUP(pwm5),
  4072. SH_PFC_PIN_GROUP(pwm6),
  4073. SH_PFC_PIN_GROUP(qspi_ctrl),
  4074. SH_PFC_PIN_GROUP(qspi_data2),
  4075. SH_PFC_PIN_GROUP(qspi_data4),
  4076. SH_PFC_PIN_GROUP(scif0_data),
  4077. SH_PFC_PIN_GROUP(scif0_clk),
  4078. SH_PFC_PIN_GROUP(scif0_ctrl),
  4079. SH_PFC_PIN_GROUP(scif0_data_b),
  4080. SH_PFC_PIN_GROUP(scif1_data),
  4081. SH_PFC_PIN_GROUP(scif1_clk),
  4082. SH_PFC_PIN_GROUP(scif1_ctrl),
  4083. SH_PFC_PIN_GROUP(scif1_data_b),
  4084. SH_PFC_PIN_GROUP(scif1_data_c),
  4085. SH_PFC_PIN_GROUP(scif1_data_d),
  4086. SH_PFC_PIN_GROUP(scif1_clk_d),
  4087. SH_PFC_PIN_GROUP(scif1_data_e),
  4088. SH_PFC_PIN_GROUP(scif1_clk_e),
  4089. SH_PFC_PIN_GROUP(scif2_data),
  4090. SH_PFC_PIN_GROUP(scif2_clk),
  4091. SH_PFC_PIN_GROUP(scif2_data_b),
  4092. SH_PFC_PIN_GROUP(scifa0_data),
  4093. SH_PFC_PIN_GROUP(scifa0_clk),
  4094. SH_PFC_PIN_GROUP(scifa0_ctrl),
  4095. SH_PFC_PIN_GROUP(scifa0_data_b),
  4096. SH_PFC_PIN_GROUP(scifa0_clk_b),
  4097. SH_PFC_PIN_GROUP(scifa0_ctrl_b),
  4098. SH_PFC_PIN_GROUP(scifa1_data),
  4099. SH_PFC_PIN_GROUP(scifa1_clk),
  4100. SH_PFC_PIN_GROUP(scifa1_ctrl),
  4101. SH_PFC_PIN_GROUP(scifa1_data_b),
  4102. SH_PFC_PIN_GROUP(scifa1_clk_b),
  4103. SH_PFC_PIN_GROUP(scifa1_ctrl_b),
  4104. SH_PFC_PIN_GROUP(scifa1_data_c),
  4105. SH_PFC_PIN_GROUP(scifa1_clk_c),
  4106. SH_PFC_PIN_GROUP(scifa1_ctrl_c),
  4107. SH_PFC_PIN_GROUP(scifa1_data_d),
  4108. SH_PFC_PIN_GROUP(scifa1_clk_d),
  4109. SH_PFC_PIN_GROUP(scifa1_ctrl_d),
  4110. SH_PFC_PIN_GROUP(scifa2_data),
  4111. SH_PFC_PIN_GROUP(scifa2_clk),
  4112. SH_PFC_PIN_GROUP(scifa2_ctrl),
  4113. SH_PFC_PIN_GROUP(scifa2_data_b),
  4114. SH_PFC_PIN_GROUP(scifa2_data_c),
  4115. SH_PFC_PIN_GROUP(scifa2_clk_c),
  4116. SH_PFC_PIN_GROUP(scifb0_data),
  4117. SH_PFC_PIN_GROUP(scifb0_clk),
  4118. SH_PFC_PIN_GROUP(scifb0_ctrl),
  4119. SH_PFC_PIN_GROUP(scifb0_data_b),
  4120. SH_PFC_PIN_GROUP(scifb0_clk_b),
  4121. SH_PFC_PIN_GROUP(scifb0_ctrl_b),
  4122. SH_PFC_PIN_GROUP(scifb0_data_c),
  4123. SH_PFC_PIN_GROUP(scifb1_data),
  4124. SH_PFC_PIN_GROUP(scifb1_clk),
  4125. SH_PFC_PIN_GROUP(scifb1_ctrl),
  4126. SH_PFC_PIN_GROUP(scifb1_data_b),
  4127. SH_PFC_PIN_GROUP(scifb1_clk_b),
  4128. SH_PFC_PIN_GROUP(scifb1_ctrl_b),
  4129. SH_PFC_PIN_GROUP(scifb1_data_c),
  4130. SH_PFC_PIN_GROUP(scifb1_data_d),
  4131. SH_PFC_PIN_GROUP(scifb1_data_e),
  4132. SH_PFC_PIN_GROUP(scifb1_clk_e),
  4133. SH_PFC_PIN_GROUP(scifb1_data_f),
  4134. SH_PFC_PIN_GROUP(scifb1_data_g),
  4135. SH_PFC_PIN_GROUP(scifb1_clk_g),
  4136. SH_PFC_PIN_GROUP(scifb2_data),
  4137. SH_PFC_PIN_GROUP(scifb2_clk),
  4138. SH_PFC_PIN_GROUP(scifb2_ctrl),
  4139. SH_PFC_PIN_GROUP(scifb2_data_b),
  4140. SH_PFC_PIN_GROUP(scifb2_clk_b),
  4141. SH_PFC_PIN_GROUP(scifb2_ctrl_b),
  4142. SH_PFC_PIN_GROUP(scifb2_data_c),
  4143. SH_PFC_PIN_GROUP(scif_clk),
  4144. SH_PFC_PIN_GROUP(scif_clk_b),
  4145. SH_PFC_PIN_GROUP(sdhi0_data1),
  4146. SH_PFC_PIN_GROUP(sdhi0_data4),
  4147. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  4148. SH_PFC_PIN_GROUP(sdhi0_cd),
  4149. SH_PFC_PIN_GROUP(sdhi0_wp),
  4150. SH_PFC_PIN_GROUP(sdhi1_data1),
  4151. SH_PFC_PIN_GROUP(sdhi1_data4),
  4152. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  4153. SH_PFC_PIN_GROUP(sdhi1_cd),
  4154. SH_PFC_PIN_GROUP(sdhi1_wp),
  4155. SH_PFC_PIN_GROUP(sdhi2_data1),
  4156. SH_PFC_PIN_GROUP(sdhi2_data4),
  4157. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  4158. SH_PFC_PIN_GROUP(sdhi2_cd),
  4159. SH_PFC_PIN_GROUP(sdhi2_wp),
  4160. SH_PFC_PIN_GROUP(sdhi3_data1),
  4161. SH_PFC_PIN_GROUP(sdhi3_data4),
  4162. SH_PFC_PIN_GROUP(sdhi3_ctrl),
  4163. SH_PFC_PIN_GROUP(sdhi3_cd),
  4164. SH_PFC_PIN_GROUP(sdhi3_wp),
  4165. SH_PFC_PIN_GROUP(ssi0_data),
  4166. SH_PFC_PIN_GROUP(ssi0129_ctrl),
  4167. SH_PFC_PIN_GROUP(ssi1_data),
  4168. SH_PFC_PIN_GROUP(ssi1_ctrl),
  4169. SH_PFC_PIN_GROUP(ssi2_data),
  4170. SH_PFC_PIN_GROUP(ssi2_ctrl),
  4171. SH_PFC_PIN_GROUP(ssi3_data),
  4172. SH_PFC_PIN_GROUP(ssi34_ctrl),
  4173. SH_PFC_PIN_GROUP(ssi4_data),
  4174. SH_PFC_PIN_GROUP(ssi4_ctrl),
  4175. SH_PFC_PIN_GROUP(ssi5),
  4176. SH_PFC_PIN_GROUP(ssi5_b),
  4177. SH_PFC_PIN_GROUP(ssi5_c),
  4178. SH_PFC_PIN_GROUP(ssi6),
  4179. SH_PFC_PIN_GROUP(ssi6_b),
  4180. SH_PFC_PIN_GROUP(ssi7_data),
  4181. SH_PFC_PIN_GROUP(ssi7_b_data),
  4182. SH_PFC_PIN_GROUP(ssi7_c_data),
  4183. SH_PFC_PIN_GROUP(ssi78_ctrl),
  4184. SH_PFC_PIN_GROUP(ssi78_b_ctrl),
  4185. SH_PFC_PIN_GROUP(ssi78_c_ctrl),
  4186. SH_PFC_PIN_GROUP(ssi8_data),
  4187. SH_PFC_PIN_GROUP(ssi8_b_data),
  4188. SH_PFC_PIN_GROUP(ssi8_c_data),
  4189. SH_PFC_PIN_GROUP(ssi9_data),
  4190. SH_PFC_PIN_GROUP(ssi9_ctrl),
  4191. SH_PFC_PIN_GROUP(tpu0_to0),
  4192. SH_PFC_PIN_GROUP(tpu0_to1),
  4193. SH_PFC_PIN_GROUP(tpu0_to2),
  4194. SH_PFC_PIN_GROUP(tpu0_to3),
  4195. SH_PFC_PIN_GROUP(usb0),
  4196. SH_PFC_PIN_GROUP(usb0_ovc_vbus),
  4197. SH_PFC_PIN_GROUP(usb1),
  4198. SH_PFC_PIN_GROUP(usb1_pwen),
  4199. SH_PFC_PIN_GROUP(usb2),
  4200. VIN_DATA_PIN_GROUP(vin0_data, 24),
  4201. VIN_DATA_PIN_GROUP(vin0_data, 20),
  4202. SH_PFC_PIN_GROUP(vin0_data18),
  4203. VIN_DATA_PIN_GROUP(vin0_data, 16),
  4204. VIN_DATA_PIN_GROUP(vin0_data, 12),
  4205. VIN_DATA_PIN_GROUP(vin0_data, 10),
  4206. VIN_DATA_PIN_GROUP(vin0_data, 8),
  4207. VIN_DATA_PIN_GROUP(vin0_data, 4),
  4208. SH_PFC_PIN_GROUP(vin0_sync),
  4209. SH_PFC_PIN_GROUP(vin0_field),
  4210. SH_PFC_PIN_GROUP(vin0_clkenb),
  4211. SH_PFC_PIN_GROUP(vin0_clk),
  4212. VIN_DATA_PIN_GROUP(vin1_data, 24),
  4213. VIN_DATA_PIN_GROUP(vin1_data, 20),
  4214. SH_PFC_PIN_GROUP(vin1_data18),
  4215. VIN_DATA_PIN_GROUP(vin1_data, 16),
  4216. VIN_DATA_PIN_GROUP(vin1_data, 12),
  4217. VIN_DATA_PIN_GROUP(vin1_data, 10),
  4218. VIN_DATA_PIN_GROUP(vin1_data, 8),
  4219. VIN_DATA_PIN_GROUP(vin1_data, 4),
  4220. SH_PFC_PIN_GROUP(vin1_sync),
  4221. SH_PFC_PIN_GROUP(vin1_field),
  4222. SH_PFC_PIN_GROUP(vin1_clkenb),
  4223. SH_PFC_PIN_GROUP(vin1_clk),
  4224. VIN_DATA_PIN_GROUP(vin2_data, 24),
  4225. SH_PFC_PIN_GROUP(vin2_data18),
  4226. VIN_DATA_PIN_GROUP(vin2_data, 16),
  4227. VIN_DATA_PIN_GROUP(vin2_data, 8),
  4228. VIN_DATA_PIN_GROUP(vin2_data, 4),
  4229. SH_PFC_PIN_GROUP(vin2_sync),
  4230. SH_PFC_PIN_GROUP(vin2_field),
  4231. SH_PFC_PIN_GROUP(vin2_clkenb),
  4232. SH_PFC_PIN_GROUP(vin2_clk),
  4233. SH_PFC_PIN_GROUP(vin3_data8),
  4234. SH_PFC_PIN_GROUP(vin3_sync),
  4235. SH_PFC_PIN_GROUP(vin3_field),
  4236. SH_PFC_PIN_GROUP(vin3_clkenb),
  4237. SH_PFC_PIN_GROUP(vin3_clk),
  4238. },
  4239. .automotive = {
  4240. SH_PFC_PIN_GROUP(mlb_3pin),
  4241. }
  4242. };
  4243. static const char * const audio_clk_groups[] = {
  4244. "audio_clk_a",
  4245. "audio_clk_b",
  4246. "audio_clk_c",
  4247. "audio_clkout",
  4248. "audio_clkout_b",
  4249. "audio_clkout_c",
  4250. "audio_clkout_d",
  4251. };
  4252. static const char * const avb_groups[] = {
  4253. "avb_link",
  4254. "avb_magic",
  4255. "avb_phy_int",
  4256. "avb_mdio",
  4257. "avb_mii",
  4258. "avb_gmii",
  4259. };
  4260. static const char * const can0_groups[] = {
  4261. "can0_data",
  4262. "can0_data_b",
  4263. "can0_data_c",
  4264. "can0_data_d",
  4265. };
  4266. static const char * const can1_groups[] = {
  4267. "can1_data",
  4268. "can1_data_b",
  4269. };
  4270. static const char * const can_clk_groups[] = {
  4271. "can_clk",
  4272. "can_clk_b",
  4273. };
  4274. static const char * const du_groups[] = {
  4275. "du_rgb666",
  4276. "du_rgb888",
  4277. "du_clk_out_0",
  4278. "du_clk_out_1",
  4279. "du_sync_0",
  4280. "du_sync_1",
  4281. "du_cde",
  4282. };
  4283. static const char * const du0_groups[] = {
  4284. "du0_clk_in",
  4285. };
  4286. static const char * const du1_groups[] = {
  4287. "du1_clk_in",
  4288. };
  4289. static const char * const du2_groups[] = {
  4290. "du2_clk_in",
  4291. };
  4292. static const char * const eth_groups[] = {
  4293. "eth_link",
  4294. "eth_magic",
  4295. "eth_mdio",
  4296. "eth_rmii",
  4297. };
  4298. static const char * const hscif0_groups[] = {
  4299. "hscif0_data",
  4300. "hscif0_clk",
  4301. "hscif0_ctrl",
  4302. "hscif0_data_b",
  4303. "hscif0_ctrl_b",
  4304. "hscif0_data_c",
  4305. "hscif0_ctrl_c",
  4306. "hscif0_data_d",
  4307. "hscif0_ctrl_d",
  4308. "hscif0_data_e",
  4309. "hscif0_ctrl_e",
  4310. "hscif0_data_f",
  4311. "hscif0_ctrl_f",
  4312. };
  4313. static const char * const hscif1_groups[] = {
  4314. "hscif1_data",
  4315. "hscif1_clk",
  4316. "hscif1_ctrl",
  4317. "hscif1_data_b",
  4318. "hscif1_clk_b",
  4319. "hscif1_ctrl_b",
  4320. };
  4321. static const char * const i2c0_groups[] = {
  4322. "i2c0",
  4323. };
  4324. static const char * const i2c1_groups[] = {
  4325. "i2c1",
  4326. "i2c1_b",
  4327. "i2c1_c",
  4328. };
  4329. static const char * const i2c2_groups[] = {
  4330. "i2c2",
  4331. "i2c2_b",
  4332. "i2c2_c",
  4333. "i2c2_d",
  4334. "i2c2_e",
  4335. };
  4336. static const char * const i2c3_groups[] = {
  4337. "i2c3",
  4338. };
  4339. static const char * const iic0_groups[] = {
  4340. "iic0",
  4341. };
  4342. static const char * const iic1_groups[] = {
  4343. "iic1",
  4344. "iic1_b",
  4345. "iic1_c",
  4346. };
  4347. static const char * const iic2_groups[] = {
  4348. "iic2",
  4349. "iic2_b",
  4350. "iic2_c",
  4351. "iic2_d",
  4352. "iic2_e",
  4353. };
  4354. static const char * const iic3_groups[] = {
  4355. "iic3",
  4356. };
  4357. static const char * const intc_groups[] = {
  4358. "intc_irq0",
  4359. "intc_irq1",
  4360. "intc_irq2",
  4361. "intc_irq3",
  4362. };
  4363. static const char * const mlb_groups[] = {
  4364. "mlb_3pin",
  4365. };
  4366. static const char * const mmc0_groups[] = {
  4367. "mmc0_data1",
  4368. "mmc0_data4",
  4369. "mmc0_data8",
  4370. "mmc0_ctrl",
  4371. };
  4372. static const char * const mmc1_groups[] = {
  4373. "mmc1_data1",
  4374. "mmc1_data4",
  4375. "mmc1_data8",
  4376. "mmc1_ctrl",
  4377. };
  4378. static const char * const msiof0_groups[] = {
  4379. "msiof0_clk",
  4380. "msiof0_sync",
  4381. "msiof0_ss1",
  4382. "msiof0_ss2",
  4383. "msiof0_rx",
  4384. "msiof0_tx",
  4385. "msiof0_clk_b",
  4386. "msiof0_ss1_b",
  4387. "msiof0_ss2_b",
  4388. "msiof0_rx_b",
  4389. "msiof0_tx_b",
  4390. };
  4391. static const char * const msiof1_groups[] = {
  4392. "msiof1_clk",
  4393. "msiof1_sync",
  4394. "msiof1_ss1",
  4395. "msiof1_ss2",
  4396. "msiof1_rx",
  4397. "msiof1_tx",
  4398. "msiof1_clk_b",
  4399. "msiof1_ss1_b",
  4400. "msiof1_ss2_b",
  4401. "msiof1_rx_b",
  4402. "msiof1_tx_b",
  4403. };
  4404. static const char * const msiof2_groups[] = {
  4405. "msiof2_clk",
  4406. "msiof2_sync",
  4407. "msiof2_ss1",
  4408. "msiof2_ss2",
  4409. "msiof2_rx",
  4410. "msiof2_tx",
  4411. };
  4412. static const char * const msiof3_groups[] = {
  4413. "msiof3_clk",
  4414. "msiof3_sync",
  4415. "msiof3_ss1",
  4416. "msiof3_ss2",
  4417. "msiof3_rx",
  4418. "msiof3_tx",
  4419. "msiof3_clk_b",
  4420. "msiof3_sync_b",
  4421. "msiof3_rx_b",
  4422. "msiof3_tx_b",
  4423. };
  4424. static const char * const pwm0_groups[] = {
  4425. "pwm0",
  4426. "pwm0_b",
  4427. };
  4428. static const char * const pwm1_groups[] = {
  4429. "pwm1",
  4430. "pwm1_b",
  4431. };
  4432. static const char * const pwm2_groups[] = {
  4433. "pwm2",
  4434. };
  4435. static const char * const pwm3_groups[] = {
  4436. "pwm3",
  4437. };
  4438. static const char * const pwm4_groups[] = {
  4439. "pwm4",
  4440. };
  4441. static const char * const pwm5_groups[] = {
  4442. "pwm5",
  4443. };
  4444. static const char * const pwm6_groups[] = {
  4445. "pwm6",
  4446. };
  4447. static const char * const qspi_groups[] = {
  4448. "qspi_ctrl",
  4449. "qspi_data2",
  4450. "qspi_data4",
  4451. };
  4452. static const char * const scif0_groups[] = {
  4453. "scif0_data",
  4454. "scif0_clk",
  4455. "scif0_ctrl",
  4456. "scif0_data_b",
  4457. };
  4458. static const char * const scif1_groups[] = {
  4459. "scif1_data",
  4460. "scif1_clk",
  4461. "scif1_ctrl",
  4462. "scif1_data_b",
  4463. "scif1_data_c",
  4464. "scif1_data_d",
  4465. "scif1_clk_d",
  4466. "scif1_data_e",
  4467. "scif1_clk_e",
  4468. };
  4469. static const char * const scif2_groups[] = {
  4470. "scif2_data",
  4471. "scif2_clk",
  4472. "scif2_data_b",
  4473. };
  4474. static const char * const scifa0_groups[] = {
  4475. "scifa0_data",
  4476. "scifa0_clk",
  4477. "scifa0_ctrl",
  4478. "scifa0_data_b",
  4479. "scifa0_clk_b",
  4480. "scifa0_ctrl_b",
  4481. };
  4482. static const char * const scifa1_groups[] = {
  4483. "scifa1_data",
  4484. "scifa1_clk",
  4485. "scifa1_ctrl",
  4486. "scifa1_data_b",
  4487. "scifa1_clk_b",
  4488. "scifa1_ctrl_b",
  4489. "scifa1_data_c",
  4490. "scifa1_clk_c",
  4491. "scifa1_ctrl_c",
  4492. "scifa1_data_d",
  4493. "scifa1_clk_d",
  4494. "scifa1_ctrl_d",
  4495. };
  4496. static const char * const scifa2_groups[] = {
  4497. "scifa2_data",
  4498. "scifa2_clk",
  4499. "scifa2_ctrl",
  4500. "scifa2_data_b",
  4501. "scifa2_data_c",
  4502. "scifa2_clk_c",
  4503. };
  4504. static const char * const scifb0_groups[] = {
  4505. "scifb0_data",
  4506. "scifb0_clk",
  4507. "scifb0_ctrl",
  4508. "scifb0_data_b",
  4509. "scifb0_clk_b",
  4510. "scifb0_ctrl_b",
  4511. "scifb0_data_c",
  4512. };
  4513. static const char * const scifb1_groups[] = {
  4514. "scifb1_data",
  4515. "scifb1_clk",
  4516. "scifb1_ctrl",
  4517. "scifb1_data_b",
  4518. "scifb1_clk_b",
  4519. "scifb1_ctrl_b",
  4520. "scifb1_data_c",
  4521. "scifb1_data_d",
  4522. "scifb1_data_e",
  4523. "scifb1_clk_e",
  4524. "scifb1_data_f",
  4525. "scifb1_data_g",
  4526. "scifb1_clk_g",
  4527. };
  4528. static const char * const scifb2_groups[] = {
  4529. "scifb2_data",
  4530. "scifb2_clk",
  4531. "scifb2_ctrl",
  4532. "scifb2_data_b",
  4533. "scifb2_clk_b",
  4534. "scifb2_ctrl_b",
  4535. "scifb2_data_c",
  4536. };
  4537. static const char * const scif_clk_groups[] = {
  4538. "scif_clk",
  4539. "scif_clk_b",
  4540. };
  4541. static const char * const sdhi0_groups[] = {
  4542. "sdhi0_data1",
  4543. "sdhi0_data4",
  4544. "sdhi0_ctrl",
  4545. "sdhi0_cd",
  4546. "sdhi0_wp",
  4547. };
  4548. static const char * const sdhi1_groups[] = {
  4549. "sdhi1_data1",
  4550. "sdhi1_data4",
  4551. "sdhi1_ctrl",
  4552. "sdhi1_cd",
  4553. "sdhi1_wp",
  4554. };
  4555. static const char * const sdhi2_groups[] = {
  4556. "sdhi2_data1",
  4557. "sdhi2_data4",
  4558. "sdhi2_ctrl",
  4559. "sdhi2_cd",
  4560. "sdhi2_wp",
  4561. };
  4562. static const char * const sdhi3_groups[] = {
  4563. "sdhi3_data1",
  4564. "sdhi3_data4",
  4565. "sdhi3_ctrl",
  4566. "sdhi3_cd",
  4567. "sdhi3_wp",
  4568. };
  4569. static const char * const ssi_groups[] = {
  4570. "ssi0_data",
  4571. "ssi0129_ctrl",
  4572. "ssi1_data",
  4573. "ssi1_ctrl",
  4574. "ssi2_data",
  4575. "ssi2_ctrl",
  4576. "ssi3_data",
  4577. "ssi34_ctrl",
  4578. "ssi4_data",
  4579. "ssi4_ctrl",
  4580. "ssi5",
  4581. "ssi5_b",
  4582. "ssi5_c",
  4583. "ssi6",
  4584. "ssi6_b",
  4585. "ssi7_data",
  4586. "ssi7_b_data",
  4587. "ssi7_c_data",
  4588. "ssi78_ctrl",
  4589. "ssi78_b_ctrl",
  4590. "ssi78_c_ctrl",
  4591. "ssi8_data",
  4592. "ssi8_b_data",
  4593. "ssi8_c_data",
  4594. "ssi9_data",
  4595. "ssi9_ctrl",
  4596. };
  4597. static const char * const tpu0_groups[] = {
  4598. "tpu0_to0",
  4599. "tpu0_to1",
  4600. "tpu0_to2",
  4601. "tpu0_to3",
  4602. };
  4603. static const char * const usb0_groups[] = {
  4604. "usb0",
  4605. "usb0_ovc_vbus",
  4606. };
  4607. static const char * const usb1_groups[] = {
  4608. "usb1",
  4609. "usb1_pwen",
  4610. };
  4611. static const char * const usb2_groups[] = {
  4612. "usb2",
  4613. };
  4614. static const char * const vin0_groups[] = {
  4615. "vin0_data24",
  4616. "vin0_data20",
  4617. "vin0_data18",
  4618. "vin0_data16",
  4619. "vin0_data12",
  4620. "vin0_data10",
  4621. "vin0_data8",
  4622. "vin0_data4",
  4623. "vin0_sync",
  4624. "vin0_field",
  4625. "vin0_clkenb",
  4626. "vin0_clk",
  4627. };
  4628. static const char * const vin1_groups[] = {
  4629. "vin1_data24",
  4630. "vin1_data20",
  4631. "vin1_data18",
  4632. "vin1_data16",
  4633. "vin1_data12",
  4634. "vin1_data10",
  4635. "vin1_data8",
  4636. "vin1_data4",
  4637. "vin1_sync",
  4638. "vin1_field",
  4639. "vin1_clkenb",
  4640. "vin1_clk",
  4641. };
  4642. static const char * const vin2_groups[] = {
  4643. "vin2_data24",
  4644. "vin2_data18",
  4645. "vin2_data16",
  4646. "vin2_data8",
  4647. "vin2_data4",
  4648. "vin2_sync",
  4649. "vin2_field",
  4650. "vin2_clkenb",
  4651. "vin2_clk",
  4652. };
  4653. static const char * const vin3_groups[] = {
  4654. "vin3_data8",
  4655. "vin3_sync",
  4656. "vin3_field",
  4657. "vin3_clkenb",
  4658. "vin3_clk",
  4659. };
  4660. static const struct {
  4661. struct sh_pfc_function common[58];
  4662. struct sh_pfc_function automotive[1];
  4663. } pinmux_functions = {
  4664. .common = {
  4665. SH_PFC_FUNCTION(audio_clk),
  4666. SH_PFC_FUNCTION(avb),
  4667. SH_PFC_FUNCTION(du),
  4668. SH_PFC_FUNCTION(can0),
  4669. SH_PFC_FUNCTION(can1),
  4670. SH_PFC_FUNCTION(can_clk),
  4671. SH_PFC_FUNCTION(du0),
  4672. SH_PFC_FUNCTION(du1),
  4673. SH_PFC_FUNCTION(du2),
  4674. SH_PFC_FUNCTION(eth),
  4675. SH_PFC_FUNCTION(hscif0),
  4676. SH_PFC_FUNCTION(hscif1),
  4677. SH_PFC_FUNCTION(i2c0),
  4678. SH_PFC_FUNCTION(i2c1),
  4679. SH_PFC_FUNCTION(i2c2),
  4680. SH_PFC_FUNCTION(i2c3),
  4681. SH_PFC_FUNCTION(iic0),
  4682. SH_PFC_FUNCTION(iic1),
  4683. SH_PFC_FUNCTION(iic2),
  4684. SH_PFC_FUNCTION(iic3),
  4685. SH_PFC_FUNCTION(intc),
  4686. SH_PFC_FUNCTION(mmc0),
  4687. SH_PFC_FUNCTION(mmc1),
  4688. SH_PFC_FUNCTION(msiof0),
  4689. SH_PFC_FUNCTION(msiof1),
  4690. SH_PFC_FUNCTION(msiof2),
  4691. SH_PFC_FUNCTION(msiof3),
  4692. SH_PFC_FUNCTION(pwm0),
  4693. SH_PFC_FUNCTION(pwm1),
  4694. SH_PFC_FUNCTION(pwm2),
  4695. SH_PFC_FUNCTION(pwm3),
  4696. SH_PFC_FUNCTION(pwm4),
  4697. SH_PFC_FUNCTION(pwm5),
  4698. SH_PFC_FUNCTION(pwm6),
  4699. SH_PFC_FUNCTION(qspi),
  4700. SH_PFC_FUNCTION(scif0),
  4701. SH_PFC_FUNCTION(scif1),
  4702. SH_PFC_FUNCTION(scif2),
  4703. SH_PFC_FUNCTION(scifa0),
  4704. SH_PFC_FUNCTION(scifa1),
  4705. SH_PFC_FUNCTION(scifa2),
  4706. SH_PFC_FUNCTION(scifb0),
  4707. SH_PFC_FUNCTION(scifb1),
  4708. SH_PFC_FUNCTION(scifb2),
  4709. SH_PFC_FUNCTION(scif_clk),
  4710. SH_PFC_FUNCTION(sdhi0),
  4711. SH_PFC_FUNCTION(sdhi1),
  4712. SH_PFC_FUNCTION(sdhi2),
  4713. SH_PFC_FUNCTION(sdhi3),
  4714. SH_PFC_FUNCTION(ssi),
  4715. SH_PFC_FUNCTION(tpu0),
  4716. SH_PFC_FUNCTION(usb0),
  4717. SH_PFC_FUNCTION(usb1),
  4718. SH_PFC_FUNCTION(usb2),
  4719. SH_PFC_FUNCTION(vin0),
  4720. SH_PFC_FUNCTION(vin1),
  4721. SH_PFC_FUNCTION(vin2),
  4722. SH_PFC_FUNCTION(vin3),
  4723. },
  4724. .automotive = {
  4725. SH_PFC_FUNCTION(mlb),
  4726. }
  4727. };
  4728. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  4729. { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
  4730. GP_0_31_FN, FN_IP3_17_15,
  4731. GP_0_30_FN, FN_IP3_14_12,
  4732. GP_0_29_FN, FN_IP3_11_8,
  4733. GP_0_28_FN, FN_IP3_7_4,
  4734. GP_0_27_FN, FN_IP3_3_0,
  4735. GP_0_26_FN, FN_IP2_28_26,
  4736. GP_0_25_FN, FN_IP2_25_22,
  4737. GP_0_24_FN, FN_IP2_21_18,
  4738. GP_0_23_FN, FN_IP2_17_15,
  4739. GP_0_22_FN, FN_IP2_14_12,
  4740. GP_0_21_FN, FN_IP2_11_9,
  4741. GP_0_20_FN, FN_IP2_8_6,
  4742. GP_0_19_FN, FN_IP2_5_3,
  4743. GP_0_18_FN, FN_IP2_2_0,
  4744. GP_0_17_FN, FN_IP1_29_28,
  4745. GP_0_16_FN, FN_IP1_27_26,
  4746. GP_0_15_FN, FN_IP1_25_22,
  4747. GP_0_14_FN, FN_IP1_21_18,
  4748. GP_0_13_FN, FN_IP1_17_15,
  4749. GP_0_12_FN, FN_IP1_14_12,
  4750. GP_0_11_FN, FN_IP1_11_8,
  4751. GP_0_10_FN, FN_IP1_7_4,
  4752. GP_0_9_FN, FN_IP1_3_0,
  4753. GP_0_8_FN, FN_IP0_30_27,
  4754. GP_0_7_FN, FN_IP0_26_23,
  4755. GP_0_6_FN, FN_IP0_22_20,
  4756. GP_0_5_FN, FN_IP0_19_16,
  4757. GP_0_4_FN, FN_IP0_15_12,
  4758. GP_0_3_FN, FN_IP0_11_9,
  4759. GP_0_2_FN, FN_IP0_8_6,
  4760. GP_0_1_FN, FN_IP0_5_3,
  4761. GP_0_0_FN, FN_IP0_2_0 ))
  4762. },
  4763. { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
  4764. 0, 0,
  4765. 0, 0,
  4766. GP_1_29_FN, FN_IP6_13_11,
  4767. GP_1_28_FN, FN_IP6_10_9,
  4768. GP_1_27_FN, FN_IP6_8_6,
  4769. GP_1_26_FN, FN_IP6_5_3,
  4770. GP_1_25_FN, FN_IP6_2_0,
  4771. GP_1_24_FN, FN_IP5_29_27,
  4772. GP_1_23_FN, FN_IP5_26_24,
  4773. GP_1_22_FN, FN_IP5_23_21,
  4774. GP_1_21_FN, FN_IP5_20_18,
  4775. GP_1_20_FN, FN_IP5_17_15,
  4776. GP_1_19_FN, FN_IP5_14_13,
  4777. GP_1_18_FN, FN_IP5_12_10,
  4778. GP_1_17_FN, FN_IP5_9_6,
  4779. GP_1_16_FN, FN_IP5_5_3,
  4780. GP_1_15_FN, FN_IP5_2_0,
  4781. GP_1_14_FN, FN_IP4_29_27,
  4782. GP_1_13_FN, FN_IP4_26_24,
  4783. GP_1_12_FN, FN_IP4_23_21,
  4784. GP_1_11_FN, FN_IP4_20_18,
  4785. GP_1_10_FN, FN_IP4_17_15,
  4786. GP_1_9_FN, FN_IP4_14_12,
  4787. GP_1_8_FN, FN_IP4_11_9,
  4788. GP_1_7_FN, FN_IP4_8_6,
  4789. GP_1_6_FN, FN_IP4_5_3,
  4790. GP_1_5_FN, FN_IP4_2_0,
  4791. GP_1_4_FN, FN_IP3_31_29,
  4792. GP_1_3_FN, FN_IP3_28_26,
  4793. GP_1_2_FN, FN_IP3_25_23,
  4794. GP_1_1_FN, FN_IP3_22_20,
  4795. GP_1_0_FN, FN_IP3_19_18, ))
  4796. },
  4797. { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
  4798. 0, 0,
  4799. 0, 0,
  4800. GP_2_29_FN, FN_IP7_15_13,
  4801. GP_2_28_FN, FN_IP7_12_10,
  4802. GP_2_27_FN, FN_IP7_9_8,
  4803. GP_2_26_FN, FN_IP7_7_6,
  4804. GP_2_25_FN, FN_IP7_5_3,
  4805. GP_2_24_FN, FN_IP7_2_0,
  4806. GP_2_23_FN, FN_IP6_31_29,
  4807. GP_2_22_FN, FN_IP6_28_26,
  4808. GP_2_21_FN, FN_IP6_25_23,
  4809. GP_2_20_FN, FN_IP6_22_20,
  4810. GP_2_19_FN, FN_IP6_19_17,
  4811. GP_2_18_FN, FN_IP6_16_14,
  4812. GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
  4813. GP_2_16_FN, FN_IP8_27,
  4814. GP_2_15_FN, FN_IP8_26,
  4815. GP_2_14_FN, FN_IP8_25_24,
  4816. GP_2_13_FN, FN_IP8_23_22,
  4817. GP_2_12_FN, FN_IP8_21_20,
  4818. GP_2_11_FN, FN_IP8_19_18,
  4819. GP_2_10_FN, FN_IP8_17_16,
  4820. GP_2_9_FN, FN_IP8_15_14,
  4821. GP_2_8_FN, FN_IP8_13_12,
  4822. GP_2_7_FN, FN_IP8_11_10,
  4823. GP_2_6_FN, FN_IP8_9_8,
  4824. GP_2_5_FN, FN_IP8_7_6,
  4825. GP_2_4_FN, FN_IP8_5_4,
  4826. GP_2_3_FN, FN_IP8_3_2,
  4827. GP_2_2_FN, FN_IP8_1_0,
  4828. GP_2_1_FN, FN_IP7_30_29,
  4829. GP_2_0_FN, FN_IP7_28_27 ))
  4830. },
  4831. { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
  4832. GP_3_31_FN, FN_IP11_21_18,
  4833. GP_3_30_FN, FN_IP11_17_15,
  4834. GP_3_29_FN, FN_IP11_14_13,
  4835. GP_3_28_FN, FN_IP11_12_11,
  4836. GP_3_27_FN, FN_IP11_10_9,
  4837. GP_3_26_FN, FN_IP11_8_7,
  4838. GP_3_25_FN, FN_IP11_6_5,
  4839. GP_3_24_FN, FN_IP11_4,
  4840. GP_3_23_FN, FN_IP11_3_0,
  4841. GP_3_22_FN, FN_IP10_29_26,
  4842. GP_3_21_FN, FN_IP10_25_23,
  4843. GP_3_20_FN, FN_IP10_22_19,
  4844. GP_3_19_FN, FN_IP10_18_15,
  4845. GP_3_18_FN, FN_IP10_14_11,
  4846. GP_3_17_FN, FN_IP10_10_7,
  4847. GP_3_16_FN, FN_IP10_6_4,
  4848. GP_3_15_FN, FN_IP10_3_0,
  4849. GP_3_14_FN, FN_IP9_31_28,
  4850. GP_3_13_FN, FN_IP9_27_26,
  4851. GP_3_12_FN, FN_IP9_25_24,
  4852. GP_3_11_FN, FN_IP9_23_22,
  4853. GP_3_10_FN, FN_IP9_21_20,
  4854. GP_3_9_FN, FN_IP9_19_18,
  4855. GP_3_8_FN, FN_IP9_17_16,
  4856. GP_3_7_FN, FN_IP9_15_12,
  4857. GP_3_6_FN, FN_IP9_11_8,
  4858. GP_3_5_FN, FN_IP9_7_6,
  4859. GP_3_4_FN, FN_IP9_5_4,
  4860. GP_3_3_FN, FN_IP9_3_2,
  4861. GP_3_2_FN, FN_IP9_1_0,
  4862. GP_3_1_FN, FN_IP8_30_29,
  4863. GP_3_0_FN, FN_IP8_28 ))
  4864. },
  4865. { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
  4866. GP_4_31_FN, FN_IP14_18_16,
  4867. GP_4_30_FN, FN_IP14_15_12,
  4868. GP_4_29_FN, FN_IP14_11_9,
  4869. GP_4_28_FN, FN_IP14_8_6,
  4870. GP_4_27_FN, FN_IP14_5_3,
  4871. GP_4_26_FN, FN_IP14_2_0,
  4872. GP_4_25_FN, FN_IP13_30_29,
  4873. GP_4_24_FN, FN_IP13_28_26,
  4874. GP_4_23_FN, FN_IP13_25_23,
  4875. GP_4_22_FN, FN_IP13_22_19,
  4876. GP_4_21_FN, FN_IP13_18_16,
  4877. GP_4_20_FN, FN_IP13_15_13,
  4878. GP_4_19_FN, FN_IP13_12_10,
  4879. GP_4_18_FN, FN_IP13_9_7,
  4880. GP_4_17_FN, FN_IP13_6_3,
  4881. GP_4_16_FN, FN_IP13_2_0,
  4882. GP_4_15_FN, FN_IP12_30_28,
  4883. GP_4_14_FN, FN_IP12_27_25,
  4884. GP_4_13_FN, FN_IP12_24_23,
  4885. GP_4_12_FN, FN_IP12_22_20,
  4886. GP_4_11_FN, FN_IP12_19_17,
  4887. GP_4_10_FN, FN_IP12_16_14,
  4888. GP_4_9_FN, FN_IP12_13_11,
  4889. GP_4_8_FN, FN_IP12_10_8,
  4890. GP_4_7_FN, FN_IP12_7_6,
  4891. GP_4_6_FN, FN_IP12_5_4,
  4892. GP_4_5_FN, FN_IP12_3_2,
  4893. GP_4_4_FN, FN_IP12_1_0,
  4894. GP_4_3_FN, FN_IP11_31_30,
  4895. GP_4_2_FN, FN_IP11_29_27,
  4896. GP_4_1_FN, FN_IP11_26_24,
  4897. GP_4_0_FN, FN_IP11_23_22 ))
  4898. },
  4899. { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
  4900. GP_5_31_FN, FN_IP7_24_22,
  4901. GP_5_30_FN, FN_IP7_21_19,
  4902. GP_5_29_FN, FN_IP7_18_16,
  4903. GP_5_28_FN, FN_DU_DOTCLKIN2,
  4904. GP_5_27_FN, FN_IP7_26_25,
  4905. GP_5_26_FN, FN_DU_DOTCLKIN0,
  4906. GP_5_25_FN, FN_AVS2,
  4907. GP_5_24_FN, FN_AVS1,
  4908. GP_5_23_FN, FN_USB2_OVC,
  4909. GP_5_22_FN, FN_USB2_PWEN,
  4910. GP_5_21_FN, FN_IP16_7,
  4911. GP_5_20_FN, FN_IP16_6,
  4912. GP_5_19_FN, FN_USB0_OVC_VBUS,
  4913. GP_5_18_FN, FN_USB0_PWEN,
  4914. GP_5_17_FN, FN_IP16_5_3,
  4915. GP_5_16_FN, FN_IP16_2_0,
  4916. GP_5_15_FN, FN_IP15_29_28,
  4917. GP_5_14_FN, FN_IP15_27_26,
  4918. GP_5_13_FN, FN_IP15_25_23,
  4919. GP_5_12_FN, FN_IP15_22_20,
  4920. GP_5_11_FN, FN_IP15_19_18,
  4921. GP_5_10_FN, FN_IP15_17_16,
  4922. GP_5_9_FN, FN_IP15_15_14,
  4923. GP_5_8_FN, FN_IP15_13_12,
  4924. GP_5_7_FN, FN_IP15_11_9,
  4925. GP_5_6_FN, FN_IP15_8_6,
  4926. GP_5_5_FN, FN_IP15_5_3,
  4927. GP_5_4_FN, FN_IP15_2_0,
  4928. GP_5_3_FN, FN_IP14_30_28,
  4929. GP_5_2_FN, FN_IP14_27_25,
  4930. GP_5_1_FN, FN_IP14_24_22,
  4931. GP_5_0_FN, FN_IP14_21_19 ))
  4932. },
  4933. { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
  4934. GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
  4935. GROUP(
  4936. /* IP0_31 [1] */
  4937. 0, 0,
  4938. /* IP0_30_27 [4] */
  4939. FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
  4940. FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
  4941. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4942. /* IP0_26_23 [4] */
  4943. FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
  4944. FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
  4945. FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
  4946. /* IP0_22_20 [3] */
  4947. FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
  4948. FN_I2C2_SCL_C, 0, 0,
  4949. /* IP0_19_16 [4] */
  4950. FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
  4951. FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
  4952. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4953. /* IP0_15_12 [4] */
  4954. FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
  4955. FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
  4956. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4957. /* IP0_11_9 [3] */
  4958. FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
  4959. 0, 0, 0,
  4960. /* IP0_8_6 [3] */
  4961. FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
  4962. 0, 0, 0,
  4963. /* IP0_5_3 [3] */
  4964. FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
  4965. 0, 0, 0,
  4966. /* IP0_2_0 [3] */
  4967. FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
  4968. 0, 0, 0, ))
  4969. },
  4970. { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
  4971. GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
  4972. GROUP(
  4973. /* IP1_31_30 [2] */
  4974. 0, 0, 0, 0,
  4975. /* IP1_29_28 [2] */
  4976. FN_A1, FN_PWM4, 0, 0,
  4977. /* IP1_27_26 [2] */
  4978. FN_A0, FN_PWM3, 0, 0,
  4979. /* IP1_25_22 [4] */
  4980. FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
  4981. FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
  4982. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4983. /* IP1_21_18 [4] */
  4984. FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
  4985. FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
  4986. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4987. /* IP1_17_15 [3] */
  4988. FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
  4989. FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
  4990. 0, 0, 0,
  4991. /* IP1_14_12 [3] */
  4992. FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
  4993. FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
  4994. 0, 0,
  4995. /* IP1_11_8 [4] */
  4996. FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
  4997. FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
  4998. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4999. /* IP1_7_4 [4] */
  5000. FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
  5001. FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
  5002. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5003. /* IP1_3_0 [4] */
  5004. FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
  5005. FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
  5006. 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
  5007. },
  5008. { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
  5009. GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
  5010. GROUP(
  5011. /* IP2_31_29 [3] */
  5012. 0, 0, 0, 0, 0, 0, 0, 0,
  5013. /* IP2_28_26 [3] */
  5014. FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
  5015. FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
  5016. /* IP2_25_22 [4] */
  5017. FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
  5018. FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
  5019. 0, 0, 0, 0, 0, 0, 0, 0,
  5020. /* IP2_21_18 [4] */
  5021. FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
  5022. FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
  5023. 0, 0, 0, 0, 0, 0, 0, 0,
  5024. /* IP2_17_15 [3] */
  5025. FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
  5026. 0, 0, 0, 0,
  5027. /* IP2_14_12 [3] */
  5028. FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
  5029. /* IP2_11_9 [3] */
  5030. FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
  5031. /* IP2_8_6 [3] */
  5032. FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
  5033. /* IP2_5_3 [3] */
  5034. FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
  5035. /* IP2_2_0 [3] */
  5036. FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
  5037. },
  5038. { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
  5039. GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
  5040. GROUP(
  5041. /* IP3_31_29 [3] */
  5042. FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
  5043. 0, 0, 0,
  5044. /* IP3_28_26 [3] */
  5045. FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
  5046. 0, 0, 0, 0,
  5047. /* IP3_25_23 [3] */
  5048. FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
  5049. /* IP3_22_20 [3] */
  5050. FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
  5051. /* IP3_19_18 [2] */
  5052. FN_A16, FN_ATAWR1_N, 0, 0,
  5053. /* IP3_17_15 [3] */
  5054. FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
  5055. 0, 0, 0, 0,
  5056. /* IP3_14_12 [3] */
  5057. FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
  5058. 0, 0, 0, 0,
  5059. /* IP3_11_8 [4] */
  5060. FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
  5061. FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
  5062. FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
  5063. /* IP3_7_4 [4] */
  5064. FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
  5065. FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
  5066. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  5067. /* IP3_3_0 [4] */
  5068. FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
  5069. FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
  5070. 0, 0, 0, 0, 0, 0, 0, 0, ))
  5071. },
  5072. { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
  5073. GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  5074. GROUP(
  5075. /* IP4_31_30 [2] */
  5076. 0, 0, 0, 0,
  5077. /* IP4_29_27 [3] */
  5078. FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
  5079. FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
  5080. /* IP4_26_24 [3] */
  5081. FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
  5082. FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
  5083. /* IP4_23_21 [3] */
  5084. FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
  5085. FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
  5086. /* IP4_20_18 [3] */
  5087. FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
  5088. FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
  5089. /* IP4_17_15 [3] */
  5090. FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
  5091. 0, 0, 0,
  5092. /* IP4_14_12 [3] */
  5093. FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
  5094. FN_VI2_FIELD_B, 0, 0,
  5095. /* IP4_11_9 [3] */
  5096. FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
  5097. FN_VI2_CLKENB_B, 0, 0,
  5098. /* IP4_8_6 [3] */
  5099. FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
  5100. /* IP4_5_3 [3] */
  5101. FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
  5102. /* IP4_2_0 [3] */
  5103. FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
  5104. ))
  5105. },
  5106. { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
  5107. GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
  5108. GROUP(
  5109. /* IP5_31_30 [2] */
  5110. 0, 0, 0, 0,
  5111. /* IP5_29_27 [3] */
  5112. FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
  5113. FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
  5114. /* IP5_26_24 [3] */
  5115. FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
  5116. FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
  5117. FN_MSIOF0_SCK_B, 0,
  5118. /* IP5_23_21 [3] */
  5119. FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
  5120. FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
  5121. /* IP5_20_18 [3] */
  5122. FN_WE0_N, FN_IECLK, FN_CAN_CLK,
  5123. FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
  5124. /* IP5_17_15 [3] */
  5125. FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
  5126. FN_INTC_IRQ4_N, 0, 0,
  5127. /* IP5_14_13 [2] */
  5128. FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
  5129. /* IP5_12_10 [3] */
  5130. FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
  5131. 0, 0,
  5132. /* IP5_9_6 [4] */
  5133. FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
  5134. FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
  5135. FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
  5136. /* IP5_5_3 [3] */
  5137. FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
  5138. FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
  5139. FN_INTC_EN0_N, FN_I2C1_SCL,
  5140. /* IP5_2_0 [3] */
  5141. FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
  5142. FN_VI2_R3, 0, 0, ))
  5143. },
  5144. { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
  5145. GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
  5146. GROUP(
  5147. /* IP6_31_29 [3] */
  5148. FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
  5149. FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
  5150. /* IP6_28_26 [3] */
  5151. FN_ETH_LINK, 0, FN_HTX0_E,
  5152. FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
  5153. /* IP6_25_23 [3] */
  5154. FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
  5155. FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
  5156. /* IP6_22_20 [3] */
  5157. FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
  5158. FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
  5159. /* IP6_19_17 [3] */
  5160. FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
  5161. FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
  5162. /* IP6_16_14 [3] */
  5163. FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
  5164. FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
  5165. FN_I2C2_SCL_E, 0,
  5166. /* IP6_13_11 [3] */
  5167. FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
  5168. FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
  5169. /* IP6_10_9 [2] */
  5170. FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
  5171. /* IP6_8_6 [3] */
  5172. FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
  5173. FN_SSI_SDATA8_C, 0, 0, 0,
  5174. /* IP6_5_3 [3] */
  5175. FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
  5176. FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
  5177. /* IP6_2_0 [3] */
  5178. FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
  5179. FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
  5180. },
  5181. { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
  5182. GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
  5183. GROUP(
  5184. /* IP7_31 [1] */
  5185. 0, 0,
  5186. /* IP7_30_29 [2] */
  5187. FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
  5188. /* IP7_28_27 [2] */
  5189. FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
  5190. /* IP7_26_25 [2] */
  5191. FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
  5192. /* IP7_24_22 [3] */
  5193. FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
  5194. 0, 0, 0,
  5195. /* IP7_21_19 [3] */
  5196. FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
  5197. FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
  5198. /* IP7_18_16 [3] */
  5199. FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
  5200. FN_GLO_SS_C, 0, 0, 0,
  5201. /* IP7_15_13 [3] */
  5202. FN_ETH_MDC, 0, FN_STP_ISD_1_B,
  5203. FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
  5204. /* IP7_12_10 [3] */
  5205. FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
  5206. FN_GLO_SCLK_C, 0, 0, 0,
  5207. /* IP7_9_8 [2] */
  5208. FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
  5209. /* IP7_7_6 [2] */
  5210. FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
  5211. /* IP7_5_3 [3] */
  5212. FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
  5213. /* IP7_2_0 [3] */
  5214. FN_ETH_MDIO, 0, FN_HRTS0_N_E,
  5215. FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
  5216. },
  5217. { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
  5218. GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
  5219. 2, 2, 2, 2, 2, 2),
  5220. GROUP(
  5221. /* IP8_31 [1] */
  5222. 0, 0,
  5223. /* IP8_30_29 [2] */
  5224. FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
  5225. /* IP8_28 [1] */
  5226. FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
  5227. /* IP8_27 [1] */
  5228. FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
  5229. /* IP8_26 [1] */
  5230. FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
  5231. /* IP8_25_24 [2] */
  5232. FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
  5233. FN_AVB_MAGIC, 0,
  5234. /* IP8_23_22 [2] */
  5235. FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
  5236. /* IP8_21_20 [2] */
  5237. FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
  5238. /* IP8_19_18 [2] */
  5239. FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
  5240. /* IP8_17_16 [2] */
  5241. FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
  5242. /* IP8_15_14 [2] */
  5243. FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
  5244. /* IP8_13_12 [2] */
  5245. FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
  5246. /* IP8_11_10 [2] */
  5247. FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
  5248. /* IP8_9_8 [2] */
  5249. FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
  5250. /* IP8_7_6 [2] */
  5251. FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
  5252. /* IP8_5_4 [2] */
  5253. FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
  5254. /* IP8_3_2 [2] */
  5255. FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
  5256. /* IP8_1_0 [2] */
  5257. FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
  5258. },
  5259. { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
  5260. GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
  5261. GROUP(
  5262. /* IP9_31_28 [4] */
  5263. FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
  5264. FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
  5265. FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
  5266. /* IP9_27_26 [2] */
  5267. FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
  5268. /* IP9_25_24 [2] */
  5269. FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
  5270. /* IP9_23_22 [2] */
  5271. FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
  5272. /* IP9_21_20 [2] */
  5273. FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
  5274. /* IP9_19_18 [2] */
  5275. FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
  5276. /* IP9_17_16 [2] */
  5277. FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
  5278. /* IP9_15_12 [4] */
  5279. FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
  5280. FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
  5281. FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
  5282. /* IP9_11_8 [4] */
  5283. FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
  5284. FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
  5285. FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
  5286. /* IP9_7_6 [2] */
  5287. FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
  5288. /* IP9_5_4 [2] */
  5289. FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
  5290. /* IP9_3_2 [2] */
  5291. FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
  5292. /* IP9_1_0 [2] */
  5293. FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
  5294. },
  5295. { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
  5296. GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
  5297. GROUP(
  5298. /* IP10_31_30 [2] */
  5299. 0, 0, 0, 0,
  5300. /* IP10_29_26 [4] */
  5301. FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
  5302. FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
  5303. FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
  5304. /* IP10_25_23 [3] */
  5305. FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
  5306. FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
  5307. /* IP10_22_19 [4] */
  5308. FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
  5309. FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
  5310. FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
  5311. /* IP10_18_15 [4] */
  5312. FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
  5313. FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
  5314. FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
  5315. 0, 0, 0, 0, 0, 0,
  5316. /* IP10_14_11 [4] */
  5317. FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
  5318. FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
  5319. FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
  5320. 0, 0, 0, 0, 0, 0, 0,
  5321. /* IP10_10_7 [4] */
  5322. FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
  5323. FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
  5324. FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
  5325. 0, 0, 0, 0, 0, 0, 0,
  5326. /* IP10_6_4 [3] */
  5327. FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
  5328. FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
  5329. FN_VI3_DATA0_B, 0,
  5330. /* IP10_3_0 [4] */
  5331. FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
  5332. FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
  5333. FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
  5334. },
  5335. { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
  5336. GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
  5337. GROUP(
  5338. /* IP11_31_30 [2] */
  5339. FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
  5340. /* IP11_29_27 [3] */
  5341. FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
  5342. 0, 0, 0,
  5343. /* IP11_26_24 [3] */
  5344. FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
  5345. 0, 0, 0,
  5346. /* IP11_23_22 [2] */
  5347. FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
  5348. /* IP11_21_18 [4] */
  5349. FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
  5350. 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
  5351. /* IP11_17_15 [3] */
  5352. FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
  5353. FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
  5354. /* IP11_14_13 [2] */
  5355. FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
  5356. /* IP11_12_11 [2] */
  5357. FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
  5358. /* IP11_10_9 [2] */
  5359. FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
  5360. /* IP11_8_7 [2] */
  5361. FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
  5362. /* IP11_6_5 [2] */
  5363. FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
  5364. /* IP11_4 [1] */
  5365. FN_SD3_CLK, FN_MMC1_CLK,
  5366. /* IP11_3_0 [4] */
  5367. FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
  5368. FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
  5369. FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
  5370. },
  5371. { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
  5372. GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
  5373. GROUP(
  5374. /* IP12_31 [1] */
  5375. 0, 0,
  5376. /* IP12_30_28 [3] */
  5377. FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
  5378. FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
  5379. FN_CAN_DEBUGOUT4, 0, 0,
  5380. /* IP12_27_25 [3] */
  5381. FN_SSI_SCK5, FN_SCIFB1_SCK,
  5382. FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
  5383. FN_CAN_DEBUGOUT3, 0, 0,
  5384. /* IP12_24_23 [2] */
  5385. FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
  5386. FN_CAN_DEBUGOUT2,
  5387. /* IP12_22_20 [3] */
  5388. FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
  5389. FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
  5390. /* IP12_19_17 [3] */
  5391. FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
  5392. FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
  5393. /* IP12_16_14 [3] */
  5394. FN_SSI_SDATA3, FN_STP_ISCLK_0,
  5395. FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
  5396. /* IP12_13_11 [3] */
  5397. FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
  5398. FN_CAN_STEP0, 0, 0, 0,
  5399. /* IP12_10_8 [3] */
  5400. FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
  5401. FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
  5402. /* IP12_7_6 [2] */
  5403. FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
  5404. /* IP12_5_4 [2] */
  5405. FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
  5406. /* IP12_3_2 [2] */
  5407. FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
  5408. /* IP12_1_0 [2] */
  5409. FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
  5410. },
  5411. { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
  5412. GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
  5413. GROUP(
  5414. /* IP13_31 [1] */
  5415. 0, 0,
  5416. /* IP13_30_29 [2] */
  5417. FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
  5418. /* IP13_28_26 [3] */
  5419. FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
  5420. FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
  5421. /* IP13_25_23 [3] */
  5422. FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
  5423. FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
  5424. /* IP13_22_19 [4] */
  5425. FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
  5426. FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
  5427. 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
  5428. /* IP13_18_16 [3] */
  5429. FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
  5430. FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
  5431. /* IP13_15_13 [3] */
  5432. FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
  5433. FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
  5434. /* IP13_12_10 [3] */
  5435. FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
  5436. FN_CAN_DEBUGOUT8, 0, 0,
  5437. /* IP13_9_7 [3] */
  5438. FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
  5439. FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
  5440. /* IP13_6_3 [4] */
  5441. FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
  5442. FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
  5443. FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
  5444. /* IP13_2_0 [3] */
  5445. FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
  5446. FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
  5447. },
  5448. { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
  5449. GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
  5450. GROUP(
  5451. /* IP14_30 [1] */
  5452. 0, 0,
  5453. /* IP14_30_28 [3] */
  5454. FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
  5455. FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
  5456. FN_HRTS0_N_C, 0,
  5457. /* IP14_27_25 [3] */
  5458. FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
  5459. FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
  5460. /* IP14_24_22 [3] */
  5461. FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
  5462. FN_LCDOUT9, 0, 0, 0,
  5463. /* IP14_21_19 [3] */
  5464. FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
  5465. FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
  5466. /* IP14_18_16 [3] */
  5467. FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
  5468. FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
  5469. /* IP14_15_12 [4] */
  5470. FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
  5471. FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
  5472. 0, 0, 0, 0, 0, 0, 0,
  5473. /* IP14_11_9 [3] */
  5474. FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
  5475. 0, 0, 0,
  5476. /* IP14_8_6 [3] */
  5477. FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
  5478. 0, 0, 0,
  5479. /* IP14_5_3 [3] */
  5480. FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
  5481. FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
  5482. /* IP14_2_0 [3] */
  5483. FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
  5484. FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
  5485. FN_REMOCON, 0, ))
  5486. },
  5487. { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
  5488. GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
  5489. GROUP(
  5490. /* IP15_31_30 [2] */
  5491. 0, 0, 0, 0,
  5492. /* IP15_29_28 [2] */
  5493. FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
  5494. /* IP15_27_26 [2] */
  5495. FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
  5496. /* IP15_25_23 [3] */
  5497. FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
  5498. FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
  5499. /* IP15_22_20 [3] */
  5500. FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
  5501. FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
  5502. /* IP15_19_18 [2] */
  5503. FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
  5504. /* IP15_17_16 [2] */
  5505. FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
  5506. /* IP15_15_14 [2] */
  5507. FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
  5508. /* IP15_13_12 [2] */
  5509. FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
  5510. /* IP15_11_9 [3] */
  5511. FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
  5512. 0, 0, 0,
  5513. /* IP15_8_6 [3] */
  5514. FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
  5515. FN_IIC2_SDA, FN_I2C2_SDA, 0,
  5516. /* IP15_5_3 [3] */
  5517. FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
  5518. FN_IIC2_SCL, FN_I2C2_SCL, 0,
  5519. /* IP15_2_0 [3] */
  5520. FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
  5521. FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
  5522. },
  5523. { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
  5524. GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
  5525. GROUP(
  5526. /* IP16_31_28 [4] */
  5527. 0, 0, 0, 0, 0, 0, 0, 0,
  5528. 0, 0, 0, 0, 0, 0, 0, 0,
  5529. /* IP16_27_24 [4] */
  5530. 0, 0, 0, 0, 0, 0, 0, 0,
  5531. 0, 0, 0, 0, 0, 0, 0, 0,
  5532. /* IP16_23_20 [4] */
  5533. 0, 0, 0, 0, 0, 0, 0, 0,
  5534. 0, 0, 0, 0, 0, 0, 0, 0,
  5535. /* IP16_19_16 [4] */
  5536. 0, 0, 0, 0, 0, 0, 0, 0,
  5537. 0, 0, 0, 0, 0, 0, 0, 0,
  5538. /* IP16_15_12 [4] */
  5539. 0, 0, 0, 0, 0, 0, 0, 0,
  5540. 0, 0, 0, 0, 0, 0, 0, 0,
  5541. /* IP16_11_8 [4] */
  5542. 0, 0, 0, 0, 0, 0, 0, 0,
  5543. 0, 0, 0, 0, 0, 0, 0, 0,
  5544. /* IP16_7 [1] */
  5545. FN_USB1_OVC, FN_TCLK1_B,
  5546. /* IP16_6 [1] */
  5547. FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
  5548. /* IP16_5_3 [3] */
  5549. FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
  5550. FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
  5551. /* IP16_2_0 [3] */
  5552. FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
  5553. FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
  5554. },
  5555. { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
  5556. GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
  5557. 1, 1, 1, 2, 1, 1, 2, 1, 1),
  5558. GROUP(
  5559. /* SEL_SCIF1 [3] */
  5560. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
  5561. FN_SEL_SCIF1_4, 0, 0, 0,
  5562. /* SEL_SCIFB [2] */
  5563. FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
  5564. /* SEL_SCIFB2 [2] */
  5565. FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
  5566. /* SEL_SCIFB1 [3] */
  5567. FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
  5568. FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
  5569. FN_SEL_SCIFB1_6, 0,
  5570. /* SEL_SCIFA1 [2] */
  5571. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
  5572. FN_SEL_SCIFA1_3,
  5573. /* SEL_SCIF0 [1] */
  5574. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
  5575. /* SEL_SCIFA [1] */
  5576. FN_SEL_SCFA_0, FN_SEL_SCFA_1,
  5577. /* SEL_SOF1 [1] */
  5578. FN_SEL_SOF1_0, FN_SEL_SOF1_1,
  5579. /* SEL_SSI7 [2] */
  5580. FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
  5581. /* SEL_SSI6 [1] */
  5582. FN_SEL_SSI6_0, FN_SEL_SSI6_1,
  5583. /* SEL_SSI5 [2] */
  5584. FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
  5585. /* SEL_VI3 [1] */
  5586. FN_SEL_VI3_0, FN_SEL_VI3_1,
  5587. /* SEL_VI2 [1] */
  5588. FN_SEL_VI2_0, FN_SEL_VI2_1,
  5589. /* SEL_VI1 [1] */
  5590. FN_SEL_VI1_0, FN_SEL_VI1_1,
  5591. /* SEL_VI0 [1] */
  5592. FN_SEL_VI0_0, FN_SEL_VI0_1,
  5593. /* SEL_TSIF1 [2] */
  5594. FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
  5595. /* RESERVED [1] */
  5596. 0, 0,
  5597. /* SEL_LBS [1] */
  5598. FN_SEL_LBS_0, FN_SEL_LBS_1,
  5599. /* SEL_TSIF0 [2] */
  5600. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  5601. /* SEL_SOF3 [1] */
  5602. FN_SEL_SOF3_0, FN_SEL_SOF3_1,
  5603. /* SEL_SOF0 [1] */
  5604. FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
  5605. },
  5606. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
  5607. GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
  5608. 3, 3, 2, 3, 2, 2),
  5609. GROUP(
  5610. /* RESERVED [3] */
  5611. 0, 0, 0, 0, 0, 0, 0, 0,
  5612. /* SEL_TMU1 [1] */
  5613. FN_SEL_TMU1_0, FN_SEL_TMU1_1,
  5614. /* SEL_HSCIF1 [1] */
  5615. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
  5616. /* SEL_SCIFCLK [1] */
  5617. FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
  5618. /* SEL_CAN0 [2] */
  5619. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  5620. /* SEL_CANCLK [1] */
  5621. FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
  5622. /* SEL_SCIFA2 [2] */
  5623. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
  5624. /* SEL_CAN1 [1] */
  5625. FN_SEL_CAN1_0, FN_SEL_CAN1_1,
  5626. /* RESERVED [2] */
  5627. 0, 0, 0, 0,
  5628. /* SEL_SCIF2 [1] */
  5629. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
  5630. /* SEL_ADI [1] */
  5631. FN_SEL_ADI_0, FN_SEL_ADI_1,
  5632. /* SEL_SSP [1] */
  5633. FN_SEL_SSP_0, FN_SEL_SSP_1,
  5634. /* SEL_FM [3] */
  5635. FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
  5636. FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
  5637. /* SEL_HSCIF0 [3] */
  5638. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
  5639. FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
  5640. /* SEL_GPS [2] */
  5641. FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
  5642. /* RESERVED [3] */
  5643. 0, 0, 0, 0, 0, 0, 0, 0,
  5644. /* SEL_SIM [2] */
  5645. FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
  5646. /* SEL_SSI8 [2] */
  5647. FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
  5648. },
  5649. { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
  5650. GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
  5651. GROUP(
  5652. /* SEL_IICDVFS [1] */
  5653. FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
  5654. /* SEL_IIC0 [1] */
  5655. FN_SEL_IIC0_0, FN_SEL_IIC0_1,
  5656. /* RESERVED [2] */
  5657. 0, 0, 0, 0,
  5658. /* RESERVED [4] */
  5659. 0, 0, 0, 0, 0, 0, 0, 0,
  5660. 0, 0, 0, 0, 0, 0, 0, 0,
  5661. /* RESERVED [4] */
  5662. 0, 0, 0, 0, 0, 0, 0, 0,
  5663. 0, 0, 0, 0, 0, 0, 0, 0,
  5664. /* RESERVED [2] */
  5665. 0, 0, 0, 0,
  5666. /* SEL_IEB [2] */
  5667. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
  5668. /* RESERVED [4] */
  5669. 0, 0, 0, 0, 0, 0, 0, 0,
  5670. 0, 0, 0, 0, 0, 0, 0, 0,
  5671. /* RESERVED [2] */
  5672. 0, 0, 0, 0,
  5673. /* SEL_IIC2 [3] */
  5674. FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
  5675. FN_SEL_IIC2_4, 0, 0, 0,
  5676. /* SEL_IIC1 [2] */
  5677. FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
  5678. /* SEL_I2C2 [3] */
  5679. FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
  5680. FN_SEL_I2C2_4, 0, 0, 0,
  5681. /* SEL_I2C1 [2] */
  5682. FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
  5683. },
  5684. { },
  5685. };
  5686. static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
  5687. {
  5688. if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
  5689. return -EINVAL;
  5690. *pocctrl = 0xe606008c;
  5691. return 31 - (pin & 0x1f);
  5692. }
  5693. static const struct soc_device_attribute r8a7790_tdsel[] = {
  5694. { .soc_id = "r8a7790", .revision = "ES1.0" },
  5695. { /* sentinel */ }
  5696. };
  5697. static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
  5698. {
  5699. /* Initialize TDSEL on old revisions */
  5700. if (soc_device_match(r8a7790_tdsel))
  5701. sh_pfc_write(pfc, 0xe6060088, 0x00155554);
  5702. return 0;
  5703. }
  5704. static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
  5705. .init = r8a7790_pinmux_soc_init,
  5706. .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
  5707. };
  5708. #ifdef CONFIG_PINCTRL_PFC_R8A7742
  5709. const struct sh_pfc_soc_info r8a7742_pinmux_info = {
  5710. .name = "r8a77420_pfc",
  5711. .ops = &r8a7790_pinmux_ops,
  5712. .unlock_reg = 0xe6060000, /* PMMR */
  5713. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5714. .pins = pinmux_pins,
  5715. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5716. .groups = pinmux_groups.common,
  5717. .nr_groups = ARRAY_SIZE(pinmux_groups.common),
  5718. .functions = pinmux_functions.common,
  5719. .nr_functions = ARRAY_SIZE(pinmux_functions.common),
  5720. .cfg_regs = pinmux_config_regs,
  5721. .pinmux_data = pinmux_data,
  5722. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5723. };
  5724. #endif
  5725. #ifdef CONFIG_PINCTRL_PFC_R8A7790
  5726. const struct sh_pfc_soc_info r8a7790_pinmux_info = {
  5727. .name = "r8a77900_pfc",
  5728. .ops = &r8a7790_pinmux_ops,
  5729. .unlock_reg = 0xe6060000, /* PMMR */
  5730. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  5731. .pins = pinmux_pins,
  5732. .nr_pins = ARRAY_SIZE(pinmux_pins),
  5733. .groups = pinmux_groups.common,
  5734. .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
  5735. ARRAY_SIZE(pinmux_groups.automotive),
  5736. .functions = pinmux_functions.common,
  5737. .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
  5738. ARRAY_SIZE(pinmux_functions.automotive),
  5739. .cfg_regs = pinmux_config_regs,
  5740. .pinmux_data = pinmux_data,
  5741. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  5742. };
  5743. #endif