pfc-r8a7778.c 105 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a7778 processor support - PFC hardware block
  4. *
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  7. * Copyright (C) 2013 Cogent Embedded, Inc.
  8. * Copyright (C) 2015 Ulrich Hecht
  9. *
  10. * based on
  11. * Copyright (C) 2011 Renesas Solutions Corp.
  12. * Copyright (C) 2011 Magnus Damm
  13. */
  14. #include <linux/io.h>
  15. #include <linux/kernel.h>
  16. #include <linux/pinctrl/pinconf-generic.h>
  17. #include "core.h"
  18. #include "sh_pfc.h"
  19. #define PORT_GP_PUP_1(bank, pin, fn, sfx) \
  20. PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  21. #define CPU_ALL_GP(fn, sfx) \
  22. PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
  23. PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
  24. PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
  25. PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
  26. PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  27. #define CPU_ALL_NOGP(fn) \
  28. PIN_NOGP(CLKOUT, "B25", fn), \
  29. PIN_NOGP(CS0, "A20", fn), \
  30. PIN_NOGP(CS1_A26, "C20", fn)
  31. enum {
  32. PINMUX_RESERVED = 0,
  33. PINMUX_DATA_BEGIN,
  34. GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
  35. PINMUX_DATA_END,
  36. PINMUX_FUNCTION_BEGIN,
  37. GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
  38. /* GPSR0 */
  39. FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2,
  40. FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1,
  41. FN_A2, FN_A3, FN_IP0_15, FN_IP0_16,
  42. FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20,
  43. FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24,
  44. FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28,
  45. FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1,
  46. FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11,
  47. /* GPSR1 */
  48. FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25,
  49. FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6,
  50. FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17,
  51. FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2,
  52. FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13,
  53. FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24,
  54. FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30,
  55. FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4,
  56. /* GPSR2 */
  57. FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11,
  58. FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21,
  59. FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0,
  60. FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7,
  61. FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13,
  62. FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
  63. FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29,
  64. FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7,
  65. /* GPSR3 */
  66. FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10,
  67. FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16,
  68. FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22,
  69. FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30,
  70. FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6,
  71. FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  72. FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29,
  73. FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9,
  74. /* GPSR4 */
  75. FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19,
  76. FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0,
  77. FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12,
  78. FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24,
  79. FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6,
  80. FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19,
  81. FN_IP10_24_22, FN_AVS1, FN_AVS2,
  82. /* IPSR0 */
  83. FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0,
  84. FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B,
  85. FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C,
  86. FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A,
  87. FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A,
  88. FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0,
  89. FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5,
  90. FN_A6, FN_A7, FN_A8, FN_A9,
  91. FN_A10, FN_A11, FN_A12, FN_A13,
  92. FN_A14, FN_A15, FN_A16, FN_A17,
  93. FN_A18, FN_A19,
  94. /* IPSR1 */
  95. FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B,
  96. FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
  97. FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
  98. FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24,
  99. FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A,
  100. FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A,
  101. FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT,
  102. FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B,
  103. FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
  104. FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR,
  105. FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0,
  106. FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1,
  107. FN_MMC_D4,
  108. /* IPSR2 */
  109. FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2,
  110. FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3,
  111. FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4,
  112. FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A,
  113. FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A,
  114. FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0,
  115. FN_PWM0_C, FN_D0, FN_D1, FN_D2,
  116. FN_D3, FN_D4, FN_D5, FN_D6,
  117. FN_D7, FN_D8, FN_D9, FN_D10,
  118. FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK,
  119. FN_IRQ1_A,
  120. /* IPSR3 */
  121. FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
  122. FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
  123. FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B,
  124. FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A,
  125. FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A,
  126. FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
  127. FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B,
  128. FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0,
  129. FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2,
  130. FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4,
  131. FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3,
  132. FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
  133. FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3,
  134. FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5,
  135. FN_DU0_DR6, FN_LCDOUT6,
  136. /* IPSR4 */
  137. FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
  138. FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D,
  139. FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9,
  140. FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D,
  141. FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10,
  142. FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12,
  143. FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B,
  144. FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7,
  145. FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B,
  146. FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6,
  147. FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B,
  148. FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
  149. FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A,
  150. FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2,
  151. FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19,
  152. FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20,
  153. /* IPSR5 */
  154. FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B,
  155. FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B,
  156. FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN,
  157. FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK,
  158. FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A,
  159. FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
  160. FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
  161. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
  162. FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP,
  163. FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK,
  164. FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB,
  165. FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D,
  166. FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
  167. FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
  168. FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B,
  169. FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B,
  170. FN_RX2_A, FN_CAN0_RX_B,
  171. /* IPSR6 */
  172. FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B,
  173. FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B,
  174. FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5,
  175. FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5,
  176. FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8,
  177. FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9,
  178. FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
  179. FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
  180. FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12,
  181. FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13,
  182. FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
  183. FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0,
  184. FN_ARM_TRACEDATA_15,
  185. FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST,
  186. FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK,
  187. FN_SD0_DAT2, FN_SUB_TDI,
  188. /* IPSR7 */
  189. FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A,
  190. FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A,
  191. FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A,
  192. FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A,
  193. FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC,
  194. FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C,
  195. FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C,
  196. FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A,
  197. FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
  198. FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B,
  199. FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A,
  200. FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2,
  201. FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B,
  202. /* IPSR8 */
  203. FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
  204. FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0,
  205. FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1,
  206. FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2,
  207. FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3,
  208. FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4,
  209. FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5,
  210. FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B,
  211. FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A,
  212. FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
  213. FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4,
  214. FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B,
  215. FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B,
  216. /* IPSR9 */
  217. FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
  218. FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7,
  219. FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK,
  220. FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A,
  221. FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2,
  222. FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7,
  223. FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV,
  224. FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN,
  225. FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER,
  226. FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A,
  227. FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C,
  228. FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A,
  229. FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C,
  230. FN_RX2_D, FN_SCL2_C,
  231. /* IPSR10 */
  232. FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1,
  233. FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A,
  234. FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1,
  235. FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP,
  236. FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A,
  237. FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
  238. FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A,
  239. FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B,
  240. FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B,
  241. FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A,
  242. FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B,
  243. FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B,
  244. FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C,
  245. /* SEL */
  246. FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
  247. FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
  248. FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
  249. FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
  250. FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
  251. FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
  252. FN_SEL_SSI2_A, FN_SEL_SSI2_B,
  253. FN_SEL_SSI1_A, FN_SEL_SSI1_B,
  254. FN_SEL_VI1_A, FN_SEL_VI1_B,
  255. FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D,
  256. FN_SEL_SD2_A, FN_SEL_SD2_B,
  257. FN_SEL_SD1_A, FN_SEL_SD1_B,
  258. FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
  259. FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C,
  260. FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
  261. FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
  262. FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
  263. FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
  264. FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
  265. FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
  266. FN_SEL_CAN1_A, FN_SEL_CAN1_B,
  267. FN_SEL_CAN0_A, FN_SEL_CAN0_B,
  268. FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
  269. FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
  270. FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
  271. FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
  272. FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C,
  273. FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D,
  274. FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C,
  275. FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
  276. FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
  277. FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
  278. FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
  279. FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C,
  280. FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C,
  281. FN_SEL_I2C1_A, FN_SEL_I2C1_B,
  282. PINMUX_FUNCTION_END,
  283. PINMUX_MARK_BEGIN,
  284. /* GPSR0 */
  285. PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK,
  286. /* GPSR1 */
  287. WE0_MARK,
  288. /* GPSR2 */
  289. AUDIO_CLKA_MARK,
  290. AUDIO_CLKB_MARK,
  291. /* GPSR3 */
  292. SSI_SCK34_MARK,
  293. /* GPSR4 */
  294. AVS1_MARK,
  295. AVS2_MARK,
  296. VI0_R0_C_MARK, /* see sel_vi0 */
  297. VI0_R1_C_MARK, /* see sel_vi0 */
  298. VI0_R2_C_MARK, /* see sel_vi0 */
  299. /* VI0_R3_C_MARK, */
  300. VI0_R4_C_MARK, /* see sel_vi0 */
  301. VI0_R5_C_MARK, /* see sel_vi0 */
  302. VI0_R0_D_MARK, /* see sel_vi0 */
  303. VI0_R1_D_MARK, /* see sel_vi0 */
  304. VI0_R2_D_MARK, /* see sel_vi0 */
  305. VI0_R3_D_MARK, /* see sel_vi0 */
  306. VI0_R4_D_MARK, /* see sel_vi0 */
  307. VI0_R5_D_MARK, /* see sel_vi0 */
  308. /* IPSR0 */
  309. PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK,
  310. ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK,
  311. TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK,
  312. GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK,
  313. SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK,
  314. ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK,
  315. MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK,
  316. A4_MARK, A5_MARK, A6_MARK, A7_MARK,
  317. A8_MARK, A9_MARK, A10_MARK, A11_MARK,
  318. A12_MARK, A13_MARK, A14_MARK, A15_MARK,
  319. A16_MARK, A17_MARK, A18_MARK, A19_MARK,
  320. /* IPSR1 */
  321. A20_MARK, HSPI_CS1_B_MARK, A21_MARK,
  322. HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK,
  323. RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK,
  324. TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK,
  325. SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK,
  326. HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK,
  327. MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK,
  328. RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK,
  329. HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK,
  330. HSPI_RX1_B_MARK, SSI_SCK1_B_MARK,
  331. ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK,
  332. MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK,
  333. ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK,
  334. TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK,
  335. /* IPSR2 */
  336. SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK,
  337. SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK,
  338. SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK,
  339. EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK,
  340. MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK,
  341. DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK,
  342. DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK,
  343. D1_MARK, D2_MARK, D3_MARK, D4_MARK,
  344. D5_MARK, D6_MARK, D7_MARK, D8_MARK,
  345. D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK,
  346. IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK,
  347. /* IPSR3 */
  348. MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK,
  349. MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK,
  350. SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK,
  351. CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK,
  352. TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK,
  353. RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK,
  354. SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK,
  355. HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK,
  356. HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK,
  357. DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK,
  358. SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK,
  359. SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK,
  360. ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK,
  361. TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
  362. DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
  363. DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
  364. /* IPSR4 */
  365. DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
  366. AUDATA4_MARK, ARM_TRACEDATA_4_MARK,
  367. TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK,
  368. LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK,
  369. RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK,
  370. LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK,
  371. LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK,
  372. TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK,
  373. DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK,
  374. VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK,
  375. ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK,
  376. ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK,
  377. VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK,
  378. ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK,
  379. TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
  380. VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK,
  381. DU0_DB4_MARK, LCDOUT20_MARK,
  382. /* IPSR5 */
  383. VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK,
  384. DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK,
  385. DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK,
  386. QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
  387. QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK,
  388. AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK,
  389. DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
  390. DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
  391. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
  392. QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK,
  393. DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK,
  394. BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK,
  395. AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK,
  396. SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK,
  397. TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK,
  398. RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK,
  399. SSI_SCK2_A_MARK, HSPI_CS0_B_MARK,
  400. TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK,
  401. HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK,
  402. /* IPSR6 */
  403. SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK,
  404. CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK,
  405. BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK,
  406. HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK,
  407. RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK,
  408. RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK,
  409. SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
  410. SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK,
  411. SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK,
  412. TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
  413. SSI_SDATA2_MARK, HSPI_CS2_A_MARK,
  414. ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK,
  415. ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK,
  416. SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK,
  417. SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK,
  418. SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK,
  419. SD0_DAT2_MARK, SUB_TDI_MARK,
  420. /* IPSR7 */
  421. SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK,
  422. SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK,
  423. HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK,
  424. HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK,
  425. HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK,
  426. VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK,
  427. TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK,
  428. IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK,
  429. CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK,
  430. VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK,
  431. RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK,
  432. VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK,
  433. TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK,
  434. DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK,
  435. /* IPSR8 */
  436. VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK,
  437. HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK,
  438. DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK,
  439. DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK,
  440. DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK,
  441. DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK,
  442. DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK,
  443. DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK,
  444. VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK,
  445. PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK,
  446. RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK,
  447. DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK,
  448. VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK,
  449. /* IPSR9 */
  450. VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK,
  451. DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK,
  452. VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK,
  453. VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK,
  454. VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK,
  455. PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK,
  456. DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK,
  457. ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK,
  458. VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK,
  459. TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK,
  460. IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK,
  461. DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK,
  462. BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK,
  463. DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK,
  464. RX2_D_MARK, SCL2_C_MARK,
  465. /* IPSR10 */
  466. SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK,
  467. ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK,
  468. DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK,
  469. ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK,
  470. DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK,
  471. CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK,
  472. ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK,
  473. PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK,
  474. DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK,
  475. GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK,
  476. DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK,
  477. GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK,
  478. EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK,
  479. REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK,
  480. EX_WAIT2_B_MARK, DACK0_B_MARK,
  481. HSPI_TX2_B_MARK, CAN_CLK_C_MARK,
  482. PINMUX_MARK_END,
  483. };
  484. static const u16 pinmux_data[] = {
  485. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  486. PINMUX_SINGLE(PENC0),
  487. PINMUX_SINGLE(PENC1),
  488. PINMUX_SINGLE(A1),
  489. PINMUX_SINGLE(A2),
  490. PINMUX_SINGLE(A3),
  491. PINMUX_SINGLE(WE0),
  492. PINMUX_SINGLE(AUDIO_CLKA),
  493. PINMUX_SINGLE(AUDIO_CLKB),
  494. PINMUX_SINGLE(SSI_SCK34),
  495. PINMUX_SINGLE(AVS1),
  496. PINMUX_SINGLE(AVS2),
  497. /* IPSR0 */
  498. PINMUX_IPSR_GPSR(IP0_1_0, PRESETOUT),
  499. PINMUX_IPSR_GPSR(IP0_1_0, PWM1),
  500. PINMUX_IPSR_GPSR(IP0_4_2, AUDATA0),
  501. PINMUX_IPSR_GPSR(IP0_4_2, ARM_TRACEDATA_0),
  502. PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C),
  503. PINMUX_IPSR_GPSR(IP0_4_2, USB_OVC0),
  504. PINMUX_IPSR_GPSR(IP0_4_2, TX2_E),
  505. PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B),
  506. PINMUX_IPSR_GPSR(IP0_7_5, AUDATA1),
  507. PINMUX_IPSR_GPSR(IP0_7_5, ARM_TRACEDATA_1),
  508. PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C),
  509. PINMUX_IPSR_GPSR(IP0_7_5, USB_OVC1),
  510. PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E),
  511. PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B),
  512. PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A),
  513. PINMUX_IPSR_GPSR(IP0_11_8, MMC_D2),
  514. PINMUX_IPSR_GPSR(IP0_11_8, BS),
  515. PINMUX_IPSR_GPSR(IP0_11_8, ATADIR0_A),
  516. PINMUX_IPSR_GPSR(IP0_11_8, SDSELF_A),
  517. PINMUX_IPSR_GPSR(IP0_11_8, PWM4_B),
  518. PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A),
  519. PINMUX_IPSR_GPSR(IP0_14_12, MMC_D3),
  520. PINMUX_IPSR_GPSR(IP0_14_12, A0),
  521. PINMUX_IPSR_GPSR(IP0_14_12, ATAG0_A),
  522. PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B),
  523. PINMUX_IPSR_GPSR(IP0_15, A4),
  524. PINMUX_IPSR_GPSR(IP0_16, A5),
  525. PINMUX_IPSR_GPSR(IP0_17, A6),
  526. PINMUX_IPSR_GPSR(IP0_18, A7),
  527. PINMUX_IPSR_GPSR(IP0_19, A8),
  528. PINMUX_IPSR_GPSR(IP0_20, A9),
  529. PINMUX_IPSR_GPSR(IP0_21, A10),
  530. PINMUX_IPSR_GPSR(IP0_22, A11),
  531. PINMUX_IPSR_GPSR(IP0_23, A12),
  532. PINMUX_IPSR_GPSR(IP0_24, A13),
  533. PINMUX_IPSR_GPSR(IP0_25, A14),
  534. PINMUX_IPSR_GPSR(IP0_26, A15),
  535. PINMUX_IPSR_GPSR(IP0_27, A16),
  536. PINMUX_IPSR_GPSR(IP0_28, A17),
  537. PINMUX_IPSR_GPSR(IP0_29, A18),
  538. PINMUX_IPSR_GPSR(IP0_30, A19),
  539. /* IPSR1 */
  540. PINMUX_IPSR_GPSR(IP1_0, A20),
  541. PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B),
  542. PINMUX_IPSR_GPSR(IP1_1, A21),
  543. PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B),
  544. PINMUX_IPSR_GPSR(IP1_4_2, A22),
  545. PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B),
  546. PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B),
  547. PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A),
  548. PINMUX_IPSR_GPSR(IP1_7_5, A23),
  549. PINMUX_IPSR_GPSR(IP1_7_5, HTX0_B),
  550. PINMUX_IPSR_GPSR(IP1_7_5, TX2_B),
  551. PINMUX_IPSR_GPSR(IP1_7_5, DACK2_A),
  552. PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A),
  553. PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A),
  554. PINMUX_IPSR_GPSR(IP1_10_8, MMC_D6),
  555. PINMUX_IPSR_GPSR(IP1_10_8, A24),
  556. PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A),
  557. PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B),
  558. PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A),
  559. PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A),
  560. PINMUX_IPSR_GPSR(IP1_14_11, MMC_D7),
  561. PINMUX_IPSR_GPSR(IP1_14_11, A25),
  562. PINMUX_IPSR_GPSR(IP1_14_11, DACK1_A),
  563. PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B),
  564. PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C),
  565. PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A),
  566. PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT),
  567. PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B),
  568. PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B),
  569. PINMUX_IPSR_NOGP(IP1_17, CS0),
  570. PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B),
  571. PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B),
  572. PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B),
  573. PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26),
  574. PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A),
  575. PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B),
  576. PINMUX_IPSR_GPSR(IP1_23_21, MMC_D5),
  577. PINMUX_IPSR_GPSR(IP1_23_21, ATADIR0_B),
  578. PINMUX_IPSR_GPSR(IP1_23_21, RD_WR),
  579. PINMUX_IPSR_GPSR(IP1_24, WE1),
  580. PINMUX_IPSR_GPSR(IP1_24, ATAWR0_B),
  581. PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B),
  582. PINMUX_IPSR_GPSR(IP1_27_25, EX_CS0),
  583. PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A),
  584. PINMUX_IPSR_GPSR(IP1_27_25, TX3_C),
  585. PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A),
  586. PINMUX_IPSR_GPSR(IP1_29_28, EX_CS1),
  587. PINMUX_IPSR_GPSR(IP1_29_28, MMC_D4),
  588. /* IPSR2 */
  589. PINMUX_IPSR_GPSR(IP2_2_0, SD1_CLK_A),
  590. PINMUX_IPSR_GPSR(IP2_2_0, MMC_CLK),
  591. PINMUX_IPSR_GPSR(IP2_2_0, ATACS00),
  592. PINMUX_IPSR_GPSR(IP2_2_0, EX_CS2),
  593. PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A),
  594. PINMUX_IPSR_GPSR(IP2_5_3, MMC_CMD),
  595. PINMUX_IPSR_GPSR(IP2_5_3, ATACS10),
  596. PINMUX_IPSR_GPSR(IP2_5_3, EX_CS3),
  597. PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A),
  598. PINMUX_IPSR_GPSR(IP2_8_6, MMC_D0),
  599. PINMUX_IPSR_GPSR(IP2_8_6, ATARD0),
  600. PINMUX_IPSR_GPSR(IP2_8_6, EX_CS4),
  601. PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A),
  602. PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A),
  603. PINMUX_IPSR_GPSR(IP2_11_9, MMC_D1),
  604. PINMUX_IPSR_GPSR(IP2_11_9, ATAWR0_A),
  605. PINMUX_IPSR_GPSR(IP2_11_9, EX_CS5),
  606. PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A),
  607. PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A),
  608. PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A),
  609. PINMUX_IPSR_GPSR(IP2_16_14, DACK0),
  610. PINMUX_IPSR_GPSR(IP2_16_14, TX3_A),
  611. PINMUX_IPSR_GPSR(IP2_16_14, DRACK0),
  612. PINMUX_IPSR_GPSR(IP2_17, EX_WAIT0),
  613. PINMUX_IPSR_GPSR(IP2_17, PWM0_C),
  614. PINMUX_IPSR_NOGP(IP2_18, D0),
  615. PINMUX_IPSR_NOGP(IP2_19, D1),
  616. PINMUX_IPSR_NOGP(IP2_20, D2),
  617. PINMUX_IPSR_NOGP(IP2_21, D3),
  618. PINMUX_IPSR_NOGP(IP2_22, D4),
  619. PINMUX_IPSR_NOGP(IP2_23, D5),
  620. PINMUX_IPSR_NOGP(IP2_24, D6),
  621. PINMUX_IPSR_NOGP(IP2_25, D7),
  622. PINMUX_IPSR_NOGP(IP2_26, D8),
  623. PINMUX_IPSR_NOGP(IP2_27, D9),
  624. PINMUX_IPSR_NOGP(IP2_28, D10),
  625. PINMUX_IPSR_NOGP(IP2_29, D11),
  626. PINMUX_IPSR_GPSR(IP2_30, RD_WR_B),
  627. PINMUX_IPSR_GPSR(IP2_30, IRQ0),
  628. PINMUX_IPSR_GPSR(IP2_31, MLB_CLK),
  629. PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A),
  630. /* IPSR3 */
  631. PINMUX_IPSR_GPSR(IP3_1_0, MLB_SIG),
  632. PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B),
  633. PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A),
  634. PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A),
  635. PINMUX_IPSR_GPSR(IP3_4_2, MLB_DAT),
  636. PINMUX_IPSR_GPSR(IP3_4_2, TX5_B),
  637. PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A),
  638. PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A),
  639. PINMUX_IPSR_GPSR(IP3_4_2, SDSELF_B),
  640. PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B),
  641. PINMUX_IPSR_GPSR(IP3_7_5, SCIF_CLK),
  642. PINMUX_IPSR_GPSR(IP3_7_5, AUDIO_CLKOUT_B),
  643. PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B),
  644. PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B),
  645. PINMUX_IPSR_GPSR(IP3_9_8, SD1_CLK_B),
  646. PINMUX_IPSR_GPSR(IP3_9_8, HTX0_A),
  647. PINMUX_IPSR_GPSR(IP3_9_8, TX0_A),
  648. PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B),
  649. PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A),
  650. PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A),
  651. PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B),
  652. PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A),
  653. PINMUX_IPSR_GPSR(IP3_15_13, SCK0),
  654. PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B),
  655. PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B),
  656. PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A),
  657. PINMUX_IPSR_GPSR(IP3_18_16, CTS0),
  658. PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B),
  659. PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A),
  660. PINMUX_IPSR_GPSR(IP3_20_19, RTS0),
  661. PINMUX_IPSR_GPSR(IP3_23_21, SSI_SCK4),
  662. PINMUX_IPSR_GPSR(IP3_23_21, DU0_DR0),
  663. PINMUX_IPSR_GPSR(IP3_23_21, LCDOUT0),
  664. PINMUX_IPSR_GPSR(IP3_23_21, AUDATA2),
  665. PINMUX_IPSR_GPSR(IP3_23_21, ARM_TRACEDATA_2),
  666. PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C),
  667. PINMUX_IPSR_GPSR(IP3_23_21, ADICHS1),
  668. PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B),
  669. PINMUX_IPSR_GPSR(IP3_26_24, SSI_WS4),
  670. PINMUX_IPSR_GPSR(IP3_26_24, DU0_DR1),
  671. PINMUX_IPSR_GPSR(IP3_26_24, LCDOUT1),
  672. PINMUX_IPSR_GPSR(IP3_26_24, AUDATA3),
  673. PINMUX_IPSR_GPSR(IP3_26_24, ARM_TRACEDATA_3),
  674. PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C),
  675. PINMUX_IPSR_GPSR(IP3_26_24, ADICHS2),
  676. PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B),
  677. PINMUX_IPSR_GPSR(IP3_27, DU0_DR2),
  678. PINMUX_IPSR_GPSR(IP3_27, LCDOUT2),
  679. PINMUX_IPSR_GPSR(IP3_28, DU0_DR3),
  680. PINMUX_IPSR_GPSR(IP3_28, LCDOUT3),
  681. PINMUX_IPSR_GPSR(IP3_29, DU0_DR4),
  682. PINMUX_IPSR_GPSR(IP3_29, LCDOUT4),
  683. PINMUX_IPSR_GPSR(IP3_30, DU0_DR5),
  684. PINMUX_IPSR_GPSR(IP3_30, LCDOUT5),
  685. PINMUX_IPSR_GPSR(IP3_31, DU0_DR6),
  686. PINMUX_IPSR_GPSR(IP3_31, LCDOUT6),
  687. /* IPSR4 */
  688. PINMUX_IPSR_GPSR(IP4_0, DU0_DR7),
  689. PINMUX_IPSR_GPSR(IP4_0, LCDOUT7),
  690. PINMUX_IPSR_GPSR(IP4_3_1, DU0_DG0),
  691. PINMUX_IPSR_GPSR(IP4_3_1, LCDOUT8),
  692. PINMUX_IPSR_GPSR(IP4_3_1, AUDATA4),
  693. PINMUX_IPSR_GPSR(IP4_3_1, ARM_TRACEDATA_4),
  694. PINMUX_IPSR_GPSR(IP4_3_1, TX1_D),
  695. PINMUX_IPSR_GPSR(IP4_3_1, CAN0_TX_A),
  696. PINMUX_IPSR_GPSR(IP4_3_1, ADICHS0),
  697. PINMUX_IPSR_GPSR(IP4_6_4, DU0_DG1),
  698. PINMUX_IPSR_GPSR(IP4_6_4, LCDOUT9),
  699. PINMUX_IPSR_GPSR(IP4_6_4, AUDATA5),
  700. PINMUX_IPSR_GPSR(IP4_6_4, ARM_TRACEDATA_5),
  701. PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D),
  702. PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A),
  703. PINMUX_IPSR_GPSR(IP4_6_4, ADIDATA),
  704. PINMUX_IPSR_GPSR(IP4_7, DU0_DG2),
  705. PINMUX_IPSR_GPSR(IP4_7, LCDOUT10),
  706. PINMUX_IPSR_GPSR(IP4_8, DU0_DG3),
  707. PINMUX_IPSR_GPSR(IP4_8, LCDOUT11),
  708. PINMUX_IPSR_GPSR(IP4_10_9, DU0_DG4),
  709. PINMUX_IPSR_GPSR(IP4_10_9, LCDOUT12),
  710. PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B),
  711. PINMUX_IPSR_GPSR(IP4_12_11, DU0_DG5),
  712. PINMUX_IPSR_GPSR(IP4_12_11, LCDOUT13),
  713. PINMUX_IPSR_GPSR(IP4_12_11, TX0_B),
  714. PINMUX_IPSR_GPSR(IP4_14_13, DU0_DG6),
  715. PINMUX_IPSR_GPSR(IP4_14_13, LCDOUT14),
  716. PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A),
  717. PINMUX_IPSR_GPSR(IP4_16_15, DU0_DG7),
  718. PINMUX_IPSR_GPSR(IP4_16_15, LCDOUT15),
  719. PINMUX_IPSR_GPSR(IP4_16_15, TX4_A),
  720. PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B),
  721. PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */
  722. PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */
  723. PINMUX_IPSR_GPSR(IP4_20_17, DU0_DB0),
  724. PINMUX_IPSR_GPSR(IP4_20_17, LCDOUT16),
  725. PINMUX_IPSR_GPSR(IP4_20_17, AUDATA6),
  726. PINMUX_IPSR_GPSR(IP4_20_17, ARM_TRACEDATA_6),
  727. PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A),
  728. PINMUX_IPSR_GPSR(IP4_20_17, PWM0_A),
  729. PINMUX_IPSR_GPSR(IP4_20_17, ADICLK),
  730. PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B),
  731. PINMUX_IPSR_GPSR(IP4_24_21, AUDIO_CLKC),
  732. PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */
  733. PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */
  734. PINMUX_IPSR_GPSR(IP4_24_21, DU0_DB1),
  735. PINMUX_IPSR_GPSR(IP4_24_21, LCDOUT17),
  736. PINMUX_IPSR_GPSR(IP4_24_21, AUDATA7),
  737. PINMUX_IPSR_GPSR(IP4_24_21, ARM_TRACEDATA_7),
  738. PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A),
  739. PINMUX_IPSR_GPSR(IP4_24_21, ADICS_SAMP),
  740. PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B),
  741. PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */
  742. PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */
  743. PINMUX_IPSR_GPSR(IP4_26_25, DU0_DB2),
  744. PINMUX_IPSR_GPSR(IP4_26_25, LCDOUT18),
  745. PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B),
  746. PINMUX_IPSR_GPSR(IP4_28_27, DU0_DB3),
  747. PINMUX_IPSR_GPSR(IP4_28_27, LCDOUT19),
  748. PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */
  749. PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */
  750. PINMUX_IPSR_GPSR(IP4_30_29, DU0_DB4),
  751. PINMUX_IPSR_GPSR(IP4_30_29, LCDOUT20),
  752. /* IPSR5 */
  753. PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */
  754. PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */
  755. PINMUX_IPSR_GPSR(IP5_1_0, DU0_DB5),
  756. PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT21),
  757. PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B),
  758. PINMUX_IPSR_GPSR(IP5_3_2, DU0_DB6),
  759. PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT22),
  760. PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B),
  761. PINMUX_IPSR_GPSR(IP5_5_4, DU0_DB7),
  762. PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT23),
  763. PINMUX_IPSR_GPSR(IP5_6, DU0_DOTCLKIN),
  764. PINMUX_IPSR_GPSR(IP5_6, QSTVA_QVS),
  765. PINMUX_IPSR_GPSR(IP5_7, DU0_DOTCLKO_UT0),
  766. PINMUX_IPSR_GPSR(IP5_7, QCLK),
  767. PINMUX_IPSR_GPSR(IP5_9_8, DU0_DOTCLKO_UT1),
  768. PINMUX_IPSR_GPSR(IP5_9_8, QSTVB_QVE),
  769. PINMUX_IPSR_GPSR(IP5_9_8, AUDIO_CLKOUT_A),
  770. PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C),
  771. PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B),
  772. PINMUX_IPSR_GPSR(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC),
  773. PINMUX_IPSR_GPSR(IP5_11_10, QSTH_QHS),
  774. PINMUX_IPSR_GPSR(IP5_12, DU0_EXVSYNC_DU0_VSYNC),
  775. PINMUX_IPSR_GPSR(IP5_12, QSTB_QHE),
  776. PINMUX_IPSR_GPSR(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE),
  777. PINMUX_IPSR_GPSR(IP5_14_13, QCPV_QDE),
  778. PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D),
  779. PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A),
  780. PINMUX_IPSR_GPSR(IP5_17_15, DU0_DISP),
  781. PINMUX_IPSR_GPSR(IP5_17_15, QPOLA),
  782. PINMUX_IPSR_GPSR(IP5_17_15, AUDCK),
  783. PINMUX_IPSR_GPSR(IP5_17_15, ARM_TRACECLK),
  784. PINMUX_IPSR_GPSR(IP5_17_15, BPFCLK_D),
  785. PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A),
  786. PINMUX_IPSR_GPSR(IP5_20_18, DU0_CDE),
  787. PINMUX_IPSR_GPSR(IP5_20_18, QPOLB),
  788. PINMUX_IPSR_GPSR(IP5_20_18, AUDSYNC),
  789. PINMUX_IPSR_GPSR(IP5_20_18, ARM_TRACECTL),
  790. PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D),
  791. PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B),
  792. PINMUX_IPSR_GPSR(IP5_22_21, SSI_SCK78),
  793. PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B),
  794. PINMUX_IPSR_GPSR(IP5_22_21, TX1_B),
  795. PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B),
  796. PINMUX_IPSR_GPSR(IP5_25_23, SSI_WS78),
  797. PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B),
  798. PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B),
  799. PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D),
  800. PINMUX_IPSR_GPSR(IP5_28_26, SSI_SDATA8),
  801. PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A),
  802. PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B),
  803. PINMUX_IPSR_GPSR(IP5_28_26, TX2_A),
  804. PINMUX_IPSR_GPSR(IP5_28_26, CAN0_TX_B),
  805. PINMUX_IPSR_GPSR(IP5_30_29, SSI_SDATA7),
  806. PINMUX_IPSR_GPSR(IP5_30_29, HSPI_TX0_B),
  807. PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A),
  808. PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B),
  809. /* IPSR6 */
  810. PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK6),
  811. PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A),
  812. PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B),
  813. PINMUX_IPSR_GPSR(IP6_1_0, CAN1_TX_B),
  814. PINMUX_IPSR_GPSR(IP6_4_2, SSI_WS6),
  815. PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A),
  816. PINMUX_IPSR_GPSR(IP6_4_2, BPFCLK_B),
  817. PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B),
  818. PINMUX_IPSR_GPSR(IP6_6_5, SSI_SDATA6),
  819. PINMUX_IPSR_GPSR(IP6_6_5, HSPI_TX2_A),
  820. PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B),
  821. PINMUX_IPSR_GPSR(IP6_7, SSI_SCK5),
  822. PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C),
  823. PINMUX_IPSR_GPSR(IP6_8, SSI_WS5),
  824. PINMUX_IPSR_GPSR(IP6_8, TX4_C),
  825. PINMUX_IPSR_GPSR(IP6_9, SSI_SDATA5),
  826. PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D),
  827. PINMUX_IPSR_GPSR(IP6_10, SSI_WS34),
  828. PINMUX_IPSR_GPSR(IP6_10, ARM_TRACEDATA_8),
  829. PINMUX_IPSR_GPSR(IP6_12_11, SSI_SDATA4),
  830. PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A),
  831. PINMUX_IPSR_GPSR(IP6_12_11, ARM_TRACEDATA_9),
  832. PINMUX_IPSR_GPSR(IP6_13, SSI_SDATA3),
  833. PINMUX_IPSR_GPSR(IP6_13, ARM_TRACEDATA_10),
  834. PINMUX_IPSR_GPSR(IP6_15_14, SSI_SCK012),
  835. PINMUX_IPSR_GPSR(IP6_15_14, ARM_TRACEDATA_11),
  836. PINMUX_IPSR_GPSR(IP6_15_14, TX0_D),
  837. PINMUX_IPSR_GPSR(IP6_16, SSI_WS012),
  838. PINMUX_IPSR_GPSR(IP6_16, ARM_TRACEDATA_12),
  839. PINMUX_IPSR_GPSR(IP6_18_17, SSI_SDATA2),
  840. PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A),
  841. PINMUX_IPSR_GPSR(IP6_18_17, ARM_TRACEDATA_13),
  842. PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A),
  843. PINMUX_IPSR_GPSR(IP6_20_19, SSI_SDATA1),
  844. PINMUX_IPSR_GPSR(IP6_20_19, ARM_TRACEDATA_14),
  845. PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A),
  846. PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A),
  847. PINMUX_IPSR_GPSR(IP6_21, SSI_SDATA0),
  848. PINMUX_IPSR_GPSR(IP6_21, ARM_TRACEDATA_15),
  849. PINMUX_IPSR_GPSR(IP6_23_22, SD0_CLK),
  850. PINMUX_IPSR_GPSR(IP6_23_22, SUB_TDO),
  851. PINMUX_IPSR_GPSR(IP6_25_24, SD0_CMD),
  852. PINMUX_IPSR_GPSR(IP6_25_24, SUB_TRST),
  853. PINMUX_IPSR_GPSR(IP6_27_26, SD0_DAT0),
  854. PINMUX_IPSR_GPSR(IP6_27_26, SUB_TMS),
  855. PINMUX_IPSR_GPSR(IP6_29_28, SD0_DAT1),
  856. PINMUX_IPSR_GPSR(IP6_29_28, SUB_TCK),
  857. PINMUX_IPSR_GPSR(IP6_31_30, SD0_DAT2),
  858. PINMUX_IPSR_GPSR(IP6_31_30, SUB_TDI),
  859. /* IPSR7 */
  860. PINMUX_IPSR_GPSR(IP7_1_0, SD0_DAT3),
  861. PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B),
  862. PINMUX_IPSR_GPSR(IP7_3_2, SD0_CD),
  863. PINMUX_IPSR_GPSR(IP7_3_2, TX5_A),
  864. PINMUX_IPSR_GPSR(IP7_5_4, SD0_WP),
  865. PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A),
  866. PINMUX_IPSR_GPSR(IP7_8_6, VI1_CLKENB),
  867. PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A),
  868. PINMUX_IPSR_GPSR(IP7_8_6, HTX1_A),
  869. PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C),
  870. PINMUX_IPSR_GPSR(IP7_11_9, VI1_FIELD),
  871. PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A),
  872. PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A),
  873. PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C),
  874. PINMUX_IPSR_GPSR(IP7_14_12, VI1_HSYNC),
  875. PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A),
  876. PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A),
  877. PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A),
  878. PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C),
  879. PINMUX_IPSR_GPSR(IP7_17_15, VI1_VSYNC),
  880. PINMUX_IPSR_GPSR(IP7_17_15, HSPI_TX0),
  881. PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A),
  882. PINMUX_IPSR_GPSR(IP7_17_15, BPFCLK_A),
  883. PINMUX_IPSR_GPSR(IP7_17_15, TX1_C),
  884. PINMUX_IPSR_GPSR(IP7_20_18, TCLK0),
  885. PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A),
  886. PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A),
  887. PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C),
  888. PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C),
  889. PINMUX_IPSR_GPSR(IP7_20_18, SPEEDIN),
  890. PINMUX_IPSR_GPSR(IP7_21, VI0_CLK),
  891. PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A),
  892. PINMUX_IPSR_GPSR(IP7_24_22, VI0_CLKENB),
  893. PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B),
  894. PINMUX_IPSR_GPSR(IP7_24_22, VI1_DATA0),
  895. PINMUX_IPSR_GPSR(IP7_24_22, DU1_DG6),
  896. PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A),
  897. PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B),
  898. PINMUX_IPSR_GPSR(IP7_28_25, VI0_FIELD),
  899. PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B),
  900. PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */
  901. PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */
  902. PINMUX_IPSR_GPSR(IP7_28_25, VI1_DATA1),
  903. PINMUX_IPSR_GPSR(IP7_28_25, DU1_DG7),
  904. PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A),
  905. PINMUX_IPSR_GPSR(IP7_28_25, TX4_B),
  906. PINMUX_IPSR_GPSR(IP7_31_29, VI0_HSYNC),
  907. PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B),
  908. PINMUX_IPSR_GPSR(IP7_31_29, VI1_DATA2),
  909. PINMUX_IPSR_GPSR(IP7_31_29, DU1_DR2),
  910. PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A),
  911. PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B),
  912. /* IPSR8 */
  913. PINMUX_IPSR_GPSR(IP8_2_0, VI0_VSYNC),
  914. PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B),
  915. PINMUX_IPSR_GPSR(IP8_2_0, VI1_DATA3),
  916. PINMUX_IPSR_GPSR(IP8_2_0, DU1_DR3),
  917. PINMUX_IPSR_GPSR(IP8_2_0, HSPI_TX1_A),
  918. PINMUX_IPSR_GPSR(IP8_2_0, TX3_B),
  919. PINMUX_IPSR_GPSR(IP8_5_3, VI0_DATA0_VI0_B0),
  920. PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG2),
  921. PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B),
  922. PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D),
  923. PINMUX_IPSR_GPSR(IP8_8_6, VI0_DATA1_VI0_B1),
  924. PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG3),
  925. PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B),
  926. PINMUX_IPSR_GPSR(IP8_8_6, TX3_D),
  927. PINMUX_IPSR_GPSR(IP8_10_9, VI0_DATA2_VI0_B2),
  928. PINMUX_IPSR_GPSR(IP8_10_9, DU1_DG4),
  929. PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C),
  930. PINMUX_IPSR_GPSR(IP8_13_11, VI0_DATA3_VI0_B3),
  931. PINMUX_IPSR_GPSR(IP8_13_11, DU1_DG5),
  932. PINMUX_IPSR_GPSR(IP8_13_11, TX1_A),
  933. PINMUX_IPSR_GPSR(IP8_13_11, TX0_C),
  934. PINMUX_IPSR_GPSR(IP8_15_14, VI0_DATA4_VI0_B4),
  935. PINMUX_IPSR_GPSR(IP8_15_14, DU1_DB2),
  936. PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A),
  937. PINMUX_IPSR_GPSR(IP8_18_16, VI0_DATA5_VI0_B5),
  938. PINMUX_IPSR_GPSR(IP8_18_16, DU1_DB3),
  939. PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A),
  940. PINMUX_IPSR_GPSR(IP8_18_16, PWM4),
  941. PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B),
  942. PINMUX_IPSR_GPSR(IP8_21_19, VI0_DATA6_VI0_G0),
  943. PINMUX_IPSR_GPSR(IP8_21_19, DU1_DB4),
  944. PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A),
  945. PINMUX_IPSR_GPSR(IP8_21_19, PWM5),
  946. PINMUX_IPSR_GPSR(IP8_23_22, VI0_DATA7_VI0_G1),
  947. PINMUX_IPSR_GPSR(IP8_23_22, DU1_DB5),
  948. PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A),
  949. PINMUX_IPSR_GPSR(IP8_26_24, VI0_G2),
  950. PINMUX_IPSR_GPSR(IP8_26_24, SD2_CLK_B),
  951. PINMUX_IPSR_GPSR(IP8_26_24, VI1_DATA4),
  952. PINMUX_IPSR_GPSR(IP8_26_24, DU1_DR4),
  953. PINMUX_IPSR_GPSR(IP8_26_24, HTX1_B),
  954. PINMUX_IPSR_GPSR(IP8_29_27, VI0_G3),
  955. PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B),
  956. PINMUX_IPSR_GPSR(IP8_29_27, VI1_DATA5),
  957. PINMUX_IPSR_GPSR(IP8_29_27, DU1_DR5),
  958. PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B),
  959. /* IPSR9 */
  960. PINMUX_IPSR_GPSR(IP9_2_0, VI0_G4),
  961. PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B),
  962. PINMUX_IPSR_GPSR(IP9_2_0, VI1_DATA6),
  963. PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR6),
  964. PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B),
  965. PINMUX_IPSR_GPSR(IP9_5_3, VI0_G5),
  966. PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B),
  967. PINMUX_IPSR_GPSR(IP9_5_3, VI1_DATA7),
  968. PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR7),
  969. PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B),
  970. PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */
  971. PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */
  972. PINMUX_IPSR_GPSR(IP9_8_6, VI1_CLK),
  973. PINMUX_IPSR_GPSR(IP9_8_6, ETH_REF_CLK),
  974. PINMUX_IPSR_GPSR(IP9_8_6, DU1_DOTCLKIN),
  975. PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */
  976. PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */
  977. PINMUX_IPSR_GPSR(IP9_11_9, VI1_DATA8),
  978. PINMUX_IPSR_GPSR(IP9_11_9, DU1_DB6),
  979. PINMUX_IPSR_GPSR(IP9_11_9, ETH_TXD0),
  980. PINMUX_IPSR_GPSR(IP9_11_9, PWM2),
  981. PINMUX_IPSR_GPSR(IP9_11_9, TCLK1),
  982. PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */
  983. PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */
  984. PINMUX_IPSR_GPSR(IP9_14_12, VI1_DATA9),
  985. PINMUX_IPSR_GPSR(IP9_14_12, DU1_DB7),
  986. PINMUX_IPSR_GPSR(IP9_14_12, ETH_TXD1),
  987. PINMUX_IPSR_GPSR(IP9_14_12, PWM3),
  988. PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A),
  989. PINMUX_IPSR_GPSR(IP9_17_15, ETH_CRS_DV),
  990. PINMUX_IPSR_GPSR(IP9_17_15, IECLK),
  991. PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C),
  992. PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */
  993. PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */
  994. PINMUX_IPSR_GPSR(IP9_20_18, ETH_TX_EN),
  995. PINMUX_IPSR_GPSR(IP9_20_18, IETX),
  996. PINMUX_IPSR_GPSR(IP9_20_18, TX2_C),
  997. PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */
  998. PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */
  999. PINMUX_IPSR_GPSR(IP9_23_21, ETH_RX_ER),
  1000. PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C),
  1001. PINMUX_IPSR_GPSR(IP9_23_21, IERX),
  1002. PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C),
  1003. PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A),
  1004. PINMUX_IPSR_GPSR(IP9_26_24, DU1_DOTCLKOUT),
  1005. PINMUX_IPSR_GPSR(IP9_26_24, ETH_RXD0),
  1006. PINMUX_IPSR_GPSR(IP9_26_24, BPFCLK_C),
  1007. PINMUX_IPSR_GPSR(IP9_26_24, TX2_D),
  1008. PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C),
  1009. PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A),
  1010. PINMUX_IPSR_GPSR(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC),
  1011. PINMUX_IPSR_GPSR(IP9_29_27, ETH_RXD1),
  1012. PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C),
  1013. PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D),
  1014. PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C),
  1015. /* IPSR10 */
  1016. PINMUX_IPSR_GPSR(IP10_2_0, SD2_CLK_A),
  1017. PINMUX_IPSR_GPSR(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC),
  1018. PINMUX_IPSR_GPSR(IP10_2_0, ATARD1),
  1019. PINMUX_IPSR_GPSR(IP10_2_0, ETH_MDC),
  1020. PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B),
  1021. PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A),
  1022. PINMUX_IPSR_GPSR(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE),
  1023. PINMUX_IPSR_GPSR(IP10_5_3, ATAWR1),
  1024. PINMUX_IPSR_GPSR(IP10_5_3, ETH_MDIO),
  1025. PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B),
  1026. PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A),
  1027. PINMUX_IPSR_GPSR(IP10_8_6, DU1_DISP),
  1028. PINMUX_IPSR_GPSR(IP10_8_6, ATACS01),
  1029. PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B),
  1030. PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
  1031. PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A),
  1032. PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A),
  1033. PINMUX_IPSR_GPSR(IP10_12_9, DU1_CDE),
  1034. PINMUX_IPSR_GPSR(IP10_12_9, ATACS11),
  1035. PINMUX_IPSR_GPSR(IP10_12_9, DACK1_B),
  1036. PINMUX_IPSR_GPSR(IP10_12_9, ETH_MAGIC),
  1037. PINMUX_IPSR_GPSR(IP10_12_9, CAN1_TX_A),
  1038. PINMUX_IPSR_GPSR(IP10_12_9, PWM6),
  1039. PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A),
  1040. PINMUX_IPSR_GPSR(IP10_15_13, VI1_DATA12),
  1041. PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B),
  1042. PINMUX_IPSR_GPSR(IP10_15_13, ATADIR1),
  1043. PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B),
  1044. PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B),
  1045. PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A),
  1046. PINMUX_IPSR_GPSR(IP10_18_16, VI1_DATA13),
  1047. PINMUX_IPSR_GPSR(IP10_18_16, DACK2_B),
  1048. PINMUX_IPSR_GPSR(IP10_18_16, ATAG1),
  1049. PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B),
  1050. PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B),
  1051. PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A),
  1052. PINMUX_IPSR_GPSR(IP10_21_19, VI1_DATA14),
  1053. PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B),
  1054. PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B),
  1055. PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B),
  1056. PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A),
  1057. PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A),
  1058. PINMUX_IPSR_GPSR(IP10_24_22, VI1_DATA15),
  1059. PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B),
  1060. PINMUX_IPSR_GPSR(IP10_24_22, DACK0_B),
  1061. PINMUX_IPSR_GPSR(IP10_24_22, HSPI_TX2_B),
  1062. PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
  1063. };
  1064. /*
  1065. * Pins not associated with a GPIO port.
  1066. */
  1067. enum {
  1068. GP_ASSIGN_LAST(),
  1069. NOGP_ALL(),
  1070. };
  1071. static const struct sh_pfc_pin pinmux_pins[] = {
  1072. PINMUX_GPIO_GP_ALL(),
  1073. PINMUX_NOGP_ALL(),
  1074. };
  1075. /* - macro */
  1076. #define SH_PFC_PINS(name, args...) \
  1077. static const unsigned int name ##_pins[] = { args }
  1078. #define SH_PFC_MUX1(name, arg1) \
  1079. static const unsigned int name ##_mux[] = { arg1##_MARK }
  1080. #define SH_PFC_MUX2(name, arg1, arg2) \
  1081. static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, }
  1082. #define SH_PFC_MUX3(name, arg1, arg2, arg3) \
  1083. static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
  1084. arg3##_MARK }
  1085. #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \
  1086. static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
  1087. arg3##_MARK, arg4##_MARK }
  1088. #define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
  1089. static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
  1090. arg3##_MARK, arg4##_MARK, \
  1091. arg5##_MARK, arg6##_MARK, \
  1092. arg7##_MARK, arg8##_MARK, }
  1093. /* - AUDIO macro -------------------------------------------------------------*/
  1094. #define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin)
  1095. #define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin)
  1096. /* - AUDIO clock -------------------------------------------------------------*/
  1097. AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22));
  1098. AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA);
  1099. AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23));
  1100. AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB);
  1101. AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7));
  1102. AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC);
  1103. AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16));
  1104. AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A);
  1105. AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16));
  1106. AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B);
  1107. /* - CAN macro --------_----------------------------------------------------- */
  1108. #define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
  1109. #define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
  1110. #define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
  1111. /* - CAN0 ------------------------------------------------------------------- */
  1112. CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
  1113. CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A);
  1114. CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
  1115. CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B);
  1116. /* - CAN1 ------------------------------------------------------------------- */
  1117. CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19));
  1118. CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A);
  1119. CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
  1120. CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B);
  1121. /* - CAN_CLK --------------------------------------------------------------- */
  1122. CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24));
  1123. CAN_PFC_CLK(can_clk_a, CAN_CLK_A);
  1124. CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16));
  1125. CAN_PFC_CLK(can_clk_b, CAN_CLK_B);
  1126. CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24));
  1127. CAN_PFC_CLK(can_clk_c, CAN_CLK_C);
  1128. CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25));
  1129. CAN_PFC_CLK(can_clk_d, CAN_CLK_D);
  1130. /* - Ether ------------------------------------------------------------------ */
  1131. SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
  1132. RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
  1133. RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
  1134. RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14),
  1135. RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17));
  1136. static const unsigned int ether_rmii_mux[] = {
  1137. ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
  1138. ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
  1139. ETH_MDIO_MARK, ETH_MDC_MARK,
  1140. };
  1141. SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19));
  1142. SH_PFC_MUX1(ether_link, ETH_LINK);
  1143. SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20));
  1144. SH_PFC_MUX1(ether_magic, ETH_MAGIC);
  1145. /* - SCIF macro ------------------------------------------------------------- */
  1146. #define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
  1147. #define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
  1148. #define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts)
  1149. #define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck)
  1150. /* - HSCIF0 ----------------------------------------------------------------- */
  1151. SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
  1152. SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A);
  1153. SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30));
  1154. SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B);
  1155. SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
  1156. SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A);
  1157. SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28));
  1158. SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B);
  1159. SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19));
  1160. SCIF_PFC_CLK(hscif0_clk, HSCK0);
  1161. /* - HSCIF1 ----------------------------------------------------------------- */
  1162. SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20));
  1163. SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A);
  1164. SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
  1165. SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B);
  1166. SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
  1167. SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A);
  1168. SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7));
  1169. SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B);
  1170. SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23));
  1171. SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A);
  1172. SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2));
  1173. SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B);
  1174. /* - HSPI macro --------------------------------------------------------------*/
  1175. #define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
  1176. #define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx)
  1177. /* - HSPI0 -------------------------------------------------------------------*/
  1178. HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
  1179. RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
  1180. HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A,
  1181. HSPI_RX0_A, HSPI_TX0);
  1182. HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
  1183. RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27));
  1184. HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B,
  1185. HSPI_RX0_B, HSPI_TX0_B);
  1186. /* - HSPI1 -------------------------------------------------------------------*/
  1187. HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
  1188. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28));
  1189. HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A,
  1190. HSPI_RX1_A, HSPI_TX1_A);
  1191. HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26),
  1192. PIN_CS0, PIN_CLKOUT);
  1193. HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B,
  1194. HSPI_RX1_B, HSPI_TX1_B);
  1195. /* - HSPI2 -------------------------------------------------------------------*/
  1196. HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8),
  1197. RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30));
  1198. HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A,
  1199. HSPI_RX2_A, HSPI_TX2_A);
  1200. HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
  1201. RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24));
  1202. HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B,
  1203. HSPI_RX2_B, HSPI_TX2_B);
  1204. /* - I2C macro ------------------------------------------------------------- */
  1205. #define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
  1206. #define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl)
  1207. /* - I2C1 ------------------------------------------------------------------ */
  1208. I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9));
  1209. I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A);
  1210. I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
  1211. I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B);
  1212. /* - I2C2 ------------------------------------------------------------------ */
  1213. I2C_PFC_PIN(i2c2_a, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
  1214. I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A);
  1215. I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
  1216. I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B);
  1217. I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
  1218. I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C);
  1219. /* - I2C3 ------------------------------------------------------------------ */
  1220. I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15));
  1221. I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A);
  1222. I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19));
  1223. I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B);
  1224. I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
  1225. I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
  1226. /* - MMC macro -------------------------------------------------------------- */
  1227. #define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
  1228. #define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
  1229. #define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
  1230. #define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
  1231. #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
  1232. SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
  1233. /* - MMC -------------------------------------------------------------------- */
  1234. MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
  1235. MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
  1236. MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
  1237. MMC_PFC_DAT1(mmc_data1, MMC_D0);
  1238. MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
  1239. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
  1240. MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
  1241. MMC_D2, MMC_D3);
  1242. MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
  1243. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  1244. RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
  1245. RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
  1246. MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
  1247. MMC_D2, MMC_D3,
  1248. MMC_D4, MMC_D5,
  1249. MMC_D6, MMC_D7);
  1250. /* - SCIF CLOCK ------------------------------------------------------------- */
  1251. SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16));
  1252. SCIF_PFC_CLK(scif_clk, SCIF_CLK);
  1253. /* - SCIF0 ------------------------------------------------------------------ */
  1254. SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
  1255. SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A);
  1256. SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2));
  1257. SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B);
  1258. SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31));
  1259. SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C);
  1260. SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1));
  1261. SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D);
  1262. SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
  1263. SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0);
  1264. SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19));
  1265. SCIF_PFC_CLK(scif0_clk, SCK0);
  1266. /* - SCIF1 ------------------------------------------------------------------ */
  1267. SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1));
  1268. SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A);
  1269. SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
  1270. SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B);
  1271. SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
  1272. SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C);
  1273. SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
  1274. SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D);
  1275. SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
  1276. SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A);
  1277. SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19));
  1278. SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C);
  1279. SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2));
  1280. SCIF_PFC_CLK(scif1_clk_a, SCK1_A);
  1281. SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20));
  1282. SCIF_PFC_CLK(scif1_clk_c, SCK1_C);
  1283. /* - SCIF2 ------------------------------------------------------------------ */
  1284. SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
  1285. SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A);
  1286. SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28));
  1287. SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B);
  1288. SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14));
  1289. SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C);
  1290. SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
  1291. SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D);
  1292. SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
  1293. SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E);
  1294. SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9));
  1295. SCIF_PFC_CLK(scif2_clk_a, SCK2_A);
  1296. SCIF_PFC_PIN(scif2_clk_b, PIN_CS1_A26);
  1297. SCIF_PFC_CLK(scif2_clk_b, SCK2_B);
  1298. SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12));
  1299. SCIF_PFC_CLK(scif2_clk_c, SCK2_C);
  1300. /* - SCIF3 ------------------------------------------------------------------ */
  1301. SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9));
  1302. SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A);
  1303. SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27));
  1304. SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B);
  1305. SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31));
  1306. SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C);
  1307. SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29));
  1308. SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D);
  1309. /* - SCIF4 ------------------------------------------------------------------ */
  1310. SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4));
  1311. SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A);
  1312. SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25));
  1313. SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B);
  1314. SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31));
  1315. SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C);
  1316. /* - SCIF5 ------------------------------------------------------------------ */
  1317. SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18));
  1318. SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A);
  1319. SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14));
  1320. SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
  1321. /* - SDHI macro ------------------------------------------------------------- */
  1322. #define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
  1323. #define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
  1324. #define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
  1325. #define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
  1326. #define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
  1327. #define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp)
  1328. /* - SDHI0 ------------------------------------------------------------------ */
  1329. SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17));
  1330. SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
  1331. SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
  1332. SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
  1333. SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
  1334. SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
  1335. SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  1336. RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
  1337. SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
  1338. SD0_DAT2, SD0_DAT3);
  1339. SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
  1340. SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
  1341. /* - SDHI1 ------------------------------------------------------------------ */
  1342. SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30));
  1343. SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A);
  1344. SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24));
  1345. SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B);
  1346. SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
  1347. SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
  1348. SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
  1349. SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
  1350. SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
  1351. SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
  1352. SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
  1353. SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
  1354. SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
  1355. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
  1356. SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
  1357. SD1_DAT2_A, SD1_DAT3_A);
  1358. SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
  1359. RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
  1360. SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
  1361. SD1_DAT2_B, SD1_DAT3_B);
  1362. SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
  1363. SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
  1364. SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25));
  1365. SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B);
  1366. /* - SDH2 ------------------------------------------------------------------- */
  1367. SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23));
  1368. SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A);
  1369. SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27));
  1370. SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B);
  1371. SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
  1372. SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
  1373. SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
  1374. SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
  1375. SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
  1376. SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
  1377. SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
  1378. SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
  1379. SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
  1380. RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
  1381. SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
  1382. SD2_DAT2_A, SD2_DAT3_A);
  1383. SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
  1384. RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
  1385. SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
  1386. SD2_DAT2_B, SD2_DAT3_B);
  1387. SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
  1388. SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
  1389. SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28));
  1390. SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B);
  1391. /* - SSI macro -------------------------------------------------------------- */
  1392. #define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
  1393. #define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws)
  1394. #define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d)
  1395. /* - SSI 0/1/2 -------------------------------------------------------------- */
  1396. SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7));
  1397. SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012);
  1398. SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10));
  1399. SSI_PFC_DATA(ssi0_data, SSI_SDATA0);
  1400. SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21));
  1401. SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A);
  1402. SSI_PFC_PINS(ssi1_b_ctrl, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
  1403. SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B);
  1404. SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9));
  1405. SSI_PFC_DATA(ssi1_data, SSI_SDATA1);
  1406. SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4));
  1407. SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A);
  1408. SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17));
  1409. SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B);
  1410. SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8));
  1411. SSI_PFC_DATA(ssi2_data, SSI_SDATA2);
  1412. /* - SSI 3/4 ---------------------------------------------------------------- */
  1413. SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3));
  1414. SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34);
  1415. SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5));
  1416. SSI_PFC_DATA(ssi3_data, SSI_SDATA3);
  1417. SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
  1418. SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4);
  1419. SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4));
  1420. SSI_PFC_DATA(ssi4_data, SSI_SDATA4);
  1421. /* - SSI 5 ------------------------------------------------------------------ */
  1422. SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0));
  1423. SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5);
  1424. SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1));
  1425. SSI_PFC_DATA(ssi5_data, SSI_SDATA5);
  1426. /* - SSI 6 ------------------------------------------------------------------ */
  1427. SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
  1428. SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6);
  1429. SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30));
  1430. SSI_PFC_DATA(ssi6_data, SSI_SDATA6);
  1431. /* - SSI 7/8 --------------------------------------------------------------- */
  1432. SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
  1433. SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78);
  1434. SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27));
  1435. SSI_PFC_DATA(ssi7_data, SSI_SDATA7);
  1436. SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26));
  1437. SSI_PFC_DATA(ssi8_data, SSI_SDATA8);
  1438. /* - USB0 ------------------------------------------------------------------- */
  1439. SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1));
  1440. SH_PFC_MUX1(usb0, PENC0);
  1441. SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3));
  1442. SH_PFC_MUX1(usb0_ovc, USB_OVC0);
  1443. /* - USB1 ------------------------------------------------------------------- */
  1444. SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2));
  1445. SH_PFC_MUX1(usb1, PENC1);
  1446. SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4));
  1447. SH_PFC_MUX1(usb1_ovc, USB_OVC1);
  1448. /* - VIN macros ------------------------------------------------------------- */
  1449. #define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
  1450. #define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
  1451. SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
  1452. #define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
  1453. #define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync)
  1454. /* - VIN0 ------------------------------------------------------------------- */
  1455. VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30),
  1456. RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0),
  1457. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
  1458. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
  1459. VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1,
  1460. VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3,
  1461. VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5,
  1462. VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1);
  1463. VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24));
  1464. VIN_PFC_CLK(vin0_clk, VI0_CLK);
  1465. VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28));
  1466. VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC);
  1467. /* - VIN1 ------------------------------------------------------------------- */
  1468. VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
  1469. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  1470. RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
  1471. RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8));
  1472. VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1,
  1473. VI1_DATA2, VI1_DATA3,
  1474. VI1_DATA4, VI1_DATA5,
  1475. VI1_DATA6, VI1_DATA7);
  1476. VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9));
  1477. VIN_PFC_CLK(vin1_clk, VI1_CLK);
  1478. VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
  1479. VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC);
  1480. static const struct sh_pfc_pin_group pinmux_groups[] = {
  1481. SH_PFC_PIN_GROUP(audio_clk_a),
  1482. SH_PFC_PIN_GROUP(audio_clk_b),
  1483. SH_PFC_PIN_GROUP(audio_clk_c),
  1484. SH_PFC_PIN_GROUP(audio_clkout_a),
  1485. SH_PFC_PIN_GROUP(audio_clkout_b),
  1486. SH_PFC_PIN_GROUP(can0_data_a),
  1487. SH_PFC_PIN_GROUP(can0_data_b),
  1488. SH_PFC_PIN_GROUP(can1_data_a),
  1489. SH_PFC_PIN_GROUP(can1_data_b),
  1490. SH_PFC_PIN_GROUP(can_clk_a),
  1491. SH_PFC_PIN_GROUP(can_clk_b),
  1492. SH_PFC_PIN_GROUP(can_clk_c),
  1493. SH_PFC_PIN_GROUP(can_clk_d),
  1494. SH_PFC_PIN_GROUP(ether_rmii),
  1495. SH_PFC_PIN_GROUP(ether_link),
  1496. SH_PFC_PIN_GROUP(ether_magic),
  1497. SH_PFC_PIN_GROUP(hscif0_data_a),
  1498. SH_PFC_PIN_GROUP(hscif0_data_b),
  1499. SH_PFC_PIN_GROUP(hscif0_ctrl_a),
  1500. SH_PFC_PIN_GROUP(hscif0_ctrl_b),
  1501. SH_PFC_PIN_GROUP(hscif0_clk),
  1502. SH_PFC_PIN_GROUP(hscif1_data_a),
  1503. SH_PFC_PIN_GROUP(hscif1_data_b),
  1504. SH_PFC_PIN_GROUP(hscif1_ctrl_a),
  1505. SH_PFC_PIN_GROUP(hscif1_ctrl_b),
  1506. SH_PFC_PIN_GROUP(hscif1_clk_a),
  1507. SH_PFC_PIN_GROUP(hscif1_clk_b),
  1508. SH_PFC_PIN_GROUP(hspi0_a),
  1509. SH_PFC_PIN_GROUP(hspi0_b),
  1510. SH_PFC_PIN_GROUP(hspi1_a),
  1511. SH_PFC_PIN_GROUP(hspi1_b),
  1512. SH_PFC_PIN_GROUP(hspi2_a),
  1513. SH_PFC_PIN_GROUP(hspi2_b),
  1514. SH_PFC_PIN_GROUP(i2c1_a),
  1515. SH_PFC_PIN_GROUP(i2c1_b),
  1516. SH_PFC_PIN_GROUP(i2c2_a),
  1517. SH_PFC_PIN_GROUP(i2c2_b),
  1518. SH_PFC_PIN_GROUP(i2c2_c),
  1519. SH_PFC_PIN_GROUP(i2c3_a),
  1520. SH_PFC_PIN_GROUP(i2c3_b),
  1521. SH_PFC_PIN_GROUP(i2c3_c),
  1522. SH_PFC_PIN_GROUP(mmc_ctrl),
  1523. SH_PFC_PIN_GROUP(mmc_data1),
  1524. SH_PFC_PIN_GROUP(mmc_data4),
  1525. SH_PFC_PIN_GROUP(mmc_data8),
  1526. SH_PFC_PIN_GROUP(scif_clk),
  1527. SH_PFC_PIN_GROUP(scif0_data_a),
  1528. SH_PFC_PIN_GROUP(scif0_data_b),
  1529. SH_PFC_PIN_GROUP(scif0_data_c),
  1530. SH_PFC_PIN_GROUP(scif0_data_d),
  1531. SH_PFC_PIN_GROUP(scif0_ctrl),
  1532. SH_PFC_PIN_GROUP(scif0_clk),
  1533. SH_PFC_PIN_GROUP(scif1_data_a),
  1534. SH_PFC_PIN_GROUP(scif1_data_b),
  1535. SH_PFC_PIN_GROUP(scif1_data_c),
  1536. SH_PFC_PIN_GROUP(scif1_data_d),
  1537. SH_PFC_PIN_GROUP(scif1_ctrl_a),
  1538. SH_PFC_PIN_GROUP(scif1_ctrl_c),
  1539. SH_PFC_PIN_GROUP(scif1_clk_a),
  1540. SH_PFC_PIN_GROUP(scif1_clk_c),
  1541. SH_PFC_PIN_GROUP(scif2_data_a),
  1542. SH_PFC_PIN_GROUP(scif2_data_b),
  1543. SH_PFC_PIN_GROUP(scif2_data_c),
  1544. SH_PFC_PIN_GROUP(scif2_data_d),
  1545. SH_PFC_PIN_GROUP(scif2_data_e),
  1546. SH_PFC_PIN_GROUP(scif2_clk_a),
  1547. SH_PFC_PIN_GROUP(scif2_clk_b),
  1548. SH_PFC_PIN_GROUP(scif2_clk_c),
  1549. SH_PFC_PIN_GROUP(scif3_data_a),
  1550. SH_PFC_PIN_GROUP(scif3_data_b),
  1551. SH_PFC_PIN_GROUP(scif3_data_c),
  1552. SH_PFC_PIN_GROUP(scif3_data_d),
  1553. SH_PFC_PIN_GROUP(scif4_data_a),
  1554. SH_PFC_PIN_GROUP(scif4_data_b),
  1555. SH_PFC_PIN_GROUP(scif4_data_c),
  1556. SH_PFC_PIN_GROUP(scif5_data_a),
  1557. SH_PFC_PIN_GROUP(scif5_data_b),
  1558. SH_PFC_PIN_GROUP(sdhi0_cd),
  1559. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  1560. SH_PFC_PIN_GROUP(sdhi0_data1),
  1561. SH_PFC_PIN_GROUP(sdhi0_data4),
  1562. SH_PFC_PIN_GROUP(sdhi0_wp),
  1563. SH_PFC_PIN_GROUP(sdhi1_cd_a),
  1564. SH_PFC_PIN_GROUP(sdhi1_cd_b),
  1565. SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
  1566. SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
  1567. SH_PFC_PIN_GROUP(sdhi1_data1_a),
  1568. SH_PFC_PIN_GROUP(sdhi1_data1_b),
  1569. SH_PFC_PIN_GROUP(sdhi1_data4_a),
  1570. SH_PFC_PIN_GROUP(sdhi1_data4_b),
  1571. SH_PFC_PIN_GROUP(sdhi1_wp_a),
  1572. SH_PFC_PIN_GROUP(sdhi1_wp_b),
  1573. SH_PFC_PIN_GROUP(sdhi2_cd_a),
  1574. SH_PFC_PIN_GROUP(sdhi2_cd_b),
  1575. SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
  1576. SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
  1577. SH_PFC_PIN_GROUP(sdhi2_data1_a),
  1578. SH_PFC_PIN_GROUP(sdhi2_data1_b),
  1579. SH_PFC_PIN_GROUP(sdhi2_data4_a),
  1580. SH_PFC_PIN_GROUP(sdhi2_data4_b),
  1581. SH_PFC_PIN_GROUP(sdhi2_wp_a),
  1582. SH_PFC_PIN_GROUP(sdhi2_wp_b),
  1583. SH_PFC_PIN_GROUP(ssi012_ctrl),
  1584. SH_PFC_PIN_GROUP(ssi0_data),
  1585. SH_PFC_PIN_GROUP(ssi1_a_ctrl),
  1586. SH_PFC_PIN_GROUP(ssi1_b_ctrl),
  1587. SH_PFC_PIN_GROUP(ssi1_data),
  1588. SH_PFC_PIN_GROUP(ssi2_a_ctrl),
  1589. SH_PFC_PIN_GROUP(ssi2_b_ctrl),
  1590. SH_PFC_PIN_GROUP(ssi2_data),
  1591. SH_PFC_PIN_GROUP(ssi34_ctrl),
  1592. SH_PFC_PIN_GROUP(ssi3_data),
  1593. SH_PFC_PIN_GROUP(ssi4_ctrl),
  1594. SH_PFC_PIN_GROUP(ssi4_data),
  1595. SH_PFC_PIN_GROUP(ssi5_ctrl),
  1596. SH_PFC_PIN_GROUP(ssi5_data),
  1597. SH_PFC_PIN_GROUP(ssi6_ctrl),
  1598. SH_PFC_PIN_GROUP(ssi6_data),
  1599. SH_PFC_PIN_GROUP(ssi78_ctrl),
  1600. SH_PFC_PIN_GROUP(ssi7_data),
  1601. SH_PFC_PIN_GROUP(ssi8_data),
  1602. SH_PFC_PIN_GROUP(usb0),
  1603. SH_PFC_PIN_GROUP(usb0_ovc),
  1604. SH_PFC_PIN_GROUP(usb1),
  1605. SH_PFC_PIN_GROUP(usb1_ovc),
  1606. SH_PFC_PIN_GROUP(vin0_data8),
  1607. SH_PFC_PIN_GROUP(vin0_clk),
  1608. SH_PFC_PIN_GROUP(vin0_sync),
  1609. SH_PFC_PIN_GROUP(vin1_data8),
  1610. SH_PFC_PIN_GROUP(vin1_clk),
  1611. SH_PFC_PIN_GROUP(vin1_sync),
  1612. };
  1613. static const char * const audio_clk_groups[] = {
  1614. "audio_clk_a",
  1615. "audio_clk_b",
  1616. "audio_clk_c",
  1617. "audio_clkout_a",
  1618. "audio_clkout_b",
  1619. };
  1620. static const char * const can0_groups[] = {
  1621. "can0_data_a",
  1622. "can0_data_b",
  1623. "can_clk_a",
  1624. "can_clk_b",
  1625. "can_clk_c",
  1626. "can_clk_d",
  1627. };
  1628. static const char * const can1_groups[] = {
  1629. "can1_data_a",
  1630. "can1_data_b",
  1631. "can_clk_a",
  1632. "can_clk_b",
  1633. "can_clk_c",
  1634. "can_clk_d",
  1635. };
  1636. static const char * const ether_groups[] = {
  1637. "ether_rmii",
  1638. "ether_link",
  1639. "ether_magic",
  1640. };
  1641. static const char * const hscif0_groups[] = {
  1642. "hscif0_data_a",
  1643. "hscif0_data_b",
  1644. "hscif0_ctrl_a",
  1645. "hscif0_ctrl_b",
  1646. "hscif0_clk",
  1647. };
  1648. static const char * const hscif1_groups[] = {
  1649. "hscif1_data_a",
  1650. "hscif1_data_b",
  1651. "hscif1_ctrl_a",
  1652. "hscif1_ctrl_b",
  1653. "hscif1_clk_a",
  1654. "hscif1_clk_b",
  1655. };
  1656. static const char * const hspi0_groups[] = {
  1657. "hspi0_a",
  1658. "hspi0_b",
  1659. };
  1660. static const char * const hspi1_groups[] = {
  1661. "hspi1_a",
  1662. "hspi1_b",
  1663. };
  1664. static const char * const hspi2_groups[] = {
  1665. "hspi2_a",
  1666. "hspi2_b",
  1667. };
  1668. static const char * const i2c1_groups[] = {
  1669. "i2c1_a",
  1670. "i2c1_b",
  1671. };
  1672. static const char * const i2c2_groups[] = {
  1673. "i2c2_a",
  1674. "i2c2_b",
  1675. "i2c2_c",
  1676. };
  1677. static const char * const i2c3_groups[] = {
  1678. "i2c3_a",
  1679. "i2c3_b",
  1680. "i2c3_c",
  1681. };
  1682. static const char * const mmc_groups[] = {
  1683. "mmc_ctrl",
  1684. "mmc_data1",
  1685. "mmc_data4",
  1686. "mmc_data8",
  1687. };
  1688. static const char * const scif_clk_groups[] = {
  1689. "scif_clk",
  1690. };
  1691. static const char * const scif0_groups[] = {
  1692. "scif0_data_a",
  1693. "scif0_data_b",
  1694. "scif0_data_c",
  1695. "scif0_data_d",
  1696. "scif0_ctrl",
  1697. "scif0_clk",
  1698. };
  1699. static const char * const scif1_groups[] = {
  1700. "scif1_data_a",
  1701. "scif1_data_b",
  1702. "scif1_data_c",
  1703. "scif1_data_d",
  1704. "scif1_ctrl_a",
  1705. "scif1_ctrl_c",
  1706. "scif1_clk_a",
  1707. "scif1_clk_c",
  1708. };
  1709. static const char * const scif2_groups[] = {
  1710. "scif2_data_a",
  1711. "scif2_data_b",
  1712. "scif2_data_c",
  1713. "scif2_data_d",
  1714. "scif2_data_e",
  1715. "scif2_clk_a",
  1716. "scif2_clk_b",
  1717. "scif2_clk_c",
  1718. };
  1719. static const char * const scif3_groups[] = {
  1720. "scif3_data_a",
  1721. "scif3_data_b",
  1722. "scif3_data_c",
  1723. "scif3_data_d",
  1724. };
  1725. static const char * const scif4_groups[] = {
  1726. "scif4_data_a",
  1727. "scif4_data_b",
  1728. "scif4_data_c",
  1729. };
  1730. static const char * const scif5_groups[] = {
  1731. "scif5_data_a",
  1732. "scif5_data_b",
  1733. };
  1734. static const char * const sdhi0_groups[] = {
  1735. "sdhi0_cd",
  1736. "sdhi0_ctrl",
  1737. "sdhi0_data1",
  1738. "sdhi0_data4",
  1739. "sdhi0_wp",
  1740. };
  1741. static const char * const sdhi1_groups[] = {
  1742. "sdhi1_cd_a",
  1743. "sdhi1_cd_b",
  1744. "sdhi1_ctrl_a",
  1745. "sdhi1_ctrl_b",
  1746. "sdhi1_data1_a",
  1747. "sdhi1_data1_b",
  1748. "sdhi1_data4_a",
  1749. "sdhi1_data4_b",
  1750. "sdhi1_wp_a",
  1751. "sdhi1_wp_b",
  1752. };
  1753. static const char * const sdhi2_groups[] = {
  1754. "sdhi2_cd_a",
  1755. "sdhi2_cd_b",
  1756. "sdhi2_ctrl_a",
  1757. "sdhi2_ctrl_b",
  1758. "sdhi2_data1_a",
  1759. "sdhi2_data1_b",
  1760. "sdhi2_data4_a",
  1761. "sdhi2_data4_b",
  1762. "sdhi2_wp_a",
  1763. "sdhi2_wp_b",
  1764. };
  1765. static const char * const ssi_groups[] = {
  1766. "ssi012_ctrl",
  1767. "ssi0_data",
  1768. "ssi1_a_ctrl",
  1769. "ssi1_b_ctrl",
  1770. "ssi1_data",
  1771. "ssi2_a_ctrl",
  1772. "ssi2_b_ctrl",
  1773. "ssi2_data",
  1774. "ssi34_ctrl",
  1775. "ssi3_data",
  1776. "ssi4_ctrl",
  1777. "ssi4_data",
  1778. "ssi5_ctrl",
  1779. "ssi5_data",
  1780. "ssi6_ctrl",
  1781. "ssi6_data",
  1782. "ssi78_ctrl",
  1783. "ssi7_data",
  1784. "ssi8_data",
  1785. };
  1786. static const char * const usb0_groups[] = {
  1787. "usb0",
  1788. "usb0_ovc",
  1789. };
  1790. static const char * const usb1_groups[] = {
  1791. "usb1",
  1792. "usb1_ovc",
  1793. };
  1794. static const char * const vin0_groups[] = {
  1795. "vin0_data8",
  1796. "vin0_clk",
  1797. "vin0_sync",
  1798. };
  1799. static const char * const vin1_groups[] = {
  1800. "vin1_data8",
  1801. "vin1_clk",
  1802. "vin1_sync",
  1803. };
  1804. static const struct sh_pfc_function pinmux_functions[] = {
  1805. SH_PFC_FUNCTION(audio_clk),
  1806. SH_PFC_FUNCTION(can0),
  1807. SH_PFC_FUNCTION(can1),
  1808. SH_PFC_FUNCTION(ether),
  1809. SH_PFC_FUNCTION(hscif0),
  1810. SH_PFC_FUNCTION(hscif1),
  1811. SH_PFC_FUNCTION(hspi0),
  1812. SH_PFC_FUNCTION(hspi1),
  1813. SH_PFC_FUNCTION(hspi2),
  1814. SH_PFC_FUNCTION(i2c1),
  1815. SH_PFC_FUNCTION(i2c2),
  1816. SH_PFC_FUNCTION(i2c3),
  1817. SH_PFC_FUNCTION(mmc),
  1818. SH_PFC_FUNCTION(scif_clk),
  1819. SH_PFC_FUNCTION(scif0),
  1820. SH_PFC_FUNCTION(scif1),
  1821. SH_PFC_FUNCTION(scif2),
  1822. SH_PFC_FUNCTION(scif3),
  1823. SH_PFC_FUNCTION(scif4),
  1824. SH_PFC_FUNCTION(scif5),
  1825. SH_PFC_FUNCTION(sdhi0),
  1826. SH_PFC_FUNCTION(sdhi1),
  1827. SH_PFC_FUNCTION(sdhi2),
  1828. SH_PFC_FUNCTION(ssi),
  1829. SH_PFC_FUNCTION(usb0),
  1830. SH_PFC_FUNCTION(usb1),
  1831. SH_PFC_FUNCTION(vin0),
  1832. SH_PFC_FUNCTION(vin1),
  1833. };
  1834. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  1835. { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
  1836. GP_0_31_FN, FN_IP1_14_11,
  1837. GP_0_30_FN, FN_IP1_10_8,
  1838. GP_0_29_FN, FN_IP1_7_5,
  1839. GP_0_28_FN, FN_IP1_4_2,
  1840. GP_0_27_FN, FN_IP1_1,
  1841. GP_0_26_FN, FN_IP1_0,
  1842. GP_0_25_FN, FN_IP0_30,
  1843. GP_0_24_FN, FN_IP0_29,
  1844. GP_0_23_FN, FN_IP0_28,
  1845. GP_0_22_FN, FN_IP0_27,
  1846. GP_0_21_FN, FN_IP0_26,
  1847. GP_0_20_FN, FN_IP0_25,
  1848. GP_0_19_FN, FN_IP0_24,
  1849. GP_0_18_FN, FN_IP0_23,
  1850. GP_0_17_FN, FN_IP0_22,
  1851. GP_0_16_FN, FN_IP0_21,
  1852. GP_0_15_FN, FN_IP0_20,
  1853. GP_0_14_FN, FN_IP0_19,
  1854. GP_0_13_FN, FN_IP0_18,
  1855. GP_0_12_FN, FN_IP0_17,
  1856. GP_0_11_FN, FN_IP0_16,
  1857. GP_0_10_FN, FN_IP0_15,
  1858. GP_0_9_FN, FN_A3,
  1859. GP_0_8_FN, FN_A2,
  1860. GP_0_7_FN, FN_A1,
  1861. GP_0_6_FN, FN_IP0_14_12,
  1862. GP_0_5_FN, FN_IP0_11_8,
  1863. GP_0_4_FN, FN_IP0_7_5,
  1864. GP_0_3_FN, FN_IP0_4_2,
  1865. GP_0_2_FN, FN_PENC1,
  1866. GP_0_1_FN, FN_PENC0,
  1867. GP_0_0_FN, FN_IP0_1_0 ))
  1868. },
  1869. { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
  1870. GP_1_31_FN, FN_IP4_6_4,
  1871. GP_1_30_FN, FN_IP4_3_1,
  1872. GP_1_29_FN, FN_IP4_0,
  1873. GP_1_28_FN, FN_IP3_31,
  1874. GP_1_27_FN, FN_IP3_30,
  1875. GP_1_26_FN, FN_IP3_29,
  1876. GP_1_25_FN, FN_IP3_28,
  1877. GP_1_24_FN, FN_IP3_27,
  1878. GP_1_23_FN, FN_IP3_26_24,
  1879. GP_1_22_FN, FN_IP3_23_21,
  1880. GP_1_21_FN, FN_IP3_20_19,
  1881. GP_1_20_FN, FN_IP3_18_16,
  1882. GP_1_19_FN, FN_IP3_15_13,
  1883. GP_1_18_FN, FN_IP3_12_10,
  1884. GP_1_17_FN, FN_IP3_9_8,
  1885. GP_1_16_FN, FN_IP3_7_5,
  1886. GP_1_15_FN, FN_IP3_4_2,
  1887. GP_1_14_FN, FN_IP3_1_0,
  1888. GP_1_13_FN, FN_IP2_31,
  1889. GP_1_12_FN, FN_IP2_30,
  1890. GP_1_11_FN, FN_IP2_17,
  1891. GP_1_10_FN, FN_IP2_16_14,
  1892. GP_1_9_FN, FN_IP2_13_12,
  1893. GP_1_8_FN, FN_IP2_11_9,
  1894. GP_1_7_FN, FN_IP2_8_6,
  1895. GP_1_6_FN, FN_IP2_5_3,
  1896. GP_1_5_FN, FN_IP2_2_0,
  1897. GP_1_4_FN, FN_IP1_29_28,
  1898. GP_1_3_FN, FN_IP1_27_25,
  1899. GP_1_2_FN, FN_IP1_24,
  1900. GP_1_1_FN, FN_WE0,
  1901. GP_1_0_FN, FN_IP1_23_21 ))
  1902. },
  1903. { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
  1904. GP_2_31_FN, FN_IP6_7,
  1905. GP_2_30_FN, FN_IP6_6_5,
  1906. GP_2_29_FN, FN_IP6_4_2,
  1907. GP_2_28_FN, FN_IP6_1_0,
  1908. GP_2_27_FN, FN_IP5_30_29,
  1909. GP_2_26_FN, FN_IP5_28_26,
  1910. GP_2_25_FN, FN_IP5_25_23,
  1911. GP_2_24_FN, FN_IP5_22_21,
  1912. GP_2_23_FN, FN_AUDIO_CLKB,
  1913. GP_2_22_FN, FN_AUDIO_CLKA,
  1914. GP_2_21_FN, FN_IP5_20_18,
  1915. GP_2_20_FN, FN_IP5_17_15,
  1916. GP_2_19_FN, FN_IP5_14_13,
  1917. GP_2_18_FN, FN_IP5_12,
  1918. GP_2_17_FN, FN_IP5_11_10,
  1919. GP_2_16_FN, FN_IP5_9_8,
  1920. GP_2_15_FN, FN_IP5_7,
  1921. GP_2_14_FN, FN_IP5_6,
  1922. GP_2_13_FN, FN_IP5_5_4,
  1923. GP_2_12_FN, FN_IP5_3_2,
  1924. GP_2_11_FN, FN_IP5_1_0,
  1925. GP_2_10_FN, FN_IP4_30_29,
  1926. GP_2_9_FN, FN_IP4_28_27,
  1927. GP_2_8_FN, FN_IP4_26_25,
  1928. GP_2_7_FN, FN_IP4_24_21,
  1929. GP_2_6_FN, FN_IP4_20_17,
  1930. GP_2_5_FN, FN_IP4_16_15,
  1931. GP_2_4_FN, FN_IP4_14_13,
  1932. GP_2_3_FN, FN_IP4_12_11,
  1933. GP_2_2_FN, FN_IP4_10_9,
  1934. GP_2_1_FN, FN_IP4_8,
  1935. GP_2_0_FN, FN_IP4_7 ))
  1936. },
  1937. { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
  1938. GP_3_31_FN, FN_IP8_10_9,
  1939. GP_3_30_FN, FN_IP8_8_6,
  1940. GP_3_29_FN, FN_IP8_5_3,
  1941. GP_3_28_FN, FN_IP8_2_0,
  1942. GP_3_27_FN, FN_IP7_31_29,
  1943. GP_3_26_FN, FN_IP7_28_25,
  1944. GP_3_25_FN, FN_IP7_24_22,
  1945. GP_3_24_FN, FN_IP7_21,
  1946. GP_3_23_FN, FN_IP7_20_18,
  1947. GP_3_22_FN, FN_IP7_17_15,
  1948. GP_3_21_FN, FN_IP7_14_12,
  1949. GP_3_20_FN, FN_IP7_11_9,
  1950. GP_3_19_FN, FN_IP7_8_6,
  1951. GP_3_18_FN, FN_IP7_5_4,
  1952. GP_3_17_FN, FN_IP7_3_2,
  1953. GP_3_16_FN, FN_IP7_1_0,
  1954. GP_3_15_FN, FN_IP6_31_30,
  1955. GP_3_14_FN, FN_IP6_29_28,
  1956. GP_3_13_FN, FN_IP6_27_26,
  1957. GP_3_12_FN, FN_IP6_25_24,
  1958. GP_3_11_FN, FN_IP6_23_22,
  1959. GP_3_10_FN, FN_IP6_21,
  1960. GP_3_9_FN, FN_IP6_20_19,
  1961. GP_3_8_FN, FN_IP6_18_17,
  1962. GP_3_7_FN, FN_IP6_16,
  1963. GP_3_6_FN, FN_IP6_15_14,
  1964. GP_3_5_FN, FN_IP6_13,
  1965. GP_3_4_FN, FN_IP6_12_11,
  1966. GP_3_3_FN, FN_IP6_10,
  1967. GP_3_2_FN, FN_SSI_SCK34,
  1968. GP_3_1_FN, FN_IP6_9,
  1969. GP_3_0_FN, FN_IP6_8 ))
  1970. },
  1971. { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
  1972. 0, 0,
  1973. 0, 0,
  1974. 0, 0,
  1975. 0, 0,
  1976. 0, 0,
  1977. GP_4_26_FN, FN_AVS2,
  1978. GP_4_25_FN, FN_AVS1,
  1979. GP_4_24_FN, FN_IP10_24_22,
  1980. GP_4_23_FN, FN_IP10_21_19,
  1981. GP_4_22_FN, FN_IP10_18_16,
  1982. GP_4_21_FN, FN_IP10_15_13,
  1983. GP_4_20_FN, FN_IP10_12_9,
  1984. GP_4_19_FN, FN_IP10_8_6,
  1985. GP_4_18_FN, FN_IP10_5_3,
  1986. GP_4_17_FN, FN_IP10_2_0,
  1987. GP_4_16_FN, FN_IP9_29_27,
  1988. GP_4_15_FN, FN_IP9_26_24,
  1989. GP_4_14_FN, FN_IP9_23_21,
  1990. GP_4_13_FN, FN_IP9_20_18,
  1991. GP_4_12_FN, FN_IP9_17_15,
  1992. GP_4_11_FN, FN_IP9_14_12,
  1993. GP_4_10_FN, FN_IP9_11_9,
  1994. GP_4_9_FN, FN_IP9_8_6,
  1995. GP_4_8_FN, FN_IP9_5_3,
  1996. GP_4_7_FN, FN_IP9_2_0,
  1997. GP_4_6_FN, FN_IP8_29_27,
  1998. GP_4_5_FN, FN_IP8_26_24,
  1999. GP_4_4_FN, FN_IP8_23_22,
  2000. GP_4_3_FN, FN_IP8_21_19,
  2001. GP_4_2_FN, FN_IP8_18_16,
  2002. GP_4_1_FN, FN_IP8_15_14,
  2003. GP_4_0_FN, FN_IP8_13_11 ))
  2004. },
  2005. { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
  2006. GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  2007. 1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
  2008. GROUP(
  2009. /* IP0_31 [1] */
  2010. 0, 0,
  2011. /* IP0_30 [1] */
  2012. FN_A19, 0,
  2013. /* IP0_29 [1] */
  2014. FN_A18, 0,
  2015. /* IP0_28 [1] */
  2016. FN_A17, 0,
  2017. /* IP0_27 [1] */
  2018. FN_A16, 0,
  2019. /* IP0_26 [1] */
  2020. FN_A15, 0,
  2021. /* IP0_25 [1] */
  2022. FN_A14, 0,
  2023. /* IP0_24 [1] */
  2024. FN_A13, 0,
  2025. /* IP0_23 [1] */
  2026. FN_A12, 0,
  2027. /* IP0_22 [1] */
  2028. FN_A11, 0,
  2029. /* IP0_21 [1] */
  2030. FN_A10, 0,
  2031. /* IP0_20 [1] */
  2032. FN_A9, 0,
  2033. /* IP0_19 [1] */
  2034. FN_A8, 0,
  2035. /* IP0_18 [1] */
  2036. FN_A7, 0,
  2037. /* IP0_17 [1] */
  2038. FN_A6, 0,
  2039. /* IP0_16 [1] */
  2040. FN_A5, 0,
  2041. /* IP0_15 [1] */
  2042. FN_A4, 0,
  2043. /* IP0_14_12 [3] */
  2044. FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0,
  2045. FN_ATAG0_A, 0, FN_REMOCON_B, 0,
  2046. /* IP0_11_8 [4] */
  2047. FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
  2048. FN_ATADIR0_A, 0, FN_SDSELF_A, 0,
  2049. FN_PWM4_B, 0, 0, 0,
  2050. 0, 0, 0, 0,
  2051. /* IP0_7_5 [3] */
  2052. FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1,
  2053. FN_RX2_E, FN_SCL2_B, 0, 0,
  2054. /* IP0_4_2 [3] */
  2055. FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0,
  2056. FN_TX2_E, FN_SDA2_B, 0, 0,
  2057. /* IP0_1_0 [2] */
  2058. FN_PRESETOUT, 0, FN_PWM1, 0,
  2059. ))
  2060. },
  2061. { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
  2062. GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
  2063. 3, 1, 1),
  2064. GROUP(
  2065. /* IP1_31 [1] */
  2066. 0, 0,
  2067. /* IP1_30 [1] */
  2068. 0, 0,
  2069. /* IP1_29_28 [2] */
  2070. FN_EX_CS1, FN_MMC_D4, 0, 0,
  2071. /* IP1_27_25 [3] */
  2072. FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C,
  2073. FN_TS_SCK0_A, 0, 0, 0,
  2074. /* IP1_24 [1] */
  2075. FN_WE1, FN_ATAWR0_B,
  2076. /* IP1_23_21 [3] */
  2077. FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR,
  2078. 0, 0, 0, 0,
  2079. /* IP1_20_18 [3] */
  2080. FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
  2081. FN_SCK2_B, 0, 0, 0,
  2082. /* IP1_17 [1] */
  2083. FN_CS0, FN_HSPI_RX1_B,
  2084. /* IP1_16_15 [2] */
  2085. FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0,
  2086. /* IP1_14_11 [4] */
  2087. FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25,
  2088. FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C,
  2089. FN_TS_SDAT0_A, 0, 0, 0,
  2090. 0, 0, 0, 0,
  2091. /* IP1_10_8 [3] */
  2092. FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24,
  2093. FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
  2094. /* IP1_7_5 [3] */
  2095. FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
  2096. FN_TS_SDEN0_A, 0, 0, 0,
  2097. /* IP1_4_2 [3] */
  2098. FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
  2099. 0, 0, 0, 0,
  2100. /* IP1_1 [1] */
  2101. FN_A21, FN_HSPI_CLK1_B,
  2102. /* IP1_0 [1] */
  2103. FN_A20, FN_HSPI_CS1_B,
  2104. ))
  2105. },
  2106. { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
  2107. GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  2108. 1, 1, 1, 3, 2, 3, 3, 3, 3),
  2109. GROUP(
  2110. /* IP2_31 [1] */
  2111. FN_MLB_CLK, FN_IRQ1_A,
  2112. /* IP2_30 [1] */
  2113. FN_RD_WR_B, FN_IRQ0,
  2114. /* IP2_29 [1] */
  2115. FN_D11, 0,
  2116. /* IP2_28 [1] */
  2117. FN_D10, 0,
  2118. /* IP2_27 [1] */
  2119. FN_D9, 0,
  2120. /* IP2_26 [1] */
  2121. FN_D8, 0,
  2122. /* IP2_25 [1] */
  2123. FN_D7, 0,
  2124. /* IP2_24 [1] */
  2125. FN_D6, 0,
  2126. /* IP2_23 [1] */
  2127. FN_D5, 0,
  2128. /* IP2_22 [1] */
  2129. FN_D4, 0,
  2130. /* IP2_21 [1] */
  2131. FN_D3, 0,
  2132. /* IP2_20 [1] */
  2133. FN_D2, 0,
  2134. /* IP2_19 [1] */
  2135. FN_D1, 0,
  2136. /* IP2_18 [1] */
  2137. FN_D0, 0,
  2138. /* IP2_17 [1] */
  2139. FN_EX_WAIT0, FN_PWM0_C,
  2140. /* IP2_16_14 [3] */
  2141. FN_DACK0, 0, 0, FN_TX3_A,
  2142. FN_DRACK0, 0, 0, 0,
  2143. /* IP2_13_12 [2] */
  2144. FN_DREQ0_A, 0, 0, FN_RX3_A,
  2145. /* IP2_11_9 [3] */
  2146. FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A,
  2147. FN_EX_CS5, FN_EX_WAIT2_A, 0, 0,
  2148. /* IP2_8_6 [3] */
  2149. FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0,
  2150. FN_EX_CS4, FN_EX_WAIT1_A, 0, 0,
  2151. /* IP2_5_3 [3] */
  2152. FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10,
  2153. FN_EX_CS3, 0, 0, 0,
  2154. /* IP2_2_0 [3] */
  2155. FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
  2156. FN_EX_CS2, 0, 0, 0,
  2157. ))
  2158. },
  2159. { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
  2160. GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
  2161. 3, 3, 2),
  2162. GROUP(
  2163. /* IP3_31 [1] */
  2164. FN_DU0_DR6, FN_LCDOUT6,
  2165. /* IP3_30 [1] */
  2166. FN_DU0_DR5, FN_LCDOUT5,
  2167. /* IP3_29 [1] */
  2168. FN_DU0_DR4, FN_LCDOUT4,
  2169. /* IP3_28 [1] */
  2170. FN_DU0_DR3, FN_LCDOUT3,
  2171. /* IP3_27 [1] */
  2172. FN_DU0_DR2, FN_LCDOUT2,
  2173. /* IP3_26_24 [3] */
  2174. FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3,
  2175. FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
  2176. /* IP3_23_21 [3] */
  2177. FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2,
  2178. FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B,
  2179. /* IP3_20_19 [2] */
  2180. FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0,
  2181. /* IP3_18_16 [3] */
  2182. FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0,
  2183. 0, 0, 0, 0,
  2184. /* IP3_15_13 [3] */
  2185. FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
  2186. 0, 0, 0, 0,
  2187. /* IP3_12_10 [3] */
  2188. FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0,
  2189. 0, 0, 0, 0,
  2190. /* IP3_9_8 [2] */
  2191. FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0,
  2192. /* IP3_7_5 [3] */
  2193. FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B,
  2194. FN_SDA3_B, 0, 0, 0,
  2195. /* IP3_4_2 [3] */
  2196. FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
  2197. FN_SDSELF_B, 0, 0, 0,
  2198. /* IP3_1_0 [2] */
  2199. FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
  2200. ))
  2201. },
  2202. { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
  2203. GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
  2204. 3, 3, 1),
  2205. GROUP(
  2206. /* IP4_31 [1] */
  2207. 0, 0,
  2208. /* IP4_30_29 [2] */
  2209. FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0,
  2210. /* IP4_28_27 [2] */
  2211. FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0,
  2212. /* IP4_26_25 [2] */
  2213. FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0,
  2214. /* IP4_24_21 [4] */
  2215. FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
  2216. FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0,
  2217. FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0,
  2218. 0, 0, 0, 0,
  2219. /* IP4_20_17 [4] */
  2220. FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16,
  2221. FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A,
  2222. FN_ADICLK, FN_TS_SDAT0_B, 0, 0,
  2223. 0, 0, 0, 0,
  2224. /* IP4_16_15 [2] */
  2225. FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0,
  2226. /* IP4_14_13 [2] */
  2227. FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0,
  2228. /* IP4_12_11 [2] */
  2229. FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0,
  2230. /* IP4_10_9 [2] */
  2231. FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0,
  2232. /* IP4_8 [1] */
  2233. FN_DU0_DG3, FN_LCDOUT11,
  2234. /* IP4_7 [1] */
  2235. FN_DU0_DG2, FN_LCDOUT10,
  2236. /* IP4_6_4 [3] */
  2237. FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5,
  2238. FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0,
  2239. /* IP4_3_1 [3] */
  2240. FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4,
  2241. FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
  2242. /* IP4_0 [1] */
  2243. FN_DU0_DR7, FN_LCDOUT7,
  2244. ))
  2245. },
  2246. { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
  2247. GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
  2248. 1, 2, 2, 2),
  2249. GROUP(
  2250. /* IP5_31 [1] */
  2251. 0, 0,
  2252. /* IP5_30_29 [2] */
  2253. FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B,
  2254. /* IP5_28_26 [3] */
  2255. FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A,
  2256. FN_CAN0_TX_B, 0, 0, 0,
  2257. /* IP5_25_23 [3] */
  2258. FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
  2259. FN_CAN_CLK_D, 0, 0, 0,
  2260. /* IP5_22_21 [2] */
  2261. FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
  2262. /* IP5_20_18 [3] */
  2263. FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC,
  2264. FN_ARM_TRACECTL, FN_FMIN_D, 0, 0,
  2265. /* IP5_17_15 [3] */
  2266. FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK,
  2267. FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0,
  2268. /* IP5_14_13 [2] */
  2269. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
  2270. FN_FMCLK_D, 0,
  2271. /* IP5_12 [1] */
  2272. FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
  2273. /* IP5_11_10 [2] */
  2274. FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
  2275. FN_QSTH_QHS, 0,
  2276. /* IP5_9_8 [2] */
  2277. FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE,
  2278. FN_AUDIO_CLKOUT_A, FN_REMOCON_C,
  2279. /* IP5_7 [1] */
  2280. FN_DU0_DOTCLKO_UT0, FN_QCLK,
  2281. /* IP5_6 [1] */
  2282. FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
  2283. /* IP5_5_4 [2] */
  2284. FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0,
  2285. /* IP5_3_2 [2] */
  2286. FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
  2287. /* IP5_1_0 [2] */
  2288. FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
  2289. ))
  2290. },
  2291. { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
  2292. GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
  2293. 1, 1, 1, 1, 2, 3, 2),
  2294. GROUP(
  2295. /* IP6_31_30 [2] */
  2296. FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
  2297. /* IP6_29_28 [2] */
  2298. FN_SD0_DAT1, 0, FN_SUB_TCK, 0,
  2299. /* IP6_27_26 [2] */
  2300. FN_SD0_DAT0, 0, FN_SUB_TMS, 0,
  2301. /* IP6_25_24 [2] */
  2302. FN_SD0_CMD, 0, FN_SUB_TRST, 0,
  2303. /* IP6_23_22 [2] */
  2304. FN_SD0_CLK, 0, FN_SUB_TDO, 0,
  2305. /* IP6_21 [1] */
  2306. FN_SSI_SDATA0, FN_ARM_TRACEDATA_15,
  2307. /* IP6_20_19 [2] */
  2308. FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
  2309. FN_SCL1_A, FN_SCK2_A,
  2310. /* IP6_18_17 [2] */
  2311. FN_SSI_SDATA2, FN_HSPI_CS2_A,
  2312. FN_ARM_TRACEDATA_13, FN_SDA1_A,
  2313. /* IP6_16 [1] */
  2314. FN_SSI_WS012, FN_ARM_TRACEDATA_12,
  2315. /* IP6_15_14 [2] */
  2316. FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
  2317. FN_TX0_D, 0,
  2318. /* IP6_13 [1] */
  2319. FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
  2320. /* IP6_12_11 [2] */
  2321. FN_SSI_SDATA4, FN_SSI_WS2_A,
  2322. FN_ARM_TRACEDATA_9, 0,
  2323. /* IP6_10 [1] */
  2324. FN_SSI_WS34, FN_ARM_TRACEDATA_8,
  2325. /* IP6_9 [1] */
  2326. FN_SSI_SDATA5, FN_RX0_D,
  2327. /* IP6_8 [1] */
  2328. FN_SSI_WS5, FN_TX4_C,
  2329. /* IP6_7 [1] */
  2330. FN_SSI_SCK5, FN_RX4_C,
  2331. /* IP6_6_5 [2] */
  2332. FN_SSI_SDATA6, FN_HSPI_TX2_A,
  2333. FN_FMIN_B, 0,
  2334. /* IP6_4_2 [3] */
  2335. FN_SSI_WS6, FN_HSPI_CLK2_A,
  2336. FN_BPFCLK_B, FN_CAN1_RX_B,
  2337. 0, 0, 0, 0,
  2338. /* IP6_1_0 [2] */
  2339. FN_SSI_SCK6, FN_HSPI_RX2_A,
  2340. FN_FMCLK_B, FN_CAN1_TX_B,
  2341. ))
  2342. },
  2343. { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
  2344. GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
  2345. GROUP(
  2346. /* IP7_31_29 [3] */
  2347. FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
  2348. 0, FN_HSPI_CS1_A, FN_RX3_B, 0,
  2349. /* IP7_28_25 [4] */
  2350. FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1,
  2351. FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B,
  2352. 0, 0, 0, 0,
  2353. 0, 0, 0, 0,
  2354. /* IP7_24_22 [3] */
  2355. FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
  2356. 0, FN_HSPI_RX1_A, FN_RX4_B, 0,
  2357. /* IP7_21 [1] */
  2358. FN_VI0_CLK, FN_CAN_CLK_A,
  2359. /* IP7_20_18 [3] */
  2360. FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0,
  2361. FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0,
  2362. /* IP7_17_15 [3] */
  2363. FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A,
  2364. 0, FN_TX1_C, 0, 0,
  2365. /* IP7_14_12 [3] */
  2366. FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A,
  2367. 0, FN_RX1_C, 0, 0,
  2368. /* IP7_11_9 [3] */
  2369. FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0,
  2370. FN_SCK1_C, 0, 0, 0,
  2371. /* IP7_8_6 [3] */
  2372. FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0,
  2373. FN_RTS1_C, 0, 0, 0,
  2374. /* IP7_5_4 [2] */
  2375. FN_SD0_WP, 0, FN_RX5_A, 0,
  2376. /* IP7_3_2 [2] */
  2377. FN_SD0_CD, 0, FN_TX5_A, 0,
  2378. /* IP7_1_0 [2] */
  2379. FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
  2380. ))
  2381. },
  2382. { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
  2383. GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
  2384. GROUP(
  2385. /* IP8_31 [1] */
  2386. 0, 0,
  2387. /* IP8_30 [1] */
  2388. 0, 0,
  2389. /* IP8_29_27 [3] */
  2390. FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5,
  2391. 0, FN_HRX1_B, 0, 0,
  2392. /* IP8_26_24 [3] */
  2393. FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4,
  2394. 0, FN_HTX1_B, 0, 0,
  2395. /* IP8_23_22 [2] */
  2396. FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
  2397. FN_RTS1_A, 0,
  2398. /* IP8_21_19 [3] */
  2399. FN_VI0_DATA6_VI0_G0, FN_DU1_DB4,
  2400. FN_CTS1_A, FN_PWM5,
  2401. 0, 0, 0, 0,
  2402. /* IP8_18_16 [3] */
  2403. FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4,
  2404. 0, FN_HSCK1_B, 0, 0,
  2405. /* IP8_15_14 [2] */
  2406. FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0,
  2407. /* IP8_13_11 [3] */
  2408. FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C,
  2409. 0, 0, 0, 0,
  2410. /* IP8_10_9 [2] */
  2411. FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0,
  2412. /* IP8_8_6 [3] */
  2413. FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D,
  2414. 0, 0, 0, 0,
  2415. /* IP8_5_3 [3] */
  2416. FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D,
  2417. 0, 0, 0, 0,
  2418. /* IP8_2_0 [3] */
  2419. FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
  2420. 0, FN_HSPI_TX1_A, FN_TX3_B, 0,
  2421. ))
  2422. },
  2423. { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
  2424. GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
  2425. GROUP(
  2426. /* IP9_31 [1] */
  2427. 0, 0,
  2428. /* IP9_30 [1] */
  2429. 0, 0,
  2430. /* IP9_29_27 [3] */
  2431. FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC,
  2432. FN_ETH_RXD1, FN_FMIN_C,
  2433. 0, FN_RX2_D,
  2434. FN_SCL2_C, 0,
  2435. /* IP9_26_24 [3] */
  2436. FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT,
  2437. FN_ETH_RXD0, FN_BPFCLK_C,
  2438. 0, FN_TX2_D,
  2439. FN_SDA2_C, 0,
  2440. /* IP9_23_21 [3] */
  2441. FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C,
  2442. FN_IERX, FN_RX2_C, 0, 0,
  2443. /* IP9_20_18 [3] */
  2444. FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0,
  2445. FN_IETX, FN_TX2_C, 0, 0,
  2446. /* IP9_17_15 [3] */
  2447. FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK,
  2448. FN_SCK2_C, 0, 0, 0,
  2449. /* IP9_14_12 [3] */
  2450. FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1,
  2451. 0, FN_PWM3, 0, 0,
  2452. /* IP9_11_9 [3] */
  2453. FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0,
  2454. 0, FN_PWM2, FN_TCLK1, 0,
  2455. /* IP9_8_6 [3] */
  2456. FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
  2457. 0, 0, 0, 0,
  2458. /* IP9_5_3 [3] */
  2459. FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7,
  2460. 0, FN_HCTS1_B, 0, 0,
  2461. /* IP9_2_0 [3] */
  2462. FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
  2463. 0, FN_HRTS1_B, 0, 0,
  2464. ))
  2465. },
  2466. { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
  2467. GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
  2468. 3, 3, 3),
  2469. GROUP(
  2470. /* IP10_31 [1] */
  2471. 0, 0,
  2472. /* IP10_30 [1] */
  2473. 0, 0,
  2474. /* IP10_29 [1] */
  2475. 0, 0,
  2476. /* IP10_28 [1] */
  2477. 0, 0,
  2478. /* IP10_27 [1] */
  2479. 0, 0,
  2480. /* IP10_26 [1] */
  2481. 0, 0,
  2482. /* IP10_25 [1] */
  2483. 0, 0,
  2484. /* IP10_24_22 [3] */
  2485. FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B,
  2486. FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0,
  2487. /* IP10_21_19 [3] */
  2488. FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B,
  2489. FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0,
  2490. /* IP10_18_16 [3] */
  2491. FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1,
  2492. FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0,
  2493. /* IP10_15_13 [3] */
  2494. FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1,
  2495. FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0,
  2496. /* IP10_12_9 [4] */
  2497. FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
  2498. FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6,
  2499. 0, 0, 0, 0,
  2500. 0, 0, 0, 0,
  2501. /* IP10_8_6 [3] */
  2502. FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B,
  2503. FN_ETH_LINK, FN_CAN1_RX_A, 0, 0,
  2504. /* IP10_5_3 [3] */
  2505. FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
  2506. FN_ATAWR1, FN_ETH_MDIO,
  2507. FN_SCL1_B, 0,
  2508. 0, 0,
  2509. /* IP10_2_0 [3] */
  2510. FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC,
  2511. FN_ATARD1, FN_ETH_MDC,
  2512. FN_SDA1_B, 0,
  2513. 0, 0,
  2514. ))
  2515. },
  2516. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
  2517. GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
  2518. 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
  2519. GROUP(
  2520. /* SEL 31 [1] */
  2521. 0, 0,
  2522. /* SEL_30 (SCIF5) [1] */
  2523. FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
  2524. /* SEL_29_28 (SCIF4) [2] */
  2525. FN_SEL_SCIF4_A, FN_SEL_SCIF4_B,
  2526. FN_SEL_SCIF4_C, 0,
  2527. /* SEL_27_26 (SCIF3) [2] */
  2528. FN_SEL_SCIF3_A, FN_SEL_SCIF3_B,
  2529. FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
  2530. /* SEL_25_23 (SCIF2) [3] */
  2531. FN_SEL_SCIF2_A, FN_SEL_SCIF2_B,
  2532. FN_SEL_SCIF2_C, FN_SEL_SCIF2_D,
  2533. FN_SEL_SCIF2_E, 0,
  2534. 0, 0,
  2535. /* SEL_22_21 (SCIF1) [2] */
  2536. FN_SEL_SCIF1_A, FN_SEL_SCIF1_B,
  2537. FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
  2538. /* SEL_20_19 (SCIF0) [2] */
  2539. FN_SEL_SCIF0_A, FN_SEL_SCIF0_B,
  2540. FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
  2541. /* SEL_18 [1] */
  2542. 0, 0,
  2543. /* SEL_17 (SSI2) [1] */
  2544. FN_SEL_SSI2_A, FN_SEL_SSI2_B,
  2545. /* SEL_16 (SSI1) [1] */
  2546. FN_SEL_SSI1_A, FN_SEL_SSI1_B,
  2547. /* SEL_15 (VI1) [1] */
  2548. FN_SEL_VI1_A, FN_SEL_VI1_B,
  2549. /* SEL_14_13 (VI0) [2] */
  2550. FN_SEL_VI0_A, FN_SEL_VI0_B,
  2551. FN_SEL_VI0_C, FN_SEL_VI0_D,
  2552. /* SEL_12 [1] */
  2553. 0, 0,
  2554. /* SEL_11 (SD2) [1] */
  2555. FN_SEL_SD2_A, FN_SEL_SD2_B,
  2556. /* SEL_10 (SD1) [1] */
  2557. FN_SEL_SD1_A, FN_SEL_SD1_B,
  2558. /* SEL_9 (IRQ3) [1] */
  2559. FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
  2560. /* SEL_8_7 (IRQ2) [2] */
  2561. FN_SEL_IRQ2_A, FN_SEL_IRQ2_B,
  2562. FN_SEL_IRQ2_C, 0,
  2563. /* SEL_6 (IRQ1) [1] */
  2564. FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
  2565. /* SEL_5 [1] */
  2566. 0, 0,
  2567. /* SEL_4 (DREQ2) [1] */
  2568. FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
  2569. /* SEL_3 (DREQ1) [1] */
  2570. FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
  2571. /* SEL_2 (DREQ0) [1] */
  2572. FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
  2573. /* SEL_1 (WAIT2) [1] */
  2574. FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
  2575. /* SEL_0 (WAIT1) [1] */
  2576. FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
  2577. ))
  2578. },
  2579. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
  2580. GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
  2581. 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
  2582. GROUP(
  2583. /* SEL_31 [1] */
  2584. 0, 0,
  2585. /* SEL_30 [1] */
  2586. 0, 0,
  2587. /* SEL_29 [1] */
  2588. 0, 0,
  2589. /* SEL_28 [1] */
  2590. 0, 0,
  2591. /* SEL_27 (CAN1) [1] */
  2592. FN_SEL_CAN1_A, FN_SEL_CAN1_B,
  2593. /* SEL_26 (CAN0) [1] */
  2594. FN_SEL_CAN0_A, FN_SEL_CAN0_B,
  2595. /* SEL_25_24 (CANCLK) [2] */
  2596. FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
  2597. FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
  2598. /* SEL_23 (HSCIF1) [1] */
  2599. FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
  2600. /* SEL_22 (HSCIF0) [1] */
  2601. FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
  2602. /* SEL_21 [1] */
  2603. 0, 0,
  2604. /* SEL_20 [1] */
  2605. 0, 0,
  2606. /* SEL_19 [1] */
  2607. 0, 0,
  2608. /* SEL_18 [1] */
  2609. 0, 0,
  2610. /* SEL_17 [1] */
  2611. 0, 0,
  2612. /* SEL_16 [1] */
  2613. 0, 0,
  2614. /* SEL_15 [1] */
  2615. 0, 0,
  2616. /* SEL_14_13 (REMOCON) [2] */
  2617. FN_SEL_REMOCON_A, FN_SEL_REMOCON_B,
  2618. FN_SEL_REMOCON_C, 0,
  2619. /* SEL_12_11 (FM) [2] */
  2620. FN_SEL_FM_A, FN_SEL_FM_B,
  2621. FN_SEL_FM_C, FN_SEL_FM_D,
  2622. /* SEL_10_9 (GPS) [2] */
  2623. FN_SEL_GPS_A, FN_SEL_GPS_B,
  2624. FN_SEL_GPS_C, 0,
  2625. /* SEL_8 (TSIF0) [1] */
  2626. FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
  2627. /* SEL_7 (HSPI2) [1] */
  2628. FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
  2629. /* SEL_6 (HSPI1) [1] */
  2630. FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
  2631. /* SEL_5 (HSPI0) [1] */
  2632. FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
  2633. /* SEL_4_3 (I2C3) [2] */
  2634. FN_SEL_I2C3_A, FN_SEL_I2C3_B,
  2635. FN_SEL_I2C3_C, 0,
  2636. /* SEL_2_1 (I2C2) [2] */
  2637. FN_SEL_I2C2_A, FN_SEL_I2C2_B,
  2638. FN_SEL_I2C2_C, 0,
  2639. /* SEL_0 (I2C1) [1] */
  2640. FN_SEL_I2C1_A, FN_SEL_I2C1_B,
  2641. ))
  2642. },
  2643. { },
  2644. };
  2645. static const struct pinmux_bias_reg pinmux_bias_regs[] = {
  2646. { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
  2647. [ 0] = RCAR_GP_PIN(0, 6), /* A0 */
  2648. [ 1] = RCAR_GP_PIN(0, 7), /* A1 */
  2649. [ 2] = RCAR_GP_PIN(0, 8), /* A2 */
  2650. [ 3] = RCAR_GP_PIN(0, 9), /* A3 */
  2651. [ 4] = RCAR_GP_PIN(0, 10), /* A4 */
  2652. [ 5] = RCAR_GP_PIN(0, 11), /* A5 */
  2653. [ 6] = RCAR_GP_PIN(0, 12), /* A6 */
  2654. [ 7] = RCAR_GP_PIN(0, 13), /* A7 */
  2655. [ 8] = RCAR_GP_PIN(0, 14), /* A8 */
  2656. [ 9] = RCAR_GP_PIN(0, 15), /* A9 */
  2657. [10] = RCAR_GP_PIN(0, 16), /* A10 */
  2658. [11] = RCAR_GP_PIN(0, 17), /* A11 */
  2659. [12] = RCAR_GP_PIN(0, 18), /* A12 */
  2660. [13] = RCAR_GP_PIN(0, 19), /* A13 */
  2661. [14] = RCAR_GP_PIN(0, 20), /* A14 */
  2662. [15] = RCAR_GP_PIN(0, 21), /* A15 */
  2663. [16] = RCAR_GP_PIN(0, 22), /* A16 */
  2664. [17] = RCAR_GP_PIN(0, 23), /* A17 */
  2665. [18] = RCAR_GP_PIN(0, 24), /* A18 */
  2666. [19] = RCAR_GP_PIN(0, 25), /* A19 */
  2667. [20] = RCAR_GP_PIN(0, 26), /* A20 */
  2668. [21] = RCAR_GP_PIN(0, 27), /* A21 */
  2669. [22] = RCAR_GP_PIN(0, 28), /* A22 */
  2670. [23] = RCAR_GP_PIN(0, 29), /* A23 */
  2671. [24] = RCAR_GP_PIN(0, 30), /* A24 */
  2672. [25] = RCAR_GP_PIN(0, 31), /* A25 */
  2673. [26] = RCAR_GP_PIN(1, 3), /* /EX_CS0 */
  2674. [27] = RCAR_GP_PIN(1, 4), /* /EX_CS1 */
  2675. [28] = RCAR_GP_PIN(1, 5), /* /EX_CS2 */
  2676. [29] = RCAR_GP_PIN(1, 6), /* /EX_CS3 */
  2677. [30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */
  2678. [31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */
  2679. } },
  2680. { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
  2681. [ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */
  2682. [ 1] = RCAR_GP_PIN(0, 5), /* /BS */
  2683. [ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */
  2684. [ 3] = RCAR_GP_PIN(1, 1), /* /WE0 */
  2685. [ 4] = RCAR_GP_PIN(1, 2), /* /WE1 */
  2686. [ 5] = RCAR_GP_PIN(1, 11), /* EX_WAIT0 */
  2687. [ 6] = RCAR_GP_PIN(1, 9), /* DREQ0 */
  2688. [ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */
  2689. [ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */
  2690. [ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */
  2691. [10] = SH_PFC_PIN_NONE,
  2692. [11] = SH_PFC_PIN_NONE,
  2693. [12] = SH_PFC_PIN_NONE,
  2694. [13] = SH_PFC_PIN_NONE,
  2695. [14] = SH_PFC_PIN_NONE,
  2696. [15] = SH_PFC_PIN_NONE,
  2697. [16] = SH_PFC_PIN_NONE,
  2698. [17] = SH_PFC_PIN_NONE,
  2699. [18] = SH_PFC_PIN_NONE,
  2700. [19] = SH_PFC_PIN_NONE,
  2701. [20] = SH_PFC_PIN_NONE,
  2702. [21] = SH_PFC_PIN_NONE,
  2703. [22] = SH_PFC_PIN_NONE,
  2704. [23] = SH_PFC_PIN_NONE,
  2705. [24] = SH_PFC_PIN_NONE,
  2706. [25] = SH_PFC_PIN_NONE,
  2707. [26] = SH_PFC_PIN_NONE,
  2708. [27] = SH_PFC_PIN_NONE,
  2709. [28] = SH_PFC_PIN_NONE,
  2710. [29] = SH_PFC_PIN_NONE,
  2711. [30] = SH_PFC_PIN_NONE,
  2712. [31] = SH_PFC_PIN_NONE,
  2713. } },
  2714. { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
  2715. [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
  2716. [ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */
  2717. [ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */
  2718. [ 3] = RCAR_GP_PIN(1, 25), /* DU0_DR3 */
  2719. [ 4] = RCAR_GP_PIN(1, 26), /* DU0_DR4 */
  2720. [ 5] = RCAR_GP_PIN(1, 27), /* DU0_DR5 */
  2721. [ 6] = RCAR_GP_PIN(1, 28), /* DU0_DR6 */
  2722. [ 7] = RCAR_GP_PIN(1, 29), /* DU0_DR7 */
  2723. [ 8] = RCAR_GP_PIN(1, 30), /* DU0_DG0 */
  2724. [ 9] = RCAR_GP_PIN(1, 31), /* DU0_DG1 */
  2725. [10] = RCAR_GP_PIN(2, 0), /* DU0_DG2 */
  2726. [11] = RCAR_GP_PIN(2, 1), /* DU0_DG3 */
  2727. [12] = RCAR_GP_PIN(2, 2), /* DU0_DG4 */
  2728. [13] = RCAR_GP_PIN(2, 3), /* DU0_DG5 */
  2729. [14] = RCAR_GP_PIN(2, 4), /* DU0_DG6 */
  2730. [15] = RCAR_GP_PIN(2, 5), /* DU0_DG7 */
  2731. [16] = RCAR_GP_PIN(2, 6), /* DU0_DB0 */
  2732. [17] = RCAR_GP_PIN(2, 7), /* DU0_DB1 */
  2733. [18] = RCAR_GP_PIN(2, 8), /* DU0_DB2 */
  2734. [19] = RCAR_GP_PIN(2, 9), /* DU0_DB3 */
  2735. [20] = RCAR_GP_PIN(2, 10), /* DU0_DB4 */
  2736. [21] = RCAR_GP_PIN(2, 11), /* DU0_DB5 */
  2737. [22] = RCAR_GP_PIN(2, 12), /* DU0_DB6 */
  2738. [23] = RCAR_GP_PIN(2, 13), /* DU0_DB7 */
  2739. [24] = RCAR_GP_PIN(2, 14), /* DU0_DOTCLKIN */
  2740. [25] = RCAR_GP_PIN(2, 15), /* DU0_DOTCLKOUT0 */
  2741. [26] = RCAR_GP_PIN(2, 17), /* DU0_HSYNC */
  2742. [27] = RCAR_GP_PIN(2, 18), /* DU0_VSYNC */
  2743. [28] = RCAR_GP_PIN(2, 19), /* DU0_EXODDF */
  2744. [29] = RCAR_GP_PIN(2, 20), /* DU0_DISP */
  2745. [30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */
  2746. [31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */
  2747. } },
  2748. { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
  2749. [ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */
  2750. [ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */
  2751. [ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */
  2752. [ 3] = RCAR_GP_PIN(3, 27), /* /VI0_HSYNC */
  2753. [ 4] = RCAR_GP_PIN(3, 28), /* /VI0_VSYNC */
  2754. [ 5] = RCAR_GP_PIN(3, 29), /* VI0_DATA0 */
  2755. [ 6] = RCAR_GP_PIN(3, 30), /* VI0_DATA1 */
  2756. [ 7] = RCAR_GP_PIN(3, 31), /* VI0_DATA2 */
  2757. [ 8] = RCAR_GP_PIN(4, 0), /* VI0_DATA3 */
  2758. [ 9] = RCAR_GP_PIN(4, 1), /* VI0_DATA4 */
  2759. [10] = RCAR_GP_PIN(4, 2), /* VI0_DATA5 */
  2760. [11] = RCAR_GP_PIN(4, 3), /* VI0_DATA6 */
  2761. [12] = RCAR_GP_PIN(4, 4), /* VI0_DATA7 */
  2762. [13] = RCAR_GP_PIN(4, 5), /* VI0_G2 */
  2763. [14] = RCAR_GP_PIN(4, 6), /* VI0_G3 */
  2764. [15] = RCAR_GP_PIN(4, 7), /* VI0_G4 */
  2765. [16] = RCAR_GP_PIN(4, 8), /* VI0_G5 */
  2766. [17] = RCAR_GP_PIN(4, 21), /* VI1_DATA12 */
  2767. [18] = RCAR_GP_PIN(4, 22), /* VI1_DATA13 */
  2768. [19] = RCAR_GP_PIN(4, 23), /* VI1_DATA14 */
  2769. [20] = RCAR_GP_PIN(4, 24), /* VI1_DATA15 */
  2770. [21] = RCAR_GP_PIN(4, 9), /* ETH_REF_CLK */
  2771. [22] = RCAR_GP_PIN(4, 10), /* ETH_TXD0 */
  2772. [23] = RCAR_GP_PIN(4, 11), /* ETH_TXD1 */
  2773. [24] = RCAR_GP_PIN(4, 12), /* ETH_CRS_DV */
  2774. [25] = RCAR_GP_PIN(4, 13), /* ETH_TX_EN */
  2775. [26] = RCAR_GP_PIN(4, 14), /* ETH_RX_ER */
  2776. [27] = RCAR_GP_PIN(4, 15), /* ETH_RXD0 */
  2777. [28] = RCAR_GP_PIN(4, 16), /* ETH_RXD1 */
  2778. [29] = RCAR_GP_PIN(4, 17), /* ETH_MDC */
  2779. [30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */
  2780. [31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */
  2781. } },
  2782. { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
  2783. [ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */
  2784. [ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */
  2785. [ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */
  2786. [ 3] = RCAR_GP_PIN(3, 9), /* SSI_SDATA1 */
  2787. [ 4] = RCAR_GP_PIN(3, 8), /* SSI_SDATA2 */
  2788. [ 5] = RCAR_GP_PIN(3, 2), /* SSI_SCK34 */
  2789. [ 6] = RCAR_GP_PIN(3, 3), /* SSI_WS34 */
  2790. [ 7] = RCAR_GP_PIN(3, 5), /* SSI_SDATA3 */
  2791. [ 8] = RCAR_GP_PIN(3, 4), /* SSI_SDATA4 */
  2792. [ 9] = RCAR_GP_PIN(2, 31), /* SSI_SCK5 */
  2793. [10] = RCAR_GP_PIN(3, 0), /* SSI_WS5 */
  2794. [11] = RCAR_GP_PIN(3, 1), /* SSI_SDATA5 */
  2795. [12] = RCAR_GP_PIN(2, 28), /* SSI_SCK6 */
  2796. [13] = RCAR_GP_PIN(2, 29), /* SSI_WS6 */
  2797. [14] = RCAR_GP_PIN(2, 30), /* SSI_SDATA6 */
  2798. [15] = RCAR_GP_PIN(2, 24), /* SSI_SCK78 */
  2799. [16] = RCAR_GP_PIN(2, 25), /* SSI_WS78 */
  2800. [17] = RCAR_GP_PIN(2, 27), /* SSI_SDATA7 */
  2801. [18] = RCAR_GP_PIN(2, 26), /* SSI_SDATA8 */
  2802. [19] = RCAR_GP_PIN(3, 23), /* TCLK0 */
  2803. [20] = RCAR_GP_PIN(3, 11), /* SD0_CLK */
  2804. [21] = RCAR_GP_PIN(3, 12), /* SD0_CMD */
  2805. [22] = RCAR_GP_PIN(3, 13), /* SD0_DAT0 */
  2806. [23] = RCAR_GP_PIN(3, 14), /* SD0_DAT1 */
  2807. [24] = RCAR_GP_PIN(3, 15), /* SD0_DAT2 */
  2808. [25] = RCAR_GP_PIN(3, 16), /* SD0_DAT3 */
  2809. [26] = RCAR_GP_PIN(3, 17), /* SD0_CD */
  2810. [27] = RCAR_GP_PIN(3, 18), /* SD0_WP */
  2811. [28] = RCAR_GP_PIN(2, 22), /* AUDIO_CLKA */
  2812. [29] = RCAR_GP_PIN(2, 23), /* AUDIO_CLKB */
  2813. [30] = RCAR_GP_PIN(1, 14), /* IRQ2 */
  2814. [31] = RCAR_GP_PIN(1, 15), /* IRQ3 */
  2815. } },
  2816. { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
  2817. [ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */
  2818. [ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */
  2819. [ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */
  2820. [ 3] = RCAR_GP_PIN(0, 4), /* USB_OVC1 */
  2821. [ 4] = RCAR_GP_PIN(1, 16), /* SCIF_CLK */
  2822. [ 5] = RCAR_GP_PIN(1, 17), /* TX0 */
  2823. [ 6] = RCAR_GP_PIN(1, 18), /* RX0 */
  2824. [ 7] = RCAR_GP_PIN(1, 19), /* SCK0 */
  2825. [ 8] = RCAR_GP_PIN(1, 20), /* /CTS0 */
  2826. [ 9] = RCAR_GP_PIN(1, 21), /* /RTS0 */
  2827. [10] = RCAR_GP_PIN(3, 19), /* HSPI_CLK0 */
  2828. [11] = RCAR_GP_PIN(3, 20), /* /HSPI_CS0 */
  2829. [12] = RCAR_GP_PIN(3, 21), /* HSPI_RX0 */
  2830. [13] = RCAR_GP_PIN(3, 22), /* HSPI_TX0 */
  2831. [14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */
  2832. [15] = RCAR_GP_PIN(4, 25), /* AVS1 */
  2833. [16] = RCAR_GP_PIN(4, 26), /* AVS2 */
  2834. [17] = SH_PFC_PIN_NONE,
  2835. [18] = SH_PFC_PIN_NONE,
  2836. [19] = SH_PFC_PIN_NONE,
  2837. [20] = SH_PFC_PIN_NONE,
  2838. [21] = SH_PFC_PIN_NONE,
  2839. [22] = SH_PFC_PIN_NONE,
  2840. [23] = SH_PFC_PIN_NONE,
  2841. [24] = SH_PFC_PIN_NONE,
  2842. [25] = SH_PFC_PIN_NONE,
  2843. [26] = SH_PFC_PIN_NONE,
  2844. [27] = SH_PFC_PIN_NONE,
  2845. [28] = SH_PFC_PIN_NONE,
  2846. [29] = SH_PFC_PIN_NONE,
  2847. [30] = SH_PFC_PIN_NONE,
  2848. [31] = SH_PFC_PIN_NONE,
  2849. } },
  2850. { /* sentinel */ },
  2851. };
  2852. static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
  2853. unsigned int pin)
  2854. {
  2855. const struct pinmux_bias_reg *reg;
  2856. void __iomem *addr;
  2857. unsigned int bit;
  2858. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  2859. if (!reg)
  2860. return PIN_CONFIG_BIAS_DISABLE;
  2861. addr = pfc->windows->virt + reg->puen;
  2862. if (ioread32(addr) & BIT(bit))
  2863. return PIN_CONFIG_BIAS_PULL_UP;
  2864. else
  2865. return PIN_CONFIG_BIAS_DISABLE;
  2866. }
  2867. static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  2868. unsigned int bias)
  2869. {
  2870. const struct pinmux_bias_reg *reg;
  2871. void __iomem *addr;
  2872. unsigned int bit;
  2873. u32 value;
  2874. reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
  2875. if (!reg)
  2876. return;
  2877. addr = pfc->windows->virt + reg->puen;
  2878. value = ioread32(addr) & ~BIT(bit);
  2879. if (bias == PIN_CONFIG_BIAS_PULL_UP)
  2880. value |= BIT(bit);
  2881. iowrite32(value, addr);
  2882. }
  2883. static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
  2884. .get_bias = r8a7778_pinmux_get_bias,
  2885. .set_bias = r8a7778_pinmux_set_bias,
  2886. };
  2887. const struct sh_pfc_soc_info r8a7778_pinmux_info = {
  2888. .name = "r8a7778_pfc",
  2889. .ops = &r8a7778_pfc_ops,
  2890. .unlock_reg = 0xfffc0000, /* PMMR */
  2891. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  2892. .pins = pinmux_pins,
  2893. .nr_pins = ARRAY_SIZE(pinmux_pins),
  2894. .groups = pinmux_groups,
  2895. .nr_groups = ARRAY_SIZE(pinmux_groups),
  2896. .functions = pinmux_functions,
  2897. .nr_functions = ARRAY_SIZE(pinmux_functions),
  2898. .cfg_regs = pinmux_config_regs,
  2899. .bias_regs = pinmux_bias_regs,
  2900. .pinmux_data = pinmux_data,
  2901. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  2902. };