pfc-r8a77470.c 112 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A77470 processor support - PFC hardware block.
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Corp.
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/kernel.h>
  9. #include "sh_pfc.h"
  10. #define CPU_ALL_GP(fn, sfx) \
  11. PORT_GP_4(0, fn, sfx), \
  12. PORT_GP_1(0, 4, fn, sfx), \
  13. PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  14. PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  15. PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  16. PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  17. PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  18. PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  19. PORT_GP_1(0, 11, fn, sfx), \
  20. PORT_GP_1(0, 12, fn, sfx), \
  21. PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  22. PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  23. PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  24. PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  25. PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  26. PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  27. PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  28. PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  29. PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  30. PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  31. PORT_GP_23(1, fn, sfx), \
  32. PORT_GP_32(2, fn, sfx), \
  33. PORT_GP_17(3, fn, sfx), \
  34. PORT_GP_1(3, 27, fn, sfx), \
  35. PORT_GP_1(3, 28, fn, sfx), \
  36. PORT_GP_1(3, 29, fn, sfx), \
  37. PORT_GP_14(4, fn, sfx), \
  38. PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  39. PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  40. PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  41. PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  42. PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  43. PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
  44. PORT_GP_1(4, 20, fn, sfx), \
  45. PORT_GP_1(4, 21, fn, sfx), \
  46. PORT_GP_1(4, 22, fn, sfx), \
  47. PORT_GP_1(4, 23, fn, sfx), \
  48. PORT_GP_1(4, 24, fn, sfx), \
  49. PORT_GP_1(4, 25, fn, sfx), \
  50. PORT_GP_32(5, fn, sfx)
  51. enum {
  52. PINMUX_RESERVED = 0,
  53. PINMUX_DATA_BEGIN,
  54. GP_ALL(DATA),
  55. PINMUX_DATA_END,
  56. PINMUX_FUNCTION_BEGIN,
  57. GP_ALL(FN),
  58. /* GPSR0 */
  59. FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
  60. FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
  61. FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
  62. FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
  63. FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
  64. FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
  65. /* GPSR1 */
  66. FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
  67. FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
  68. FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
  69. FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
  70. FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
  71. /* GPSR2 */
  72. FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
  73. FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
  74. FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
  75. FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
  76. FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
  77. FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
  78. FN_IP7_31_28, FN_IP8_3_0,
  79. /* GPSR3 */
  80. FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
  81. FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
  82. FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
  83. FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
  84. /* GPSR4 */
  85. FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
  86. FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
  87. FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
  88. FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
  89. FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
  90. FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
  91. /* GPSR5 */
  92. FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
  93. FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
  94. FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
  95. FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
  96. FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
  97. FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
  98. FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
  99. /* IPSR0 */
  100. FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
  101. FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
  102. FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
  103. FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
  104. FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
  105. FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
  106. FN_SD0_CD, FN_CAN0_RX_A,
  107. FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
  108. /* IPSR1 */
  109. FN_MMC0_D4, FN_SD1_CD,
  110. FN_MMC0_D5, FN_SD1_WP,
  111. FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
  112. FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
  113. FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
  114. FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
  115. FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
  116. FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
  117. /* IPSR2 */
  118. FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
  119. FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
  120. FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
  121. FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
  122. FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
  123. FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
  124. FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
  125. FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C,
  126. /* IPSR3 */
  127. FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
  128. FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
  129. FN_QSPI0_SPCLK, FN_WE0_N,
  130. FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
  131. FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
  132. FN_QSPI0_IO2, FN_CS0_N,
  133. FN_QSPI0_IO3, FN_RD_N,
  134. FN_QSPI0_SSL, FN_WE1_N,
  135. /* IPSR4 */
  136. FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
  137. FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
  138. FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
  139. FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
  140. FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
  141. FN_DU0_DR4, FN_RX1_D, FN_A4,
  142. FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
  143. FN_DU0_DR6, FN_RX2_C, FN_A6,
  144. /* IPSR5 */
  145. FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
  146. FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
  147. FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
  148. FN_DU0_DG2, FN_RX4_D, FN_A10,
  149. FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
  150. FN_DU0_DG4, FN_HRX0_A, FN_A12,
  151. FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
  152. FN_DU0_DG6, FN_HRX1_C, FN_A14,
  153. /* IPSR6 */
  154. FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
  155. FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
  156. FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
  157. FN_DU0_DB2, FN_HCTS0_N, FN_A18,
  158. FN_DU0_DB3, FN_HRTS0_N, FN_A19,
  159. FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
  160. FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
  161. FN_DU0_DB6, FN_A22,
  162. /* IPSR7 */
  163. FN_DU0_DB7, FN_A23,
  164. FN_DU0_DOTCLKIN, FN_A24,
  165. FN_DU0_DOTCLKOUT0, FN_A25,
  166. FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
  167. FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
  168. FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
  169. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
  170. FN_DU0_DISP, FN_CAN1_RX_C,
  171. /* IPSR8 */
  172. FN_DU0_CDE, FN_CAN1_TX_C,
  173. FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
  174. FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
  175. FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
  176. FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
  177. FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
  178. FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
  179. FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
  180. /* IPSR9 */
  181. FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
  182. FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
  183. FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
  184. FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
  185. FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
  186. FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
  187. FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
  188. FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
  189. /* IPSR10 */
  190. FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
  191. FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
  192. FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
  193. FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
  194. FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
  195. FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
  196. FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
  197. FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
  198. /* IPSR11 */
  199. FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
  200. FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
  201. FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
  202. FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
  203. FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
  204. FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
  205. FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
  206. FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
  207. /* IPSR12 */
  208. FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
  209. FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
  210. FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
  211. FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
  212. FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
  213. FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
  214. FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
  215. FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
  216. /* IPSR13 */
  217. FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
  218. FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
  219. FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
  220. FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
  221. FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
  222. FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
  223. FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
  224. FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
  225. /* IPSR14 */
  226. FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
  227. FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
  228. FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
  229. FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
  230. FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
  231. FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
  232. FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
  233. FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
  234. /* IPSR15 */
  235. FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
  236. FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
  237. FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
  238. FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
  239. FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
  240. FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
  241. FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
  242. FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
  243. /* IPSR16 */
  244. FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
  245. FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
  246. FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7,
  247. FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
  248. FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
  249. FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
  250. FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
  251. FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
  252. /* IPSR17 */
  253. FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
  254. FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
  255. FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
  256. FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
  257. FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
  258. FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
  259. FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
  260. /* MOD_SEL0 */
  261. FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
  262. FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
  263. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  264. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  265. FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
  266. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
  267. FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
  268. FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
  269. FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
  270. FN_SEL_AVB_0, FN_SEL_AVB_1,
  271. /* MOD_SEL1 */
  272. FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
  273. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
  274. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4,
  275. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
  276. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
  277. FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
  278. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
  279. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  280. FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
  281. FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
  282. FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
  283. FN_SEL_RCN_0, FN_SEL_RCN_1,
  284. FN_SEL_TMU2_0, FN_SEL_TMU2_1,
  285. FN_SEL_TMU1_0, FN_SEL_TMU1_1,
  286. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
  287. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
  288. /* MOD_SEL2 */
  289. FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
  290. FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
  291. FN_SEL_SSI9_0, FN_SEL_SSI9_1,
  292. FN_SEL_SSI8_0, FN_SEL_SSI8_1,
  293. FN_SEL_SSI7_0, FN_SEL_SSI7_1,
  294. FN_SEL_SSI6_0, FN_SEL_SSI6_1,
  295. FN_SEL_SSI5_0, FN_SEL_SSI5_1,
  296. FN_SEL_SSI4_0, FN_SEL_SSI4_1,
  297. FN_SEL_SSI2_0, FN_SEL_SSI2_1,
  298. FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
  299. FN_SEL_SSI0_0, FN_SEL_SSI0_1,
  300. PINMUX_FUNCTION_END,
  301. PINMUX_MARK_BEGIN,
  302. USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
  303. CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
  304. MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
  305. MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
  306. MMC0_D7_MARK,
  307. /* IPSR0 */
  308. SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
  309. SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
  310. SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
  311. SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
  312. SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
  313. SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
  314. SD0_CD_MARK, CAN0_RX_A_MARK,
  315. SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK,
  316. /* IPSR1 */
  317. MMC0_D4_MARK, SD1_CD_MARK,
  318. MMC0_D5_MARK, SD1_WP_MARK,
  319. D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK,
  320. D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
  321. D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
  322. D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
  323. D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
  324. D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
  325. /* IPSR2 */
  326. D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
  327. D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
  328. D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK,
  329. D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
  330. D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
  331. D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
  332. D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
  333. D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
  334. /* IPSR3 */
  335. D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
  336. D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
  337. QSPI0_SPCLK_MARK, WE0_N_MARK,
  338. QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
  339. QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
  340. QSPI0_IO2_MARK, CS0_N_MARK,
  341. QSPI0_IO3_MARK, RD_N_MARK,
  342. QSPI0_SSL_MARK, WE1_N_MARK,
  343. /* IPSR4 */
  344. EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
  345. DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
  346. DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
  347. DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
  348. DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
  349. DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
  350. DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
  351. DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
  352. /* IPSR5 */
  353. DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
  354. DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
  355. DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
  356. DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
  357. DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
  358. DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
  359. DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
  360. DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
  361. /* IPSR6 */
  362. DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
  363. DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
  364. DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
  365. DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
  366. DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
  367. DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
  368. DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
  369. DU0_DB6_MARK, A22_MARK,
  370. /* IPSR7 */
  371. DU0_DB7_MARK, A23_MARK,
  372. DU0_DOTCLKIN_MARK, A24_MARK,
  373. DU0_DOTCLKOUT0_MARK, A25_MARK,
  374. DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
  375. DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
  376. DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
  377. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
  378. DU0_DISP_MARK, CAN1_RX_C_MARK,
  379. /* IPSR8 */
  380. DU0_CDE_MARK, CAN1_TX_C_MARK,
  381. VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
  382. VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
  383. VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
  384. VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
  385. VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
  386. VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
  387. VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
  388. /* IPSR9 */
  389. VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
  390. VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK,
  391. VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
  392. VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
  393. VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
  394. VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
  395. VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
  396. VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
  397. /* IPSR10 */
  398. VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
  399. VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
  400. AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
  401. AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
  402. AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
  403. SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
  404. SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
  405. SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
  406. /* IPSR11 */
  407. SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
  408. MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
  409. MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
  410. MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
  411. MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
  412. MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
  413. MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
  414. HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
  415. /* IPSR12 */
  416. HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
  417. HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
  418. HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
  419. SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
  420. SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
  421. SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
  422. SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
  423. SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
  424. /* IPSR13 */
  425. SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
  426. SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
  427. SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
  428. RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
  429. TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
  430. SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
  431. SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
  432. SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
  433. /* IPSR14 */
  434. SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
  435. SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
  436. SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
  437. SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
  438. SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
  439. SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
  440. SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
  441. SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
  442. /* IPSR15 */
  443. SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
  444. SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
  445. SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
  446. SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
  447. SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
  448. SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
  449. SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
  450. SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
  451. /* IPSR16 */
  452. SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
  453. SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
  454. SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
  455. SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
  456. SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
  457. SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
  458. SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
  459. SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
  460. /* IPSR17 */
  461. SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
  462. SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
  463. SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
  464. AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
  465. AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK,
  466. AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
  467. AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
  468. PINMUX_MARK_END,
  469. };
  470. static const u16 pinmux_data[] = {
  471. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  472. PINMUX_SINGLE(USB0_PWEN),
  473. PINMUX_SINGLE(USB0_OVC),
  474. PINMUX_SINGLE(USB1_PWEN),
  475. PINMUX_SINGLE(USB1_OVC),
  476. PINMUX_SINGLE(CLKOUT),
  477. PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
  478. PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
  479. PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
  480. PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
  481. PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
  482. PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
  483. PINMUX_SINGLE(MMC0_D6),
  484. PINMUX_SINGLE(MMC0_D7),
  485. /* IPSR0 */
  486. PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
  487. PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
  488. PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
  489. PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
  490. PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
  491. PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
  492. PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
  493. PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
  494. PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
  495. PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
  496. PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
  497. PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
  498. PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
  499. PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
  500. PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
  501. PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
  502. PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
  503. PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
  504. PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
  505. PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
  506. PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
  507. PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
  508. PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
  509. /* IPSR1 */
  510. PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
  511. PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
  512. PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
  513. PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
  514. PINMUX_IPSR_GPSR(IP1_11_8, D0),
  515. PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
  516. PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
  517. PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
  518. PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
  519. PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
  520. PINMUX_IPSR_GPSR(IP1_15_12, D1),
  521. PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
  522. PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
  523. PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
  524. PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
  525. PINMUX_IPSR_GPSR(IP1_19_16, D2),
  526. PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
  527. PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
  528. PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
  529. PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
  530. PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
  531. PINMUX_IPSR_GPSR(IP1_23_20, D3),
  532. PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
  533. PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
  534. PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
  535. PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
  536. PINMUX_IPSR_GPSR(IP1_27_24, D4),
  537. PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
  538. PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
  539. PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
  540. PINMUX_IPSR_GPSR(IP1_31_28, D5),
  541. PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
  542. PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
  543. PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
  544. PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
  545. /* IPSR2 */
  546. PINMUX_IPSR_GPSR(IP2_3_0, D6),
  547. PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
  548. PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
  549. PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
  550. PINMUX_IPSR_GPSR(IP2_7_4, D7),
  551. PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
  552. PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
  553. PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
  554. PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
  555. PINMUX_IPSR_GPSR(IP2_11_8, D8),
  556. PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
  557. PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
  558. PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
  559. PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
  560. PINMUX_IPSR_GPSR(IP2_15_12, D9),
  561. PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
  562. PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
  563. PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
  564. PINMUX_IPSR_GPSR(IP2_19_16, D10),
  565. PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
  566. PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
  567. PINMUX_IPSR_GPSR(IP2_23_20, D11),
  568. PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
  569. PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
  570. PINMUX_IPSR_GPSR(IP2_27_24, D12),
  571. PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
  572. PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
  573. PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
  574. PINMUX_IPSR_GPSR(IP2_31_28, D13),
  575. PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
  576. PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
  577. /* IPSR3 */
  578. PINMUX_IPSR_GPSR(IP3_3_0, D14),
  579. PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
  580. PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
  581. PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
  582. PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
  583. PINMUX_IPSR_GPSR(IP3_7_4, D15),
  584. PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
  585. PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
  586. PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
  587. PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
  588. PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
  589. PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
  590. PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
  591. PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
  592. PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
  593. PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
  594. PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
  595. PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
  596. PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
  597. PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
  598. PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
  599. PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
  600. PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
  601. /* IPSR4 */
  602. PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
  603. PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
  604. PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
  605. PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
  606. PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
  607. PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
  608. PINMUX_IPSR_GPSR(IP4_7_4, A0),
  609. PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
  610. PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
  611. PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
  612. PINMUX_IPSR_GPSR(IP4_11_8, A1),
  613. PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
  614. PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
  615. PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
  616. PINMUX_IPSR_GPSR(IP4_15_12, A2),
  617. PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
  618. PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
  619. PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
  620. PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
  621. PINMUX_IPSR_GPSR(IP4_19_16, A3),
  622. PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
  623. PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
  624. PINMUX_IPSR_GPSR(IP4_23_20, A4),
  625. PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
  626. PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
  627. PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
  628. PINMUX_IPSR_GPSR(IP4_27_24, A5),
  629. PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
  630. PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
  631. PINMUX_IPSR_GPSR(IP4_31_28, A6),
  632. /* IPSR5 */
  633. PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
  634. PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
  635. PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
  636. PINMUX_IPSR_GPSR(IP5_3_0, A7),
  637. PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
  638. PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
  639. PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
  640. PINMUX_IPSR_GPSR(IP5_7_4, A8),
  641. PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
  642. PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
  643. PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
  644. PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
  645. PINMUX_IPSR_GPSR(IP5_11_8, A9),
  646. PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
  647. PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
  648. PINMUX_IPSR_GPSR(IP5_15_12, A10),
  649. PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
  650. PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
  651. PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
  652. PINMUX_IPSR_GPSR(IP5_19_16, A11),
  653. PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
  654. PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
  655. PINMUX_IPSR_GPSR(IP5_23_20, A12),
  656. PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
  657. PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
  658. PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
  659. PINMUX_IPSR_GPSR(IP5_27_24, A13),
  660. PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
  661. PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
  662. PINMUX_IPSR_GPSR(IP5_31_28, A14),
  663. /* IPSR6 */
  664. PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
  665. PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
  666. PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
  667. PINMUX_IPSR_GPSR(IP6_3_0, A15),
  668. PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
  669. PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
  670. PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
  671. PINMUX_IPSR_GPSR(IP6_7_4, A16),
  672. PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
  673. PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
  674. PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
  675. PINMUX_IPSR_GPSR(IP6_11_8, A17),
  676. PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
  677. PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
  678. PINMUX_IPSR_GPSR(IP6_15_12, A18),
  679. PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
  680. PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
  681. PINMUX_IPSR_GPSR(IP6_19_16, A19),
  682. PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
  683. PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
  684. PINMUX_IPSR_GPSR(IP6_23_20, A20),
  685. PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
  686. PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
  687. PINMUX_IPSR_GPSR(IP6_27_24, A21),
  688. PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
  689. PINMUX_IPSR_GPSR(IP6_31_28, A22),
  690. /* IPSR7 */
  691. PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
  692. PINMUX_IPSR_GPSR(IP7_3_0, A23),
  693. PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
  694. PINMUX_IPSR_GPSR(IP7_7_4, A24),
  695. PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
  696. PINMUX_IPSR_GPSR(IP7_11_8, A25),
  697. PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
  698. PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
  699. PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
  700. PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
  701. PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
  702. PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
  703. PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
  704. PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
  705. PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
  706. PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
  707. PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
  708. PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
  709. PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
  710. PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
  711. /* IPSR8 */
  712. PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
  713. PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
  714. PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
  715. PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
  716. PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
  717. PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
  718. PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
  719. PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
  720. PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
  721. PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
  722. PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
  723. PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
  724. PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
  725. PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
  726. PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
  727. PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
  728. PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
  729. PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
  730. PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
  731. PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
  732. PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
  733. PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
  734. PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
  735. /* IPSR9 */
  736. PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
  737. PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
  738. PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
  739. PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
  740. PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
  741. PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
  742. PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
  743. PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
  744. PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
  745. PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
  746. PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
  747. PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
  748. PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
  749. PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
  750. PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
  751. PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
  752. PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
  753. PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
  754. PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
  755. PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
  756. PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
  757. PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
  758. PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
  759. PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
  760. PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
  761. PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
  762. PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
  763. PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
  764. PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
  765. PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
  766. /* IPSR10 */
  767. PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
  768. PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
  769. PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
  770. PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
  771. PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
  772. PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
  773. PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
  774. PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
  775. PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
  776. PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
  777. PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
  778. PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
  779. PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
  780. PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
  781. PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
  782. PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
  783. PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
  784. PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
  785. PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
  786. PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
  787. PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
  788. PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
  789. PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
  790. PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
  791. PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
  792. PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
  793. PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
  794. PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
  795. PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
  796. PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
  797. PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
  798. PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
  799. PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
  800. PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
  801. PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
  802. PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
  803. PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
  804. PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
  805. PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
  806. PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
  807. PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
  808. /* IPSR11 */
  809. PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
  810. PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
  811. PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
  812. PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
  813. PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
  814. PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
  815. PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
  816. PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
  817. PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
  818. PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
  819. PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
  820. PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
  821. PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
  822. PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
  823. PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
  824. PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
  825. PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
  826. PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
  827. PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
  828. PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
  829. PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
  830. PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
  831. PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
  832. PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
  833. PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
  834. PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
  835. PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
  836. PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
  837. PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
  838. PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
  839. PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
  840. PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
  841. PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
  842. PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
  843. PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
  844. PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
  845. PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
  846. PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
  847. PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
  848. PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
  849. PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
  850. PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
  851. /* IPSR12 */
  852. PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
  853. PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
  854. PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
  855. PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
  856. PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
  857. PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
  858. PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
  859. PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
  860. PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
  861. PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
  862. PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
  863. PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
  864. PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
  865. PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
  866. PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
  867. PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
  868. PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
  869. PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
  870. PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
  871. PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
  872. PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
  873. PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
  874. PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
  875. PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
  876. PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
  877. PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
  878. PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
  879. PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
  880. PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
  881. PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
  882. PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
  883. PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
  884. PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
  885. PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
  886. PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
  887. PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
  888. /* IPSR13 */
  889. PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
  890. PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
  891. PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
  892. PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
  893. PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
  894. PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
  895. PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
  896. PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
  897. PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
  898. PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
  899. PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
  900. PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
  901. PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
  902. PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
  903. PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
  904. PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
  905. PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
  906. PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
  907. PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
  908. PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
  909. PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
  910. PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
  911. PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
  912. PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
  913. PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
  914. PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
  915. PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
  916. PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
  917. PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
  918. PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
  919. PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
  920. PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
  921. PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
  922. PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
  923. PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
  924. /* IPSR14 */
  925. PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
  926. PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
  927. PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
  928. PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
  929. PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
  930. PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
  931. PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
  932. PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
  933. PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
  934. PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
  935. PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
  936. PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
  937. PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
  938. PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
  939. PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
  940. PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
  941. PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
  942. PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
  943. PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
  944. PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
  945. PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
  946. PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
  947. PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
  948. PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
  949. PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
  950. /* IPSR15 */
  951. PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
  952. PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
  953. PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
  954. PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
  955. PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
  956. PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
  957. PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
  958. PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
  959. PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
  960. PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
  961. PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
  962. PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
  963. PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
  964. PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
  965. PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
  966. PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
  967. PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
  968. PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
  969. PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
  970. PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
  971. PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
  972. PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
  973. PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
  974. PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
  975. PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
  976. PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
  977. PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
  978. PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
  979. PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
  980. PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
  981. PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
  982. PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
  983. PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
  984. PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
  985. PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
  986. /* IPSR16 */
  987. PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
  988. PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
  989. PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
  990. PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
  991. PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
  992. PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
  993. PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
  994. PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
  995. PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
  996. PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
  997. PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
  998. PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
  999. PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
  1000. PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
  1001. PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
  1002. PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
  1003. PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
  1004. PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
  1005. PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
  1006. PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
  1007. PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
  1008. PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
  1009. PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
  1010. PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
  1011. PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
  1012. PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
  1013. PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
  1014. PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
  1015. PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
  1016. PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
  1017. PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
  1018. PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
  1019. PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
  1020. PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
  1021. PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
  1022. /* IPSR17 */
  1023. PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
  1024. PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
  1025. PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
  1026. PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
  1027. PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
  1028. PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
  1029. PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
  1030. PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
  1031. PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
  1032. PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
  1033. PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
  1034. PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
  1035. PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
  1036. PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
  1037. PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
  1038. PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
  1039. PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
  1040. PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
  1041. PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
  1042. PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
  1043. PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
  1044. PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
  1045. PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
  1046. PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
  1047. PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
  1048. };
  1049. static const struct sh_pfc_pin pinmux_pins[] = {
  1050. PINMUX_GPIO_GP_ALL(),
  1051. };
  1052. /* - AVB -------------------------------------------------------------------- */
  1053. static const unsigned int avb_col_pins[] = {
  1054. RCAR_GP_PIN(5, 18),
  1055. };
  1056. static const unsigned int avb_col_mux[] = {
  1057. AVB_COL_MARK,
  1058. };
  1059. static const unsigned int avb_crs_pins[] = {
  1060. RCAR_GP_PIN(5, 17),
  1061. };
  1062. static const unsigned int avb_crs_mux[] = {
  1063. AVB_CRS_MARK,
  1064. };
  1065. static const unsigned int avb_link_pins[] = {
  1066. RCAR_GP_PIN(5, 14),
  1067. };
  1068. static const unsigned int avb_link_mux[] = {
  1069. AVB_LINK_MARK,
  1070. };
  1071. static const unsigned int avb_magic_pins[] = {
  1072. RCAR_GP_PIN(5, 15),
  1073. };
  1074. static const unsigned int avb_magic_mux[] = {
  1075. AVB_MAGIC_MARK,
  1076. };
  1077. static const unsigned int avb_phy_int_pins[] = {
  1078. RCAR_GP_PIN(5, 16),
  1079. };
  1080. static const unsigned int avb_phy_int_mux[] = {
  1081. AVB_PHY_INT_MARK,
  1082. };
  1083. static const unsigned int avb_mdio_pins[] = {
  1084. RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
  1085. };
  1086. static const unsigned int avb_mdio_mux[] = {
  1087. AVB_MDC_MARK, AVB_MDIO_MARK,
  1088. };
  1089. static const unsigned int avb_mii_tx_rx_pins[] = {
  1090. RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
  1091. RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13),
  1092. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  1093. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
  1094. RCAR_GP_PIN(3, 10),
  1095. };
  1096. static const unsigned int avb_mii_tx_rx_mux[] = {
  1097. AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
  1098. AVB_TXD3_MARK, AVB_TX_EN_MARK,
  1099. AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1100. AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
  1101. };
  1102. static const unsigned int avb_mii_tx_er_pins[] = {
  1103. RCAR_GP_PIN(5, 23),
  1104. };
  1105. static const unsigned int avb_mii_tx_er_mux[] = {
  1106. AVB_TX_ER_MARK,
  1107. };
  1108. static const unsigned int avb_gmii_tx_rx_pins[] = {
  1109. RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  1110. RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  1111. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
  1112. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
  1113. RCAR_GP_PIN(5, 23),
  1114. RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
  1115. RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
  1116. RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
  1117. RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10),
  1118. };
  1119. static const unsigned int avb_gmii_tx_rx_mux[] = {
  1120. AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK,
  1121. AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK,
  1122. AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK,
  1123. AVB_TX_ER_MARK,
  1124. AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
  1125. AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK,
  1126. AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
  1127. };
  1128. static const unsigned int avb_avtp_match_a_pins[] = {
  1129. RCAR_GP_PIN(1, 15),
  1130. };
  1131. static const unsigned int avb_avtp_match_a_mux[] = {
  1132. AVB_AVTP_MATCH_A_MARK,
  1133. };
  1134. static const unsigned int avb_avtp_capture_a_pins[] = {
  1135. RCAR_GP_PIN(1, 14),
  1136. };
  1137. static const unsigned int avb_avtp_capture_a_mux[] = {
  1138. AVB_AVTP_CAPTURE_A_MARK,
  1139. };
  1140. static const unsigned int avb_avtp_match_b_pins[] = {
  1141. RCAR_GP_PIN(5, 20),
  1142. };
  1143. static const unsigned int avb_avtp_match_b_mux[] = {
  1144. AVB_AVTP_MATCH_B_MARK,
  1145. };
  1146. static const unsigned int avb_avtp_capture_b_pins[] = {
  1147. RCAR_GP_PIN(5, 19),
  1148. };
  1149. static const unsigned int avb_avtp_capture_b_mux[] = {
  1150. AVB_AVTP_CAPTURE_B_MARK,
  1151. };
  1152. /* - DU --------------------------------------------------------------------- */
  1153. static const unsigned int du0_rgb666_pins[] = {
  1154. /* R[7:2], G[7:2], B[7:2] */
  1155. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
  1156. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
  1157. RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  1158. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1159. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
  1160. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
  1161. };
  1162. static const unsigned int du0_rgb666_mux[] = {
  1163. DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
  1164. DU0_DR3_MARK, DU0_DR2_MARK,
  1165. DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
  1166. DU0_DG3_MARK, DU0_DG2_MARK,
  1167. DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
  1168. DU0_DB3_MARK, DU0_DB2_MARK,
  1169. };
  1170. static const unsigned int du0_rgb888_pins[] = {
  1171. /* R[7:0], G[7:0], B[7:0] */
  1172. RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
  1173. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
  1174. RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
  1175. RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
  1176. RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
  1177. RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
  1178. RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
  1179. RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
  1180. RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
  1181. };
  1182. static const unsigned int du0_rgb888_mux[] = {
  1183. DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
  1184. DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
  1185. DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
  1186. DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
  1187. DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
  1188. DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
  1189. };
  1190. static const unsigned int du0_clk0_out_pins[] = {
  1191. /* DOTCLKOUT0 */
  1192. RCAR_GP_PIN(2, 25),
  1193. };
  1194. static const unsigned int du0_clk0_out_mux[] = {
  1195. DU0_DOTCLKOUT0_MARK
  1196. };
  1197. static const unsigned int du0_clk1_out_pins[] = {
  1198. /* DOTCLKOUT1 */
  1199. RCAR_GP_PIN(2, 26),
  1200. };
  1201. static const unsigned int du0_clk1_out_mux[] = {
  1202. DU0_DOTCLKOUT1_MARK
  1203. };
  1204. static const unsigned int du0_clk_in_pins[] = {
  1205. /* CLKIN */
  1206. RCAR_GP_PIN(2, 24),
  1207. };
  1208. static const unsigned int du0_clk_in_mux[] = {
  1209. DU0_DOTCLKIN_MARK
  1210. };
  1211. static const unsigned int du0_sync_pins[] = {
  1212. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1213. RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
  1214. };
  1215. static const unsigned int du0_sync_mux[] = {
  1216. DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
  1217. };
  1218. static const unsigned int du0_oddf_pins[] = {
  1219. /* EXODDF/ODDF/DISP/CDE */
  1220. RCAR_GP_PIN(2, 29),
  1221. };
  1222. static const unsigned int du0_oddf_mux[] = {
  1223. DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
  1224. };
  1225. static const unsigned int du0_cde_pins[] = {
  1226. /* CDE */
  1227. RCAR_GP_PIN(2, 31),
  1228. };
  1229. static const unsigned int du0_cde_mux[] = {
  1230. DU0_CDE_MARK,
  1231. };
  1232. static const unsigned int du0_disp_pins[] = {
  1233. /* DISP */
  1234. RCAR_GP_PIN(2, 30),
  1235. };
  1236. static const unsigned int du0_disp_mux[] = {
  1237. DU0_DISP_MARK
  1238. };
  1239. static const unsigned int du1_rgb666_pins[] = {
  1240. /* R[7:2], G[7:2], B[7:2] */
  1241. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
  1242. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
  1243. RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
  1244. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
  1245. RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
  1246. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
  1247. };
  1248. static const unsigned int du1_rgb666_mux[] = {
  1249. DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
  1250. DU1_DR3_MARK, DU1_DR2_MARK,
  1251. DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
  1252. DU1_DG3_MARK, DU1_DG2_MARK,
  1253. DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
  1254. DU1_DB3_MARK, DU1_DB2_MARK,
  1255. };
  1256. static const unsigned int du1_rgb888_pins[] = {
  1257. /* R[7:0], G[7:0], B[7:0] */
  1258. RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
  1259. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
  1260. RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
  1261. RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
  1262. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
  1263. RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
  1264. RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
  1265. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
  1266. RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
  1267. };
  1268. static const unsigned int du1_rgb888_mux[] = {
  1269. DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
  1270. DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
  1271. DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
  1272. DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
  1273. DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
  1274. DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
  1275. };
  1276. static const unsigned int du1_clk0_out_pins[] = {
  1277. /* DOTCLKOUT0 */
  1278. RCAR_GP_PIN(5, 2),
  1279. };
  1280. static const unsigned int du1_clk0_out_mux[] = {
  1281. DU1_DOTCLKOUT0_MARK
  1282. };
  1283. static const unsigned int du1_clk1_out_pins[] = {
  1284. /* DOTCLKOUT1 */
  1285. RCAR_GP_PIN(5, 0),
  1286. };
  1287. static const unsigned int du1_clk1_out_mux[] = {
  1288. DU1_DOTCLKOUT1_MARK
  1289. };
  1290. static const unsigned int du1_clk_in_pins[] = {
  1291. /* DOTCLKIN */
  1292. RCAR_GP_PIN(5, 1),
  1293. };
  1294. static const unsigned int du1_clk_in_mux[] = {
  1295. DU1_DOTCLKIN_MARK
  1296. };
  1297. static const unsigned int du1_sync_pins[] = {
  1298. /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
  1299. RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
  1300. };
  1301. static const unsigned int du1_sync_mux[] = {
  1302. DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
  1303. };
  1304. static const unsigned int du1_oddf_pins[] = {
  1305. /* EXODDF/ODDF/DISP/CDE */
  1306. RCAR_GP_PIN(5, 3),
  1307. };
  1308. static const unsigned int du1_oddf_mux[] = {
  1309. DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
  1310. };
  1311. static const unsigned int du1_cde_pins[] = {
  1312. /* CDE */
  1313. RCAR_GP_PIN(5, 7),
  1314. };
  1315. static const unsigned int du1_cde_mux[] = {
  1316. DU1_CDE_MARK
  1317. };
  1318. static const unsigned int du1_disp_pins[] = {
  1319. /* DISP */
  1320. RCAR_GP_PIN(5, 6),
  1321. };
  1322. static const unsigned int du1_disp_mux[] = {
  1323. DU1_DISP_MARK
  1324. };
  1325. /* - I2C0 ------------------------------------------------------------------- */
  1326. static const unsigned int i2c0_a_pins[] = {
  1327. /* SCL, SDA */
  1328. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  1329. };
  1330. static const unsigned int i2c0_a_mux[] = {
  1331. SCL0_A_MARK, SDA0_A_MARK,
  1332. };
  1333. static const unsigned int i2c0_b_pins[] = {
  1334. /* SCL, SDA */
  1335. RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
  1336. };
  1337. static const unsigned int i2c0_b_mux[] = {
  1338. SCL0_B_MARK, SDA0_B_MARK,
  1339. };
  1340. static const unsigned int i2c0_c_pins[] = {
  1341. /* SCL, SDA */
  1342. RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  1343. };
  1344. static const unsigned int i2c0_c_mux[] = {
  1345. SCL0_C_MARK, SDA0_C_MARK,
  1346. };
  1347. static const unsigned int i2c0_d_pins[] = {
  1348. /* SCL, SDA */
  1349. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  1350. };
  1351. static const unsigned int i2c0_d_mux[] = {
  1352. SCL0_D_MARK, SDA0_D_MARK,
  1353. };
  1354. static const unsigned int i2c0_e_pins[] = {
  1355. /* SCL, SDA */
  1356. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
  1357. };
  1358. static const unsigned int i2c0_e_mux[] = {
  1359. SCL0_E_MARK, SDA0_E_MARK,
  1360. };
  1361. /* - I2C1 ------------------------------------------------------------------- */
  1362. static const unsigned int i2c1_a_pins[] = {
  1363. /* SCL, SDA */
  1364. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  1365. };
  1366. static const unsigned int i2c1_a_mux[] = {
  1367. SCL1_A_MARK, SDA1_A_MARK,
  1368. };
  1369. static const unsigned int i2c1_b_pins[] = {
  1370. /* SCL, SDA */
  1371. RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
  1372. };
  1373. static const unsigned int i2c1_b_mux[] = {
  1374. SCL1_B_MARK, SDA1_B_MARK,
  1375. };
  1376. static const unsigned int i2c1_c_pins[] = {
  1377. /* SCL, SDA */
  1378. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
  1379. };
  1380. static const unsigned int i2c1_c_mux[] = {
  1381. SCL1_C_MARK, SDA1_C_MARK,
  1382. };
  1383. static const unsigned int i2c1_d_pins[] = {
  1384. /* SCL, SDA */
  1385. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
  1386. };
  1387. static const unsigned int i2c1_d_mux[] = {
  1388. SCL1_D_MARK, SDA1_D_MARK,
  1389. };
  1390. static const unsigned int i2c1_e_pins[] = {
  1391. /* SCL, SDA */
  1392. RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
  1393. };
  1394. static const unsigned int i2c1_e_mux[] = {
  1395. SCL1_E_MARK, SDA1_E_MARK,
  1396. };
  1397. /* - I2C2 ------------------------------------------------------------------- */
  1398. static const unsigned int i2c2_a_pins[] = {
  1399. /* SCL, SDA */
  1400. RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
  1401. };
  1402. static const unsigned int i2c2_a_mux[] = {
  1403. SCL2_A_MARK, SDA2_A_MARK,
  1404. };
  1405. static const unsigned int i2c2_b_pins[] = {
  1406. /* SCL, SDA */
  1407. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  1408. };
  1409. static const unsigned int i2c2_b_mux[] = {
  1410. SCL2_B_MARK, SDA2_B_MARK,
  1411. };
  1412. static const unsigned int i2c2_c_pins[] = {
  1413. /* SCL, SDA */
  1414. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1415. };
  1416. static const unsigned int i2c2_c_mux[] = {
  1417. SCL2_C_MARK, SDA2_C_MARK,
  1418. };
  1419. static const unsigned int i2c2_d_pins[] = {
  1420. /* SCL, SDA */
  1421. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1422. };
  1423. static const unsigned int i2c2_d_mux[] = {
  1424. SCL2_D_MARK, SDA2_D_MARK,
  1425. };
  1426. /* - I2C3 ------------------------------------------------------------------- */
  1427. static const unsigned int i2c3_a_pins[] = {
  1428. /* SCL, SDA */
  1429. RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
  1430. };
  1431. static const unsigned int i2c3_a_mux[] = {
  1432. SCL3_A_MARK, SDA3_A_MARK,
  1433. };
  1434. static const unsigned int i2c3_b_pins[] = {
  1435. /* SCL, SDA */
  1436. RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
  1437. };
  1438. static const unsigned int i2c3_b_mux[] = {
  1439. SCL3_B_MARK, SDA3_B_MARK,
  1440. };
  1441. static const unsigned int i2c3_c_pins[] = {
  1442. /* SCL, SDA */
  1443. RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
  1444. };
  1445. static const unsigned int i2c3_c_mux[] = {
  1446. SCL3_C_MARK, SDA3_C_MARK,
  1447. };
  1448. static const unsigned int i2c3_d_pins[] = {
  1449. /* SCL, SDA */
  1450. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1451. };
  1452. static const unsigned int i2c3_d_mux[] = {
  1453. SCL3_D_MARK, SDA3_D_MARK,
  1454. };
  1455. static const unsigned int i2c3_e_pins[] = {
  1456. /* SCL, SDA */
  1457. RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
  1458. };
  1459. static const unsigned int i2c3_e_mux[] = {
  1460. SCL3_E_MARK, SDA3_E_MARK,
  1461. };
  1462. /* - I2C4 ------------------------------------------------------------------- */
  1463. static const unsigned int i2c4_a_pins[] = {
  1464. /* SCL, SDA */
  1465. RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
  1466. };
  1467. static const unsigned int i2c4_a_mux[] = {
  1468. SCL4_A_MARK, SDA4_A_MARK,
  1469. };
  1470. static const unsigned int i2c4_b_pins[] = {
  1471. /* SCL, SDA */
  1472. RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
  1473. };
  1474. static const unsigned int i2c4_b_mux[] = {
  1475. SCL4_B_MARK, SDA4_B_MARK,
  1476. };
  1477. static const unsigned int i2c4_c_pins[] = {
  1478. /* SCL, SDA */
  1479. RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
  1480. };
  1481. static const unsigned int i2c4_c_mux[] = {
  1482. SCL4_C_MARK, SDA4_C_MARK,
  1483. };
  1484. static const unsigned int i2c4_d_pins[] = {
  1485. /* SCL, SDA */
  1486. RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
  1487. };
  1488. static const unsigned int i2c4_d_mux[] = {
  1489. SCL4_D_MARK, SDA4_D_MARK,
  1490. };
  1491. static const unsigned int i2c4_e_pins[] = {
  1492. /* SCL, SDA */
  1493. RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
  1494. };
  1495. static const unsigned int i2c4_e_mux[] = {
  1496. SCL4_E_MARK, SDA4_E_MARK,
  1497. };
  1498. /* - MMC -------------------------------------------------------------------- */
  1499. static const unsigned int mmc_data1_pins[] = {
  1500. /* D0 */
  1501. RCAR_GP_PIN(0, 15),
  1502. };
  1503. static const unsigned int mmc_data1_mux[] = {
  1504. MMC0_D0_SDHI1_D0_MARK,
  1505. };
  1506. static const unsigned int mmc_data4_pins[] = {
  1507. /* D[0:3] */
  1508. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
  1509. RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
  1510. };
  1511. static const unsigned int mmc_data4_mux[] = {
  1512. MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
  1513. MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
  1514. };
  1515. static const unsigned int mmc_data8_pins[] = {
  1516. /* D[0:3] */
  1517. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
  1518. RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
  1519. RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
  1520. RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
  1521. };
  1522. static const unsigned int mmc_data8_mux[] = {
  1523. MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
  1524. MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
  1525. MMC0_D4_MARK, MMC0_D5_MARK,
  1526. MMC0_D6_MARK, MMC0_D7_MARK,
  1527. };
  1528. static const unsigned int mmc_ctrl_pins[] = {
  1529. /* CLK, CMD */
  1530. RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
  1531. };
  1532. static const unsigned int mmc_ctrl_mux[] = {
  1533. MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
  1534. };
  1535. /* - QSPI ------------------------------------------------------------------- */
  1536. static const unsigned int qspi0_ctrl_pins[] = {
  1537. /* SPCLK, SSL */
  1538. RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
  1539. };
  1540. static const unsigned int qspi0_ctrl_mux[] = {
  1541. QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
  1542. };
  1543. static const unsigned int qspi0_data2_pins[] = {
  1544. /* MOSI_IO0, MISO_IO1 */
  1545. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
  1546. };
  1547. static const unsigned int qspi0_data2_mux[] = {
  1548. QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
  1549. };
  1550. static const unsigned int qspi0_data4_pins[] = {
  1551. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  1552. RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
  1553. RCAR_GP_PIN(1, 20),
  1554. };
  1555. static const unsigned int qspi0_data4_mux[] = {
  1556. QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
  1557. QSPI0_IO2_MARK, QSPI0_IO3_MARK,
  1558. };
  1559. static const unsigned int qspi1_ctrl_pins[] = {
  1560. /* SPCLK, SSL */
  1561. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
  1562. };
  1563. static const unsigned int qspi1_ctrl_mux[] = {
  1564. QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
  1565. };
  1566. static const unsigned int qspi1_data2_pins[] = {
  1567. /* MOSI_IO0, MISO_IO1 */
  1568. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1569. };
  1570. static const unsigned int qspi1_data2_mux[] = {
  1571. QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
  1572. };
  1573. static const unsigned int qspi1_data4_pins[] = {
  1574. /* MOSI_IO0, MISO_IO1, IO2, IO3 */
  1575. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
  1576. RCAR_GP_PIN(4, 8),
  1577. };
  1578. static const unsigned int qspi1_data4_mux[] = {
  1579. QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
  1580. QSPI1_IO2_MARK, QSPI1_IO3_MARK,
  1581. };
  1582. /* - SCIF0 ------------------------------------------------------------------ */
  1583. static const unsigned int scif0_data_a_pins[] = {
  1584. /* RX, TX */
  1585. RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
  1586. };
  1587. static const unsigned int scif0_data_a_mux[] = {
  1588. RX0_A_MARK, TX0_A_MARK,
  1589. };
  1590. static const unsigned int scif0_data_b_pins[] = {
  1591. /* RX, TX */
  1592. RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
  1593. };
  1594. static const unsigned int scif0_data_b_mux[] = {
  1595. RX0_B_MARK, TX0_B_MARK,
  1596. };
  1597. static const unsigned int scif0_data_c_pins[] = {
  1598. /* RX, TX */
  1599. RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
  1600. };
  1601. static const unsigned int scif0_data_c_mux[] = {
  1602. RX0_C_MARK, TX0_C_MARK,
  1603. };
  1604. static const unsigned int scif0_data_d_pins[] = {
  1605. /* RX, TX */
  1606. RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
  1607. };
  1608. static const unsigned int scif0_data_d_mux[] = {
  1609. RX0_D_MARK, TX0_D_MARK,
  1610. };
  1611. /* - SCIF1 ------------------------------------------------------------------ */
  1612. static const unsigned int scif1_data_a_pins[] = {
  1613. /* RX, TX */
  1614. RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
  1615. };
  1616. static const unsigned int scif1_data_a_mux[] = {
  1617. RX1_A_MARK, TX1_A_MARK,
  1618. };
  1619. static const unsigned int scif1_clk_a_pins[] = {
  1620. /* SCK */
  1621. RCAR_GP_PIN(4, 15),
  1622. };
  1623. static const unsigned int scif1_clk_a_mux[] = {
  1624. SCIF1_SCK_A_MARK,
  1625. };
  1626. static const unsigned int scif1_data_b_pins[] = {
  1627. /* RX, TX */
  1628. RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
  1629. };
  1630. static const unsigned int scif1_data_b_mux[] = {
  1631. RX1_B_MARK, TX1_B_MARK,
  1632. };
  1633. static const unsigned int scif1_clk_b_pins[] = {
  1634. /* SCK */
  1635. RCAR_GP_PIN(5, 18),
  1636. };
  1637. static const unsigned int scif1_clk_b_mux[] = {
  1638. SCIF1_SCK_B_MARK,
  1639. };
  1640. static const unsigned int scif1_data_c_pins[] = {
  1641. /* RX, TX */
  1642. RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
  1643. };
  1644. static const unsigned int scif1_data_c_mux[] = {
  1645. RX1_C_MARK, TX1_C_MARK,
  1646. };
  1647. static const unsigned int scif1_clk_c_pins[] = {
  1648. /* SCK */
  1649. RCAR_GP_PIN(1, 7),
  1650. };
  1651. static const unsigned int scif1_clk_c_mux[] = {
  1652. SCIF1_SCK_C_MARK,
  1653. };
  1654. static const unsigned int scif1_data_d_pins[] = {
  1655. /* RX, TX */
  1656. RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
  1657. };
  1658. static const unsigned int scif1_data_d_mux[] = {
  1659. RX1_D_MARK, TX1_D_MARK,
  1660. };
  1661. /* - SCIF2 ------------------------------------------------------------------ */
  1662. static const unsigned int scif2_data_a_pins[] = {
  1663. /* RX, TX */
  1664. RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
  1665. };
  1666. static const unsigned int scif2_data_a_mux[] = {
  1667. RX2_A_MARK, TX2_A_MARK,
  1668. };
  1669. static const unsigned int scif2_clk_a_pins[] = {
  1670. /* SCK */
  1671. RCAR_GP_PIN(4, 20),
  1672. };
  1673. static const unsigned int scif2_clk_a_mux[] = {
  1674. SCIF2_SCK_A_MARK,
  1675. };
  1676. static const unsigned int scif2_data_b_pins[] = {
  1677. /* RX, TX */
  1678. RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
  1679. };
  1680. static const unsigned int scif2_data_b_mux[] = {
  1681. RX2_B_MARK, TX2_B_MARK,
  1682. };
  1683. static const unsigned int scif2_clk_b_pins[] = {
  1684. /* SCK */
  1685. RCAR_GP_PIN(5, 27),
  1686. };
  1687. static const unsigned int scif2_clk_b_mux[] = {
  1688. SCIF2_SCK_B_MARK,
  1689. };
  1690. static const unsigned int scif2_data_c_pins[] = {
  1691. /* RX, TX */
  1692. RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
  1693. };
  1694. static const unsigned int scif2_data_c_mux[] = {
  1695. RX2_C_MARK, TX2_C_MARK,
  1696. };
  1697. /* - SCIF3 ------------------------------------------------------------------ */
  1698. static const unsigned int scif3_data_a_pins[] = {
  1699. /* RX, TX */
  1700. RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
  1701. };
  1702. static const unsigned int scif3_data_a_mux[] = {
  1703. RX3_A_MARK, TX3_A_MARK,
  1704. };
  1705. static const unsigned int scif3_clk_pins[] = {
  1706. /* SCK */
  1707. RCAR_GP_PIN(4, 21),
  1708. };
  1709. static const unsigned int scif3_clk_mux[] = {
  1710. SCIF3_SCK_MARK,
  1711. };
  1712. static const unsigned int scif3_data_b_pins[] = {
  1713. /* RX, TX */
  1714. RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
  1715. };
  1716. static const unsigned int scif3_data_b_mux[] = {
  1717. RX3_B_MARK, TX3_B_MARK,
  1718. };
  1719. static const unsigned int scif3_data_c_pins[] = {
  1720. /* RX, TX */
  1721. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  1722. };
  1723. static const unsigned int scif3_data_c_mux[] = {
  1724. RX3_C_MARK, TX3_C_MARK,
  1725. };
  1726. /* - SCIF4 ------------------------------------------------------------------ */
  1727. static const unsigned int scif4_data_a_pins[] = {
  1728. /* RX, TX */
  1729. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  1730. };
  1731. static const unsigned int scif4_data_a_mux[] = {
  1732. RX4_A_MARK, TX4_A_MARK,
  1733. };
  1734. static const unsigned int scif4_data_b_pins[] = {
  1735. /* RX, TX */
  1736. RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
  1737. };
  1738. static const unsigned int scif4_data_b_mux[] = {
  1739. RX4_B_MARK, TX4_B_MARK,
  1740. };
  1741. static const unsigned int scif4_data_c_pins[] = {
  1742. /* RX, TX */
  1743. RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
  1744. };
  1745. static const unsigned int scif4_data_c_mux[] = {
  1746. RX4_C_MARK, TX4_C_MARK,
  1747. };
  1748. static const unsigned int scif4_data_d_pins[] = {
  1749. /* RX, TX */
  1750. RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
  1751. };
  1752. static const unsigned int scif4_data_d_mux[] = {
  1753. RX4_D_MARK, TX4_D_MARK,
  1754. };
  1755. static const unsigned int scif4_data_e_pins[] = {
  1756. /* RX, TX */
  1757. RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
  1758. };
  1759. static const unsigned int scif4_data_e_mux[] = {
  1760. RX4_E_MARK, TX4_E_MARK,
  1761. };
  1762. /* - SCIF5 ------------------------------------------------------------------ */
  1763. static const unsigned int scif5_data_a_pins[] = {
  1764. /* RX, TX */
  1765. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1766. };
  1767. static const unsigned int scif5_data_a_mux[] = {
  1768. RX5_A_MARK, TX5_A_MARK,
  1769. };
  1770. static const unsigned int scif5_data_b_pins[] = {
  1771. /* RX, TX */
  1772. RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
  1773. };
  1774. static const unsigned int scif5_data_b_mux[] = {
  1775. RX5_B_MARK, TX5_B_MARK,
  1776. };
  1777. static const unsigned int scif5_data_c_pins[] = {
  1778. /* RX, TX */
  1779. RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
  1780. };
  1781. static const unsigned int scif5_data_c_mux[] = {
  1782. RX5_C_MARK, TX5_C_MARK,
  1783. };
  1784. static const unsigned int scif5_data_d_pins[] = {
  1785. /* RX, TX */
  1786. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
  1787. };
  1788. static const unsigned int scif5_data_d_mux[] = {
  1789. RX5_D_MARK, TX5_D_MARK,
  1790. };
  1791. static const unsigned int scif5_data_e_pins[] = {
  1792. /* RX, TX */
  1793. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
  1794. };
  1795. static const unsigned int scif5_data_e_mux[] = {
  1796. RX5_E_MARK, TX5_E_MARK,
  1797. };
  1798. static const unsigned int scif5_data_f_pins[] = {
  1799. /* RX, TX */
  1800. RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
  1801. };
  1802. static const unsigned int scif5_data_f_mux[] = {
  1803. RX5_F_MARK, TX5_F_MARK,
  1804. };
  1805. /* - SCIF Clock ------------------------------------------------------------- */
  1806. static const unsigned int scif_clk_a_pins[] = {
  1807. /* SCIF_CLK */
  1808. RCAR_GP_PIN(1, 22),
  1809. };
  1810. static const unsigned int scif_clk_a_mux[] = {
  1811. SCIF_CLK_A_MARK,
  1812. };
  1813. static const unsigned int scif_clk_b_pins[] = {
  1814. /* SCIF_CLK */
  1815. RCAR_GP_PIN(3, 29),
  1816. };
  1817. static const unsigned int scif_clk_b_mux[] = {
  1818. SCIF_CLK_B_MARK,
  1819. };
  1820. /* - SDHI0 ------------------------------------------------------------------ */
  1821. static const unsigned int sdhi0_data1_pins[] = {
  1822. /* D0 */
  1823. RCAR_GP_PIN(0, 7),
  1824. };
  1825. static const unsigned int sdhi0_data1_mux[] = {
  1826. SD0_DAT0_MARK,
  1827. };
  1828. static const unsigned int sdhi0_data4_pins[] = {
  1829. /* D[0:3] */
  1830. RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
  1831. RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
  1832. };
  1833. static const unsigned int sdhi0_data4_mux[] = {
  1834. SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
  1835. };
  1836. static const unsigned int sdhi0_ctrl_pins[] = {
  1837. /* CLK, CMD */
  1838. RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
  1839. };
  1840. static const unsigned int sdhi0_ctrl_mux[] = {
  1841. SD0_CLK_MARK, SD0_CMD_MARK,
  1842. };
  1843. static const unsigned int sdhi0_cd_pins[] = {
  1844. /* CD */
  1845. RCAR_GP_PIN(0, 11),
  1846. };
  1847. static const unsigned int sdhi0_cd_mux[] = {
  1848. SD0_CD_MARK,
  1849. };
  1850. static const unsigned int sdhi0_wp_pins[] = {
  1851. /* WP */
  1852. RCAR_GP_PIN(0, 12),
  1853. };
  1854. static const unsigned int sdhi0_wp_mux[] = {
  1855. SD0_WP_MARK,
  1856. };
  1857. /* - SDHI1 ------------------------------------------------------------------ */
  1858. static const unsigned int sdhi1_data1_pins[] = {
  1859. /* D0 */
  1860. RCAR_GP_PIN(0, 15),
  1861. };
  1862. static const unsigned int sdhi1_data1_mux[] = {
  1863. MMC0_D0_SDHI1_D0_MARK,
  1864. };
  1865. static const unsigned int sdhi1_data4_pins[] = {
  1866. /* D[0:3] */
  1867. RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
  1868. RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
  1869. };
  1870. static const unsigned int sdhi1_data4_mux[] = {
  1871. MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
  1872. MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
  1873. };
  1874. static const unsigned int sdhi1_ctrl_pins[] = {
  1875. /* CLK, CMD */
  1876. RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
  1877. };
  1878. static const unsigned int sdhi1_ctrl_mux[] = {
  1879. MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
  1880. };
  1881. static const unsigned int sdhi1_cd_pins[] = {
  1882. /* CD */
  1883. RCAR_GP_PIN(0, 19),
  1884. };
  1885. static const unsigned int sdhi1_cd_mux[] = {
  1886. SD1_CD_MARK,
  1887. };
  1888. static const unsigned int sdhi1_wp_pins[] = {
  1889. /* WP */
  1890. RCAR_GP_PIN(0, 20),
  1891. };
  1892. static const unsigned int sdhi1_wp_mux[] = {
  1893. SD1_WP_MARK,
  1894. };
  1895. /* - SDHI2 ------------------------------------------------------------------ */
  1896. static const unsigned int sdhi2_data1_pins[] = {
  1897. /* D0 */
  1898. RCAR_GP_PIN(4, 16),
  1899. };
  1900. static const unsigned int sdhi2_data1_mux[] = {
  1901. SD2_DAT0_MARK,
  1902. };
  1903. static const unsigned int sdhi2_data4_pins[] = {
  1904. /* D[0:3] */
  1905. RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
  1906. RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
  1907. };
  1908. static const unsigned int sdhi2_data4_mux[] = {
  1909. SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
  1910. };
  1911. static const unsigned int sdhi2_ctrl_pins[] = {
  1912. /* CLK, CMD */
  1913. RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
  1914. };
  1915. static const unsigned int sdhi2_ctrl_mux[] = {
  1916. SD2_CLK_MARK, SD2_CMD_MARK,
  1917. };
  1918. static const unsigned int sdhi2_cd_pins[] = {
  1919. /* CD */
  1920. RCAR_GP_PIN(4, 20),
  1921. };
  1922. static const unsigned int sdhi2_cd_mux[] = {
  1923. SD2_CD_MARK,
  1924. };
  1925. static const unsigned int sdhi2_wp_pins[] = {
  1926. /* WP */
  1927. RCAR_GP_PIN(4, 21),
  1928. };
  1929. static const unsigned int sdhi2_wp_mux[] = {
  1930. SD2_WP_MARK,
  1931. };
  1932. /* - USB0 ------------------------------------------------------------------- */
  1933. static const unsigned int usb0_pins[] = {
  1934. RCAR_GP_PIN(0, 0), /* PWEN */
  1935. RCAR_GP_PIN(0, 1), /* OVC */
  1936. };
  1937. static const unsigned int usb0_mux[] = {
  1938. USB0_PWEN_MARK,
  1939. USB0_OVC_MARK,
  1940. };
  1941. /* - USB1 ------------------------------------------------------------------- */
  1942. static const unsigned int usb1_pins[] = {
  1943. RCAR_GP_PIN(0, 2), /* PWEN */
  1944. RCAR_GP_PIN(0, 3), /* OVC */
  1945. };
  1946. static const unsigned int usb1_mux[] = {
  1947. USB1_PWEN_MARK,
  1948. USB1_OVC_MARK,
  1949. };
  1950. /* - VIN0 ------------------------------------------------------------------- */
  1951. static const union vin_data vin0_data_pins = {
  1952. .data24 = {
  1953. /* B */
  1954. RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
  1955. RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
  1956. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
  1957. RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
  1958. /* G */
  1959. RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
  1960. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1961. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
  1962. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
  1963. /* R */
  1964. RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
  1965. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  1966. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  1967. RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
  1968. },
  1969. };
  1970. static const union vin_data vin0_data_mux = {
  1971. .data24 = {
  1972. /* B */
  1973. VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
  1974. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  1975. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  1976. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  1977. /* G */
  1978. VI0_G0_MARK, VI0_G1_MARK,
  1979. VI0_G2_MARK, VI0_G3_MARK,
  1980. VI0_G4_MARK, VI0_G5_MARK,
  1981. VI0_G6_MARK, VI0_G7_MARK,
  1982. /* R */
  1983. VI0_R0_MARK, VI0_R1_MARK,
  1984. VI0_R2_MARK, VI0_R3_MARK,
  1985. VI0_R4_MARK, VI0_R5_MARK,
  1986. VI0_R6_MARK, VI0_R7_MARK,
  1987. },
  1988. };
  1989. static const unsigned int vin0_data18_pins[] = {
  1990. /* B */
  1991. RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
  1992. RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
  1993. RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
  1994. /* G */
  1995. RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
  1996. RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
  1997. RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
  1998. /* R */
  1999. RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
  2000. RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
  2001. RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
  2002. };
  2003. static const unsigned int vin0_data18_mux[] = {
  2004. /* B */
  2005. VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
  2006. VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
  2007. VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
  2008. /* G */
  2009. VI0_G2_MARK, VI0_G3_MARK,
  2010. VI0_G4_MARK, VI0_G5_MARK,
  2011. VI0_G6_MARK, VI0_G7_MARK,
  2012. /* R */
  2013. VI0_R2_MARK, VI0_R3_MARK,
  2014. VI0_R4_MARK, VI0_R5_MARK,
  2015. VI0_R6_MARK, VI0_R7_MARK,
  2016. };
  2017. static const unsigned int vin0_sync_pins[] = {
  2018. RCAR_GP_PIN(5, 30), /* HSYNC */
  2019. RCAR_GP_PIN(5, 31), /* VSYNC */
  2020. };
  2021. static const unsigned int vin0_sync_mux[] = {
  2022. VI0_HSYNC_N_MARK,
  2023. VI0_VSYNC_N_MARK,
  2024. };
  2025. static const unsigned int vin0_field_pins[] = {
  2026. RCAR_GP_PIN(5, 29),
  2027. };
  2028. static const unsigned int vin0_field_mux[] = {
  2029. VI0_FIELD_MARK,
  2030. };
  2031. static const unsigned int vin0_clkenb_pins[] = {
  2032. RCAR_GP_PIN(5, 28),
  2033. };
  2034. static const unsigned int vin0_clkenb_mux[] = {
  2035. VI0_CLKENB_MARK,
  2036. };
  2037. static const unsigned int vin0_clk_pins[] = {
  2038. RCAR_GP_PIN(5, 18),
  2039. };
  2040. static const unsigned int vin0_clk_mux[] = {
  2041. VI0_CLK_MARK,
  2042. };
  2043. /* - VIN1 ------------------------------------------------------------------- */
  2044. static const union vin_data12 vin1_data_pins = {
  2045. .data12 = {
  2046. RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
  2047. RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
  2048. RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
  2049. RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
  2050. RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
  2051. RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
  2052. },
  2053. };
  2054. static const union vin_data12 vin1_data_mux = {
  2055. .data12 = {
  2056. VI1_DATA0_MARK, VI1_DATA1_MARK,
  2057. VI1_DATA2_MARK, VI1_DATA3_MARK,
  2058. VI1_DATA4_MARK, VI1_DATA5_MARK,
  2059. VI1_DATA6_MARK, VI1_DATA7_MARK,
  2060. VI1_DATA8_MARK, VI1_DATA9_MARK,
  2061. VI1_DATA10_MARK, VI1_DATA11_MARK,
  2062. },
  2063. };
  2064. static const unsigned int vin1_sync_pins[] = {
  2065. RCAR_GP_PIN(3, 11), /* HSYNC */
  2066. RCAR_GP_PIN(3, 12), /* VSYNC */
  2067. };
  2068. static const unsigned int vin1_sync_mux[] = {
  2069. VI1_HSYNC_N_MARK,
  2070. VI1_VSYNC_N_MARK,
  2071. };
  2072. static const unsigned int vin1_field_pins[] = {
  2073. RCAR_GP_PIN(3, 10),
  2074. };
  2075. static const unsigned int vin1_field_mux[] = {
  2076. VI1_FIELD_MARK,
  2077. };
  2078. static const unsigned int vin1_clkenb_pins[] = {
  2079. RCAR_GP_PIN(3, 9),
  2080. };
  2081. static const unsigned int vin1_clkenb_mux[] = {
  2082. VI1_CLKENB_MARK,
  2083. };
  2084. static const unsigned int vin1_clk_pins[] = {
  2085. RCAR_GP_PIN(3, 0),
  2086. };
  2087. static const unsigned int vin1_clk_mux[] = {
  2088. VI1_CLK_MARK,
  2089. };
  2090. static const struct sh_pfc_pin_group pinmux_groups[] = {
  2091. SH_PFC_PIN_GROUP(avb_col),
  2092. SH_PFC_PIN_GROUP(avb_crs),
  2093. SH_PFC_PIN_GROUP(avb_link),
  2094. SH_PFC_PIN_GROUP(avb_magic),
  2095. SH_PFC_PIN_GROUP(avb_phy_int),
  2096. SH_PFC_PIN_GROUP(avb_mdio),
  2097. SH_PFC_PIN_GROUP(avb_mii_tx_rx),
  2098. SH_PFC_PIN_GROUP(avb_mii_tx_er),
  2099. SH_PFC_PIN_GROUP(avb_gmii_tx_rx),
  2100. SH_PFC_PIN_GROUP(avb_avtp_match_a),
  2101. SH_PFC_PIN_GROUP(avb_avtp_capture_a),
  2102. SH_PFC_PIN_GROUP(avb_avtp_match_b),
  2103. SH_PFC_PIN_GROUP(avb_avtp_capture_b),
  2104. SH_PFC_PIN_GROUP(du0_rgb666),
  2105. SH_PFC_PIN_GROUP(du0_rgb888),
  2106. SH_PFC_PIN_GROUP(du0_clk0_out),
  2107. SH_PFC_PIN_GROUP(du0_clk1_out),
  2108. SH_PFC_PIN_GROUP(du0_clk_in),
  2109. SH_PFC_PIN_GROUP(du0_sync),
  2110. SH_PFC_PIN_GROUP(du0_oddf),
  2111. SH_PFC_PIN_GROUP(du0_cde),
  2112. SH_PFC_PIN_GROUP(du0_disp),
  2113. SH_PFC_PIN_GROUP(du1_rgb666),
  2114. SH_PFC_PIN_GROUP(du1_rgb888),
  2115. SH_PFC_PIN_GROUP(du1_clk0_out),
  2116. SH_PFC_PIN_GROUP(du1_clk1_out),
  2117. SH_PFC_PIN_GROUP(du1_clk_in),
  2118. SH_PFC_PIN_GROUP(du1_sync),
  2119. SH_PFC_PIN_GROUP(du1_oddf),
  2120. SH_PFC_PIN_GROUP(du1_cde),
  2121. SH_PFC_PIN_GROUP(du1_disp),
  2122. SH_PFC_PIN_GROUP(i2c0_a),
  2123. SH_PFC_PIN_GROUP(i2c0_b),
  2124. SH_PFC_PIN_GROUP(i2c0_c),
  2125. SH_PFC_PIN_GROUP(i2c0_d),
  2126. SH_PFC_PIN_GROUP(i2c0_e),
  2127. SH_PFC_PIN_GROUP(i2c1_a),
  2128. SH_PFC_PIN_GROUP(i2c1_b),
  2129. SH_PFC_PIN_GROUP(i2c1_c),
  2130. SH_PFC_PIN_GROUP(i2c1_d),
  2131. SH_PFC_PIN_GROUP(i2c1_e),
  2132. SH_PFC_PIN_GROUP(i2c2_a),
  2133. SH_PFC_PIN_GROUP(i2c2_b),
  2134. SH_PFC_PIN_GROUP(i2c2_c),
  2135. SH_PFC_PIN_GROUP(i2c2_d),
  2136. SH_PFC_PIN_GROUP(i2c3_a),
  2137. SH_PFC_PIN_GROUP(i2c3_b),
  2138. SH_PFC_PIN_GROUP(i2c3_c),
  2139. SH_PFC_PIN_GROUP(i2c3_d),
  2140. SH_PFC_PIN_GROUP(i2c3_e),
  2141. SH_PFC_PIN_GROUP(i2c4_a),
  2142. SH_PFC_PIN_GROUP(i2c4_b),
  2143. SH_PFC_PIN_GROUP(i2c4_c),
  2144. SH_PFC_PIN_GROUP(i2c4_d),
  2145. SH_PFC_PIN_GROUP(i2c4_e),
  2146. SH_PFC_PIN_GROUP(mmc_data1),
  2147. SH_PFC_PIN_GROUP(mmc_data4),
  2148. SH_PFC_PIN_GROUP(mmc_data8),
  2149. SH_PFC_PIN_GROUP(mmc_ctrl),
  2150. SH_PFC_PIN_GROUP(qspi0_ctrl),
  2151. SH_PFC_PIN_GROUP(qspi0_data2),
  2152. SH_PFC_PIN_GROUP(qspi0_data4),
  2153. SH_PFC_PIN_GROUP(qspi1_ctrl),
  2154. SH_PFC_PIN_GROUP(qspi1_data2),
  2155. SH_PFC_PIN_GROUP(qspi1_data4),
  2156. SH_PFC_PIN_GROUP(scif0_data_a),
  2157. SH_PFC_PIN_GROUP(scif0_data_b),
  2158. SH_PFC_PIN_GROUP(scif0_data_c),
  2159. SH_PFC_PIN_GROUP(scif0_data_d),
  2160. SH_PFC_PIN_GROUP(scif1_data_a),
  2161. SH_PFC_PIN_GROUP(scif1_clk_a),
  2162. SH_PFC_PIN_GROUP(scif1_data_b),
  2163. SH_PFC_PIN_GROUP(scif1_clk_b),
  2164. SH_PFC_PIN_GROUP(scif1_data_c),
  2165. SH_PFC_PIN_GROUP(scif1_clk_c),
  2166. SH_PFC_PIN_GROUP(scif1_data_d),
  2167. SH_PFC_PIN_GROUP(scif2_data_a),
  2168. SH_PFC_PIN_GROUP(scif2_clk_a),
  2169. SH_PFC_PIN_GROUP(scif2_data_b),
  2170. SH_PFC_PIN_GROUP(scif2_clk_b),
  2171. SH_PFC_PIN_GROUP(scif2_data_c),
  2172. SH_PFC_PIN_GROUP(scif3_data_a),
  2173. SH_PFC_PIN_GROUP(scif3_clk),
  2174. SH_PFC_PIN_GROUP(scif3_data_b),
  2175. SH_PFC_PIN_GROUP(scif3_data_c),
  2176. SH_PFC_PIN_GROUP(scif4_data_a),
  2177. SH_PFC_PIN_GROUP(scif4_data_b),
  2178. SH_PFC_PIN_GROUP(scif4_data_c),
  2179. SH_PFC_PIN_GROUP(scif4_data_d),
  2180. SH_PFC_PIN_GROUP(scif4_data_e),
  2181. SH_PFC_PIN_GROUP(scif5_data_a),
  2182. SH_PFC_PIN_GROUP(scif5_data_b),
  2183. SH_PFC_PIN_GROUP(scif5_data_c),
  2184. SH_PFC_PIN_GROUP(scif5_data_d),
  2185. SH_PFC_PIN_GROUP(scif5_data_e),
  2186. SH_PFC_PIN_GROUP(scif5_data_f),
  2187. SH_PFC_PIN_GROUP(scif_clk_a),
  2188. SH_PFC_PIN_GROUP(scif_clk_b),
  2189. SH_PFC_PIN_GROUP(sdhi0_data1),
  2190. SH_PFC_PIN_GROUP(sdhi0_data4),
  2191. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  2192. SH_PFC_PIN_GROUP(sdhi0_cd),
  2193. SH_PFC_PIN_GROUP(sdhi0_wp),
  2194. SH_PFC_PIN_GROUP(sdhi1_data1),
  2195. SH_PFC_PIN_GROUP(sdhi1_data4),
  2196. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  2197. SH_PFC_PIN_GROUP(sdhi1_cd),
  2198. SH_PFC_PIN_GROUP(sdhi1_wp),
  2199. SH_PFC_PIN_GROUP(sdhi2_data1),
  2200. SH_PFC_PIN_GROUP(sdhi2_data4),
  2201. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  2202. SH_PFC_PIN_GROUP(sdhi2_cd),
  2203. SH_PFC_PIN_GROUP(sdhi2_wp),
  2204. SH_PFC_PIN_GROUP(usb0),
  2205. SH_PFC_PIN_GROUP(usb1),
  2206. VIN_DATA_PIN_GROUP(vin0_data, 24),
  2207. VIN_DATA_PIN_GROUP(vin0_data, 20),
  2208. SH_PFC_PIN_GROUP(vin0_data18),
  2209. VIN_DATA_PIN_GROUP(vin0_data, 16),
  2210. VIN_DATA_PIN_GROUP(vin0_data, 12),
  2211. VIN_DATA_PIN_GROUP(vin0_data, 10),
  2212. VIN_DATA_PIN_GROUP(vin0_data, 8),
  2213. SH_PFC_PIN_GROUP(vin0_sync),
  2214. SH_PFC_PIN_GROUP(vin0_field),
  2215. SH_PFC_PIN_GROUP(vin0_clkenb),
  2216. SH_PFC_PIN_GROUP(vin0_clk),
  2217. VIN_DATA_PIN_GROUP(vin1_data, 12),
  2218. VIN_DATA_PIN_GROUP(vin1_data, 10),
  2219. VIN_DATA_PIN_GROUP(vin1_data, 8),
  2220. SH_PFC_PIN_GROUP(vin1_sync),
  2221. SH_PFC_PIN_GROUP(vin1_field),
  2222. SH_PFC_PIN_GROUP(vin1_clkenb),
  2223. SH_PFC_PIN_GROUP(vin1_clk),
  2224. };
  2225. static const char * const avb_groups[] = {
  2226. "avb_col",
  2227. "avb_crs",
  2228. "avb_link",
  2229. "avb_magic",
  2230. "avb_phy_int",
  2231. "avb_mdio",
  2232. "avb_mii_tx_rx",
  2233. "avb_mii_tx_er",
  2234. "avb_gmii_tx_rx",
  2235. "avb_avtp_match_a",
  2236. "avb_avtp_capture_a",
  2237. "avb_avtp_match_b",
  2238. "avb_avtp_capture_b",
  2239. };
  2240. static const char * const du0_groups[] = {
  2241. "du0_rgb666",
  2242. "du0_rgb888",
  2243. "du0_clk0_out",
  2244. "du0_clk1_out",
  2245. "du0_clk_in",
  2246. "du0_sync",
  2247. "du0_oddf",
  2248. "du0_cde",
  2249. "du0_disp",
  2250. };
  2251. static const char * const du1_groups[] = {
  2252. "du1_rgb666",
  2253. "du1_rgb888",
  2254. "du1_clk0_out",
  2255. "du1_clk1_out",
  2256. "du1_clk_in",
  2257. "du1_sync",
  2258. "du1_oddf",
  2259. "du1_cde",
  2260. "du1_disp",
  2261. };
  2262. static const char * const i2c0_groups[] = {
  2263. "i2c0_a",
  2264. "i2c0_b",
  2265. "i2c0_c",
  2266. "i2c0_d",
  2267. "i2c0_e",
  2268. };
  2269. static const char * const i2c1_groups[] = {
  2270. "i2c1_a",
  2271. "i2c1_b",
  2272. "i2c1_c",
  2273. "i2c1_d",
  2274. "i2c1_e",
  2275. };
  2276. static const char * const i2c2_groups[] = {
  2277. "i2c2_a",
  2278. "i2c2_b",
  2279. "i2c2_c",
  2280. "i2c2_d",
  2281. };
  2282. static const char * const i2c3_groups[] = {
  2283. "i2c3_a",
  2284. "i2c3_b",
  2285. "i2c3_c",
  2286. "i2c3_d",
  2287. "i2c3_e",
  2288. };
  2289. static const char * const i2c4_groups[] = {
  2290. "i2c4_a",
  2291. "i2c4_b",
  2292. "i2c4_c",
  2293. "i2c4_d",
  2294. "i2c4_e",
  2295. };
  2296. static const char * const mmc_groups[] = {
  2297. "mmc_data1",
  2298. "mmc_data4",
  2299. "mmc_data8",
  2300. "mmc_ctrl",
  2301. };
  2302. static const char * const qspi0_groups[] = {
  2303. "qspi0_ctrl",
  2304. "qspi0_data2",
  2305. "qspi0_data4",
  2306. };
  2307. static const char * const qspi1_groups[] = {
  2308. "qspi1_ctrl",
  2309. "qspi1_data2",
  2310. "qspi1_data4",
  2311. };
  2312. static const char * const scif0_groups[] = {
  2313. "scif0_data_a",
  2314. "scif0_data_b",
  2315. "scif0_data_c",
  2316. "scif0_data_d",
  2317. };
  2318. static const char * const scif1_groups[] = {
  2319. "scif1_data_a",
  2320. "scif1_clk_a",
  2321. "scif1_data_b",
  2322. "scif1_clk_b",
  2323. "scif1_data_c",
  2324. "scif1_clk_c",
  2325. "scif1_data_d",
  2326. };
  2327. static const char * const scif2_groups[] = {
  2328. "scif2_data_a",
  2329. "scif2_clk_a",
  2330. "scif2_data_b",
  2331. "scif2_clk_b",
  2332. "scif2_data_c",
  2333. };
  2334. static const char * const scif3_groups[] = {
  2335. "scif3_data_a",
  2336. "scif3_clk",
  2337. "scif3_data_b",
  2338. "scif3_data_c",
  2339. };
  2340. static const char * const scif4_groups[] = {
  2341. "scif4_data_a",
  2342. "scif4_data_b",
  2343. "scif4_data_c",
  2344. "scif4_data_d",
  2345. "scif4_data_e",
  2346. };
  2347. static const char * const scif5_groups[] = {
  2348. "scif5_data_a",
  2349. "scif5_data_b",
  2350. "scif5_data_c",
  2351. "scif5_data_d",
  2352. "scif5_data_e",
  2353. "scif5_data_f",
  2354. };
  2355. static const char * const scif_clk_groups[] = {
  2356. "scif_clk_a",
  2357. "scif_clk_b",
  2358. };
  2359. static const char * const sdhi0_groups[] = {
  2360. "sdhi0_data1",
  2361. "sdhi0_data4",
  2362. "sdhi0_ctrl",
  2363. "sdhi0_cd",
  2364. "sdhi0_wp",
  2365. };
  2366. static const char * const sdhi1_groups[] = {
  2367. "sdhi1_data1",
  2368. "sdhi1_data4",
  2369. "sdhi1_ctrl",
  2370. "sdhi1_cd",
  2371. "sdhi1_wp",
  2372. };
  2373. static const char * const sdhi2_groups[] = {
  2374. "sdhi2_data1",
  2375. "sdhi2_data4",
  2376. "sdhi2_ctrl",
  2377. "sdhi2_cd",
  2378. "sdhi2_wp",
  2379. };
  2380. static const char * const usb0_groups[] = {
  2381. "usb0",
  2382. };
  2383. static const char * const usb1_groups[] = {
  2384. "usb1",
  2385. };
  2386. static const char * const vin0_groups[] = {
  2387. "vin0_data24",
  2388. "vin0_data20",
  2389. "vin0_data18",
  2390. "vin0_data16",
  2391. "vin0_data12",
  2392. "vin0_data10",
  2393. "vin0_data8",
  2394. "vin0_sync",
  2395. "vin0_field",
  2396. "vin0_clkenb",
  2397. "vin0_clk",
  2398. };
  2399. static const char * const vin1_groups[] = {
  2400. "vin1_data12",
  2401. "vin1_data10",
  2402. "vin1_data8",
  2403. "vin1_sync",
  2404. "vin1_field",
  2405. "vin1_clkenb",
  2406. "vin1_clk",
  2407. };
  2408. static const struct sh_pfc_function pinmux_functions[] = {
  2409. SH_PFC_FUNCTION(avb),
  2410. SH_PFC_FUNCTION(du0),
  2411. SH_PFC_FUNCTION(du1),
  2412. SH_PFC_FUNCTION(i2c0),
  2413. SH_PFC_FUNCTION(i2c1),
  2414. SH_PFC_FUNCTION(i2c2),
  2415. SH_PFC_FUNCTION(i2c3),
  2416. SH_PFC_FUNCTION(i2c4),
  2417. SH_PFC_FUNCTION(mmc),
  2418. SH_PFC_FUNCTION(qspi0),
  2419. SH_PFC_FUNCTION(qspi1),
  2420. SH_PFC_FUNCTION(scif0),
  2421. SH_PFC_FUNCTION(scif1),
  2422. SH_PFC_FUNCTION(scif2),
  2423. SH_PFC_FUNCTION(scif3),
  2424. SH_PFC_FUNCTION(scif4),
  2425. SH_PFC_FUNCTION(scif5),
  2426. SH_PFC_FUNCTION(scif_clk),
  2427. SH_PFC_FUNCTION(sdhi0),
  2428. SH_PFC_FUNCTION(sdhi1),
  2429. SH_PFC_FUNCTION(sdhi2),
  2430. SH_PFC_FUNCTION(usb0),
  2431. SH_PFC_FUNCTION(usb1),
  2432. SH_PFC_FUNCTION(vin0),
  2433. SH_PFC_FUNCTION(vin1),
  2434. };
  2435. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  2436. { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
  2437. 0, 0,
  2438. 0, 0,
  2439. 0, 0,
  2440. 0, 0,
  2441. 0, 0,
  2442. 0, 0,
  2443. 0, 0,
  2444. 0, 0,
  2445. 0, 0,
  2446. GP_0_22_FN, FN_MMC0_D7,
  2447. GP_0_21_FN, FN_MMC0_D6,
  2448. GP_0_20_FN, FN_IP1_7_4,
  2449. GP_0_19_FN, FN_IP1_3_0,
  2450. GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
  2451. GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
  2452. GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
  2453. GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
  2454. GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
  2455. GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
  2456. GP_0_12_FN, FN_IP0_31_28,
  2457. GP_0_11_FN, FN_IP0_27_24,
  2458. GP_0_10_FN, FN_IP0_23_20,
  2459. GP_0_9_FN, FN_IP0_19_16,
  2460. GP_0_8_FN, FN_IP0_15_12,
  2461. GP_0_7_FN, FN_IP0_11_8,
  2462. GP_0_6_FN, FN_IP0_7_4,
  2463. GP_0_5_FN, FN_IP0_3_0,
  2464. GP_0_4_FN, FN_CLKOUT,
  2465. GP_0_3_FN, FN_USB1_OVC,
  2466. GP_0_2_FN, FN_USB1_PWEN,
  2467. GP_0_1_FN, FN_USB0_OVC,
  2468. GP_0_0_FN, FN_USB0_PWEN, ))
  2469. },
  2470. { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
  2471. 0, 0,
  2472. 0, 0,
  2473. 0, 0,
  2474. 0, 0,
  2475. 0, 0,
  2476. 0, 0,
  2477. 0, 0,
  2478. 0, 0,
  2479. 0, 0,
  2480. GP_1_22_FN, FN_IP4_3_0,
  2481. GP_1_21_FN, FN_IP3_31_28,
  2482. GP_1_20_FN, FN_IP3_27_24,
  2483. GP_1_19_FN, FN_IP3_23_20,
  2484. GP_1_18_FN, FN_IP3_19_16,
  2485. GP_1_17_FN, FN_IP3_15_12,
  2486. GP_1_16_FN, FN_IP3_11_8,
  2487. GP_1_15_FN, FN_IP3_7_4,
  2488. GP_1_14_FN, FN_IP3_3_0,
  2489. GP_1_13_FN, FN_IP2_31_28,
  2490. GP_1_12_FN, FN_IP2_27_24,
  2491. GP_1_11_FN, FN_IP2_23_20,
  2492. GP_1_10_FN, FN_IP2_19_16,
  2493. GP_1_9_FN, FN_IP2_15_12,
  2494. GP_1_8_FN, FN_IP2_11_8,
  2495. GP_1_7_FN, FN_IP2_7_4,
  2496. GP_1_6_FN, FN_IP2_3_0,
  2497. GP_1_5_FN, FN_IP1_31_28,
  2498. GP_1_4_FN, FN_IP1_27_24,
  2499. GP_1_3_FN, FN_IP1_23_20,
  2500. GP_1_2_FN, FN_IP1_19_16,
  2501. GP_1_1_FN, FN_IP1_15_12,
  2502. GP_1_0_FN, FN_IP1_11_8, ))
  2503. },
  2504. { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
  2505. GP_2_31_FN, FN_IP8_3_0,
  2506. GP_2_30_FN, FN_IP7_31_28,
  2507. GP_2_29_FN, FN_IP7_27_24,
  2508. GP_2_28_FN, FN_IP7_23_20,
  2509. GP_2_27_FN, FN_IP7_19_16,
  2510. GP_2_26_FN, FN_IP7_15_12,
  2511. GP_2_25_FN, FN_IP7_11_8,
  2512. GP_2_24_FN, FN_IP7_7_4,
  2513. GP_2_23_FN, FN_IP7_3_0,
  2514. GP_2_22_FN, FN_IP6_31_28,
  2515. GP_2_21_FN, FN_IP6_27_24,
  2516. GP_2_20_FN, FN_IP6_23_20,
  2517. GP_2_19_FN, FN_IP6_19_16,
  2518. GP_2_18_FN, FN_IP6_15_12,
  2519. GP_2_17_FN, FN_IP6_11_8,
  2520. GP_2_16_FN, FN_IP6_7_4,
  2521. GP_2_15_FN, FN_IP6_3_0,
  2522. GP_2_14_FN, FN_IP5_31_28,
  2523. GP_2_13_FN, FN_IP5_27_24,
  2524. GP_2_12_FN, FN_IP5_23_20,
  2525. GP_2_11_FN, FN_IP5_19_16,
  2526. GP_2_10_FN, FN_IP5_15_12,
  2527. GP_2_9_FN, FN_IP5_11_8,
  2528. GP_2_8_FN, FN_IP5_7_4,
  2529. GP_2_7_FN, FN_IP5_3_0,
  2530. GP_2_6_FN, FN_IP4_31_28,
  2531. GP_2_5_FN, FN_IP4_27_24,
  2532. GP_2_4_FN, FN_IP4_23_20,
  2533. GP_2_3_FN, FN_IP4_19_16,
  2534. GP_2_2_FN, FN_IP4_15_12,
  2535. GP_2_1_FN, FN_IP4_11_8,
  2536. GP_2_0_FN, FN_IP4_7_4, ))
  2537. },
  2538. { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
  2539. 0, 0,
  2540. 0, 0,
  2541. GP_3_29_FN, FN_IP10_19_16,
  2542. GP_3_28_FN, FN_IP10_15_12,
  2543. GP_3_27_FN, FN_IP10_11_8,
  2544. 0, 0,
  2545. 0, 0,
  2546. 0, 0,
  2547. 0, 0,
  2548. 0, 0,
  2549. 0, 0,
  2550. 0, 0,
  2551. 0, 0,
  2552. 0, 0,
  2553. 0, 0,
  2554. GP_3_16_FN, FN_IP10_7_4,
  2555. GP_3_15_FN, FN_IP10_3_0,
  2556. GP_3_14_FN, FN_IP9_31_28,
  2557. GP_3_13_FN, FN_IP9_27_24,
  2558. GP_3_12_FN, FN_IP9_23_20,
  2559. GP_3_11_FN, FN_IP9_19_16,
  2560. GP_3_10_FN, FN_IP9_15_12,
  2561. GP_3_9_FN, FN_IP9_11_8,
  2562. GP_3_8_FN, FN_IP9_7_4,
  2563. GP_3_7_FN, FN_IP9_3_0,
  2564. GP_3_6_FN, FN_IP8_31_28,
  2565. GP_3_5_FN, FN_IP8_27_24,
  2566. GP_3_4_FN, FN_IP8_23_20,
  2567. GP_3_3_FN, FN_IP8_19_16,
  2568. GP_3_2_FN, FN_IP8_15_12,
  2569. GP_3_1_FN, FN_IP8_11_8,
  2570. GP_3_0_FN, FN_IP8_7_4, ))
  2571. },
  2572. { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
  2573. 0, 0,
  2574. 0, 0,
  2575. 0, 0,
  2576. 0, 0,
  2577. 0, 0,
  2578. 0, 0,
  2579. GP_4_25_FN, FN_IP13_27_24,
  2580. GP_4_24_FN, FN_IP13_23_20,
  2581. GP_4_23_FN, FN_IP13_19_16,
  2582. GP_4_22_FN, FN_IP13_15_12,
  2583. GP_4_21_FN, FN_IP13_11_8,
  2584. GP_4_20_FN, FN_IP13_7_4,
  2585. GP_4_19_FN, FN_IP13_3_0,
  2586. GP_4_18_FN, FN_IP12_31_28,
  2587. GP_4_17_FN, FN_IP12_27_24,
  2588. GP_4_16_FN, FN_IP12_23_20,
  2589. GP_4_15_FN, FN_IP12_19_16,
  2590. GP_4_14_FN, FN_IP12_15_12,
  2591. GP_4_13_FN, FN_IP12_11_8,
  2592. GP_4_12_FN, FN_IP12_7_4,
  2593. GP_4_11_FN, FN_IP12_3_0,
  2594. GP_4_10_FN, FN_IP11_31_28,
  2595. GP_4_9_FN, FN_IP11_27_24,
  2596. GP_4_8_FN, FN_IP11_23_20,
  2597. GP_4_7_FN, FN_IP11_19_16,
  2598. GP_4_6_FN, FN_IP11_15_12,
  2599. GP_4_5_FN, FN_IP11_11_8,
  2600. GP_4_4_FN, FN_IP11_7_4,
  2601. GP_4_3_FN, FN_IP11_3_0,
  2602. GP_4_2_FN, FN_IP10_31_28,
  2603. GP_4_1_FN, FN_IP10_27_24,
  2604. GP_4_0_FN, FN_IP10_23_20, ))
  2605. },
  2606. { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
  2607. GP_5_31_FN, FN_IP17_27_24,
  2608. GP_5_30_FN, FN_IP17_23_20,
  2609. GP_5_29_FN, FN_IP17_19_16,
  2610. GP_5_28_FN, FN_IP17_15_12,
  2611. GP_5_27_FN, FN_IP17_11_8,
  2612. GP_5_26_FN, FN_IP17_7_4,
  2613. GP_5_25_FN, FN_IP17_3_0,
  2614. GP_5_24_FN, FN_IP16_31_28,
  2615. GP_5_23_FN, FN_IP16_27_24,
  2616. GP_5_22_FN, FN_IP16_23_20,
  2617. GP_5_21_FN, FN_IP16_19_16,
  2618. GP_5_20_FN, FN_IP16_15_12,
  2619. GP_5_19_FN, FN_IP16_11_8,
  2620. GP_5_18_FN, FN_IP16_7_4,
  2621. GP_5_17_FN, FN_IP16_3_0,
  2622. GP_5_16_FN, FN_IP15_31_28,
  2623. GP_5_15_FN, FN_IP15_27_24,
  2624. GP_5_14_FN, FN_IP15_23_20,
  2625. GP_5_13_FN, FN_IP15_19_16,
  2626. GP_5_12_FN, FN_IP15_15_12,
  2627. GP_5_11_FN, FN_IP15_11_8,
  2628. GP_5_10_FN, FN_IP15_7_4,
  2629. GP_5_9_FN, FN_IP15_3_0,
  2630. GP_5_8_FN, FN_IP14_31_28,
  2631. GP_5_7_FN, FN_IP14_27_24,
  2632. GP_5_6_FN, FN_IP14_23_20,
  2633. GP_5_5_FN, FN_IP14_19_16,
  2634. GP_5_4_FN, FN_IP14_15_12,
  2635. GP_5_3_FN, FN_IP14_11_8,
  2636. GP_5_2_FN, FN_IP14_7_4,
  2637. GP_5_1_FN, FN_IP14_3_0,
  2638. GP_5_0_FN, FN_IP13_31_28, ))
  2639. },
  2640. { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
  2641. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2642. GROUP(
  2643. /* IP0_31_28 [4] */
  2644. FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
  2645. 0, 0, 0, 0, 0, 0, 0, 0,
  2646. /* IP0_27_24 [4] */
  2647. FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
  2648. 0, 0, 0, 0, 0, 0, 0, 0,
  2649. /* IP0_23_20 [4] */
  2650. FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
  2651. 0, 0, 0, 0, 0, 0, 0, 0,
  2652. /* IP0_19_16 [4] */
  2653. FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
  2654. 0, 0, 0, 0, 0, 0, 0, 0,
  2655. /* IP0_15_12 [4] */
  2656. FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
  2657. 0, 0, 0, 0, 0, 0, 0, 0,
  2658. /* IP0_11_8 [4] */
  2659. FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
  2660. 0, 0, 0, 0, 0, 0, 0, 0,
  2661. /* IP0_7_4 [4] */
  2662. FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
  2663. 0, 0, 0, 0, 0, 0, 0, 0,
  2664. /* IP0_3_0 [4] */
  2665. FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
  2666. 0, 0, 0, 0, 0, 0, 0, 0, ))
  2667. },
  2668. { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
  2669. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2670. GROUP(
  2671. /* IP1_31_28 [4] */
  2672. FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
  2673. 0, 0, 0, 0, 0, 0, 0, 0,
  2674. /* IP1_27_24 [4] */
  2675. FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
  2676. 0, 0, 0, 0, 0, 0, 0, 0,
  2677. /* IP1_23_20 [4] */
  2678. FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
  2679. FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2680. /* IP1_19_16 [4] */
  2681. FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
  2682. FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2683. /* IP1_15_12 [4] */
  2684. FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
  2685. FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2686. /* IP1_11_8 [4] */
  2687. FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
  2688. FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2689. /* IP1_7_4 [4] */
  2690. FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
  2691. 0, 0, 0, 0, 0, 0, 0, 0,
  2692. /* IP1_3_0 [4] */
  2693. FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
  2694. 0, 0, 0, 0, 0, 0, 0, 0, ))
  2695. },
  2696. { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
  2697. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2698. GROUP(
  2699. /* IP2_31_28 [4] */
  2700. FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
  2701. 0, 0, 0, 0, 0, 0, 0,
  2702. /* IP2_27_24 [4] */
  2703. FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
  2704. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2705. /* IP2_23_20 [4] */
  2706. FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
  2707. 0, 0, 0, 0, 0, 0, 0,
  2708. /* IP2_19_16 [4] */
  2709. FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
  2710. 0, 0, 0, 0, 0, 0, 0,
  2711. /* IP2_15_12 [4] */
  2712. FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
  2713. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2714. /* IP2_11_8 [4] */
  2715. FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
  2716. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2717. /* IP2_7_4 [4] */
  2718. FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
  2719. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2720. /* IP2_3_0 [4] */
  2721. FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
  2722. 0, 0, 0, 0, 0, 0, 0, 0, ))
  2723. },
  2724. { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
  2725. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2726. GROUP(
  2727. /* IP3_31_28 [4] */
  2728. FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2729. 0, 0,
  2730. /* IP3_27_24 [4] */
  2731. FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2732. 0, 0,
  2733. /* IP3_23_20 [4] */
  2734. FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2735. 0, 0,
  2736. /* IP3_19_16 [4] */
  2737. FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2738. 0, 0, 0, 0,
  2739. /* IP3_15_12 [4] */
  2740. FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2741. 0, 0, 0,
  2742. /* IP3_11_8 [4] */
  2743. FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2744. 0, 0,
  2745. /* IP3_7_4 [4] */
  2746. FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
  2747. FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2748. /* IP3_3_0 [4] */
  2749. FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
  2750. 0, FN_AVB_AVTP_CAPTURE_A,
  2751. 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
  2752. },
  2753. { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
  2754. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2755. GROUP(
  2756. /* IP4_31_28 [4] */
  2757. FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
  2758. 0, 0, 0, 0, 0, 0, 0, 0,
  2759. /* IP4_27_24 [4] */
  2760. FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
  2761. 0, 0, 0, 0, 0, 0, 0, 0,
  2762. /* IP4_23_20 [4] */
  2763. FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
  2764. 0, 0, 0, 0, 0,
  2765. /* IP4_19_16 [4] */
  2766. FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
  2767. FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2768. /* IP4_15_12 [4] */
  2769. FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
  2770. 0, 0, 0, 0, 0, 0, 0, 0,
  2771. /* IP4_11_8 [4] */
  2772. FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
  2773. 0, 0, 0, 0, 0, 0, 0, 0,
  2774. /* IP4_7_4 [4] */
  2775. FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
  2776. 0, 0, 0, 0, 0, 0, 0, 0,
  2777. /* IP4_3_0 [4] */
  2778. FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
  2779. 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
  2780. },
  2781. { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
  2782. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2783. GROUP(
  2784. /* IP5_31_28 [4] */
  2785. FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
  2786. 0, 0, 0, 0, 0, 0,
  2787. /* IP5_27_24 [4] */
  2788. FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
  2789. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2790. /* IP5_23_20 [4] */
  2791. FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
  2792. 0, 0, 0, 0, 0, 0,
  2793. /* IP5_19_16 [4] */
  2794. FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
  2795. 0, 0, 0, 0, 0, 0, 0, 0,
  2796. /* IP5_15_12 [4] */
  2797. FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
  2798. 0, 0, 0, 0, 0, 0,
  2799. /* IP5_11_8 [4] */
  2800. FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
  2801. FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2802. /* IP5_7_4 [4] */
  2803. FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
  2804. 0, 0, 0, 0, 0, 0, 0, 0,
  2805. /* IP5_3_0 [4] */
  2806. FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
  2807. 0, 0, 0, 0, 0, 0, 0, 0, ))
  2808. },
  2809. { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
  2810. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2811. GROUP(
  2812. /* IP6_31_28 [4] */
  2813. FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
  2814. 0, 0, 0, 0, 0, 0, 0,
  2815. /* IP6_27_24 [4] */
  2816. FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
  2817. FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2818. /* IP6_23_20 [4] */
  2819. FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
  2820. FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2821. /* IP6_19_16 [4] */
  2822. FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
  2823. 0, 0, 0, 0, 0, 0,
  2824. /* IP6_15_12 [4] */
  2825. FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
  2826. 0, 0, 0, 0, 0, 0,
  2827. /* IP6_11_8 [4] */
  2828. FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
  2829. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2830. /* IP6_7_4 [4] */
  2831. FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
  2832. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2833. /* IP6_3_0 [4] */
  2834. FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
  2835. 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
  2836. },
  2837. { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
  2838. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2839. GROUP(
  2840. /* IP7_31_28 [4] */
  2841. FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
  2842. 0, 0, 0, 0, 0,
  2843. /* IP7_27_24 [4] */
  2844. FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
  2845. 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2846. /* IP7_23_20 [4] */
  2847. FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
  2848. 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2849. /* IP7_19_16 [4] */
  2850. FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
  2851. 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2852. /* IP7_15_12 [4] */
  2853. FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
  2854. FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2855. /* IP7_11_8 [4] */
  2856. FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
  2857. 0, 0, 0, 0, 0,
  2858. /* IP7_7_4 [4] */
  2859. FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
  2860. 0, 0, 0, 0, 0, 0,
  2861. /* IP7_3_0 [4] */
  2862. FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
  2863. 0, 0, 0, 0, 0, 0, 0, ))
  2864. },
  2865. { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
  2866. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2867. GROUP(
  2868. /* IP8_31_28 [4] */
  2869. FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
  2870. 0, 0, 0, 0, 0, 0,
  2871. /* IP8_27_24 [4] */
  2872. FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
  2873. 0, 0, 0, 0, 0, 0,
  2874. /* IP8_23_20 [4] */
  2875. FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
  2876. 0, 0, 0, 0, 0, 0,
  2877. /* IP8_19_16 [4] */
  2878. FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
  2879. 0, 0, 0, 0, 0, 0,
  2880. /* IP8_15_12 [4] */
  2881. FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
  2882. 0, 0, 0, 0, 0, 0,
  2883. /* IP8_11_8 [4] */
  2884. FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
  2885. 0, 0, 0, 0, 0, 0, 0,
  2886. /* IP8_7_4 [4] */
  2887. FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
  2888. 0, 0, 0, 0, 0, 0, 0,
  2889. /* IP8_3_0 [4] */
  2890. FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
  2891. 0, 0, 0, 0, ))
  2892. },
  2893. { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
  2894. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2895. GROUP(
  2896. /* IP9_31_28 [4] */
  2897. FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
  2898. 0, 0, 0, 0, 0,
  2899. /* IP9_27_24 [4] */
  2900. FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
  2901. 0, 0, 0, 0, 0,
  2902. /* IP9_23_20 [4] */
  2903. FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
  2904. FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2905. /* IP9_19_16 [4] */
  2906. FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
  2907. FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2908. /* IP9_15_12 [4] */
  2909. FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
  2910. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2911. /* IP9_11_8 [4] */
  2912. FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
  2913. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2914. /* IP9_7_4 [4] */
  2915. FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
  2916. 0, 0, 0, 0, 0, 0,
  2917. /* IP9_3_0 [4] */
  2918. FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
  2919. 0, 0, 0, 0, 0, 0, ))
  2920. },
  2921. { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
  2922. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2923. GROUP(
  2924. /* IP10_31_28 [4] */
  2925. FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
  2926. FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
  2927. /* IP10_27_24 [4] */
  2928. FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
  2929. FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2930. /* IP10_23_20 [4] */
  2931. FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
  2932. FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2933. /* IP10_19_16 [4] */
  2934. FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
  2935. FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
  2936. 0, 0,
  2937. /* IP10_15_12 [4] */
  2938. FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
  2939. FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2940. /* IP10_11_8 [4] */
  2941. FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
  2942. FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2943. /* IP10_7_4 [4] */
  2944. FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
  2945. 0, 0, 0, 0, 0, 0, 0,
  2946. /* IP10_3_0 [4] */
  2947. FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
  2948. 0, 0, 0, 0, 0, 0, 0, ))
  2949. },
  2950. { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
  2951. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2952. GROUP(
  2953. /* IP11_31_28 [4] */
  2954. FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
  2955. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2956. /* IP11_27_24 [4] */
  2957. FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
  2958. FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2959. /* IP11_23_20 [4] */
  2960. FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
  2961. FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2962. /* IP11_19_16 [4] */
  2963. FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
  2964. 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
  2965. 0, 0, 0, 0,
  2966. /* IP11_15_12 [4] */
  2967. FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
  2968. 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
  2969. 0, 0, 0, 0, 0, 0, 0, 0,
  2970. /* IP11_11_8 [4] */
  2971. FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
  2972. FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
  2973. 0, 0, 0, 0, 0, 0, 0, 0,
  2974. /* IP11_7_4 [4] */
  2975. FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
  2976. FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
  2977. 0, 0, 0, 0, 0, 0, 0, 0,
  2978. /* IP11_3_0 [4] */
  2979. FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
  2980. FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
  2981. },
  2982. { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
  2983. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  2984. GROUP(
  2985. /* IP12_31_28 [4] */
  2986. FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
  2987. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2988. /* IP12_27_24 [4] */
  2989. FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
  2990. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2991. /* IP12_23_20 [4] */
  2992. FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
  2993. FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2994. /* IP12_19_16 [4] */
  2995. FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
  2996. FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2997. /* IP12_15_12 [4] */
  2998. FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
  2999. 0, 0, 0, 0, 0, 0, 0, 0,
  3000. /* IP12_11_8 [4] */
  3001. FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
  3002. 0, 0, 0, 0, 0, 0, 0, 0,
  3003. /* IP12_7_4 [4] */
  3004. FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
  3005. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3006. /* IP12_3_0 [4] */
  3007. FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
  3008. 0, 0, 0, 0, 0, 0, ))
  3009. },
  3010. { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
  3011. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  3012. GROUP(
  3013. /* IP13_31_28 [4] */
  3014. FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
  3015. 0, 0, 0, 0, 0,
  3016. /* IP13_27_24 [4] */
  3017. FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
  3018. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3019. /* IP13_23_20 [4] */
  3020. FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
  3021. FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3022. /* IP13_19_16 [4] */
  3023. FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
  3024. FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3025. /* IP13_15_12 [4] */
  3026. FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
  3027. FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
  3028. 0, 0,
  3029. /* IP13_11_8 [4] */
  3030. FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
  3031. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3032. /* IP13_7_4 [4] */
  3033. FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
  3034. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3035. /* IP13_3_0 [4] */
  3036. FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
  3037. 0, 0, 0, 0, 0, 0, 0, 0, ))
  3038. },
  3039. { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
  3040. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  3041. GROUP(
  3042. /* IP14_31_28 [4] */
  3043. FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
  3044. FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3045. /* IP14_27_24 [4] */
  3046. FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
  3047. 0, 0, 0, 0, 0,
  3048. /* IP14_23_20 [4] */
  3049. FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
  3050. 0, 0, 0, 0, 0, 0,
  3051. /* IP14_19_16 [4] */
  3052. FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
  3053. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3054. /* IP14_15_12 [4] */
  3055. FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
  3056. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3057. /* IP14_11_8 [4] */
  3058. FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
  3059. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3060. /* IP14_7_4 [4] */
  3061. FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
  3062. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3063. /* IP14_3_0 [4] */
  3064. FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
  3065. 0, 0, 0, 0, 0, 0, ))
  3066. },
  3067. { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
  3068. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  3069. GROUP(
  3070. /* IP15_31_28 [4] */
  3071. FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
  3072. 0, 0, 0, 0, 0, 0,
  3073. /* IP15_27_24 [4] */
  3074. FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
  3075. 0, 0, 0, 0, 0, 0,
  3076. /* IP15_23_20 [4] */
  3077. FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
  3078. FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3079. /* IP15_19_16 [4] */
  3080. FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
  3081. FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3082. /* IP15_15_12 [4] */
  3083. FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
  3084. FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3085. /* IP15_11_8 [4] */
  3086. FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
  3087. FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3088. /* IP15_7_4 [4] */
  3089. FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
  3090. FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3091. /* IP15_3_0 [4] */
  3092. FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
  3093. FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
  3094. },
  3095. { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
  3096. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  3097. GROUP(
  3098. /* IP16_31_28 [4] */
  3099. FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
  3100. FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3101. /* IP16_27_24 [4] */
  3102. FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
  3103. FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3104. /* IP16_23_20 [4] */
  3105. FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
  3106. FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3107. /* IP16_19_16 [4] */
  3108. FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
  3109. 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3110. /* IP16_15_12 [4] */
  3111. FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
  3112. FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
  3113. 0, 0, 0,
  3114. /* IP16_11_8 [4] */
  3115. FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
  3116. FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3117. /* IP16_7_4 [4] */
  3118. FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
  3119. FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
  3120. /* IP16_3_0 [4] */
  3121. FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
  3122. 0, 0, 0, 0, 0, 0, ))
  3123. },
  3124. { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
  3125. GROUP(4, 4, 4, 4, 4, 4, 4, 4),
  3126. GROUP(
  3127. /* IP17_31_28 [4] */
  3128. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3129. /* IP17_27_24 [4] */
  3130. FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
  3131. FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3132. /* IP17_23_20 [4] */
  3133. FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
  3134. FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3135. /* IP17_19_16 [4] */
  3136. FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
  3137. FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3138. /* IP17_15_12 [4] */
  3139. FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
  3140. FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3141. /* IP17_11_8 [4] */
  3142. FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
  3143. FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3144. /* IP17_7_4 [4] */
  3145. FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
  3146. FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3147. /* IP17_3_0 [4] */
  3148. FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
  3149. FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
  3150. },
  3151. { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
  3152. GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
  3153. 3, 3, 1, 2, 3, 3, 1),
  3154. GROUP(
  3155. /* RESERVED [1] */
  3156. 0, 0,
  3157. /* RESERVED [1] */
  3158. 0, 0,
  3159. /* RESERVED [1] */
  3160. 0, 0,
  3161. /* RESERVED [1] */
  3162. 0, 0,
  3163. /* RESERVED [1] */
  3164. 0, 0,
  3165. /* SEL_ADGA [2] */
  3166. FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
  3167. /* RESERVED [1] */
  3168. 0, 0,
  3169. /* RESERVED [1] */
  3170. 0, 0,
  3171. /* SEL_CANCLK [2] */
  3172. FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
  3173. FN_SEL_CANCLK_3,
  3174. /* SEL_CAN1 [2] */
  3175. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  3176. /* SEL_CAN0 [2] */
  3177. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  3178. /* RESERVED [1] */
  3179. 0, 0,
  3180. /* SEL_I2C04 [3] */
  3181. FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
  3182. FN_SEL_I2C04_4, 0, 0, 0,
  3183. /* SEL_I2C03 [3] */
  3184. FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
  3185. FN_SEL_I2C03_4, 0, 0, 0,
  3186. /* RESERVED [1] */
  3187. 0, 0,
  3188. /* SEL_I2C02 [2] */
  3189. FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
  3190. /* SEL_I2C01 [3] */
  3191. FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
  3192. FN_SEL_I2C01_4, 0, 0, 0,
  3193. /* SEL_I2C00 [3] */
  3194. FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
  3195. FN_SEL_I2C00_4, 0, 0, 0,
  3196. /* SEL_AVB [1] */
  3197. FN_SEL_AVB_0, FN_SEL_AVB_1, ))
  3198. },
  3199. { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
  3200. GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
  3201. 1, 1, 2, 1, 1, 2, 2, 1),
  3202. GROUP(
  3203. /* SEL_SCIFCLK [1] */
  3204. FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
  3205. /* SEL_SCIF5 [3] */
  3206. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
  3207. FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
  3208. /* SEL_SCIF4 [3] */
  3209. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
  3210. FN_SEL_SCIF4_4, 0, 0, 0,
  3211. /* SEL_SCIF3 [2] */
  3212. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
  3213. /* SEL_SCIF2 [2] */
  3214. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
  3215. /* SEL_SCIF2_CLK [1] */
  3216. FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
  3217. /* SEL_SCIF1 [2] */
  3218. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
  3219. /* SEL_SCIF0 [2] */
  3220. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  3221. /* SEL_MSIOF2 [2] */
  3222. FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
  3223. /* RESERVED [1] */
  3224. 0, 0,
  3225. /* SEL_MSIOF1 [1] */
  3226. FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
  3227. /* RESERVED [1] */
  3228. 0, 0,
  3229. /* SEL_MSIOF0 [1] */
  3230. FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
  3231. /* SEL_RCN [1] */
  3232. FN_SEL_RCN_0, FN_SEL_RCN_1,
  3233. /* RESERVED [2] */
  3234. 0, 0, 0, 0,
  3235. /* SEL_TMU2 [1] */
  3236. FN_SEL_TMU2_0, FN_SEL_TMU2_1,
  3237. /* SEL_TMU1 [1] */
  3238. FN_SEL_TMU1_0, FN_SEL_TMU1_1,
  3239. /* RESERVED [2] */
  3240. 0, 0, 0, 0,
  3241. /* SEL_HSCIF1 [2] */
  3242. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
  3243. /* SEL_HSCIF0 [1] */
  3244. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
  3245. },
  3246. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
  3247. GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
  3248. 2, 2, 2, 2, 2, 2, 2, 2, 2),
  3249. GROUP(
  3250. /* RESERVED [1] */
  3251. 0, 0,
  3252. /* RESERVED [1] */
  3253. 0, 0,
  3254. /* RESERVED [1] */
  3255. 0, 0,
  3256. /* RESERVED [1] */
  3257. 0, 0,
  3258. /* RESERVED [1] */
  3259. 0, 0,
  3260. /* RESERVED [1] */
  3261. 0, 0,
  3262. /* RESERVED [1] */
  3263. 0, 0,
  3264. /* RESERVED [1] */
  3265. 0, 0,
  3266. /* RESERVED [1] */
  3267. 0, 0,
  3268. /* RESERVED [1] */
  3269. 0, 0,
  3270. /* SEL_ADGB [2] */
  3271. FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
  3272. /* SEL_ADGC [2] */
  3273. FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
  3274. /* SEL_SSI9 [2] */
  3275. FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
  3276. /* SEL_SSI8 [2] */
  3277. FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
  3278. /* SEL_SSI7 [2] */
  3279. FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
  3280. /* SEL_SSI6 [2] */
  3281. FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
  3282. /* SEL_SSI5 [2] */
  3283. FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
  3284. /* SEL_SSI4 [2] */
  3285. FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
  3286. /* SEL_SSI2 [2] */
  3287. FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
  3288. /* SEL_SSI1 [2] */
  3289. FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
  3290. /* SEL_SSI0 [2] */
  3291. FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
  3292. },
  3293. { },
  3294. };
  3295. static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
  3296. u32 *pocctrl)
  3297. {
  3298. int bit = -EINVAL;
  3299. *pocctrl = 0xe60600b0;
  3300. if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
  3301. bit = 0;
  3302. if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
  3303. bit = 2;
  3304. if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
  3305. bit = 1;
  3306. return bit;
  3307. }
  3308. static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
  3309. .pin_to_pocctrl = r8a77470_pin_to_pocctrl,
  3310. };
  3311. #ifdef CONFIG_PINCTRL_PFC_R8A77470
  3312. const struct sh_pfc_soc_info r8a77470_pinmux_info = {
  3313. .name = "r8a77470_pfc",
  3314. .ops = &r8a77470_pinmux_ops,
  3315. .unlock_reg = 0xe6060000, /* PMMR */
  3316. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  3317. .pins = pinmux_pins,
  3318. .nr_pins = ARRAY_SIZE(pinmux_pins),
  3319. .groups = pinmux_groups,
  3320. .nr_groups = ARRAY_SIZE(pinmux_groups),
  3321. .functions = pinmux_functions,
  3322. .nr_functions = ARRAY_SIZE(pinmux_functions),
  3323. .cfg_regs = pinmux_config_regs,
  3324. .pinmux_data = pinmux_data,
  3325. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  3326. };
  3327. #endif