pfc-r8a7740.c 113 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * R8A7740 processor support
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  7. */
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/pinctrl/pinconf-generic.h>
  11. #include "sh_pfc.h"
  12. #define CPU_ALL_PORT(fn, pfx, sfx) \
  13. PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
  14. PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
  15. PORT_10(200, fn, pfx##20, sfx), \
  16. PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
  17. #define IRQC_PIN_MUX(irq, pin) \
  18. static const unsigned int intc_irq##irq##_pins[] = { \
  19. pin, \
  20. }; \
  21. static const unsigned int intc_irq##irq##_mux[] = { \
  22. IRQ##irq##_MARK, \
  23. }
  24. #define IRQC_PINS_MUX(irq, idx, pin) \
  25. static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
  26. pin, \
  27. }; \
  28. static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
  29. IRQ##irq##_PORT##pin##_MARK, \
  30. }
  31. enum {
  32. PINMUX_RESERVED = 0,
  33. /* PORT0_DATA -> PORT211_DATA */
  34. PINMUX_DATA_BEGIN,
  35. PORT_ALL(DATA),
  36. PINMUX_DATA_END,
  37. /* PORT0_IN -> PORT211_IN */
  38. PINMUX_INPUT_BEGIN,
  39. PORT_ALL(IN),
  40. PINMUX_INPUT_END,
  41. /* PORT0_OUT -> PORT211_OUT */
  42. PINMUX_OUTPUT_BEGIN,
  43. PORT_ALL(OUT),
  44. PINMUX_OUTPUT_END,
  45. PINMUX_FUNCTION_BEGIN,
  46. PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
  47. PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
  48. PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
  49. PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
  50. PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
  51. PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
  52. PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
  53. PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
  54. PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
  55. PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
  56. MSEL1CR_31_0, MSEL1CR_31_1,
  57. MSEL1CR_30_0, MSEL1CR_30_1,
  58. MSEL1CR_29_0, MSEL1CR_29_1,
  59. MSEL1CR_28_0, MSEL1CR_28_1,
  60. MSEL1CR_27_0, MSEL1CR_27_1,
  61. MSEL1CR_26_0, MSEL1CR_26_1,
  62. MSEL1CR_16_0, MSEL1CR_16_1,
  63. MSEL1CR_15_0, MSEL1CR_15_1,
  64. MSEL1CR_14_0, MSEL1CR_14_1,
  65. MSEL1CR_13_0, MSEL1CR_13_1,
  66. MSEL1CR_12_0, MSEL1CR_12_1,
  67. MSEL1CR_9_0, MSEL1CR_9_1,
  68. MSEL1CR_7_0, MSEL1CR_7_1,
  69. MSEL1CR_6_0, MSEL1CR_6_1,
  70. MSEL1CR_5_0, MSEL1CR_5_1,
  71. MSEL1CR_4_0, MSEL1CR_4_1,
  72. MSEL1CR_3_0, MSEL1CR_3_1,
  73. MSEL1CR_2_0, MSEL1CR_2_1,
  74. MSEL1CR_0_0, MSEL1CR_0_1,
  75. MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
  76. MSEL3CR_6_0, MSEL3CR_6_1,
  77. MSEL4CR_19_0, MSEL4CR_19_1,
  78. MSEL4CR_18_0, MSEL4CR_18_1,
  79. MSEL4CR_15_0, MSEL4CR_15_1,
  80. MSEL4CR_10_0, MSEL4CR_10_1,
  81. MSEL4CR_6_0, MSEL4CR_6_1,
  82. MSEL4CR_4_0, MSEL4CR_4_1,
  83. MSEL4CR_1_0, MSEL4CR_1_1,
  84. MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
  85. MSEL5CR_30_0, MSEL5CR_30_1,
  86. MSEL5CR_29_0, MSEL5CR_29_1,
  87. MSEL5CR_27_0, MSEL5CR_27_1,
  88. MSEL5CR_25_0, MSEL5CR_25_1,
  89. MSEL5CR_23_0, MSEL5CR_23_1,
  90. MSEL5CR_21_0, MSEL5CR_21_1,
  91. MSEL5CR_19_0, MSEL5CR_19_1,
  92. MSEL5CR_17_0, MSEL5CR_17_1,
  93. MSEL5CR_15_0, MSEL5CR_15_1,
  94. MSEL5CR_14_0, MSEL5CR_14_1,
  95. MSEL5CR_13_0, MSEL5CR_13_1,
  96. MSEL5CR_12_0, MSEL5CR_12_1,
  97. MSEL5CR_11_0, MSEL5CR_11_1,
  98. MSEL5CR_10_0, MSEL5CR_10_1,
  99. MSEL5CR_8_0, MSEL5CR_8_1,
  100. MSEL5CR_7_0, MSEL5CR_7_1,
  101. MSEL5CR_6_0, MSEL5CR_6_1,
  102. MSEL5CR_5_0, MSEL5CR_5_1,
  103. MSEL5CR_4_0, MSEL5CR_4_1,
  104. MSEL5CR_3_0, MSEL5CR_3_1,
  105. MSEL5CR_2_0, MSEL5CR_2_1,
  106. MSEL5CR_0_0, MSEL5CR_0_1,
  107. PINMUX_FUNCTION_END,
  108. PINMUX_MARK_BEGIN,
  109. /* IRQ */
  110. IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
  111. IRQ1_MARK,
  112. IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
  113. IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
  114. IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
  115. IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
  116. IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
  117. IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
  118. IRQ8_MARK,
  119. IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
  120. IRQ10_MARK,
  121. IRQ11_MARK,
  122. IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
  123. IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
  124. IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
  125. IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
  126. IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
  127. IRQ17_MARK,
  128. IRQ18_MARK,
  129. IRQ19_MARK,
  130. IRQ20_MARK,
  131. IRQ21_MARK,
  132. IRQ22_MARK,
  133. IRQ23_MARK,
  134. IRQ24_MARK,
  135. IRQ25_MARK,
  136. IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
  137. IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
  138. IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
  139. IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
  140. IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
  141. IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
  142. /* Function */
  143. /* DBGT */
  144. DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
  145. DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
  146. DBGMD21_MARK,
  147. /* FSI-A */
  148. FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
  149. FSIAISLD_PORT5_MARK,
  150. FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
  151. FSIASPDIF_PORT18_MARK,
  152. FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
  153. FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
  154. FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
  155. /* FSI-B */
  156. FSIBCK_MARK,
  157. /* FMSI */
  158. FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
  159. FMSISLD_PORT6_MARK,
  160. FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
  161. FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
  162. FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
  163. /* SCIFA0 */
  164. SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
  165. SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
  166. /* SCIFA1 */
  167. SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
  168. SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
  169. /* SCIFA2 */
  170. SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
  171. SCIFA2_SCK_PORT199_MARK,
  172. SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
  173. SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
  174. /* SCIFA3 */
  175. SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
  176. SCIFA3_SCK_PORT116_MARK,
  177. SCIFA3_CTS_PORT117_MARK,
  178. SCIFA3_RXD_PORT174_MARK,
  179. SCIFA3_TXD_PORT175_MARK,
  180. SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
  181. SCIFA3_SCK_PORT158_MARK,
  182. SCIFA3_CTS_PORT162_MARK,
  183. SCIFA3_RXD_PORT159_MARK,
  184. SCIFA3_TXD_PORT160_MARK,
  185. /* SCIFA4 */
  186. SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
  187. SCIFA4_TXD_PORT13_MARK,
  188. SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
  189. SCIFA4_TXD_PORT203_MARK,
  190. SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
  191. SCIFA4_TXD_PORT93_MARK,
  192. SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
  193. SCIFA4_SCK_PORT205_MARK,
  194. /* SCIFA5 */
  195. SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
  196. SCIFA5_RXD_PORT10_MARK,
  197. SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
  198. SCIFA5_TXD_PORT208_MARK,
  199. SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
  200. SCIFA5_RXD_PORT92_MARK,
  201. SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
  202. SCIFA5_SCK_PORT206_MARK,
  203. /* SCIFA6 */
  204. SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
  205. /* SCIFA7 */
  206. SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
  207. /* SCIFB */
  208. SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
  209. SCIFB_RXD_PORT191_MARK,
  210. SCIFB_TXD_PORT192_MARK,
  211. SCIFB_RTS_PORT186_MARK,
  212. SCIFB_CTS_PORT187_MARK,
  213. SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
  214. SCIFB_RXD_PORT3_MARK,
  215. SCIFB_TXD_PORT4_MARK,
  216. SCIFB_RTS_PORT172_MARK,
  217. SCIFB_CTS_PORT173_MARK,
  218. /* LCD0 */
  219. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  220. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  221. LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
  222. LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
  223. LCD0_D16_MARK, LCD0_D17_MARK,
  224. LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
  225. LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
  226. LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
  227. LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
  228. LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
  229. LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
  230. LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
  231. LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
  232. LCD0_LCLK_PORT165_MARK,
  233. LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
  234. LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
  235. LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
  236. LCD0_LCLK_PORT102_MARK,
  237. /* LCD1 */
  238. LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
  239. LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
  240. LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
  241. LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
  242. LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
  243. LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
  244. LCD1_DON_MARK, LCD1_VCPWC_MARK,
  245. LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
  246. LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
  247. LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
  248. LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
  249. LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
  250. /* RSPI */
  251. RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
  252. RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
  253. RSPI_MISO_A_MARK,
  254. /* VIO CKO */
  255. VIO_CKO1_MARK, /* needs fixup */
  256. VIO_CKO2_MARK,
  257. VIO_CKO_1_MARK,
  258. VIO_CKO_MARK,
  259. /* VIO0 */
  260. VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
  261. VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
  262. VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
  263. VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
  264. VIO0_FIELD_MARK,
  265. VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
  266. VIO0_D14_PORT25_MARK,
  267. VIO0_D15_PORT24_MARK,
  268. VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
  269. VIO0_D14_PORT95_MARK,
  270. VIO0_D15_PORT96_MARK,
  271. /* VIO1 */
  272. VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
  273. VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
  274. VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
  275. /* TPU0 */
  276. TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
  277. TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
  278. TPU0TO2_PORT202_MARK,
  279. /* SSP1 0 */
  280. STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
  281. STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
  282. STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
  283. /* SSP1 1 */
  284. STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
  285. STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
  286. STP1_IPSYNC_MARK,
  287. STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
  288. STP1_IPEN_PORT187_MARK,
  289. STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
  290. STP1_IPEN_PORT193_MARK,
  291. /* SIM */
  292. SIM_RST_MARK, SIM_CLK_MARK,
  293. SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
  294. SIM_D_PORT199_MARK,
  295. /* SDHI0 */
  296. SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
  297. SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
  298. /* SDHI1 */
  299. SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
  300. SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
  301. /* SDHI2 */
  302. SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
  303. SDHI2_CLK_MARK, SDHI2_CMD_MARK,
  304. SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
  305. SDHI2_WP_PORT25_MARK,
  306. SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
  307. SDHI2_CD_PORT202_MARK,
  308. /* MSIOF2 */
  309. MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
  310. MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
  311. MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
  312. MSIOF2_RSCK_MARK,
  313. /* KEYSC */
  314. KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
  315. KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
  316. KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
  317. KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
  318. KEYIN1_PORT44_MARK,
  319. KEYIN2_PORT45_MARK,
  320. KEYIN3_PORT46_MARK,
  321. KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
  322. KEYIN1_PORT57_MARK,
  323. KEYIN2_PORT56_MARK,
  324. KEYIN3_PORT55_MARK,
  325. /* VOU */
  326. DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
  327. DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
  328. DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
  329. DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
  330. DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
  331. /* MEMC */
  332. MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
  333. MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
  334. MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
  335. MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
  336. MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
  337. MEMC_CS1_MARK, /* MSEL4CR_6_0 */
  338. MEMC_ADV_MARK,
  339. MEMC_WAIT_MARK,
  340. MEMC_BUSCLK_MARK,
  341. MEMC_A1_MARK, /* MSEL4CR_6_1 */
  342. MEMC_DREQ0_MARK,
  343. MEMC_DREQ1_MARK,
  344. MEMC_A0_MARK,
  345. /* MMC */
  346. MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
  347. MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
  348. MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
  349. MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
  350. MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
  351. MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
  352. MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
  353. MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
  354. /* MSIOF0 */
  355. MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
  356. MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
  357. MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
  358. MSIOF0_TSYNC_MARK,
  359. /* MSIOF1 */
  360. MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
  361. MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
  362. MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
  363. MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
  364. MSIOF1_TSYNC_PORT120_MARK,
  365. MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
  366. MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
  367. MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
  368. MSIOF1_RXD_PORT75_MARK,
  369. MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
  370. /* GPIO */
  371. GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
  372. /* USB0 */
  373. USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
  374. /* USB1 */
  375. USB1_OCI_MARK, USB1_PPON_MARK,
  376. /* BBIF1 */
  377. BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
  378. BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
  379. BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
  380. /* BBIF2 */
  381. BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
  382. BBIF2_RXD2_PORT60_MARK,
  383. BBIF2_TSYNC2_PORT6_MARK,
  384. BBIF2_TSCK2_PORT59_MARK,
  385. BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
  386. BBIF2_TXD2_PORT183_MARK,
  387. BBIF2_TSCK2_PORT89_MARK,
  388. BBIF2_TSYNC2_PORT184_MARK,
  389. /* BSC / FLCTL / PCMCIA */
  390. CS0_MARK, CS2_MARK, CS4_MARK,
  391. CS5B_MARK, CS6A_MARK,
  392. CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
  393. CS5A_PORT19_MARK,
  394. IOIS16_MARK, /* ? */
  395. A0_MARK, A1_MARK, A2_MARK, A3_MARK,
  396. A4_FOE_MARK, /* share with FLCTL */
  397. A5_FCDE_MARK, /* share with FLCTL */
  398. A6_MARK, A7_MARK, A8_MARK, A9_MARK,
  399. A10_MARK, A11_MARK, A12_MARK, A13_MARK,
  400. A14_MARK, A15_MARK, A16_MARK, A17_MARK,
  401. A18_MARK, A19_MARK, A20_MARK, A21_MARK,
  402. A22_MARK, A23_MARK, A24_MARK, A25_MARK,
  403. A26_MARK,
  404. D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
  405. D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
  406. D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
  407. D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
  408. D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
  409. D15_NAF15_MARK, /* share with FLCTL */
  410. D16_MARK, D17_MARK, D18_MARK, D19_MARK,
  411. D20_MARK, D21_MARK, D22_MARK, D23_MARK,
  412. D24_MARK, D25_MARK, D26_MARK, D27_MARK,
  413. D28_MARK, D29_MARK, D30_MARK, D31_MARK,
  414. WE0_FWE_MARK, /* share with FLCTL */
  415. WE1_MARK,
  416. WE2_ICIORD_MARK, /* share with PCMCIA */
  417. WE3_ICIOWR_MARK, /* share with PCMCIA */
  418. CKO_MARK, BS_MARK, RDWR_MARK,
  419. RD_FSC_MARK, /* share with FLCTL */
  420. WAIT_PORT177_MARK, /* WAIT Port 90/177 */
  421. WAIT_PORT90_MARK,
  422. FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
  423. /* IRDA */
  424. IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
  425. /* ATAPI */
  426. IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
  427. IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
  428. IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
  429. IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
  430. IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
  431. IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
  432. IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
  433. IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
  434. /* RMII */
  435. RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
  436. RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
  437. RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
  438. RMII_REF50CK_MARK, /* for RMII */
  439. RMII_REF125CK_MARK, /* for GMII */
  440. /* GEther */
  441. ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
  442. ET_ETXD2_MARK, ET_ETXD3_MARK,
  443. ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
  444. ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
  445. ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
  446. ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
  447. ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
  448. ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
  449. ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
  450. ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
  451. /* DMA0 */
  452. DREQ0_MARK, DACK0_MARK,
  453. /* DMA1 */
  454. DREQ1_MARK, DACK1_MARK,
  455. /* SYSC */
  456. RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
  457. /* IRREM */
  458. IROUT_MARK,
  459. /* SDENC */
  460. SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
  461. /* HDMI */
  462. HDMI_HPD_MARK, HDMI_CEC_MARK,
  463. /* DEBUG */
  464. EDEBGREQ_PULLUP_MARK, /* for JTAG */
  465. EDEBGREQ_PULLDOWN_MARK,
  466. TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
  467. TRACEAUD_FROM_LCDC0_MARK,
  468. TRACEAUD_FROM_MEMC_MARK,
  469. PINMUX_MARK_END,
  470. };
  471. static const u16 pinmux_data[] = {
  472. PINMUX_DATA_ALL(),
  473. /* Port0 */
  474. PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
  475. PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
  476. PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
  477. PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
  478. PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
  479. PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
  480. PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
  481. /* Port1 */
  482. PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
  483. PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
  484. PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
  485. PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
  486. PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
  487. PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
  488. PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
  489. /* Port2 */
  490. PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
  491. PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
  492. PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
  493. PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
  494. PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
  495. /* Port3 */
  496. PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
  497. PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
  498. PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
  499. PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
  500. /* Port4 */
  501. PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
  502. PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
  503. PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
  504. PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
  505. /* Port5 */
  506. PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
  507. PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
  508. PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
  509. PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
  510. PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
  511. /* Port6 */
  512. PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
  513. PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
  514. PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
  515. PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
  516. PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
  517. /* Port7 */
  518. PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
  519. /* Port8 */
  520. PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
  521. /* Port9 */
  522. PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
  523. PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
  524. /* Port10 */
  525. PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
  526. PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
  527. PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
  528. /* Port11 */
  529. PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
  530. PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
  531. PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
  532. /* Port12 */
  533. PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
  534. PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
  535. PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
  536. PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
  537. PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
  538. /* Port13 */
  539. PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
  540. PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
  541. PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
  542. PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
  543. /* Port14 */
  544. PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
  545. PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
  546. PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
  547. PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
  548. PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
  549. /* Port15 */
  550. PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
  551. PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
  552. PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
  553. PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
  554. PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
  555. /* Port16 */
  556. PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
  557. PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
  558. /* Port17 */
  559. PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
  560. PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
  561. /* Port18 */
  562. PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
  563. PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
  564. /* Port19 */
  565. PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
  566. PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
  567. PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
  568. /* Port20 */
  569. PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
  570. PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
  571. PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
  572. /* Port21 */
  573. PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
  574. PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
  575. PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
  576. PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
  577. PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
  578. PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
  579. /* Port22 */
  580. PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
  581. PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
  582. PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
  583. /* Port23 */
  584. PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
  585. PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
  586. PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
  587. PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
  588. PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
  589. PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
  590. /* Port24 */
  591. PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
  592. PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
  593. PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
  594. PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
  595. /* Port25 */
  596. PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
  597. PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
  598. PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
  599. PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
  600. /* Port26 */
  601. PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
  602. PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
  603. PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
  604. /* Port27 - Port39 Function */
  605. PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
  606. PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
  607. PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
  608. PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
  609. PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
  610. PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
  611. PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
  612. PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
  613. PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
  614. PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
  615. PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
  616. PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
  617. PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
  618. /* Port38 IRQ */
  619. PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
  620. /* Port40 */
  621. PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
  622. PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
  623. PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
  624. /* Port41 */
  625. PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
  626. PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
  627. PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
  628. /* Port42 */
  629. PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
  630. PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
  631. PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
  632. /* Port43 */
  633. PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
  634. PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
  635. PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
  636. PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
  637. /* Port44 */
  638. PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
  639. PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
  640. PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
  641. PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
  642. /* Port45 */
  643. PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
  644. PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
  645. PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
  646. PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
  647. /* Port46 */
  648. PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
  649. PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
  650. PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
  651. /* Port47 */
  652. PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
  653. PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
  654. PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
  655. /* Port48 */
  656. PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
  657. PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
  658. PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
  659. /* Port49 */
  660. PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
  661. PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
  662. PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
  663. PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
  664. /* Port50 */
  665. PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
  666. PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
  667. PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
  668. PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
  669. /* Port51 */
  670. PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
  671. PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
  672. PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
  673. /* Port52 */
  674. PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
  675. PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
  676. PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
  677. /* Port53 */
  678. PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
  679. PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
  680. PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
  681. /* Port54 */
  682. PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
  683. PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
  684. PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
  685. /* Port55 */
  686. PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
  687. PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
  688. PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
  689. PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
  690. /* Port56 */
  691. PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
  692. PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
  693. PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
  694. PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
  695. PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
  696. /* Port57 */
  697. PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
  698. PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
  699. PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
  700. PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
  701. PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
  702. /* Port58 */
  703. PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
  704. PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
  705. PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
  706. PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
  707. PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
  708. /* Port59 */
  709. PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
  710. PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
  711. PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
  712. /* Port60 */
  713. PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
  714. PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
  715. PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
  716. /* Port61 */
  717. PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
  718. PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
  719. /* Port62 */
  720. PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
  721. PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
  722. PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
  723. PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
  724. /* Port63 */
  725. PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
  726. PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
  727. PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
  728. /* Port64 */
  729. PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
  730. PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
  731. PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
  732. PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
  733. /* Port65 */
  734. PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
  735. PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
  736. PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
  737. /* Port66 */
  738. PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
  739. PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
  740. PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
  741. PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
  742. /* Port67 - Port73 Function1 */
  743. PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
  744. PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
  745. PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
  746. PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
  747. PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
  748. PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
  749. PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
  750. /* Port67 - Port73 Function2 */
  751. PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
  752. PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
  753. PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
  754. PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
  755. PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
  756. PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
  757. PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
  758. /* Port67 - Port73 Function4 */
  759. PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
  760. PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
  761. PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
  762. PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
  763. PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
  764. PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
  765. PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
  766. /* Port67 - Port73 Function6 */
  767. PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
  768. PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
  769. PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
  770. PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
  771. PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
  772. PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
  773. PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
  774. /* Port67 - Port71 IRQ */
  775. PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
  776. PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
  777. PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
  778. PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
  779. PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
  780. /* Port74 */
  781. PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
  782. PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
  783. PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
  784. PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
  785. PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
  786. /* Port75 */
  787. PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
  788. PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
  789. PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
  790. PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
  791. PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
  792. /* Port76 - Port80 Function */
  793. PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
  794. PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
  795. PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
  796. PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
  797. PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
  798. /* Port81 */
  799. PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
  800. PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
  801. /* Port82 - Port88 Function */
  802. PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
  803. PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
  804. PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
  805. PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
  806. PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
  807. PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
  808. PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
  809. /* Port89 */
  810. PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
  811. PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
  812. PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
  813. /* Port90 */
  814. PINMUX_DATA(DACK0_MARK, PORT90_FN1),
  815. PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
  816. PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
  817. PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
  818. /* Port91 */
  819. PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
  820. PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
  821. PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
  822. PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
  823. /* Port92 */
  824. PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
  825. PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
  826. PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
  827. PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
  828. PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
  829. /* Port93 */
  830. PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
  831. PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
  832. PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
  833. PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
  834. PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
  835. /* Port94 */
  836. PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
  837. PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
  838. PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
  839. PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
  840. PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
  841. /* Port95 */
  842. PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
  843. PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
  844. PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
  845. PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
  846. PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
  847. PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
  848. /* Port96 */
  849. PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
  850. PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
  851. PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
  852. PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
  853. PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
  854. PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
  855. /* Port97 */
  856. PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
  857. PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
  858. PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
  859. PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
  860. PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
  861. /* Port98 */
  862. PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
  863. PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
  864. PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
  865. PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
  866. /* Port99 */
  867. PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
  868. PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
  869. PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
  870. PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
  871. PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
  872. /* Port100 */
  873. PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
  874. PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
  875. PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
  876. PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
  877. /* Port101 */
  878. PINMUX_DATA(FCE0_MARK, PORT101_FN1),
  879. /* Port102 */
  880. PINMUX_DATA(FRB_MARK, PORT102_FN1),
  881. PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
  882. /* Port103 */
  883. PINMUX_DATA(CS5B_MARK, PORT103_FN1),
  884. PINMUX_DATA(FCE1_MARK, PORT103_FN2),
  885. PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
  886. /* Port104 */
  887. PINMUX_DATA(CS6A_MARK, PORT104_FN1),
  888. PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
  889. PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
  890. /* Port105 */
  891. PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
  892. PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
  893. /* Port106 */
  894. PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
  895. PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
  896. /* Port107 - Port115 Function */
  897. PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
  898. PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
  899. PINMUX_DATA(CS0_MARK, PORT109_FN1),
  900. PINMUX_DATA(CS2_MARK, PORT110_FN1),
  901. PINMUX_DATA(CS4_MARK, PORT111_FN1),
  902. PINMUX_DATA(WE1_MARK, PORT112_FN1),
  903. PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
  904. PINMUX_DATA(RDWR_MARK, PORT114_FN1),
  905. PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
  906. /* Port116 */
  907. PINMUX_DATA(A25_MARK, PORT116_FN1),
  908. PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
  909. PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
  910. PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
  911. PINMUX_DATA(GPO1_MARK, PORT116_FN5),
  912. /* Port117 */
  913. PINMUX_DATA(A24_MARK, PORT117_FN1),
  914. PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
  915. PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
  916. PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
  917. PINMUX_DATA(GPO0_MARK, PORT117_FN5),
  918. /* Port118 */
  919. PINMUX_DATA(A23_MARK, PORT118_FN1),
  920. PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
  921. PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
  922. PINMUX_DATA(GPI1_MARK, PORT118_FN5),
  923. PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
  924. /* Port119 */
  925. PINMUX_DATA(A22_MARK, PORT119_FN1),
  926. PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
  927. PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
  928. PINMUX_DATA(GPI0_MARK, PORT119_FN5),
  929. PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
  930. /* Port120 */
  931. PINMUX_DATA(A21_MARK, PORT120_FN1),
  932. PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
  933. PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
  934. PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
  935. /* Port121 */
  936. PINMUX_DATA(A20_MARK, PORT121_FN1),
  937. PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
  938. PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
  939. PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
  940. /* Port122 */
  941. PINMUX_DATA(A19_MARK, PORT122_FN1),
  942. PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
  943. /* Port123 */
  944. PINMUX_DATA(A18_MARK, PORT123_FN1),
  945. PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
  946. /* Port124 */
  947. PINMUX_DATA(A17_MARK, PORT124_FN1),
  948. PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
  949. /* Port125 - Port141 Function */
  950. PINMUX_DATA(A16_MARK, PORT125_FN1),
  951. PINMUX_DATA(A15_MARK, PORT126_FN1),
  952. PINMUX_DATA(A14_MARK, PORT127_FN1),
  953. PINMUX_DATA(A13_MARK, PORT128_FN1),
  954. PINMUX_DATA(A12_MARK, PORT129_FN1),
  955. PINMUX_DATA(A11_MARK, PORT130_FN1),
  956. PINMUX_DATA(A10_MARK, PORT131_FN1),
  957. PINMUX_DATA(A9_MARK, PORT132_FN1),
  958. PINMUX_DATA(A8_MARK, PORT133_FN1),
  959. PINMUX_DATA(A7_MARK, PORT134_FN1),
  960. PINMUX_DATA(A6_MARK, PORT135_FN1),
  961. PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
  962. PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
  963. PINMUX_DATA(A3_MARK, PORT138_FN1),
  964. PINMUX_DATA(A2_MARK, PORT139_FN1),
  965. PINMUX_DATA(A1_MARK, PORT140_FN1),
  966. PINMUX_DATA(CKO_MARK, PORT141_FN1),
  967. /* Port142 - Port157 Function1 */
  968. PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
  969. PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
  970. PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
  971. PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
  972. PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
  973. PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
  974. PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
  975. PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
  976. PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
  977. PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
  978. PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
  979. PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
  980. PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
  981. PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
  982. PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
  983. PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
  984. /* Port142 - Port149 Function3 */
  985. PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
  986. PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
  987. PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
  988. PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
  989. PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
  990. PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
  991. PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
  992. PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
  993. /* Port158 */
  994. PINMUX_DATA(D31_MARK, PORT158_FN1),
  995. PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
  996. PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
  997. PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
  998. PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
  999. PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
  1000. /* Port159 */
  1001. PINMUX_DATA(D30_MARK, PORT159_FN1),
  1002. PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
  1003. PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
  1004. PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
  1005. PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
  1006. /* Port160 */
  1007. PINMUX_DATA(D29_MARK, PORT160_FN1),
  1008. PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
  1009. PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
  1010. PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
  1011. PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
  1012. /* Port161 */
  1013. PINMUX_DATA(D28_MARK, PORT161_FN1),
  1014. PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
  1015. PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
  1016. PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
  1017. PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
  1018. PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
  1019. /* Port162 */
  1020. PINMUX_DATA(D27_MARK, PORT162_FN1),
  1021. PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
  1022. PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
  1023. PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
  1024. PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
  1025. /* Port163 */
  1026. PINMUX_DATA(D26_MARK, PORT163_FN1),
  1027. PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
  1028. PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
  1029. PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
  1030. PINMUX_DATA(IROUT_MARK, PORT163_FN5),
  1031. PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
  1032. /* Port164 */
  1033. PINMUX_DATA(D25_MARK, PORT164_FN1),
  1034. PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
  1035. PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
  1036. PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
  1037. PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
  1038. /* Port165 */
  1039. PINMUX_DATA(D24_MARK, PORT165_FN1),
  1040. PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
  1041. PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
  1042. PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
  1043. /* Port166 - Port171 Function1 */
  1044. PINMUX_DATA(D21_MARK, PORT166_FN1),
  1045. PINMUX_DATA(D20_MARK, PORT167_FN1),
  1046. PINMUX_DATA(D19_MARK, PORT168_FN1),
  1047. PINMUX_DATA(D18_MARK, PORT169_FN1),
  1048. PINMUX_DATA(D17_MARK, PORT170_FN1),
  1049. PINMUX_DATA(D16_MARK, PORT171_FN1),
  1050. /* Port166 - Port171 Function3 */
  1051. PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
  1052. PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
  1053. PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
  1054. PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
  1055. PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
  1056. PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
  1057. /* Port166 - Port171 Function6 */
  1058. PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
  1059. PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
  1060. PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
  1061. PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
  1062. PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
  1063. PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
  1064. /* Port167 - Port171 IRQ */
  1065. PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
  1066. PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
  1067. PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
  1068. PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
  1069. PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
  1070. /* Port172 */
  1071. PINMUX_DATA(D23_MARK, PORT172_FN1),
  1072. PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
  1073. PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
  1074. PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
  1075. PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
  1076. /* Port173 */
  1077. PINMUX_DATA(D22_MARK, PORT173_FN1),
  1078. PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
  1079. PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
  1080. PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
  1081. PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
  1082. /* Port174 */
  1083. PINMUX_DATA(A26_MARK, PORT174_FN1),
  1084. PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
  1085. PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
  1086. PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
  1087. /* Port175 */
  1088. PINMUX_DATA(A0_MARK, PORT175_FN1),
  1089. PINMUX_DATA(BS_MARK, PORT175_FN2),
  1090. PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
  1091. PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
  1092. /* Port176 */
  1093. PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
  1094. /* Port177 */
  1095. PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
  1096. PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
  1097. PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
  1098. PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
  1099. /* Port178 */
  1100. PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
  1101. PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
  1102. PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
  1103. /* Port179 */
  1104. PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
  1105. PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
  1106. PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
  1107. /* Port180 */
  1108. PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
  1109. PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
  1110. PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
  1111. PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
  1112. PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
  1113. /* Port181 */
  1114. PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
  1115. PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
  1116. PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
  1117. /* Port182 */
  1118. PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
  1119. PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
  1120. PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
  1121. /* Port183 */
  1122. PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
  1123. PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
  1124. PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
  1125. /* Port184 */
  1126. PINMUX_DATA(DACK1_MARK, PORT184_FN1),
  1127. PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
  1128. PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
  1129. /* Port185 - Port192 Function1 */
  1130. PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
  1131. PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
  1132. PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
  1133. PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
  1134. PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
  1135. PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
  1136. PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
  1137. /* Port185 - Port192 Function3 */
  1138. PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
  1139. PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
  1140. PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
  1141. PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
  1142. PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
  1143. PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
  1144. PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
  1145. PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
  1146. /* Port185 - Port192 Function6 */
  1147. PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
  1148. PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
  1149. PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
  1150. PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
  1151. PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
  1152. PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
  1153. PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
  1154. PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
  1155. /* Port193 */
  1156. PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
  1157. PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
  1158. PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
  1159. PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
  1160. /* Port194 */
  1161. PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
  1162. PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
  1163. PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
  1164. PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
  1165. /* Port195 */
  1166. PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
  1167. PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
  1168. PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
  1169. PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
  1170. /* Port196 */
  1171. PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
  1172. PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
  1173. PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
  1174. PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
  1175. /* Port197 */
  1176. PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
  1177. PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
  1178. PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
  1179. PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
  1180. /* Port198 */
  1181. PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
  1182. PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
  1183. PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
  1184. PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
  1185. /* Port199 */
  1186. PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
  1187. PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
  1188. PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
  1189. PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
  1190. PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
  1191. PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
  1192. /* Port200 */
  1193. PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
  1194. PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
  1195. PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
  1196. PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
  1197. PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
  1198. /* Port201 */
  1199. PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
  1200. PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
  1201. PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
  1202. PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
  1203. PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
  1204. PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
  1205. /* Port202 */
  1206. PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
  1207. PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
  1208. PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
  1209. PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
  1210. PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
  1211. PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
  1212. PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
  1213. PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
  1214. /* Port203 - Port208 Function1 */
  1215. PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
  1216. PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
  1217. PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
  1218. PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
  1219. PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
  1220. PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
  1221. /* Port203 - Port208 Function3 */
  1222. PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
  1223. PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
  1224. PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
  1225. PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
  1226. PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
  1227. PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
  1228. /* Port203 - Port208 Function6 */
  1229. PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
  1230. PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
  1231. PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
  1232. PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
  1233. PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
  1234. PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
  1235. /* Port203 - Port208 Function7 */
  1236. PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
  1237. PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
  1238. PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
  1239. PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
  1240. PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
  1241. PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
  1242. /* Port209 */
  1243. PINMUX_DATA(VBUS_MARK, PORT209_FN1),
  1244. PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
  1245. /* Port210 */
  1246. PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
  1247. PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
  1248. /* Port211 */
  1249. PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
  1250. PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
  1251. /* SDENC */
  1252. PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
  1253. PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
  1254. /* SYSC */
  1255. PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
  1256. PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
  1257. /* DEBUG */
  1258. PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
  1259. PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
  1260. PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
  1261. PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
  1262. PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
  1263. };
  1264. #define __I (SH_PFC_PIN_CFG_INPUT)
  1265. #define __O (SH_PFC_PIN_CFG_OUTPUT)
  1266. #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
  1267. #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
  1268. #define __PU (SH_PFC_PIN_CFG_PULL_UP)
  1269. #define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
  1270. #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
  1271. #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
  1272. #define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
  1273. #define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
  1274. #define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
  1275. #define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
  1276. #define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
  1277. #define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
  1278. #define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
  1279. static const struct sh_pfc_pin pinmux_pins[] = {
  1280. /* Table 56-1 (I/O and Pull U/D) */
  1281. R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
  1282. R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
  1283. R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
  1284. R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
  1285. R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
  1286. R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
  1287. R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
  1288. R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
  1289. R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
  1290. R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
  1291. R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
  1292. R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
  1293. R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
  1294. R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
  1295. R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
  1296. R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
  1297. R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
  1298. R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
  1299. R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
  1300. R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
  1301. R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
  1302. R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
  1303. R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
  1304. R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
  1305. R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
  1306. R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
  1307. R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
  1308. R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
  1309. R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
  1310. R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
  1311. R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
  1312. R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
  1313. R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
  1314. R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
  1315. R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
  1316. R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
  1317. R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
  1318. R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
  1319. R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
  1320. R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
  1321. R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
  1322. R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
  1323. R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
  1324. R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
  1325. R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
  1326. R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
  1327. R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
  1328. R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
  1329. R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
  1330. R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
  1331. R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
  1332. R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
  1333. R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
  1334. R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
  1335. R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
  1336. R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
  1337. R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
  1338. R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
  1339. R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
  1340. R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
  1341. R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
  1342. R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
  1343. R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
  1344. R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
  1345. R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
  1346. R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
  1347. R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
  1348. R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
  1349. R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
  1350. R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
  1351. R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
  1352. R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
  1353. R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
  1354. R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
  1355. R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
  1356. R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
  1357. R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
  1358. R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
  1359. R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
  1360. R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
  1361. R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
  1362. R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
  1363. R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
  1364. R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
  1365. R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
  1366. R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
  1367. R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
  1368. R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
  1369. R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
  1370. R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
  1371. R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
  1372. R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
  1373. R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
  1374. R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
  1375. R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
  1376. R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
  1377. R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
  1378. R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
  1379. R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
  1380. R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
  1381. R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
  1382. R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
  1383. R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
  1384. R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
  1385. R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
  1386. R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
  1387. };
  1388. /* - BSC -------------------------------------------------------------------- */
  1389. static const unsigned int bsc_data8_pins[] = {
  1390. /* D[0:7] */
  1391. 157, 156, 155, 154, 153, 152, 151, 150,
  1392. };
  1393. static const unsigned int bsc_data8_mux[] = {
  1394. D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
  1395. D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
  1396. };
  1397. static const unsigned int bsc_data16_pins[] = {
  1398. /* D[0:15] */
  1399. 157, 156, 155, 154, 153, 152, 151, 150,
  1400. 149, 148, 147, 146, 145, 144, 143, 142,
  1401. };
  1402. static const unsigned int bsc_data16_mux[] = {
  1403. D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
  1404. D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
  1405. D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
  1406. D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
  1407. };
  1408. static const unsigned int bsc_data32_pins[] = {
  1409. /* D[0:31] */
  1410. 157, 156, 155, 154, 153, 152, 151, 150,
  1411. 149, 148, 147, 146, 145, 144, 143, 142,
  1412. 171, 170, 169, 168, 167, 166, 173, 172,
  1413. 165, 164, 163, 162, 161, 160, 159, 158,
  1414. };
  1415. static const unsigned int bsc_data32_mux[] = {
  1416. D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
  1417. D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
  1418. D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
  1419. D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
  1420. D16_MARK, D17_MARK, D18_MARK, D19_MARK,
  1421. D20_MARK, D21_MARK, D22_MARK, D23_MARK,
  1422. D24_MARK, D25_MARK, D26_MARK, D27_MARK,
  1423. D28_MARK, D29_MARK, D30_MARK, D31_MARK,
  1424. };
  1425. static const unsigned int bsc_cs0_pins[] = {
  1426. /* CS */
  1427. 109,
  1428. };
  1429. static const unsigned int bsc_cs0_mux[] = {
  1430. CS0_MARK,
  1431. };
  1432. static const unsigned int bsc_cs2_pins[] = {
  1433. /* CS */
  1434. 110,
  1435. };
  1436. static const unsigned int bsc_cs2_mux[] = {
  1437. CS2_MARK,
  1438. };
  1439. static const unsigned int bsc_cs4_pins[] = {
  1440. /* CS */
  1441. 111,
  1442. };
  1443. static const unsigned int bsc_cs4_mux[] = {
  1444. CS4_MARK,
  1445. };
  1446. static const unsigned int bsc_cs5a_0_pins[] = {
  1447. /* CS */
  1448. 105,
  1449. };
  1450. static const unsigned int bsc_cs5a_0_mux[] = {
  1451. CS5A_PORT105_MARK,
  1452. };
  1453. static const unsigned int bsc_cs5a_1_pins[] = {
  1454. /* CS */
  1455. 19,
  1456. };
  1457. static const unsigned int bsc_cs5a_1_mux[] = {
  1458. CS5A_PORT19_MARK,
  1459. };
  1460. static const unsigned int bsc_cs5b_pins[] = {
  1461. /* CS */
  1462. 103,
  1463. };
  1464. static const unsigned int bsc_cs5b_mux[] = {
  1465. CS5B_MARK,
  1466. };
  1467. static const unsigned int bsc_cs6a_pins[] = {
  1468. /* CS */
  1469. 104,
  1470. };
  1471. static const unsigned int bsc_cs6a_mux[] = {
  1472. CS6A_MARK,
  1473. };
  1474. static const unsigned int bsc_rd_we8_pins[] = {
  1475. /* RD, WE[0] */
  1476. 115, 113,
  1477. };
  1478. static const unsigned int bsc_rd_we8_mux[] = {
  1479. RD_FSC_MARK, WE0_FWE_MARK,
  1480. };
  1481. static const unsigned int bsc_rd_we16_pins[] = {
  1482. /* RD, WE[0:1] */
  1483. 115, 113, 112,
  1484. };
  1485. static const unsigned int bsc_rd_we16_mux[] = {
  1486. RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
  1487. };
  1488. static const unsigned int bsc_rd_we32_pins[] = {
  1489. /* RD, WE[0:3] */
  1490. 115, 113, 112, 108, 107,
  1491. };
  1492. static const unsigned int bsc_rd_we32_mux[] = {
  1493. RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
  1494. };
  1495. static const unsigned int bsc_bs_pins[] = {
  1496. /* BS */
  1497. 175,
  1498. };
  1499. static const unsigned int bsc_bs_mux[] = {
  1500. BS_MARK,
  1501. };
  1502. static const unsigned int bsc_rdwr_pins[] = {
  1503. /* RDWR */
  1504. 114,
  1505. };
  1506. static const unsigned int bsc_rdwr_mux[] = {
  1507. RDWR_MARK,
  1508. };
  1509. /* - CEU0 ------------------------------------------------------------------- */
  1510. static const unsigned int ceu0_data_0_7_pins[] = {
  1511. /* D[0:7] */
  1512. 34, 33, 32, 31, 30, 29, 28, 27,
  1513. };
  1514. static const unsigned int ceu0_data_0_7_mux[] = {
  1515. VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
  1516. VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
  1517. };
  1518. static const unsigned int ceu0_data_8_15_0_pins[] = {
  1519. /* D[8:15] */
  1520. 182, 181, 180, 179, 178, 26, 25, 24,
  1521. };
  1522. static const unsigned int ceu0_data_8_15_0_mux[] = {
  1523. VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
  1524. VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
  1525. VIO0_D15_PORT24_MARK,
  1526. };
  1527. static const unsigned int ceu0_data_8_15_1_pins[] = {
  1528. /* D[8:15] */
  1529. 182, 181, 180, 179, 178, 22, 95, 96,
  1530. };
  1531. static const unsigned int ceu0_data_8_15_1_mux[] = {
  1532. VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
  1533. VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
  1534. VIO0_D15_PORT96_MARK,
  1535. };
  1536. static const unsigned int ceu0_clk_0_pins[] = {
  1537. /* CKO */
  1538. 36,
  1539. };
  1540. static const unsigned int ceu0_clk_0_mux[] = {
  1541. VIO_CKO_MARK,
  1542. };
  1543. static const unsigned int ceu0_clk_1_pins[] = {
  1544. /* CKO */
  1545. 14,
  1546. };
  1547. static const unsigned int ceu0_clk_1_mux[] = {
  1548. VIO_CKO1_MARK,
  1549. };
  1550. static const unsigned int ceu0_clk_2_pins[] = {
  1551. /* CKO */
  1552. 15,
  1553. };
  1554. static const unsigned int ceu0_clk_2_mux[] = {
  1555. VIO_CKO2_MARK,
  1556. };
  1557. static const unsigned int ceu0_sync_pins[] = {
  1558. /* CLK, VD, HD */
  1559. 35, 39, 37,
  1560. };
  1561. static const unsigned int ceu0_sync_mux[] = {
  1562. VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
  1563. };
  1564. static const unsigned int ceu0_field_pins[] = {
  1565. /* FIELD */
  1566. 38,
  1567. };
  1568. static const unsigned int ceu0_field_mux[] = {
  1569. VIO0_FIELD_MARK,
  1570. };
  1571. /* - CEU1 ------------------------------------------------------------------- */
  1572. static const unsigned int ceu1_data_pins[] = {
  1573. /* D[0:7] */
  1574. 182, 181, 180, 179, 178, 26, 25, 24,
  1575. };
  1576. static const unsigned int ceu1_data_mux[] = {
  1577. VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
  1578. VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
  1579. };
  1580. static const unsigned int ceu1_clk_pins[] = {
  1581. /* CKO */
  1582. 23,
  1583. };
  1584. static const unsigned int ceu1_clk_mux[] = {
  1585. VIO_CKO_1_MARK,
  1586. };
  1587. static const unsigned int ceu1_sync_pins[] = {
  1588. /* CLK, VD, HD */
  1589. 197, 198, 160,
  1590. };
  1591. static const unsigned int ceu1_sync_mux[] = {
  1592. VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
  1593. };
  1594. static const unsigned int ceu1_field_pins[] = {
  1595. /* FIELD */
  1596. 21,
  1597. };
  1598. static const unsigned int ceu1_field_mux[] = {
  1599. VIO1_FIELD_MARK,
  1600. };
  1601. /* - FSIA ------------------------------------------------------------------- */
  1602. static const unsigned int fsia_mclk_in_pins[] = {
  1603. /* CK */
  1604. 11,
  1605. };
  1606. static const unsigned int fsia_mclk_in_mux[] = {
  1607. FSIACK_MARK,
  1608. };
  1609. static const unsigned int fsia_mclk_out_pins[] = {
  1610. /* OMC */
  1611. 10,
  1612. };
  1613. static const unsigned int fsia_mclk_out_mux[] = {
  1614. FSIAOMC_MARK,
  1615. };
  1616. static const unsigned int fsia_sclk_in_pins[] = {
  1617. /* ILR, IBT */
  1618. 12, 13,
  1619. };
  1620. static const unsigned int fsia_sclk_in_mux[] = {
  1621. FSIAILR_MARK, FSIAIBT_MARK,
  1622. };
  1623. static const unsigned int fsia_sclk_out_pins[] = {
  1624. /* OLR, OBT */
  1625. 7, 8,
  1626. };
  1627. static const unsigned int fsia_sclk_out_mux[] = {
  1628. FSIAOLR_MARK, FSIAOBT_MARK,
  1629. };
  1630. static const unsigned int fsia_data_in_0_pins[] = {
  1631. /* ISLD */
  1632. 0,
  1633. };
  1634. static const unsigned int fsia_data_in_0_mux[] = {
  1635. FSIAISLD_PORT0_MARK,
  1636. };
  1637. static const unsigned int fsia_data_in_1_pins[] = {
  1638. /* ISLD */
  1639. 5,
  1640. };
  1641. static const unsigned int fsia_data_in_1_mux[] = {
  1642. FSIAISLD_PORT5_MARK,
  1643. };
  1644. static const unsigned int fsia_data_out_0_pins[] = {
  1645. /* OSLD */
  1646. 9,
  1647. };
  1648. static const unsigned int fsia_data_out_0_mux[] = {
  1649. FSIAOSLD_MARK,
  1650. };
  1651. static const unsigned int fsia_data_out_1_pins[] = {
  1652. /* OSLD */
  1653. 0,
  1654. };
  1655. static const unsigned int fsia_data_out_1_mux[] = {
  1656. FSIAOSLD1_MARK,
  1657. };
  1658. static const unsigned int fsia_data_out_2_pins[] = {
  1659. /* OSLD */
  1660. 1,
  1661. };
  1662. static const unsigned int fsia_data_out_2_mux[] = {
  1663. FSIAOSLD2_MARK,
  1664. };
  1665. static const unsigned int fsia_spdif_0_pins[] = {
  1666. /* SPDIF */
  1667. 9,
  1668. };
  1669. static const unsigned int fsia_spdif_0_mux[] = {
  1670. FSIASPDIF_PORT9_MARK,
  1671. };
  1672. static const unsigned int fsia_spdif_1_pins[] = {
  1673. /* SPDIF */
  1674. 18,
  1675. };
  1676. static const unsigned int fsia_spdif_1_mux[] = {
  1677. FSIASPDIF_PORT18_MARK,
  1678. };
  1679. /* - FSIB ------------------------------------------------------------------- */
  1680. static const unsigned int fsib_mclk_in_pins[] = {
  1681. /* CK */
  1682. 11,
  1683. };
  1684. static const unsigned int fsib_mclk_in_mux[] = {
  1685. FSIBCK_MARK,
  1686. };
  1687. /* - GETHER ----------------------------------------------------------------- */
  1688. static const unsigned int gether_rmii_pins[] = {
  1689. /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
  1690. 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
  1691. };
  1692. static const unsigned int gether_rmii_mux[] = {
  1693. RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
  1694. RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
  1695. RMII_MDC_MARK, RMII_MDIO_MARK,
  1696. };
  1697. static const unsigned int gether_mii_pins[] = {
  1698. /* RXD[0:3], RX_CLK, RX_DV, RX_ER
  1699. * TXD[0:3], TX_CLK, TX_EN, TX_ER
  1700. * CRS, COL, MDC, MDIO,
  1701. */
  1702. 185, 186, 187, 188, 174, 161, 204,
  1703. 171, 170, 169, 168, 184, 183, 203,
  1704. 205, 163, 206, 207,
  1705. };
  1706. static const unsigned int gether_mii_mux[] = {
  1707. ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
  1708. ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
  1709. ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
  1710. ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
  1711. ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
  1712. };
  1713. static const unsigned int gether_gmii_pins[] = {
  1714. /* RXD[0:7], RX_CLK, RX_DV, RX_ER
  1715. * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
  1716. * CRS, COL, MDC, MDIO, REF125CK_MARK,
  1717. */
  1718. 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
  1719. 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
  1720. 205, 163, 206, 207, 158,
  1721. };
  1722. static const unsigned int gether_gmii_mux[] = {
  1723. ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
  1724. ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
  1725. ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
  1726. ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
  1727. ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
  1728. ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
  1729. ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
  1730. RMII_REF125CK_MARK,
  1731. };
  1732. static const unsigned int gether_int_pins[] = {
  1733. /* PHY_INT */
  1734. 164,
  1735. };
  1736. static const unsigned int gether_int_mux[] = {
  1737. ET_PHY_INT_MARK,
  1738. };
  1739. static const unsigned int gether_link_pins[] = {
  1740. /* LINK */
  1741. 177,
  1742. };
  1743. static const unsigned int gether_link_mux[] = {
  1744. ET_LINK_MARK,
  1745. };
  1746. static const unsigned int gether_wol_pins[] = {
  1747. /* WOL */
  1748. 175,
  1749. };
  1750. static const unsigned int gether_wol_mux[] = {
  1751. ET_WOL_MARK,
  1752. };
  1753. /* - HDMI ------------------------------------------------------------------- */
  1754. static const unsigned int hdmi_pins[] = {
  1755. /* HPD, CEC */
  1756. 210, 211,
  1757. };
  1758. static const unsigned int hdmi_mux[] = {
  1759. HDMI_HPD_MARK, HDMI_CEC_MARK,
  1760. };
  1761. /* - INTC ------------------------------------------------------------------- */
  1762. IRQC_PINS_MUX(0, 0, 2);
  1763. IRQC_PINS_MUX(0, 1, 13);
  1764. IRQC_PIN_MUX(1, 20);
  1765. IRQC_PINS_MUX(2, 0, 11);
  1766. IRQC_PINS_MUX(2, 1, 12);
  1767. IRQC_PINS_MUX(3, 0, 10);
  1768. IRQC_PINS_MUX(3, 1, 14);
  1769. IRQC_PINS_MUX(4, 0, 15);
  1770. IRQC_PINS_MUX(4, 1, 172);
  1771. IRQC_PINS_MUX(5, 0, 0);
  1772. IRQC_PINS_MUX(5, 1, 1);
  1773. IRQC_PINS_MUX(6, 0, 121);
  1774. IRQC_PINS_MUX(6, 1, 173);
  1775. IRQC_PINS_MUX(7, 0, 120);
  1776. IRQC_PINS_MUX(7, 1, 209);
  1777. IRQC_PIN_MUX(8, 119);
  1778. IRQC_PINS_MUX(9, 0, 118);
  1779. IRQC_PINS_MUX(9, 1, 210);
  1780. IRQC_PIN_MUX(10, 19);
  1781. IRQC_PIN_MUX(11, 104);
  1782. IRQC_PINS_MUX(12, 0, 42);
  1783. IRQC_PINS_MUX(12, 1, 97);
  1784. IRQC_PINS_MUX(13, 0, 64);
  1785. IRQC_PINS_MUX(13, 1, 98);
  1786. IRQC_PINS_MUX(14, 0, 63);
  1787. IRQC_PINS_MUX(14, 1, 99);
  1788. IRQC_PINS_MUX(15, 0, 62);
  1789. IRQC_PINS_MUX(15, 1, 100);
  1790. IRQC_PINS_MUX(16, 0, 68);
  1791. IRQC_PINS_MUX(16, 1, 211);
  1792. IRQC_PIN_MUX(17, 69);
  1793. IRQC_PIN_MUX(18, 70);
  1794. IRQC_PIN_MUX(19, 71);
  1795. IRQC_PIN_MUX(20, 67);
  1796. IRQC_PIN_MUX(21, 202);
  1797. IRQC_PIN_MUX(22, 95);
  1798. IRQC_PIN_MUX(23, 96);
  1799. IRQC_PIN_MUX(24, 180);
  1800. IRQC_PIN_MUX(25, 38);
  1801. IRQC_PINS_MUX(26, 0, 58);
  1802. IRQC_PINS_MUX(26, 1, 81);
  1803. IRQC_PINS_MUX(27, 0, 57);
  1804. IRQC_PINS_MUX(27, 1, 168);
  1805. IRQC_PINS_MUX(28, 0, 56);
  1806. IRQC_PINS_MUX(28, 1, 169);
  1807. IRQC_PINS_MUX(29, 0, 50);
  1808. IRQC_PINS_MUX(29, 1, 170);
  1809. IRQC_PINS_MUX(30, 0, 49);
  1810. IRQC_PINS_MUX(30, 1, 171);
  1811. IRQC_PINS_MUX(31, 0, 41);
  1812. IRQC_PINS_MUX(31, 1, 167);
  1813. /* - LCD0 ------------------------------------------------------------------- */
  1814. static const unsigned int lcd0_data8_pins[] = {
  1815. /* D[0:7] */
  1816. 58, 57, 56, 55, 54, 53, 52, 51,
  1817. };
  1818. static const unsigned int lcd0_data8_mux[] = {
  1819. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  1820. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  1821. };
  1822. static const unsigned int lcd0_data9_pins[] = {
  1823. /* D[0:8] */
  1824. 58, 57, 56, 55, 54, 53, 52, 51,
  1825. 50,
  1826. };
  1827. static const unsigned int lcd0_data9_mux[] = {
  1828. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  1829. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  1830. LCD0_D8_MARK,
  1831. };
  1832. static const unsigned int lcd0_data12_pins[] = {
  1833. /* D[0:11] */
  1834. 58, 57, 56, 55, 54, 53, 52, 51,
  1835. 50, 49, 48, 47,
  1836. };
  1837. static const unsigned int lcd0_data12_mux[] = {
  1838. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  1839. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  1840. LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
  1841. };
  1842. static const unsigned int lcd0_data16_pins[] = {
  1843. /* D[0:15] */
  1844. 58, 57, 56, 55, 54, 53, 52, 51,
  1845. 50, 49, 48, 47, 46, 45, 44, 43,
  1846. };
  1847. static const unsigned int lcd0_data16_mux[] = {
  1848. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  1849. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  1850. LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
  1851. LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
  1852. };
  1853. static const unsigned int lcd0_data18_pins[] = {
  1854. /* D[0:17] */
  1855. 58, 57, 56, 55, 54, 53, 52, 51,
  1856. 50, 49, 48, 47, 46, 45, 44, 43,
  1857. 42, 41,
  1858. };
  1859. static const unsigned int lcd0_data18_mux[] = {
  1860. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  1861. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  1862. LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
  1863. LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
  1864. LCD0_D16_MARK, LCD0_D17_MARK,
  1865. };
  1866. static const unsigned int lcd0_data24_0_pins[] = {
  1867. /* D[0:23] */
  1868. 58, 57, 56, 55, 54, 53, 52, 51,
  1869. 50, 49, 48, 47, 46, 45, 44, 43,
  1870. 42, 41, 40, 4, 3, 2, 0, 1,
  1871. };
  1872. static const unsigned int lcd0_data24_0_mux[] = {
  1873. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  1874. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  1875. LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
  1876. LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
  1877. LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
  1878. LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
  1879. LCD0_D23_PORT1_MARK,
  1880. };
  1881. static const unsigned int lcd0_data24_1_pins[] = {
  1882. /* D[0:23] */
  1883. 58, 57, 56, 55, 54, 53, 52, 51,
  1884. 50, 49, 48, 47, 46, 45, 44, 43,
  1885. 42, 41, 163, 162, 161, 158, 160, 159,
  1886. };
  1887. static const unsigned int lcd0_data24_1_mux[] = {
  1888. LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
  1889. LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
  1890. LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
  1891. LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
  1892. LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
  1893. LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
  1894. LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
  1895. };
  1896. static const unsigned int lcd0_display_pins[] = {
  1897. /* DON, VCPWC, VEPWC */
  1898. 61, 59, 60,
  1899. };
  1900. static const unsigned int lcd0_display_mux[] = {
  1901. LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
  1902. };
  1903. static const unsigned int lcd0_lclk_0_pins[] = {
  1904. /* LCLK */
  1905. 102,
  1906. };
  1907. static const unsigned int lcd0_lclk_0_mux[] = {
  1908. LCD0_LCLK_PORT102_MARK,
  1909. };
  1910. static const unsigned int lcd0_lclk_1_pins[] = {
  1911. /* LCLK */
  1912. 165,
  1913. };
  1914. static const unsigned int lcd0_lclk_1_mux[] = {
  1915. LCD0_LCLK_PORT165_MARK,
  1916. };
  1917. static const unsigned int lcd0_sync_pins[] = {
  1918. /* VSYN, HSYN, DCK, DISP */
  1919. 63, 64, 62, 65,
  1920. };
  1921. static const unsigned int lcd0_sync_mux[] = {
  1922. LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
  1923. };
  1924. static const unsigned int lcd0_sys_pins[] = {
  1925. /* CS, WR, RD, RS */
  1926. 64, 62, 164, 65,
  1927. };
  1928. static const unsigned int lcd0_sys_mux[] = {
  1929. LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
  1930. };
  1931. /* - LCD1 ------------------------------------------------------------------- */
  1932. static const unsigned int lcd1_data8_pins[] = {
  1933. /* D[0:7] */
  1934. 4, 3, 2, 1, 0, 91, 92, 23,
  1935. };
  1936. static const unsigned int lcd1_data8_mux[] = {
  1937. LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
  1938. LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
  1939. };
  1940. static const unsigned int lcd1_data9_pins[] = {
  1941. /* D[0:8] */
  1942. 4, 3, 2, 1, 0, 91, 92, 23,
  1943. 93,
  1944. };
  1945. static const unsigned int lcd1_data9_mux[] = {
  1946. LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
  1947. LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
  1948. LCD1_D8_MARK,
  1949. };
  1950. static const unsigned int lcd1_data12_pins[] = {
  1951. /* D[0:11] */
  1952. 4, 3, 2, 1, 0, 91, 92, 23,
  1953. 93, 94, 21, 201,
  1954. };
  1955. static const unsigned int lcd1_data12_mux[] = {
  1956. LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
  1957. LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
  1958. LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
  1959. };
  1960. static const unsigned int lcd1_data16_pins[] = {
  1961. /* D[0:15] */
  1962. 4, 3, 2, 1, 0, 91, 92, 23,
  1963. 93, 94, 21, 201, 200, 199, 196, 195,
  1964. };
  1965. static const unsigned int lcd1_data16_mux[] = {
  1966. LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
  1967. LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
  1968. LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
  1969. LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
  1970. };
  1971. static const unsigned int lcd1_data18_pins[] = {
  1972. /* D[0:17] */
  1973. 4, 3, 2, 1, 0, 91, 92, 23,
  1974. 93, 94, 21, 201, 200, 199, 196, 195,
  1975. 194, 193,
  1976. };
  1977. static const unsigned int lcd1_data18_mux[] = {
  1978. LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
  1979. LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
  1980. LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
  1981. LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
  1982. LCD1_D16_MARK, LCD1_D17_MARK,
  1983. };
  1984. static const unsigned int lcd1_data24_pins[] = {
  1985. /* D[0:23] */
  1986. 4, 3, 2, 1, 0, 91, 92, 23,
  1987. 93, 94, 21, 201, 200, 199, 196, 195,
  1988. 194, 193, 198, 197, 75, 74, 15, 14,
  1989. };
  1990. static const unsigned int lcd1_data24_mux[] = {
  1991. LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
  1992. LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
  1993. LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
  1994. LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
  1995. LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
  1996. LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
  1997. };
  1998. static const unsigned int lcd1_display_pins[] = {
  1999. /* DON, VCPWC, VEPWC */
  2000. 100, 5, 6,
  2001. };
  2002. static const unsigned int lcd1_display_mux[] = {
  2003. LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
  2004. };
  2005. static const unsigned int lcd1_lclk_pins[] = {
  2006. /* LCLK */
  2007. 40,
  2008. };
  2009. static const unsigned int lcd1_lclk_mux[] = {
  2010. LCD1_LCLK_MARK,
  2011. };
  2012. static const unsigned int lcd1_sync_pins[] = {
  2013. /* VSYN, HSYN, DCK, DISP */
  2014. 98, 97, 99, 12,
  2015. };
  2016. static const unsigned int lcd1_sync_mux[] = {
  2017. LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
  2018. };
  2019. static const unsigned int lcd1_sys_pins[] = {
  2020. /* CS, WR, RD, RS */
  2021. 97, 99, 13, 12,
  2022. };
  2023. static const unsigned int lcd1_sys_mux[] = {
  2024. LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
  2025. };
  2026. /* - MMCIF ------------------------------------------------------------------ */
  2027. static const unsigned int mmc0_data1_0_pins[] = {
  2028. /* D[0] */
  2029. 68,
  2030. };
  2031. static const unsigned int mmc0_data1_0_mux[] = {
  2032. MMC0_D0_PORT68_MARK,
  2033. };
  2034. static const unsigned int mmc0_data4_0_pins[] = {
  2035. /* D[0:3] */
  2036. 68, 69, 70, 71,
  2037. };
  2038. static const unsigned int mmc0_data4_0_mux[] = {
  2039. MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
  2040. };
  2041. static const unsigned int mmc0_data8_0_pins[] = {
  2042. /* D[0:7] */
  2043. 68, 69, 70, 71, 72, 73, 74, 75,
  2044. };
  2045. static const unsigned int mmc0_data8_0_mux[] = {
  2046. MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
  2047. MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
  2048. };
  2049. static const unsigned int mmc0_ctrl_0_pins[] = {
  2050. /* CMD, CLK */
  2051. 67, 66,
  2052. };
  2053. static const unsigned int mmc0_ctrl_0_mux[] = {
  2054. MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
  2055. };
  2056. static const unsigned int mmc0_data1_1_pins[] = {
  2057. /* D[0] */
  2058. 149,
  2059. };
  2060. static const unsigned int mmc0_data1_1_mux[] = {
  2061. MMC1_D0_PORT149_MARK,
  2062. };
  2063. static const unsigned int mmc0_data4_1_pins[] = {
  2064. /* D[0:3] */
  2065. 149, 148, 147, 146,
  2066. };
  2067. static const unsigned int mmc0_data4_1_mux[] = {
  2068. MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
  2069. };
  2070. static const unsigned int mmc0_data8_1_pins[] = {
  2071. /* D[0:7] */
  2072. 149, 148, 147, 146, 145, 144, 143, 142,
  2073. };
  2074. static const unsigned int mmc0_data8_1_mux[] = {
  2075. MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
  2076. MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
  2077. };
  2078. static const unsigned int mmc0_ctrl_1_pins[] = {
  2079. /* CMD, CLK */
  2080. 104, 103,
  2081. };
  2082. static const unsigned int mmc0_ctrl_1_mux[] = {
  2083. MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
  2084. };
  2085. /* - SCIFA0 ----------------------------------------------------------------- */
  2086. static const unsigned int scifa0_data_pins[] = {
  2087. /* RXD, TXD */
  2088. 197, 198,
  2089. };
  2090. static const unsigned int scifa0_data_mux[] = {
  2091. SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
  2092. };
  2093. static const unsigned int scifa0_clk_pins[] = {
  2094. /* SCK */
  2095. 188,
  2096. };
  2097. static const unsigned int scifa0_clk_mux[] = {
  2098. SCIFA0_SCK_MARK,
  2099. };
  2100. static const unsigned int scifa0_ctrl_pins[] = {
  2101. /* RTS, CTS */
  2102. 194, 193,
  2103. };
  2104. static const unsigned int scifa0_ctrl_mux[] = {
  2105. SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
  2106. };
  2107. /* - SCIFA1 ----------------------------------------------------------------- */
  2108. static const unsigned int scifa1_data_pins[] = {
  2109. /* RXD, TXD */
  2110. 195, 196,
  2111. };
  2112. static const unsigned int scifa1_data_mux[] = {
  2113. SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
  2114. };
  2115. static const unsigned int scifa1_clk_pins[] = {
  2116. /* SCK */
  2117. 185,
  2118. };
  2119. static const unsigned int scifa1_clk_mux[] = {
  2120. SCIFA1_SCK_MARK,
  2121. };
  2122. static const unsigned int scifa1_ctrl_pins[] = {
  2123. /* RTS, CTS */
  2124. 23, 21,
  2125. };
  2126. static const unsigned int scifa1_ctrl_mux[] = {
  2127. SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
  2128. };
  2129. /* - SCIFA2 ----------------------------------------------------------------- */
  2130. static const unsigned int scifa2_data_pins[] = {
  2131. /* RXD, TXD */
  2132. 200, 201,
  2133. };
  2134. static const unsigned int scifa2_data_mux[] = {
  2135. SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
  2136. };
  2137. static const unsigned int scifa2_clk_0_pins[] = {
  2138. /* SCK */
  2139. 22,
  2140. };
  2141. static const unsigned int scifa2_clk_0_mux[] = {
  2142. SCIFA2_SCK_PORT22_MARK,
  2143. };
  2144. static const unsigned int scifa2_clk_1_pins[] = {
  2145. /* SCK */
  2146. 199,
  2147. };
  2148. static const unsigned int scifa2_clk_1_mux[] = {
  2149. SCIFA2_SCK_PORT199_MARK,
  2150. };
  2151. static const unsigned int scifa2_ctrl_pins[] = {
  2152. /* RTS, CTS */
  2153. 96, 95,
  2154. };
  2155. static const unsigned int scifa2_ctrl_mux[] = {
  2156. SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
  2157. };
  2158. /* - SCIFA3 ----------------------------------------------------------------- */
  2159. static const unsigned int scifa3_data_0_pins[] = {
  2160. /* RXD, TXD */
  2161. 174, 175,
  2162. };
  2163. static const unsigned int scifa3_data_0_mux[] = {
  2164. SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
  2165. };
  2166. static const unsigned int scifa3_clk_0_pins[] = {
  2167. /* SCK */
  2168. 116,
  2169. };
  2170. static const unsigned int scifa3_clk_0_mux[] = {
  2171. SCIFA3_SCK_PORT116_MARK,
  2172. };
  2173. static const unsigned int scifa3_ctrl_0_pins[] = {
  2174. /* RTS, CTS */
  2175. 105, 117,
  2176. };
  2177. static const unsigned int scifa3_ctrl_0_mux[] = {
  2178. SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
  2179. };
  2180. static const unsigned int scifa3_data_1_pins[] = {
  2181. /* RXD, TXD */
  2182. 159, 160,
  2183. };
  2184. static const unsigned int scifa3_data_1_mux[] = {
  2185. SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
  2186. };
  2187. static const unsigned int scifa3_clk_1_pins[] = {
  2188. /* SCK */
  2189. 158,
  2190. };
  2191. static const unsigned int scifa3_clk_1_mux[] = {
  2192. SCIFA3_SCK_PORT158_MARK,
  2193. };
  2194. static const unsigned int scifa3_ctrl_1_pins[] = {
  2195. /* RTS, CTS */
  2196. 161, 162,
  2197. };
  2198. static const unsigned int scifa3_ctrl_1_mux[] = {
  2199. SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
  2200. };
  2201. /* - SCIFA4 ----------------------------------------------------------------- */
  2202. static const unsigned int scifa4_data_0_pins[] = {
  2203. /* RXD, TXD */
  2204. 12, 13,
  2205. };
  2206. static const unsigned int scifa4_data_0_mux[] = {
  2207. SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
  2208. };
  2209. static const unsigned int scifa4_data_1_pins[] = {
  2210. /* RXD, TXD */
  2211. 204, 203,
  2212. };
  2213. static const unsigned int scifa4_data_1_mux[] = {
  2214. SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
  2215. };
  2216. static const unsigned int scifa4_data_2_pins[] = {
  2217. /* RXD, TXD */
  2218. 94, 93,
  2219. };
  2220. static const unsigned int scifa4_data_2_mux[] = {
  2221. SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
  2222. };
  2223. static const unsigned int scifa4_clk_0_pins[] = {
  2224. /* SCK */
  2225. 21,
  2226. };
  2227. static const unsigned int scifa4_clk_0_mux[] = {
  2228. SCIFA4_SCK_PORT21_MARK,
  2229. };
  2230. static const unsigned int scifa4_clk_1_pins[] = {
  2231. /* SCK */
  2232. 205,
  2233. };
  2234. static const unsigned int scifa4_clk_1_mux[] = {
  2235. SCIFA4_SCK_PORT205_MARK,
  2236. };
  2237. /* - SCIFA5 ----------------------------------------------------------------- */
  2238. static const unsigned int scifa5_data_0_pins[] = {
  2239. /* RXD, TXD */
  2240. 10, 20,
  2241. };
  2242. static const unsigned int scifa5_data_0_mux[] = {
  2243. SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
  2244. };
  2245. static const unsigned int scifa5_data_1_pins[] = {
  2246. /* RXD, TXD */
  2247. 207, 208,
  2248. };
  2249. static const unsigned int scifa5_data_1_mux[] = {
  2250. SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
  2251. };
  2252. static const unsigned int scifa5_data_2_pins[] = {
  2253. /* RXD, TXD */
  2254. 92, 91,
  2255. };
  2256. static const unsigned int scifa5_data_2_mux[] = {
  2257. SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
  2258. };
  2259. static const unsigned int scifa5_clk_0_pins[] = {
  2260. /* SCK */
  2261. 23,
  2262. };
  2263. static const unsigned int scifa5_clk_0_mux[] = {
  2264. SCIFA5_SCK_PORT23_MARK,
  2265. };
  2266. static const unsigned int scifa5_clk_1_pins[] = {
  2267. /* SCK */
  2268. 206,
  2269. };
  2270. static const unsigned int scifa5_clk_1_mux[] = {
  2271. SCIFA5_SCK_PORT206_MARK,
  2272. };
  2273. /* - SCIFA6 ----------------------------------------------------------------- */
  2274. static const unsigned int scifa6_data_pins[] = {
  2275. /* RXD, TXD */
  2276. 25, 26,
  2277. };
  2278. static const unsigned int scifa6_data_mux[] = {
  2279. SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
  2280. };
  2281. static const unsigned int scifa6_clk_pins[] = {
  2282. /* SCK */
  2283. 24,
  2284. };
  2285. static const unsigned int scifa6_clk_mux[] = {
  2286. SCIFA6_SCK_MARK,
  2287. };
  2288. /* - SCIFA7 ----------------------------------------------------------------- */
  2289. static const unsigned int scifa7_data_pins[] = {
  2290. /* RXD, TXD */
  2291. 0, 1,
  2292. };
  2293. static const unsigned int scifa7_data_mux[] = {
  2294. SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
  2295. };
  2296. /* - SCIFB ------------------------------------------------------------------ */
  2297. static const unsigned int scifb_data_0_pins[] = {
  2298. /* RXD, TXD */
  2299. 191, 192,
  2300. };
  2301. static const unsigned int scifb_data_0_mux[] = {
  2302. SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
  2303. };
  2304. static const unsigned int scifb_clk_0_pins[] = {
  2305. /* SCK */
  2306. 190,
  2307. };
  2308. static const unsigned int scifb_clk_0_mux[] = {
  2309. SCIFB_SCK_PORT190_MARK,
  2310. };
  2311. static const unsigned int scifb_ctrl_0_pins[] = {
  2312. /* RTS, CTS */
  2313. 186, 187,
  2314. };
  2315. static const unsigned int scifb_ctrl_0_mux[] = {
  2316. SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
  2317. };
  2318. static const unsigned int scifb_data_1_pins[] = {
  2319. /* RXD, TXD */
  2320. 3, 4,
  2321. };
  2322. static const unsigned int scifb_data_1_mux[] = {
  2323. SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
  2324. };
  2325. static const unsigned int scifb_clk_1_pins[] = {
  2326. /* SCK */
  2327. 2,
  2328. };
  2329. static const unsigned int scifb_clk_1_mux[] = {
  2330. SCIFB_SCK_PORT2_MARK,
  2331. };
  2332. static const unsigned int scifb_ctrl_1_pins[] = {
  2333. /* RTS, CTS */
  2334. 172, 173,
  2335. };
  2336. static const unsigned int scifb_ctrl_1_mux[] = {
  2337. SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
  2338. };
  2339. /* - SDHI0 ------------------------------------------------------------------ */
  2340. static const unsigned int sdhi0_data1_pins[] = {
  2341. /* D0 */
  2342. 77,
  2343. };
  2344. static const unsigned int sdhi0_data1_mux[] = {
  2345. SDHI0_D0_MARK,
  2346. };
  2347. static const unsigned int sdhi0_data4_pins[] = {
  2348. /* D[0:3] */
  2349. 77, 78, 79, 80,
  2350. };
  2351. static const unsigned int sdhi0_data4_mux[] = {
  2352. SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
  2353. };
  2354. static const unsigned int sdhi0_ctrl_pins[] = {
  2355. /* CMD, CLK */
  2356. 76, 82,
  2357. };
  2358. static const unsigned int sdhi0_ctrl_mux[] = {
  2359. SDHI0_CMD_MARK, SDHI0_CLK_MARK,
  2360. };
  2361. static const unsigned int sdhi0_cd_pins[] = {
  2362. /* CD */
  2363. 81,
  2364. };
  2365. static const unsigned int sdhi0_cd_mux[] = {
  2366. SDHI0_CD_MARK,
  2367. };
  2368. static const unsigned int sdhi0_wp_pins[] = {
  2369. /* WP */
  2370. 83,
  2371. };
  2372. static const unsigned int sdhi0_wp_mux[] = {
  2373. SDHI0_WP_MARK,
  2374. };
  2375. /* - SDHI1 ------------------------------------------------------------------ */
  2376. static const unsigned int sdhi1_data1_pins[] = {
  2377. /* D0 */
  2378. 68,
  2379. };
  2380. static const unsigned int sdhi1_data1_mux[] = {
  2381. SDHI1_D0_MARK,
  2382. };
  2383. static const unsigned int sdhi1_data4_pins[] = {
  2384. /* D[0:3] */
  2385. 68, 69, 70, 71,
  2386. };
  2387. static const unsigned int sdhi1_data4_mux[] = {
  2388. SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
  2389. };
  2390. static const unsigned int sdhi1_ctrl_pins[] = {
  2391. /* CMD, CLK */
  2392. 67, 66,
  2393. };
  2394. static const unsigned int sdhi1_ctrl_mux[] = {
  2395. SDHI1_CMD_MARK, SDHI1_CLK_MARK,
  2396. };
  2397. static const unsigned int sdhi1_cd_pins[] = {
  2398. /* CD */
  2399. 72,
  2400. };
  2401. static const unsigned int sdhi1_cd_mux[] = {
  2402. SDHI1_CD_MARK,
  2403. };
  2404. static const unsigned int sdhi1_wp_pins[] = {
  2405. /* WP */
  2406. 73,
  2407. };
  2408. static const unsigned int sdhi1_wp_mux[] = {
  2409. SDHI1_WP_MARK,
  2410. };
  2411. /* - SDHI2 ------------------------------------------------------------------ */
  2412. static const unsigned int sdhi2_data1_pins[] = {
  2413. /* D0 */
  2414. 205,
  2415. };
  2416. static const unsigned int sdhi2_data1_mux[] = {
  2417. SDHI2_D0_MARK,
  2418. };
  2419. static const unsigned int sdhi2_data4_pins[] = {
  2420. /* D[0:3] */
  2421. 205, 206, 207, 208,
  2422. };
  2423. static const unsigned int sdhi2_data4_mux[] = {
  2424. SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
  2425. };
  2426. static const unsigned int sdhi2_ctrl_pins[] = {
  2427. /* CMD, CLK */
  2428. 204, 203,
  2429. };
  2430. static const unsigned int sdhi2_ctrl_mux[] = {
  2431. SDHI2_CMD_MARK, SDHI2_CLK_MARK,
  2432. };
  2433. static const unsigned int sdhi2_cd_0_pins[] = {
  2434. /* CD */
  2435. 202,
  2436. };
  2437. static const unsigned int sdhi2_cd_0_mux[] = {
  2438. SDHI2_CD_PORT202_MARK,
  2439. };
  2440. static const unsigned int sdhi2_wp_0_pins[] = {
  2441. /* WP */
  2442. 177,
  2443. };
  2444. static const unsigned int sdhi2_wp_0_mux[] = {
  2445. SDHI2_WP_PORT177_MARK,
  2446. };
  2447. static const unsigned int sdhi2_cd_1_pins[] = {
  2448. /* CD */
  2449. 24,
  2450. };
  2451. static const unsigned int sdhi2_cd_1_mux[] = {
  2452. SDHI2_CD_PORT24_MARK,
  2453. };
  2454. static const unsigned int sdhi2_wp_1_pins[] = {
  2455. /* WP */
  2456. 25,
  2457. };
  2458. static const unsigned int sdhi2_wp_1_mux[] = {
  2459. SDHI2_WP_PORT25_MARK,
  2460. };
  2461. /* - TPU0 ------------------------------------------------------------------- */
  2462. static const unsigned int tpu0_to0_pins[] = {
  2463. /* TO */
  2464. 23,
  2465. };
  2466. static const unsigned int tpu0_to0_mux[] = {
  2467. TPU0TO0_MARK,
  2468. };
  2469. static const unsigned int tpu0_to1_pins[] = {
  2470. /* TO */
  2471. 21,
  2472. };
  2473. static const unsigned int tpu0_to1_mux[] = {
  2474. TPU0TO1_MARK,
  2475. };
  2476. static const unsigned int tpu0_to2_0_pins[] = {
  2477. /* TO */
  2478. 66,
  2479. };
  2480. static const unsigned int tpu0_to2_0_mux[] = {
  2481. TPU0TO2_PORT66_MARK,
  2482. };
  2483. static const unsigned int tpu0_to2_1_pins[] = {
  2484. /* TO */
  2485. 202,
  2486. };
  2487. static const unsigned int tpu0_to2_1_mux[] = {
  2488. TPU0TO2_PORT202_MARK,
  2489. };
  2490. static const unsigned int tpu0_to3_pins[] = {
  2491. /* TO */
  2492. 180,
  2493. };
  2494. static const unsigned int tpu0_to3_mux[] = {
  2495. TPU0TO3_MARK,
  2496. };
  2497. static const struct sh_pfc_pin_group pinmux_groups[] = {
  2498. SH_PFC_PIN_GROUP(bsc_data8),
  2499. SH_PFC_PIN_GROUP(bsc_data16),
  2500. SH_PFC_PIN_GROUP(bsc_data32),
  2501. SH_PFC_PIN_GROUP(bsc_cs0),
  2502. SH_PFC_PIN_GROUP(bsc_cs2),
  2503. SH_PFC_PIN_GROUP(bsc_cs4),
  2504. SH_PFC_PIN_GROUP(bsc_cs5a_0),
  2505. SH_PFC_PIN_GROUP(bsc_cs5a_1),
  2506. SH_PFC_PIN_GROUP(bsc_cs5b),
  2507. SH_PFC_PIN_GROUP(bsc_cs6a),
  2508. SH_PFC_PIN_GROUP(bsc_rd_we8),
  2509. SH_PFC_PIN_GROUP(bsc_rd_we16),
  2510. SH_PFC_PIN_GROUP(bsc_rd_we32),
  2511. SH_PFC_PIN_GROUP(bsc_bs),
  2512. SH_PFC_PIN_GROUP(bsc_rdwr),
  2513. SH_PFC_PIN_GROUP(ceu0_data_0_7),
  2514. SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
  2515. SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
  2516. SH_PFC_PIN_GROUP(ceu0_clk_0),
  2517. SH_PFC_PIN_GROUP(ceu0_clk_1),
  2518. SH_PFC_PIN_GROUP(ceu0_clk_2),
  2519. SH_PFC_PIN_GROUP(ceu0_sync),
  2520. SH_PFC_PIN_GROUP(ceu0_field),
  2521. SH_PFC_PIN_GROUP(ceu1_data),
  2522. SH_PFC_PIN_GROUP(ceu1_clk),
  2523. SH_PFC_PIN_GROUP(ceu1_sync),
  2524. SH_PFC_PIN_GROUP(ceu1_field),
  2525. SH_PFC_PIN_GROUP(fsia_mclk_in),
  2526. SH_PFC_PIN_GROUP(fsia_mclk_out),
  2527. SH_PFC_PIN_GROUP(fsia_sclk_in),
  2528. SH_PFC_PIN_GROUP(fsia_sclk_out),
  2529. SH_PFC_PIN_GROUP(fsia_data_in_0),
  2530. SH_PFC_PIN_GROUP(fsia_data_in_1),
  2531. SH_PFC_PIN_GROUP(fsia_data_out_0),
  2532. SH_PFC_PIN_GROUP(fsia_data_out_1),
  2533. SH_PFC_PIN_GROUP(fsia_data_out_2),
  2534. SH_PFC_PIN_GROUP(fsia_spdif_0),
  2535. SH_PFC_PIN_GROUP(fsia_spdif_1),
  2536. SH_PFC_PIN_GROUP(fsib_mclk_in),
  2537. SH_PFC_PIN_GROUP(gether_rmii),
  2538. SH_PFC_PIN_GROUP(gether_mii),
  2539. SH_PFC_PIN_GROUP(gether_gmii),
  2540. SH_PFC_PIN_GROUP(gether_int),
  2541. SH_PFC_PIN_GROUP(gether_link),
  2542. SH_PFC_PIN_GROUP(gether_wol),
  2543. SH_PFC_PIN_GROUP(hdmi),
  2544. SH_PFC_PIN_GROUP(intc_irq0_0),
  2545. SH_PFC_PIN_GROUP(intc_irq0_1),
  2546. SH_PFC_PIN_GROUP(intc_irq1),
  2547. SH_PFC_PIN_GROUP(intc_irq2_0),
  2548. SH_PFC_PIN_GROUP(intc_irq2_1),
  2549. SH_PFC_PIN_GROUP(intc_irq3_0),
  2550. SH_PFC_PIN_GROUP(intc_irq3_1),
  2551. SH_PFC_PIN_GROUP(intc_irq4_0),
  2552. SH_PFC_PIN_GROUP(intc_irq4_1),
  2553. SH_PFC_PIN_GROUP(intc_irq5_0),
  2554. SH_PFC_PIN_GROUP(intc_irq5_1),
  2555. SH_PFC_PIN_GROUP(intc_irq6_0),
  2556. SH_PFC_PIN_GROUP(intc_irq6_1),
  2557. SH_PFC_PIN_GROUP(intc_irq7_0),
  2558. SH_PFC_PIN_GROUP(intc_irq7_1),
  2559. SH_PFC_PIN_GROUP(intc_irq8),
  2560. SH_PFC_PIN_GROUP(intc_irq9_0),
  2561. SH_PFC_PIN_GROUP(intc_irq9_1),
  2562. SH_PFC_PIN_GROUP(intc_irq10),
  2563. SH_PFC_PIN_GROUP(intc_irq11),
  2564. SH_PFC_PIN_GROUP(intc_irq12_0),
  2565. SH_PFC_PIN_GROUP(intc_irq12_1),
  2566. SH_PFC_PIN_GROUP(intc_irq13_0),
  2567. SH_PFC_PIN_GROUP(intc_irq13_1),
  2568. SH_PFC_PIN_GROUP(intc_irq14_0),
  2569. SH_PFC_PIN_GROUP(intc_irq14_1),
  2570. SH_PFC_PIN_GROUP(intc_irq15_0),
  2571. SH_PFC_PIN_GROUP(intc_irq15_1),
  2572. SH_PFC_PIN_GROUP(intc_irq16_0),
  2573. SH_PFC_PIN_GROUP(intc_irq16_1),
  2574. SH_PFC_PIN_GROUP(intc_irq17),
  2575. SH_PFC_PIN_GROUP(intc_irq18),
  2576. SH_PFC_PIN_GROUP(intc_irq19),
  2577. SH_PFC_PIN_GROUP(intc_irq20),
  2578. SH_PFC_PIN_GROUP(intc_irq21),
  2579. SH_PFC_PIN_GROUP(intc_irq22),
  2580. SH_PFC_PIN_GROUP(intc_irq23),
  2581. SH_PFC_PIN_GROUP(intc_irq24),
  2582. SH_PFC_PIN_GROUP(intc_irq25),
  2583. SH_PFC_PIN_GROUP(intc_irq26_0),
  2584. SH_PFC_PIN_GROUP(intc_irq26_1),
  2585. SH_PFC_PIN_GROUP(intc_irq27_0),
  2586. SH_PFC_PIN_GROUP(intc_irq27_1),
  2587. SH_PFC_PIN_GROUP(intc_irq28_0),
  2588. SH_PFC_PIN_GROUP(intc_irq28_1),
  2589. SH_PFC_PIN_GROUP(intc_irq29_0),
  2590. SH_PFC_PIN_GROUP(intc_irq29_1),
  2591. SH_PFC_PIN_GROUP(intc_irq30_0),
  2592. SH_PFC_PIN_GROUP(intc_irq30_1),
  2593. SH_PFC_PIN_GROUP(intc_irq31_0),
  2594. SH_PFC_PIN_GROUP(intc_irq31_1),
  2595. SH_PFC_PIN_GROUP(lcd0_data8),
  2596. SH_PFC_PIN_GROUP(lcd0_data9),
  2597. SH_PFC_PIN_GROUP(lcd0_data12),
  2598. SH_PFC_PIN_GROUP(lcd0_data16),
  2599. SH_PFC_PIN_GROUP(lcd0_data18),
  2600. SH_PFC_PIN_GROUP(lcd0_data24_0),
  2601. SH_PFC_PIN_GROUP(lcd0_data24_1),
  2602. SH_PFC_PIN_GROUP(lcd0_display),
  2603. SH_PFC_PIN_GROUP(lcd0_lclk_0),
  2604. SH_PFC_PIN_GROUP(lcd0_lclk_1),
  2605. SH_PFC_PIN_GROUP(lcd0_sync),
  2606. SH_PFC_PIN_GROUP(lcd0_sys),
  2607. SH_PFC_PIN_GROUP(lcd1_data8),
  2608. SH_PFC_PIN_GROUP(lcd1_data9),
  2609. SH_PFC_PIN_GROUP(lcd1_data12),
  2610. SH_PFC_PIN_GROUP(lcd1_data16),
  2611. SH_PFC_PIN_GROUP(lcd1_data18),
  2612. SH_PFC_PIN_GROUP(lcd1_data24),
  2613. SH_PFC_PIN_GROUP(lcd1_display),
  2614. SH_PFC_PIN_GROUP(lcd1_lclk),
  2615. SH_PFC_PIN_GROUP(lcd1_sync),
  2616. SH_PFC_PIN_GROUP(lcd1_sys),
  2617. SH_PFC_PIN_GROUP(mmc0_data1_0),
  2618. SH_PFC_PIN_GROUP(mmc0_data4_0),
  2619. SH_PFC_PIN_GROUP(mmc0_data8_0),
  2620. SH_PFC_PIN_GROUP(mmc0_ctrl_0),
  2621. SH_PFC_PIN_GROUP(mmc0_data1_1),
  2622. SH_PFC_PIN_GROUP(mmc0_data4_1),
  2623. SH_PFC_PIN_GROUP(mmc0_data8_1),
  2624. SH_PFC_PIN_GROUP(mmc0_ctrl_1),
  2625. SH_PFC_PIN_GROUP(scifa0_data),
  2626. SH_PFC_PIN_GROUP(scifa0_clk),
  2627. SH_PFC_PIN_GROUP(scifa0_ctrl),
  2628. SH_PFC_PIN_GROUP(scifa1_data),
  2629. SH_PFC_PIN_GROUP(scifa1_clk),
  2630. SH_PFC_PIN_GROUP(scifa1_ctrl),
  2631. SH_PFC_PIN_GROUP(scifa2_data),
  2632. SH_PFC_PIN_GROUP(scifa2_clk_0),
  2633. SH_PFC_PIN_GROUP(scifa2_clk_1),
  2634. SH_PFC_PIN_GROUP(scifa2_ctrl),
  2635. SH_PFC_PIN_GROUP(scifa3_data_0),
  2636. SH_PFC_PIN_GROUP(scifa3_clk_0),
  2637. SH_PFC_PIN_GROUP(scifa3_ctrl_0),
  2638. SH_PFC_PIN_GROUP(scifa3_data_1),
  2639. SH_PFC_PIN_GROUP(scifa3_clk_1),
  2640. SH_PFC_PIN_GROUP(scifa3_ctrl_1),
  2641. SH_PFC_PIN_GROUP(scifa4_data_0),
  2642. SH_PFC_PIN_GROUP(scifa4_data_1),
  2643. SH_PFC_PIN_GROUP(scifa4_data_2),
  2644. SH_PFC_PIN_GROUP(scifa4_clk_0),
  2645. SH_PFC_PIN_GROUP(scifa4_clk_1),
  2646. SH_PFC_PIN_GROUP(scifa5_data_0),
  2647. SH_PFC_PIN_GROUP(scifa5_data_1),
  2648. SH_PFC_PIN_GROUP(scifa5_data_2),
  2649. SH_PFC_PIN_GROUP(scifa5_clk_0),
  2650. SH_PFC_PIN_GROUP(scifa5_clk_1),
  2651. SH_PFC_PIN_GROUP(scifa6_data),
  2652. SH_PFC_PIN_GROUP(scifa6_clk),
  2653. SH_PFC_PIN_GROUP(scifa7_data),
  2654. SH_PFC_PIN_GROUP(scifb_data_0),
  2655. SH_PFC_PIN_GROUP(scifb_clk_0),
  2656. SH_PFC_PIN_GROUP(scifb_ctrl_0),
  2657. SH_PFC_PIN_GROUP(scifb_data_1),
  2658. SH_PFC_PIN_GROUP(scifb_clk_1),
  2659. SH_PFC_PIN_GROUP(scifb_ctrl_1),
  2660. SH_PFC_PIN_GROUP(sdhi0_data1),
  2661. SH_PFC_PIN_GROUP(sdhi0_data4),
  2662. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  2663. SH_PFC_PIN_GROUP(sdhi0_cd),
  2664. SH_PFC_PIN_GROUP(sdhi0_wp),
  2665. SH_PFC_PIN_GROUP(sdhi1_data1),
  2666. SH_PFC_PIN_GROUP(sdhi1_data4),
  2667. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  2668. SH_PFC_PIN_GROUP(sdhi1_cd),
  2669. SH_PFC_PIN_GROUP(sdhi1_wp),
  2670. SH_PFC_PIN_GROUP(sdhi2_data1),
  2671. SH_PFC_PIN_GROUP(sdhi2_data4),
  2672. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  2673. SH_PFC_PIN_GROUP(sdhi2_cd_0),
  2674. SH_PFC_PIN_GROUP(sdhi2_wp_0),
  2675. SH_PFC_PIN_GROUP(sdhi2_cd_1),
  2676. SH_PFC_PIN_GROUP(sdhi2_wp_1),
  2677. SH_PFC_PIN_GROUP(tpu0_to0),
  2678. SH_PFC_PIN_GROUP(tpu0_to1),
  2679. SH_PFC_PIN_GROUP(tpu0_to2_0),
  2680. SH_PFC_PIN_GROUP(tpu0_to2_1),
  2681. SH_PFC_PIN_GROUP(tpu0_to3),
  2682. };
  2683. static const char * const bsc_groups[] = {
  2684. "bsc_data8",
  2685. "bsc_data16",
  2686. "bsc_data32",
  2687. "bsc_cs0",
  2688. "bsc_cs2",
  2689. "bsc_cs4",
  2690. "bsc_cs5a_0",
  2691. "bsc_cs5a_1",
  2692. "bsc_cs5b",
  2693. "bsc_cs6a",
  2694. "bsc_rd_we8",
  2695. "bsc_rd_we16",
  2696. "bsc_rd_we32",
  2697. "bsc_bs",
  2698. "bsc_rdwr",
  2699. };
  2700. static const char * const ceu0_groups[] = {
  2701. "ceu0_data_0_7",
  2702. "ceu0_data_8_15_0",
  2703. "ceu0_data_8_15_1",
  2704. "ceu0_clk_0",
  2705. "ceu0_clk_1",
  2706. "ceu0_clk_2",
  2707. "ceu0_sync",
  2708. "ceu0_field",
  2709. };
  2710. static const char * const ceu1_groups[] = {
  2711. "ceu1_data",
  2712. "ceu1_clk",
  2713. "ceu1_sync",
  2714. "ceu1_field",
  2715. };
  2716. static const char * const fsia_groups[] = {
  2717. "fsia_mclk_in",
  2718. "fsia_mclk_out",
  2719. "fsia_sclk_in",
  2720. "fsia_sclk_out",
  2721. "fsia_data_in_0",
  2722. "fsia_data_in_1",
  2723. "fsia_data_out_0",
  2724. "fsia_data_out_1",
  2725. "fsia_data_out_2",
  2726. "fsia_spdif_0",
  2727. "fsia_spdif_1",
  2728. };
  2729. static const char * const fsib_groups[] = {
  2730. "fsib_mclk_in",
  2731. };
  2732. static const char * const gether_groups[] = {
  2733. "gether_rmii",
  2734. "gether_mii",
  2735. "gether_gmii",
  2736. "gether_int",
  2737. "gether_link",
  2738. "gether_wol",
  2739. };
  2740. static const char * const hdmi_groups[] = {
  2741. "hdmi",
  2742. };
  2743. static const char * const intc_groups[] = {
  2744. "intc_irq0_0",
  2745. "intc_irq0_1",
  2746. "intc_irq1",
  2747. "intc_irq2_0",
  2748. "intc_irq2_1",
  2749. "intc_irq3_0",
  2750. "intc_irq3_1",
  2751. "intc_irq4_0",
  2752. "intc_irq4_1",
  2753. "intc_irq5_0",
  2754. "intc_irq5_1",
  2755. "intc_irq6_0",
  2756. "intc_irq6_1",
  2757. "intc_irq7_0",
  2758. "intc_irq7_1",
  2759. "intc_irq8",
  2760. "intc_irq9_0",
  2761. "intc_irq9_1",
  2762. "intc_irq10",
  2763. "intc_irq11",
  2764. "intc_irq12_0",
  2765. "intc_irq12_1",
  2766. "intc_irq13_0",
  2767. "intc_irq13_1",
  2768. "intc_irq14_0",
  2769. "intc_irq14_1",
  2770. "intc_irq15_0",
  2771. "intc_irq15_1",
  2772. "intc_irq16_0",
  2773. "intc_irq16_1",
  2774. "intc_irq17",
  2775. "intc_irq18",
  2776. "intc_irq19",
  2777. "intc_irq20",
  2778. "intc_irq21",
  2779. "intc_irq22",
  2780. "intc_irq23",
  2781. "intc_irq24",
  2782. "intc_irq25",
  2783. "intc_irq26_0",
  2784. "intc_irq26_1",
  2785. "intc_irq27_0",
  2786. "intc_irq27_1",
  2787. "intc_irq28_0",
  2788. "intc_irq28_1",
  2789. "intc_irq29_0",
  2790. "intc_irq29_1",
  2791. "intc_irq30_0",
  2792. "intc_irq30_1",
  2793. "intc_irq31_0",
  2794. "intc_irq31_1",
  2795. };
  2796. static const char * const lcd0_groups[] = {
  2797. "lcd0_data8",
  2798. "lcd0_data9",
  2799. "lcd0_data12",
  2800. "lcd0_data16",
  2801. "lcd0_data18",
  2802. "lcd0_data24_0",
  2803. "lcd0_data24_1",
  2804. "lcd0_display",
  2805. "lcd0_lclk_0",
  2806. "lcd0_lclk_1",
  2807. "lcd0_sync",
  2808. "lcd0_sys",
  2809. };
  2810. static const char * const lcd1_groups[] = {
  2811. "lcd1_data8",
  2812. "lcd1_data9",
  2813. "lcd1_data12",
  2814. "lcd1_data16",
  2815. "lcd1_data18",
  2816. "lcd1_data24",
  2817. "lcd1_display",
  2818. "lcd1_lclk",
  2819. "lcd1_sync",
  2820. "lcd1_sys",
  2821. };
  2822. static const char * const mmc0_groups[] = {
  2823. "mmc0_data1_0",
  2824. "mmc0_data4_0",
  2825. "mmc0_data8_0",
  2826. "mmc0_ctrl_0",
  2827. "mmc0_data1_1",
  2828. "mmc0_data4_1",
  2829. "mmc0_data8_1",
  2830. "mmc0_ctrl_1",
  2831. };
  2832. static const char * const scifa0_groups[] = {
  2833. "scifa0_data",
  2834. "scifa0_clk",
  2835. "scifa0_ctrl",
  2836. };
  2837. static const char * const scifa1_groups[] = {
  2838. "scifa1_data",
  2839. "scifa1_clk",
  2840. "scifa1_ctrl",
  2841. };
  2842. static const char * const scifa2_groups[] = {
  2843. "scifa2_data",
  2844. "scifa2_clk_0",
  2845. "scifa2_clk_1",
  2846. "scifa2_ctrl",
  2847. };
  2848. static const char * const scifa3_groups[] = {
  2849. "scifa3_data_0",
  2850. "scifa3_clk_0",
  2851. "scifa3_ctrl_0",
  2852. "scifa3_data_1",
  2853. "scifa3_clk_1",
  2854. "scifa3_ctrl_1",
  2855. };
  2856. static const char * const scifa4_groups[] = {
  2857. "scifa4_data_0",
  2858. "scifa4_data_1",
  2859. "scifa4_data_2",
  2860. "scifa4_clk_0",
  2861. "scifa4_clk_1",
  2862. };
  2863. static const char * const scifa5_groups[] = {
  2864. "scifa5_data_0",
  2865. "scifa5_data_1",
  2866. "scifa5_data_2",
  2867. "scifa5_clk_0",
  2868. "scifa5_clk_1",
  2869. };
  2870. static const char * const scifa6_groups[] = {
  2871. "scifa6_data",
  2872. "scifa6_clk",
  2873. };
  2874. static const char * const scifa7_groups[] = {
  2875. "scifa7_data",
  2876. };
  2877. static const char * const scifb_groups[] = {
  2878. "scifb_data_0",
  2879. "scifb_clk_0",
  2880. "scifb_ctrl_0",
  2881. "scifb_data_1",
  2882. "scifb_clk_1",
  2883. "scifb_ctrl_1",
  2884. };
  2885. static const char * const sdhi0_groups[] = {
  2886. "sdhi0_data1",
  2887. "sdhi0_data4",
  2888. "sdhi0_ctrl",
  2889. "sdhi0_cd",
  2890. "sdhi0_wp",
  2891. };
  2892. static const char * const sdhi1_groups[] = {
  2893. "sdhi1_data1",
  2894. "sdhi1_data4",
  2895. "sdhi1_ctrl",
  2896. "sdhi1_cd",
  2897. "sdhi1_wp",
  2898. };
  2899. static const char * const sdhi2_groups[] = {
  2900. "sdhi2_data1",
  2901. "sdhi2_data4",
  2902. "sdhi2_ctrl",
  2903. "sdhi2_cd_0",
  2904. "sdhi2_wp_0",
  2905. "sdhi2_cd_1",
  2906. "sdhi2_wp_1",
  2907. };
  2908. static const char * const tpu0_groups[] = {
  2909. "tpu0_to0",
  2910. "tpu0_to1",
  2911. "tpu0_to2_0",
  2912. "tpu0_to2_1",
  2913. "tpu0_to3",
  2914. };
  2915. static const struct sh_pfc_function pinmux_functions[] = {
  2916. SH_PFC_FUNCTION(bsc),
  2917. SH_PFC_FUNCTION(ceu0),
  2918. SH_PFC_FUNCTION(ceu1),
  2919. SH_PFC_FUNCTION(fsia),
  2920. SH_PFC_FUNCTION(fsib),
  2921. SH_PFC_FUNCTION(gether),
  2922. SH_PFC_FUNCTION(hdmi),
  2923. SH_PFC_FUNCTION(intc),
  2924. SH_PFC_FUNCTION(lcd0),
  2925. SH_PFC_FUNCTION(lcd1),
  2926. SH_PFC_FUNCTION(mmc0),
  2927. SH_PFC_FUNCTION(scifa0),
  2928. SH_PFC_FUNCTION(scifa1),
  2929. SH_PFC_FUNCTION(scifa2),
  2930. SH_PFC_FUNCTION(scifa3),
  2931. SH_PFC_FUNCTION(scifa4),
  2932. SH_PFC_FUNCTION(scifa5),
  2933. SH_PFC_FUNCTION(scifa6),
  2934. SH_PFC_FUNCTION(scifa7),
  2935. SH_PFC_FUNCTION(scifb),
  2936. SH_PFC_FUNCTION(sdhi0),
  2937. SH_PFC_FUNCTION(sdhi1),
  2938. SH_PFC_FUNCTION(sdhi2),
  2939. SH_PFC_FUNCTION(tpu0),
  2940. };
  2941. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  2942. PORTCR(0, 0xe6050000), /* PORT0CR */
  2943. PORTCR(1, 0xe6050001), /* PORT1CR */
  2944. PORTCR(2, 0xe6050002), /* PORT2CR */
  2945. PORTCR(3, 0xe6050003), /* PORT3CR */
  2946. PORTCR(4, 0xe6050004), /* PORT4CR */
  2947. PORTCR(5, 0xe6050005), /* PORT5CR */
  2948. PORTCR(6, 0xe6050006), /* PORT6CR */
  2949. PORTCR(7, 0xe6050007), /* PORT7CR */
  2950. PORTCR(8, 0xe6050008), /* PORT8CR */
  2951. PORTCR(9, 0xe6050009), /* PORT9CR */
  2952. PORTCR(10, 0xe605000a), /* PORT10CR */
  2953. PORTCR(11, 0xe605000b), /* PORT11CR */
  2954. PORTCR(12, 0xe605000c), /* PORT12CR */
  2955. PORTCR(13, 0xe605000d), /* PORT13CR */
  2956. PORTCR(14, 0xe605000e), /* PORT14CR */
  2957. PORTCR(15, 0xe605000f), /* PORT15CR */
  2958. PORTCR(16, 0xe6050010), /* PORT16CR */
  2959. PORTCR(17, 0xe6050011), /* PORT17CR */
  2960. PORTCR(18, 0xe6050012), /* PORT18CR */
  2961. PORTCR(19, 0xe6050013), /* PORT19CR */
  2962. PORTCR(20, 0xe6050014), /* PORT20CR */
  2963. PORTCR(21, 0xe6050015), /* PORT21CR */
  2964. PORTCR(22, 0xe6050016), /* PORT22CR */
  2965. PORTCR(23, 0xe6050017), /* PORT23CR */
  2966. PORTCR(24, 0xe6050018), /* PORT24CR */
  2967. PORTCR(25, 0xe6050019), /* PORT25CR */
  2968. PORTCR(26, 0xe605001a), /* PORT26CR */
  2969. PORTCR(27, 0xe605001b), /* PORT27CR */
  2970. PORTCR(28, 0xe605001c), /* PORT28CR */
  2971. PORTCR(29, 0xe605001d), /* PORT29CR */
  2972. PORTCR(30, 0xe605001e), /* PORT30CR */
  2973. PORTCR(31, 0xe605001f), /* PORT31CR */
  2974. PORTCR(32, 0xe6050020), /* PORT32CR */
  2975. PORTCR(33, 0xe6050021), /* PORT33CR */
  2976. PORTCR(34, 0xe6050022), /* PORT34CR */
  2977. PORTCR(35, 0xe6050023), /* PORT35CR */
  2978. PORTCR(36, 0xe6050024), /* PORT36CR */
  2979. PORTCR(37, 0xe6050025), /* PORT37CR */
  2980. PORTCR(38, 0xe6050026), /* PORT38CR */
  2981. PORTCR(39, 0xe6050027), /* PORT39CR */
  2982. PORTCR(40, 0xe6050028), /* PORT40CR */
  2983. PORTCR(41, 0xe6050029), /* PORT41CR */
  2984. PORTCR(42, 0xe605002a), /* PORT42CR */
  2985. PORTCR(43, 0xe605002b), /* PORT43CR */
  2986. PORTCR(44, 0xe605002c), /* PORT44CR */
  2987. PORTCR(45, 0xe605002d), /* PORT45CR */
  2988. PORTCR(46, 0xe605002e), /* PORT46CR */
  2989. PORTCR(47, 0xe605002f), /* PORT47CR */
  2990. PORTCR(48, 0xe6050030), /* PORT48CR */
  2991. PORTCR(49, 0xe6050031), /* PORT49CR */
  2992. PORTCR(50, 0xe6050032), /* PORT50CR */
  2993. PORTCR(51, 0xe6050033), /* PORT51CR */
  2994. PORTCR(52, 0xe6050034), /* PORT52CR */
  2995. PORTCR(53, 0xe6050035), /* PORT53CR */
  2996. PORTCR(54, 0xe6050036), /* PORT54CR */
  2997. PORTCR(55, 0xe6050037), /* PORT55CR */
  2998. PORTCR(56, 0xe6050038), /* PORT56CR */
  2999. PORTCR(57, 0xe6050039), /* PORT57CR */
  3000. PORTCR(58, 0xe605003a), /* PORT58CR */
  3001. PORTCR(59, 0xe605003b), /* PORT59CR */
  3002. PORTCR(60, 0xe605003c), /* PORT60CR */
  3003. PORTCR(61, 0xe605003d), /* PORT61CR */
  3004. PORTCR(62, 0xe605003e), /* PORT62CR */
  3005. PORTCR(63, 0xe605003f), /* PORT63CR */
  3006. PORTCR(64, 0xe6050040), /* PORT64CR */
  3007. PORTCR(65, 0xe6050041), /* PORT65CR */
  3008. PORTCR(66, 0xe6050042), /* PORT66CR */
  3009. PORTCR(67, 0xe6050043), /* PORT67CR */
  3010. PORTCR(68, 0xe6050044), /* PORT68CR */
  3011. PORTCR(69, 0xe6050045), /* PORT69CR */
  3012. PORTCR(70, 0xe6050046), /* PORT70CR */
  3013. PORTCR(71, 0xe6050047), /* PORT71CR */
  3014. PORTCR(72, 0xe6050048), /* PORT72CR */
  3015. PORTCR(73, 0xe6050049), /* PORT73CR */
  3016. PORTCR(74, 0xe605004a), /* PORT74CR */
  3017. PORTCR(75, 0xe605004b), /* PORT75CR */
  3018. PORTCR(76, 0xe605004c), /* PORT76CR */
  3019. PORTCR(77, 0xe605004d), /* PORT77CR */
  3020. PORTCR(78, 0xe605004e), /* PORT78CR */
  3021. PORTCR(79, 0xe605004f), /* PORT79CR */
  3022. PORTCR(80, 0xe6050050), /* PORT80CR */
  3023. PORTCR(81, 0xe6050051), /* PORT81CR */
  3024. PORTCR(82, 0xe6050052), /* PORT82CR */
  3025. PORTCR(83, 0xe6050053), /* PORT83CR */
  3026. PORTCR(84, 0xe6051054), /* PORT84CR */
  3027. PORTCR(85, 0xe6051055), /* PORT85CR */
  3028. PORTCR(86, 0xe6051056), /* PORT86CR */
  3029. PORTCR(87, 0xe6051057), /* PORT87CR */
  3030. PORTCR(88, 0xe6051058), /* PORT88CR */
  3031. PORTCR(89, 0xe6051059), /* PORT89CR */
  3032. PORTCR(90, 0xe605105a), /* PORT90CR */
  3033. PORTCR(91, 0xe605105b), /* PORT91CR */
  3034. PORTCR(92, 0xe605105c), /* PORT92CR */
  3035. PORTCR(93, 0xe605105d), /* PORT93CR */
  3036. PORTCR(94, 0xe605105e), /* PORT94CR */
  3037. PORTCR(95, 0xe605105f), /* PORT95CR */
  3038. PORTCR(96, 0xe6051060), /* PORT96CR */
  3039. PORTCR(97, 0xe6051061), /* PORT97CR */
  3040. PORTCR(98, 0xe6051062), /* PORT98CR */
  3041. PORTCR(99, 0xe6051063), /* PORT99CR */
  3042. PORTCR(100, 0xe6051064), /* PORT100CR */
  3043. PORTCR(101, 0xe6051065), /* PORT101CR */
  3044. PORTCR(102, 0xe6051066), /* PORT102CR */
  3045. PORTCR(103, 0xe6051067), /* PORT103CR */
  3046. PORTCR(104, 0xe6051068), /* PORT104CR */
  3047. PORTCR(105, 0xe6051069), /* PORT105CR */
  3048. PORTCR(106, 0xe605106a), /* PORT106CR */
  3049. PORTCR(107, 0xe605106b), /* PORT107CR */
  3050. PORTCR(108, 0xe605106c), /* PORT108CR */
  3051. PORTCR(109, 0xe605106d), /* PORT109CR */
  3052. PORTCR(110, 0xe605106e), /* PORT110CR */
  3053. PORTCR(111, 0xe605106f), /* PORT111CR */
  3054. PORTCR(112, 0xe6051070), /* PORT112CR */
  3055. PORTCR(113, 0xe6051071), /* PORT113CR */
  3056. PORTCR(114, 0xe6051072), /* PORT114CR */
  3057. PORTCR(115, 0xe6052073), /* PORT115CR */
  3058. PORTCR(116, 0xe6052074), /* PORT116CR */
  3059. PORTCR(117, 0xe6052075), /* PORT117CR */
  3060. PORTCR(118, 0xe6052076), /* PORT118CR */
  3061. PORTCR(119, 0xe6052077), /* PORT119CR */
  3062. PORTCR(120, 0xe6052078), /* PORT120CR */
  3063. PORTCR(121, 0xe6052079), /* PORT121CR */
  3064. PORTCR(122, 0xe605207a), /* PORT122CR */
  3065. PORTCR(123, 0xe605207b), /* PORT123CR */
  3066. PORTCR(124, 0xe605207c), /* PORT124CR */
  3067. PORTCR(125, 0xe605207d), /* PORT125CR */
  3068. PORTCR(126, 0xe605207e), /* PORT126CR */
  3069. PORTCR(127, 0xe605207f), /* PORT127CR */
  3070. PORTCR(128, 0xe6052080), /* PORT128CR */
  3071. PORTCR(129, 0xe6052081), /* PORT129CR */
  3072. PORTCR(130, 0xe6052082), /* PORT130CR */
  3073. PORTCR(131, 0xe6052083), /* PORT131CR */
  3074. PORTCR(132, 0xe6052084), /* PORT132CR */
  3075. PORTCR(133, 0xe6052085), /* PORT133CR */
  3076. PORTCR(134, 0xe6052086), /* PORT134CR */
  3077. PORTCR(135, 0xe6052087), /* PORT135CR */
  3078. PORTCR(136, 0xe6052088), /* PORT136CR */
  3079. PORTCR(137, 0xe6052089), /* PORT137CR */
  3080. PORTCR(138, 0xe605208a), /* PORT138CR */
  3081. PORTCR(139, 0xe605208b), /* PORT139CR */
  3082. PORTCR(140, 0xe605208c), /* PORT140CR */
  3083. PORTCR(141, 0xe605208d), /* PORT141CR */
  3084. PORTCR(142, 0xe605208e), /* PORT142CR */
  3085. PORTCR(143, 0xe605208f), /* PORT143CR */
  3086. PORTCR(144, 0xe6052090), /* PORT144CR */
  3087. PORTCR(145, 0xe6052091), /* PORT145CR */
  3088. PORTCR(146, 0xe6052092), /* PORT146CR */
  3089. PORTCR(147, 0xe6052093), /* PORT147CR */
  3090. PORTCR(148, 0xe6052094), /* PORT148CR */
  3091. PORTCR(149, 0xe6052095), /* PORT149CR */
  3092. PORTCR(150, 0xe6052096), /* PORT150CR */
  3093. PORTCR(151, 0xe6052097), /* PORT151CR */
  3094. PORTCR(152, 0xe6052098), /* PORT152CR */
  3095. PORTCR(153, 0xe6052099), /* PORT153CR */
  3096. PORTCR(154, 0xe605209a), /* PORT154CR */
  3097. PORTCR(155, 0xe605209b), /* PORT155CR */
  3098. PORTCR(156, 0xe605209c), /* PORT156CR */
  3099. PORTCR(157, 0xe605209d), /* PORT157CR */
  3100. PORTCR(158, 0xe605209e), /* PORT158CR */
  3101. PORTCR(159, 0xe605209f), /* PORT159CR */
  3102. PORTCR(160, 0xe60520a0), /* PORT160CR */
  3103. PORTCR(161, 0xe60520a1), /* PORT161CR */
  3104. PORTCR(162, 0xe60520a2), /* PORT162CR */
  3105. PORTCR(163, 0xe60520a3), /* PORT163CR */
  3106. PORTCR(164, 0xe60520a4), /* PORT164CR */
  3107. PORTCR(165, 0xe60520a5), /* PORT165CR */
  3108. PORTCR(166, 0xe60520a6), /* PORT166CR */
  3109. PORTCR(167, 0xe60520a7), /* PORT167CR */
  3110. PORTCR(168, 0xe60520a8), /* PORT168CR */
  3111. PORTCR(169, 0xe60520a9), /* PORT169CR */
  3112. PORTCR(170, 0xe60520aa), /* PORT170CR */
  3113. PORTCR(171, 0xe60520ab), /* PORT171CR */
  3114. PORTCR(172, 0xe60520ac), /* PORT172CR */
  3115. PORTCR(173, 0xe60520ad), /* PORT173CR */
  3116. PORTCR(174, 0xe60520ae), /* PORT174CR */
  3117. PORTCR(175, 0xe60520af), /* PORT175CR */
  3118. PORTCR(176, 0xe60520b0), /* PORT176CR */
  3119. PORTCR(177, 0xe60520b1), /* PORT177CR */
  3120. PORTCR(178, 0xe60520b2), /* PORT178CR */
  3121. PORTCR(179, 0xe60520b3), /* PORT179CR */
  3122. PORTCR(180, 0xe60520b4), /* PORT180CR */
  3123. PORTCR(181, 0xe60520b5), /* PORT181CR */
  3124. PORTCR(182, 0xe60520b6), /* PORT182CR */
  3125. PORTCR(183, 0xe60520b7), /* PORT183CR */
  3126. PORTCR(184, 0xe60520b8), /* PORT184CR */
  3127. PORTCR(185, 0xe60520b9), /* PORT185CR */
  3128. PORTCR(186, 0xe60520ba), /* PORT186CR */
  3129. PORTCR(187, 0xe60520bb), /* PORT187CR */
  3130. PORTCR(188, 0xe60520bc), /* PORT188CR */
  3131. PORTCR(189, 0xe60520bd), /* PORT189CR */
  3132. PORTCR(190, 0xe60520be), /* PORT190CR */
  3133. PORTCR(191, 0xe60520bf), /* PORT191CR */
  3134. PORTCR(192, 0xe60520c0), /* PORT192CR */
  3135. PORTCR(193, 0xe60520c1), /* PORT193CR */
  3136. PORTCR(194, 0xe60520c2), /* PORT194CR */
  3137. PORTCR(195, 0xe60520c3), /* PORT195CR */
  3138. PORTCR(196, 0xe60520c4), /* PORT196CR */
  3139. PORTCR(197, 0xe60520c5), /* PORT197CR */
  3140. PORTCR(198, 0xe60520c6), /* PORT198CR */
  3141. PORTCR(199, 0xe60520c7), /* PORT199CR */
  3142. PORTCR(200, 0xe60520c8), /* PORT200CR */
  3143. PORTCR(201, 0xe60520c9), /* PORT201CR */
  3144. PORTCR(202, 0xe60520ca), /* PORT202CR */
  3145. PORTCR(203, 0xe60520cb), /* PORT203CR */
  3146. PORTCR(204, 0xe60520cc), /* PORT204CR */
  3147. PORTCR(205, 0xe60520cd), /* PORT205CR */
  3148. PORTCR(206, 0xe60520ce), /* PORT206CR */
  3149. PORTCR(207, 0xe60520cf), /* PORT207CR */
  3150. PORTCR(208, 0xe60520d0), /* PORT208CR */
  3151. PORTCR(209, 0xe60520d1), /* PORT209CR */
  3152. PORTCR(210, 0xe60530d2), /* PORT210CR */
  3153. PORTCR(211, 0xe60530d3), /* PORT211CR */
  3154. { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
  3155. MSEL1CR_31_0, MSEL1CR_31_1,
  3156. MSEL1CR_30_0, MSEL1CR_30_1,
  3157. MSEL1CR_29_0, MSEL1CR_29_1,
  3158. MSEL1CR_28_0, MSEL1CR_28_1,
  3159. MSEL1CR_27_0, MSEL1CR_27_1,
  3160. MSEL1CR_26_0, MSEL1CR_26_1,
  3161. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  3162. 0, 0, 0, 0, 0, 0, 0, 0,
  3163. MSEL1CR_16_0, MSEL1CR_16_1,
  3164. MSEL1CR_15_0, MSEL1CR_15_1,
  3165. MSEL1CR_14_0, MSEL1CR_14_1,
  3166. MSEL1CR_13_0, MSEL1CR_13_1,
  3167. MSEL1CR_12_0, MSEL1CR_12_1,
  3168. 0, 0, 0, 0,
  3169. MSEL1CR_9_0, MSEL1CR_9_1,
  3170. 0, 0,
  3171. MSEL1CR_7_0, MSEL1CR_7_1,
  3172. MSEL1CR_6_0, MSEL1CR_6_1,
  3173. MSEL1CR_5_0, MSEL1CR_5_1,
  3174. MSEL1CR_4_0, MSEL1CR_4_1,
  3175. MSEL1CR_3_0, MSEL1CR_3_1,
  3176. MSEL1CR_2_0, MSEL1CR_2_1,
  3177. 0, 0,
  3178. MSEL1CR_0_0, MSEL1CR_0_1,
  3179. ))
  3180. },
  3181. { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
  3182. 0, 0, 0, 0, 0, 0, 0, 0,
  3183. 0, 0, 0, 0, 0, 0, 0, 0,
  3184. 0, 0, 0, 0, 0, 0, 0, 0,
  3185. 0, 0, 0, 0, 0, 0, 0, 0,
  3186. MSEL3CR_15_0, MSEL3CR_15_1,
  3187. 0, 0, 0, 0, 0, 0, 0, 0,
  3188. 0, 0, 0, 0, 0, 0, 0, 0,
  3189. MSEL3CR_6_0, MSEL3CR_6_1,
  3190. 0, 0, 0, 0, 0, 0, 0, 0,
  3191. 0, 0, 0, 0,
  3192. ))
  3193. },
  3194. { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
  3195. 0, 0, 0, 0, 0, 0, 0, 0,
  3196. 0, 0, 0, 0, 0, 0, 0, 0,
  3197. 0, 0, 0, 0, 0, 0, 0, 0,
  3198. MSEL4CR_19_0, MSEL4CR_19_1,
  3199. MSEL4CR_18_0, MSEL4CR_18_1,
  3200. 0, 0, 0, 0,
  3201. MSEL4CR_15_0, MSEL4CR_15_1,
  3202. 0, 0, 0, 0, 0, 0, 0, 0,
  3203. MSEL4CR_10_0, MSEL4CR_10_1,
  3204. 0, 0, 0, 0, 0, 0,
  3205. MSEL4CR_6_0, MSEL4CR_6_1,
  3206. 0, 0,
  3207. MSEL4CR_4_0, MSEL4CR_4_1,
  3208. 0, 0, 0, 0,
  3209. MSEL4CR_1_0, MSEL4CR_1_1,
  3210. 0, 0,
  3211. ))
  3212. },
  3213. { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
  3214. MSEL5CR_31_0, MSEL5CR_31_1,
  3215. MSEL5CR_30_0, MSEL5CR_30_1,
  3216. MSEL5CR_29_0, MSEL5CR_29_1,
  3217. 0, 0,
  3218. MSEL5CR_27_0, MSEL5CR_27_1,
  3219. 0, 0,
  3220. MSEL5CR_25_0, MSEL5CR_25_1,
  3221. 0, 0,
  3222. MSEL5CR_23_0, MSEL5CR_23_1,
  3223. 0, 0,
  3224. MSEL5CR_21_0, MSEL5CR_21_1,
  3225. 0, 0,
  3226. MSEL5CR_19_0, MSEL5CR_19_1,
  3227. 0, 0,
  3228. MSEL5CR_17_0, MSEL5CR_17_1,
  3229. 0, 0,
  3230. MSEL5CR_15_0, MSEL5CR_15_1,
  3231. MSEL5CR_14_0, MSEL5CR_14_1,
  3232. MSEL5CR_13_0, MSEL5CR_13_1,
  3233. MSEL5CR_12_0, MSEL5CR_12_1,
  3234. MSEL5CR_11_0, MSEL5CR_11_1,
  3235. MSEL5CR_10_0, MSEL5CR_10_1,
  3236. 0, 0,
  3237. MSEL5CR_8_0, MSEL5CR_8_1,
  3238. MSEL5CR_7_0, MSEL5CR_7_1,
  3239. MSEL5CR_6_0, MSEL5CR_6_1,
  3240. MSEL5CR_5_0, MSEL5CR_5_1,
  3241. MSEL5CR_4_0, MSEL5CR_4_1,
  3242. MSEL5CR_3_0, MSEL5CR_3_1,
  3243. MSEL5CR_2_0, MSEL5CR_2_1,
  3244. 0, 0,
  3245. MSEL5CR_0_0, MSEL5CR_0_1,
  3246. ))
  3247. },
  3248. { },
  3249. };
  3250. static const struct pinmux_data_reg pinmux_data_regs[] = {
  3251. { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
  3252. PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
  3253. PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
  3254. PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
  3255. PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
  3256. PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
  3257. PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
  3258. PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
  3259. PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
  3260. },
  3261. { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
  3262. PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
  3263. PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
  3264. PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
  3265. PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
  3266. PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
  3267. PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
  3268. PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
  3269. PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
  3270. },
  3271. { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
  3272. 0, 0, 0, 0,
  3273. 0, 0, 0, 0,
  3274. 0, 0, 0, 0,
  3275. PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
  3276. PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
  3277. PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
  3278. PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
  3279. PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
  3280. },
  3281. { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
  3282. PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
  3283. PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
  3284. PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
  3285. 0, 0, 0, 0,
  3286. 0, 0, 0, 0,
  3287. 0, 0, 0, 0,
  3288. 0, 0, 0, 0,
  3289. 0, 0, 0, 0 ))
  3290. },
  3291. { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
  3292. 0, 0, 0, 0,
  3293. 0, 0, 0, 0,
  3294. 0, 0, 0, 0,
  3295. 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
  3296. PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
  3297. PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
  3298. PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
  3299. PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
  3300. },
  3301. { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
  3302. PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
  3303. PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
  3304. PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
  3305. PORT115_DATA, 0, 0, 0,
  3306. 0, 0, 0, 0,
  3307. 0, 0, 0, 0,
  3308. 0, 0, 0, 0,
  3309. 0, 0, 0, 0 ))
  3310. },
  3311. { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
  3312. PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
  3313. PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
  3314. PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
  3315. PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
  3316. PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
  3317. PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
  3318. PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
  3319. PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
  3320. },
  3321. { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
  3322. PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
  3323. PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
  3324. PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
  3325. PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
  3326. PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
  3327. PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
  3328. PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
  3329. PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
  3330. },
  3331. { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
  3332. 0, 0, 0, 0,
  3333. 0, 0, 0, 0,
  3334. 0, 0, 0, 0,
  3335. 0, 0, PORT209_DATA, PORT208_DATA,
  3336. PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
  3337. PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
  3338. PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
  3339. PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
  3340. },
  3341. { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
  3342. 0, 0, 0, 0,
  3343. 0, 0, 0, 0,
  3344. 0, 0, 0, 0,
  3345. PORT211_DATA, PORT210_DATA, 0, 0,
  3346. 0, 0, 0, 0,
  3347. 0, 0, 0, 0,
  3348. 0, 0, 0, 0,
  3349. 0, 0, 0, 0 ))
  3350. },
  3351. { },
  3352. };
  3353. static const struct pinmux_irq pinmux_irqs[] = {
  3354. PINMUX_IRQ(2, 13), /* IRQ0A */
  3355. PINMUX_IRQ(20), /* IRQ1A */
  3356. PINMUX_IRQ(11, 12), /* IRQ2A */
  3357. PINMUX_IRQ(10, 14), /* IRQ3A */
  3358. PINMUX_IRQ(15, 172), /* IRQ4A */
  3359. PINMUX_IRQ(0, 1), /* IRQ5A */
  3360. PINMUX_IRQ(121, 173), /* IRQ6A */
  3361. PINMUX_IRQ(120, 209), /* IRQ7A */
  3362. PINMUX_IRQ(119), /* IRQ8A */
  3363. PINMUX_IRQ(118, 210), /* IRQ9A */
  3364. PINMUX_IRQ(19), /* IRQ10A */
  3365. PINMUX_IRQ(104), /* IRQ11A */
  3366. PINMUX_IRQ(42, 97), /* IRQ12A */
  3367. PINMUX_IRQ(64, 98), /* IRQ13A */
  3368. PINMUX_IRQ(63, 99), /* IRQ14A */
  3369. PINMUX_IRQ(62, 100), /* IRQ15A */
  3370. PINMUX_IRQ(68, 211), /* IRQ16A */
  3371. PINMUX_IRQ(69), /* IRQ17A */
  3372. PINMUX_IRQ(70), /* IRQ18A */
  3373. PINMUX_IRQ(71), /* IRQ19A */
  3374. PINMUX_IRQ(67), /* IRQ20A */
  3375. PINMUX_IRQ(202), /* IRQ21A */
  3376. PINMUX_IRQ(95), /* IRQ22A */
  3377. PINMUX_IRQ(96), /* IRQ23A */
  3378. PINMUX_IRQ(180), /* IRQ24A */
  3379. PINMUX_IRQ(38), /* IRQ25A */
  3380. PINMUX_IRQ(58, 81), /* IRQ26A */
  3381. PINMUX_IRQ(57, 168), /* IRQ27A */
  3382. PINMUX_IRQ(56, 169), /* IRQ28A */
  3383. PINMUX_IRQ(50, 170), /* IRQ29A */
  3384. PINMUX_IRQ(49, 171), /* IRQ30A */
  3385. PINMUX_IRQ(41, 167), /* IRQ31A */
  3386. };
  3387. #define PORTnCR_PULMD_OFF (0 << 6)
  3388. #define PORTnCR_PULMD_DOWN (2 << 6)
  3389. #define PORTnCR_PULMD_UP (3 << 6)
  3390. #define PORTnCR_PULMD_MASK (3 << 6)
  3391. struct r8a7740_portcr_group {
  3392. unsigned int end_pin;
  3393. unsigned int offset;
  3394. };
  3395. static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
  3396. { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
  3397. };
  3398. static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
  3399. {
  3400. unsigned int i;
  3401. for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
  3402. const struct r8a7740_portcr_group *group =
  3403. &r8a7740_portcr_offsets[i];
  3404. if (pin <= group->end_pin)
  3405. return pfc->windows->virt + group->offset + pin;
  3406. }
  3407. return NULL;
  3408. }
  3409. static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
  3410. {
  3411. void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
  3412. u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
  3413. switch (value) {
  3414. case PORTnCR_PULMD_UP:
  3415. return PIN_CONFIG_BIAS_PULL_UP;
  3416. case PORTnCR_PULMD_DOWN:
  3417. return PIN_CONFIG_BIAS_PULL_DOWN;
  3418. case PORTnCR_PULMD_OFF:
  3419. default:
  3420. return PIN_CONFIG_BIAS_DISABLE;
  3421. }
  3422. }
  3423. static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  3424. unsigned int bias)
  3425. {
  3426. void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
  3427. u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
  3428. switch (bias) {
  3429. case PIN_CONFIG_BIAS_PULL_UP:
  3430. value |= PORTnCR_PULMD_UP;
  3431. break;
  3432. case PIN_CONFIG_BIAS_PULL_DOWN:
  3433. value |= PORTnCR_PULMD_DOWN;
  3434. break;
  3435. }
  3436. iowrite8(value, addr);
  3437. }
  3438. static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
  3439. .get_bias = r8a7740_pinmux_get_bias,
  3440. .set_bias = r8a7740_pinmux_set_bias,
  3441. };
  3442. const struct sh_pfc_soc_info r8a7740_pinmux_info = {
  3443. .name = "r8a7740_pfc",
  3444. .ops = &r8a7740_pfc_ops,
  3445. .input = { PINMUX_INPUT_BEGIN,
  3446. PINMUX_INPUT_END },
  3447. .output = { PINMUX_OUTPUT_BEGIN,
  3448. PINMUX_OUTPUT_END },
  3449. .function = { PINMUX_FUNCTION_BEGIN,
  3450. PINMUX_FUNCTION_END },
  3451. .pins = pinmux_pins,
  3452. .nr_pins = ARRAY_SIZE(pinmux_pins),
  3453. .groups = pinmux_groups,
  3454. .nr_groups = ARRAY_SIZE(pinmux_groups),
  3455. .functions = pinmux_functions,
  3456. .nr_functions = ARRAY_SIZE(pinmux_functions),
  3457. .cfg_regs = pinmux_config_regs,
  3458. .data_regs = pinmux_data_regs,
  3459. .pinmux_data = pinmux_data,
  3460. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  3461. .gpio_irq = pinmux_irqs,
  3462. .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
  3463. };