pinctrl-u300.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the U300 pin controller
  4. *
  5. * Based on the original U300 padmux functions
  6. * Copyright (C) 2009-2011 ST-Ericsson AB
  7. * Author: Martin Persson <martin.persson@stericsson.com>
  8. * Author: Linus Walleij <linus.walleij@linaro.org>
  9. *
  10. * The DB3350 design and control registers are oriented around pads rather than
  11. * pins, so we enumerate the pads we can mux rather than actual pins. The pads
  12. * are connected to different pins in different packaging types, so it would
  13. * be confusing.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/io.h>
  20. #include <linux/slab.h>
  21. #include <linux/err.h>
  22. #include <linux/pinctrl/pinctrl.h>
  23. #include <linux/pinctrl/pinmux.h>
  24. #include <linux/pinctrl/pinconf.h>
  25. #include <linux/pinctrl/pinconf-generic.h>
  26. #include "pinctrl-coh901.h"
  27. /*
  28. * Register definitions for the U300 Padmux control registers in the
  29. * system controller
  30. */
  31. /* PAD MUX Control register 1 (LOW) 16bit (R/W) */
  32. #define U300_SYSCON_PMC1LR 0x007C
  33. #define U300_SYSCON_PMC1LR_MASK 0xFFFF
  34. #define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
  35. #define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
  36. #define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
  37. /* For BS335 */
  38. #define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
  39. #define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
  40. /* For BS365 */
  41. #define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
  42. #define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
  43. /* Common defs */
  44. #define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
  45. #define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
  46. #define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
  47. #define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
  48. #define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
  49. #define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
  50. #define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
  51. #define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
  52. #define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
  53. #define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
  54. #define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
  55. #define U300_SYSCON_PMC1LR_ETM_APP 0x0100
  56. #define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
  57. #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
  58. #define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
  59. #define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
  60. #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
  61. #define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
  62. #define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
  63. #define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
  64. #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
  65. #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
  66. #define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
  67. #define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
  68. #define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
  69. #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
  70. #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
  71. #define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
  72. #define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
  73. #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
  74. #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
  75. #define U300_SYSCON_PMC1LR_EMIF_1 0x0003
  76. /* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
  77. #define U300_SYSCON_PMC1HR 0x007E
  78. #define U300_SYSCON_PMC1HR_MASK 0xFFFF
  79. #define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
  80. #define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
  81. #define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
  82. #define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
  83. #define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
  84. #define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
  85. #define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
  86. #define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
  87. #define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
  88. #define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
  89. #define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
  90. #define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
  91. #define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
  92. #define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
  93. #define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
  94. #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
  95. #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
  96. #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
  97. #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
  98. #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
  99. #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
  100. #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
  101. #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
  102. #define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
  103. #define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
  104. #define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
  105. #define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
  106. #define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
  107. #define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
  108. #define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
  109. #define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
  110. #define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
  111. #define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
  112. #define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
  113. #define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
  114. #define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
  115. #define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
  116. /* Padmux 2 control */
  117. #define U300_SYSCON_PMC2R 0x100
  118. #define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
  119. #define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
  120. #define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
  121. #define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
  122. #define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
  123. #define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
  124. #define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
  125. #define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
  126. #define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
  127. #define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
  128. #define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
  129. #define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
  130. #define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
  131. #define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
  132. #define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
  133. #define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
  134. #define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
  135. #define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
  136. #define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
  137. #define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
  138. #define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
  139. #define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
  140. #define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
  141. #define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
  142. #define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
  143. /* TODO: More SYSCON registers missing */
  144. #define U300_SYSCON_PMC3R 0x10C
  145. #define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
  146. #define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
  147. #define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
  148. #define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
  149. /* TODO: Missing other configs */
  150. #define U300_SYSCON_PMC4R 0x168
  151. #define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
  152. #define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
  153. #define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
  154. #define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
  155. #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
  156. #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
  157. #define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
  158. #define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
  159. #define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
  160. #define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
  161. #define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
  162. #define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
  163. #define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
  164. #define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
  165. #define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
  166. #define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
  167. #define DRIVER_NAME "pinctrl-u300"
  168. /*
  169. * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
  170. * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
  171. * Data taken from the PadRing chart, arranged like this:
  172. *
  173. * 0 ..... 104
  174. * 466 105
  175. * . .
  176. * . .
  177. * 358 224
  178. * 357 .... 225
  179. */
  180. #define U300_NUM_PADS 467
  181. /* Pad names for the pinmux subsystem */
  182. static const struct pinctrl_pin_desc u300_pads[] = {
  183. /* Pads along the top edge of the chip */
  184. PINCTRL_PIN(0, "P PAD VDD 28"),
  185. PINCTRL_PIN(1, "P PAD GND 28"),
  186. PINCTRL_PIN(2, "PO SIM RST N"),
  187. PINCTRL_PIN(3, "VSSIO 25"),
  188. PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
  189. PINCTRL_PIN(5, "PWR VSSCOMMON"),
  190. PINCTRL_PIN(6, "PI ADC I1 POS"),
  191. PINCTRL_PIN(7, "PI ADC I1 NEG"),
  192. PINCTRL_PIN(8, "PWR VSSAD0"),
  193. PINCTRL_PIN(9, "PWR VCCAD0"),
  194. PINCTRL_PIN(10, "PI ADC Q1 NEG"),
  195. PINCTRL_PIN(11, "PI ADC Q1 POS"),
  196. PINCTRL_PIN(12, "PWR VDDAD"),
  197. PINCTRL_PIN(13, "PWR GNDAD"),
  198. PINCTRL_PIN(14, "PI ADC I2 POS"),
  199. PINCTRL_PIN(15, "PI ADC I2 NEG"),
  200. PINCTRL_PIN(16, "PWR VSSAD1"),
  201. PINCTRL_PIN(17, "PWR VCCAD1"),
  202. PINCTRL_PIN(18, "PI ADC Q2 NEG"),
  203. PINCTRL_PIN(19, "PI ADC Q2 POS"),
  204. PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
  205. PINCTRL_PIN(21, "PWR VCCGPAD"),
  206. PINCTRL_PIN(22, "PI TX POW"),
  207. PINCTRL_PIN(23, "PWR VSSGPAD"),
  208. PINCTRL_PIN(24, "PO DAC I POS"),
  209. PINCTRL_PIN(25, "PO DAC I NEG"),
  210. PINCTRL_PIN(26, "PO DAC Q POS"),
  211. PINCTRL_PIN(27, "PO DAC Q NEG"),
  212. PINCTRL_PIN(28, "PWR VSSDA"),
  213. PINCTRL_PIN(29, "PWR VCCDA"),
  214. PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
  215. PINCTRL_PIN(31, "P PAD VDDIO 11"),
  216. PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
  217. PINCTRL_PIN(33, "PI PLL 26 VCONT"),
  218. PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
  219. PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
  220. PINCTRL_PIN(36, "VDDA PLL ESD"),
  221. PINCTRL_PIN(37, "VSSA PLL ESD"),
  222. PINCTRL_PIN(38, "VSS PLL"),
  223. PINCTRL_PIN(39, "VDDC PLL"),
  224. PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
  225. PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
  226. PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
  227. PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
  228. PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
  229. PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
  230. PINCTRL_PIN(46, "P PAD VSSIO 11"),
  231. PINCTRL_PIN(47, "P PAD VSSIO 12"),
  232. PINCTRL_PIN(48, "PI POW RST N"),
  233. PINCTRL_PIN(49, "VDDC IO"),
  234. PINCTRL_PIN(50, "P PAD VDDIO 16"),
  235. PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
  236. PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
  237. PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
  238. PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
  239. PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
  240. PINCTRL_PIN(56, "PO GSM PA ENABLE"),
  241. PINCTRL_PIN(57, "PO RF DATA STRB"),
  242. PINCTRL_PIN(58, "PO RF DATA2"),
  243. PINCTRL_PIN(59, "PIO RF DATA1"),
  244. PINCTRL_PIN(60, "PIO RF DATA0"),
  245. PINCTRL_PIN(61, "P PAD VDD 11"),
  246. PINCTRL_PIN(62, "P PAD GND 11"),
  247. PINCTRL_PIN(63, "P PAD VSSIO 16"),
  248. PINCTRL_PIN(64, "P PAD VDDIO 18"),
  249. PINCTRL_PIN(65, "PO RF CTRL STRB2"),
  250. PINCTRL_PIN(66, "PO RF CTRL STRB1"),
  251. PINCTRL_PIN(67, "PO RF CTRL STRB0"),
  252. PINCTRL_PIN(68, "PIO RF CTRL DATA"),
  253. PINCTRL_PIN(69, "PO RF CTRL CLK"),
  254. PINCTRL_PIN(70, "PO TX ADC STRB"),
  255. PINCTRL_PIN(71, "PO ANT SW 2"),
  256. PINCTRL_PIN(72, "PO ANT SW 3"),
  257. PINCTRL_PIN(73, "PO ANT SW 0"),
  258. PINCTRL_PIN(74, "PO ANT SW 1"),
  259. PINCTRL_PIN(75, "PO M CLKRQ"),
  260. PINCTRL_PIN(76, "PI M CLK"),
  261. PINCTRL_PIN(77, "PI RTC CLK"),
  262. PINCTRL_PIN(78, "P PAD VDD 8"),
  263. PINCTRL_PIN(79, "P PAD GND 8"),
  264. PINCTRL_PIN(80, "P PAD VSSIO 13"),
  265. PINCTRL_PIN(81, "P PAD VDDIO 13"),
  266. PINCTRL_PIN(82, "PO SYS 1 CLK"),
  267. PINCTRL_PIN(83, "PO SYS 2 CLK"),
  268. PINCTRL_PIN(84, "PO SYS 0 CLK"),
  269. PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
  270. PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
  271. PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
  272. PINCTRL_PIN(88, "PO RESOUT2 RST N"),
  273. PINCTRL_PIN(89, "PO RESOUT1 RST N"),
  274. PINCTRL_PIN(90, "PO RESOUT0 RST N"),
  275. PINCTRL_PIN(91, "PI SERVICE N"),
  276. PINCTRL_PIN(92, "P PAD VDD 29"),
  277. PINCTRL_PIN(93, "P PAD GND 29"),
  278. PINCTRL_PIN(94, "P PAD VSSIO 8"),
  279. PINCTRL_PIN(95, "P PAD VDDIO 8"),
  280. PINCTRL_PIN(96, "PI EXT IRQ1 N"),
  281. PINCTRL_PIN(97, "PI EXT IRQ0 N"),
  282. PINCTRL_PIN(98, "PIO DC ON"),
  283. PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
  284. PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
  285. PINCTRL_PIN(101, "P PAD VDD 12"),
  286. PINCTRL_PIN(102, "P PAD GND 12"),
  287. PINCTRL_PIN(103, "P PAD VSSIO 14"),
  288. PINCTRL_PIN(104, "P PAD VDDIO 14"),
  289. /* Pads along the right edge of the chip */
  290. PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
  291. PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
  292. PINCTRL_PIN(107, "PO KEY OUT0"),
  293. PINCTRL_PIN(108, "PO KEY OUT1"),
  294. PINCTRL_PIN(109, "PO KEY OUT2"),
  295. PINCTRL_PIN(110, "PO KEY OUT3"),
  296. PINCTRL_PIN(111, "PO KEY OUT4"),
  297. PINCTRL_PIN(112, "PI KEY IN0"),
  298. PINCTRL_PIN(113, "PI KEY IN1"),
  299. PINCTRL_PIN(114, "PI KEY IN2"),
  300. PINCTRL_PIN(115, "P PAD VDDIO 15"),
  301. PINCTRL_PIN(116, "P PAD VSSIO 15"),
  302. PINCTRL_PIN(117, "P PAD GND 13"),
  303. PINCTRL_PIN(118, "P PAD VDD 13"),
  304. PINCTRL_PIN(119, "PI KEY IN3"),
  305. PINCTRL_PIN(120, "PI KEY IN4"),
  306. PINCTRL_PIN(121, "PI KEY IN5"),
  307. PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
  308. PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
  309. PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
  310. PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
  311. PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
  312. PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
  313. PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
  314. PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
  315. PINCTRL_PIN(130, "P PAD VDD 17"),
  316. PINCTRL_PIN(131, "P PAD GND 17"),
  317. PINCTRL_PIN(132, "P PAD VSSIO 19"),
  318. PINCTRL_PIN(133, "P PAD VDDIO 19"),
  319. PINCTRL_PIN(134, "UART0 RTS"),
  320. PINCTRL_PIN(135, "UART0 CTS"),
  321. PINCTRL_PIN(136, "UART0 TX"),
  322. PINCTRL_PIN(137, "UART0 RX"),
  323. PINCTRL_PIN(138, "PIO ACC SPI DO"),
  324. PINCTRL_PIN(139, "PIO ACC SPI DI"),
  325. PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
  326. PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
  327. PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
  328. PINCTRL_PIN(143, "PIO ACC SPI CLK"),
  329. PINCTRL_PIN(144, "PO PDI EXT RST N"),
  330. PINCTRL_PIN(145, "P PAD VDDIO 22"),
  331. PINCTRL_PIN(146, "P PAD VSSIO 22"),
  332. PINCTRL_PIN(147, "P PAD GND 18"),
  333. PINCTRL_PIN(148, "P PAD VDD 18"),
  334. PINCTRL_PIN(149, "PIO PDI C0"),
  335. PINCTRL_PIN(150, "PIO PDI C1"),
  336. PINCTRL_PIN(151, "PIO PDI C2"),
  337. PINCTRL_PIN(152, "PIO PDI C3"),
  338. PINCTRL_PIN(153, "PIO PDI C4"),
  339. PINCTRL_PIN(154, "PIO PDI C5"),
  340. PINCTRL_PIN(155, "PIO PDI D0"),
  341. PINCTRL_PIN(156, "PIO PDI D1"),
  342. PINCTRL_PIN(157, "PIO PDI D2"),
  343. PINCTRL_PIN(158, "PIO PDI D3"),
  344. PINCTRL_PIN(159, "P PAD VDDIO 21"),
  345. PINCTRL_PIN(160, "P PAD VSSIO 21"),
  346. PINCTRL_PIN(161, "PIO PDI D4"),
  347. PINCTRL_PIN(162, "PIO PDI D5"),
  348. PINCTRL_PIN(163, "PIO PDI D6"),
  349. PINCTRL_PIN(164, "PIO PDI D7"),
  350. PINCTRL_PIN(165, "PIO MS INS"),
  351. PINCTRL_PIN(166, "MMC DATA DIR LS"),
  352. PINCTRL_PIN(167, "MMC DATA 3"),
  353. PINCTRL_PIN(168, "MMC DATA 2"),
  354. PINCTRL_PIN(169, "MMC DATA 1"),
  355. PINCTRL_PIN(170, "MMC DATA 0"),
  356. PINCTRL_PIN(171, "MMC CMD DIR LS"),
  357. PINCTRL_PIN(172, "P PAD VDD 27"),
  358. PINCTRL_PIN(173, "P PAD GND 27"),
  359. PINCTRL_PIN(174, "P PAD VSSIO 20"),
  360. PINCTRL_PIN(175, "P PAD VDDIO 20"),
  361. PINCTRL_PIN(176, "MMC CMD"),
  362. PINCTRL_PIN(177, "MMC CLK"),
  363. PINCTRL_PIN(178, "PIO APP GPIO 14"),
  364. PINCTRL_PIN(179, "PIO APP GPIO 13"),
  365. PINCTRL_PIN(180, "PIO APP GPIO 11"),
  366. PINCTRL_PIN(181, "PIO APP GPIO 25"),
  367. PINCTRL_PIN(182, "PIO APP GPIO 24"),
  368. PINCTRL_PIN(183, "PIO APP GPIO 23"),
  369. PINCTRL_PIN(184, "PIO APP GPIO 22"),
  370. PINCTRL_PIN(185, "PIO APP GPIO 21"),
  371. PINCTRL_PIN(186, "PIO APP GPIO 20"),
  372. PINCTRL_PIN(187, "P PAD VDD 19"),
  373. PINCTRL_PIN(188, "P PAD GND 19"),
  374. PINCTRL_PIN(189, "P PAD VSSIO 23"),
  375. PINCTRL_PIN(190, "P PAD VDDIO 23"),
  376. PINCTRL_PIN(191, "PIO APP GPIO 19"),
  377. PINCTRL_PIN(192, "PIO APP GPIO 18"),
  378. PINCTRL_PIN(193, "PIO APP GPIO 17"),
  379. PINCTRL_PIN(194, "PIO APP GPIO 16"),
  380. PINCTRL_PIN(195, "PI CI D1"),
  381. PINCTRL_PIN(196, "PI CI D0"),
  382. PINCTRL_PIN(197, "PI CI HSYNC"),
  383. PINCTRL_PIN(198, "PI CI VSYNC"),
  384. PINCTRL_PIN(199, "PI CI EXT CLK"),
  385. PINCTRL_PIN(200, "PO CI EXT RST N"),
  386. PINCTRL_PIN(201, "P PAD VSSIO 43"),
  387. PINCTRL_PIN(202, "P PAD VDDIO 43"),
  388. PINCTRL_PIN(203, "PI CI D6"),
  389. PINCTRL_PIN(204, "PI CI D7"),
  390. PINCTRL_PIN(205, "PI CI D2"),
  391. PINCTRL_PIN(206, "PI CI D3"),
  392. PINCTRL_PIN(207, "PI CI D4"),
  393. PINCTRL_PIN(208, "PI CI D5"),
  394. PINCTRL_PIN(209, "PI CI D8"),
  395. PINCTRL_PIN(210, "PI CI D9"),
  396. PINCTRL_PIN(211, "P PAD VDD 20"),
  397. PINCTRL_PIN(212, "P PAD GND 20"),
  398. PINCTRL_PIN(213, "P PAD VSSIO 24"),
  399. PINCTRL_PIN(214, "P PAD VDDIO 24"),
  400. PINCTRL_PIN(215, "P PAD VDDIO 26"),
  401. PINCTRL_PIN(216, "PO EMIF 1 A26"),
  402. PINCTRL_PIN(217, "PO EMIF 1 A25"),
  403. PINCTRL_PIN(218, "P PAD VSSIO 26"),
  404. PINCTRL_PIN(219, "PO EMIF 1 A24"),
  405. PINCTRL_PIN(220, "PO EMIF 1 A23"),
  406. /* Pads along the bottom edge of the chip */
  407. PINCTRL_PIN(221, "PO EMIF 1 A22"),
  408. PINCTRL_PIN(222, "PO EMIF 1 A21"),
  409. PINCTRL_PIN(223, "P PAD VDD 21"),
  410. PINCTRL_PIN(224, "P PAD GND 21"),
  411. PINCTRL_PIN(225, "P PAD VSSIO 27"),
  412. PINCTRL_PIN(226, "P PAD VDDIO 27"),
  413. PINCTRL_PIN(227, "PO EMIF 1 A20"),
  414. PINCTRL_PIN(228, "PO EMIF 1 A19"),
  415. PINCTRL_PIN(229, "PO EMIF 1 A18"),
  416. PINCTRL_PIN(230, "PO EMIF 1 A17"),
  417. PINCTRL_PIN(231, "P PAD VDDIO 28"),
  418. PINCTRL_PIN(232, "P PAD VSSIO 28"),
  419. PINCTRL_PIN(233, "PO EMIF 1 A16"),
  420. PINCTRL_PIN(234, "PIO EMIF 1 D15"),
  421. PINCTRL_PIN(235, "PO EMIF 1 A15"),
  422. PINCTRL_PIN(236, "PIO EMIF 1 D14"),
  423. PINCTRL_PIN(237, "P PAD VDD 22"),
  424. PINCTRL_PIN(238, "P PAD GND 22"),
  425. PINCTRL_PIN(239, "P PAD VSSIO 29"),
  426. PINCTRL_PIN(240, "P PAD VDDIO 29"),
  427. PINCTRL_PIN(241, "PO EMIF 1 A14"),
  428. PINCTRL_PIN(242, "PIO EMIF 1 D13"),
  429. PINCTRL_PIN(243, "PO EMIF 1 A13"),
  430. PINCTRL_PIN(244, "PIO EMIF 1 D12"),
  431. PINCTRL_PIN(245, "P PAD VSSIO 30"),
  432. PINCTRL_PIN(246, "P PAD VDDIO 30"),
  433. PINCTRL_PIN(247, "PO EMIF 1 A12"),
  434. PINCTRL_PIN(248, "PIO EMIF 1 D11"),
  435. PINCTRL_PIN(249, "PO EMIF 1 A11"),
  436. PINCTRL_PIN(250, "PIO EMIF 1 D10"),
  437. PINCTRL_PIN(251, "P PAD VSSIO 31"),
  438. PINCTRL_PIN(252, "P PAD VDDIO 31"),
  439. PINCTRL_PIN(253, "PO EMIF 1 A10"),
  440. PINCTRL_PIN(254, "PIO EMIF 1 D09"),
  441. PINCTRL_PIN(255, "PO EMIF 1 A09"),
  442. PINCTRL_PIN(256, "P PAD VDDIO 32"),
  443. PINCTRL_PIN(257, "P PAD VSSIO 32"),
  444. PINCTRL_PIN(258, "P PAD GND 24"),
  445. PINCTRL_PIN(259, "P PAD VDD 24"),
  446. PINCTRL_PIN(260, "PIO EMIF 1 D08"),
  447. PINCTRL_PIN(261, "PO EMIF 1 A08"),
  448. PINCTRL_PIN(262, "PIO EMIF 1 D07"),
  449. PINCTRL_PIN(263, "PO EMIF 1 A07"),
  450. PINCTRL_PIN(264, "P PAD VDDIO 33"),
  451. PINCTRL_PIN(265, "P PAD VSSIO 33"),
  452. PINCTRL_PIN(266, "PIO EMIF 1 D06"),
  453. PINCTRL_PIN(267, "PO EMIF 1 A06"),
  454. PINCTRL_PIN(268, "PIO EMIF 1 D05"),
  455. PINCTRL_PIN(269, "PO EMIF 1 A05"),
  456. PINCTRL_PIN(270, "P PAD VDDIO 34"),
  457. PINCTRL_PIN(271, "P PAD VSSIO 34"),
  458. PINCTRL_PIN(272, "PIO EMIF 1 D04"),
  459. PINCTRL_PIN(273, "PO EMIF 1 A04"),
  460. PINCTRL_PIN(274, "PIO EMIF 1 D03"),
  461. PINCTRL_PIN(275, "PO EMIF 1 A03"),
  462. PINCTRL_PIN(276, "P PAD VDDIO 35"),
  463. PINCTRL_PIN(277, "P PAD VSSIO 35"),
  464. PINCTRL_PIN(278, "P PAD GND 23"),
  465. PINCTRL_PIN(279, "P PAD VDD 23"),
  466. PINCTRL_PIN(280, "PIO EMIF 1 D02"),
  467. PINCTRL_PIN(281, "PO EMIF 1 A02"),
  468. PINCTRL_PIN(282, "PIO EMIF 1 D01"),
  469. PINCTRL_PIN(283, "PO EMIF 1 A01"),
  470. PINCTRL_PIN(284, "P PAD VDDIO 36"),
  471. PINCTRL_PIN(285, "P PAD VSSIO 36"),
  472. PINCTRL_PIN(286, "PIO EMIF 1 D00"),
  473. PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
  474. PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
  475. PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
  476. PINCTRL_PIN(290, "P PAD VDDIO 37"),
  477. PINCTRL_PIN(291, "P PAD VSSIO 37"),
  478. PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
  479. PINCTRL_PIN(293, "PO EMIF 1 OE N"),
  480. PINCTRL_PIN(294, "PO EMIF 1 WE N"),
  481. PINCTRL_PIN(295, "P PAD VDDIO 38"),
  482. PINCTRL_PIN(296, "P PAD VSSIO 38"),
  483. PINCTRL_PIN(297, "PO EMIF 1 CLK"),
  484. PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
  485. PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
  486. PINCTRL_PIN(300, "P PAD VDDIO 42"),
  487. PINCTRL_PIN(301, "P PAD VSSIO 42"),
  488. PINCTRL_PIN(302, "P PAD GND 31"),
  489. PINCTRL_PIN(303, "P PAD VDD 31"),
  490. PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
  491. PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
  492. PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
  493. PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
  494. PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
  495. PINCTRL_PIN(309, "P PAD VDD 25"),
  496. PINCTRL_PIN(310, "P PAD GND 25"),
  497. PINCTRL_PIN(311, "P PAD VSSIO 39"),
  498. PINCTRL_PIN(312, "P PAD VDDIO 39"),
  499. PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
  500. PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
  501. PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
  502. PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
  503. PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
  504. PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
  505. PINCTRL_PIN(319, "P PAD VDD 30"),
  506. PINCTRL_PIN(320, "P PAD GND 30"),
  507. PINCTRL_PIN(321, "P PAD VSSIO 44"),
  508. PINCTRL_PIN(322, "P PAD VDDIO 44"),
  509. PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
  510. PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
  511. PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
  512. PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
  513. PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
  514. PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
  515. PINCTRL_PIN(329, "P PAD VDD 26"),
  516. PINCTRL_PIN(330, "P PAD GND 26"),
  517. PINCTRL_PIN(331, "P PAD VSSIO 40"),
  518. PINCTRL_PIN(332, "P PAD VDDIO 40"),
  519. PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
  520. PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
  521. PINCTRL_PIN(335, "PO ETM TRACE CLK"),
  522. PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
  523. PINCTRL_PIN(337, "PIO ACC GPIO 33"),
  524. PINCTRL_PIN(338, "PIO ACC GPIO 32"),
  525. PINCTRL_PIN(339, "PIO ACC GPIO 30"),
  526. PINCTRL_PIN(340, "PIO ACC GPIO 29"),
  527. PINCTRL_PIN(341, "P PAD VDDIO 17"),
  528. PINCTRL_PIN(342, "P PAD VSSIO 17"),
  529. PINCTRL_PIN(343, "P PAD GND 15"),
  530. PINCTRL_PIN(344, "P PAD VDD 15"),
  531. PINCTRL_PIN(345, "PIO ACC GPIO 28"),
  532. PINCTRL_PIN(346, "PIO ACC GPIO 27"),
  533. PINCTRL_PIN(347, "PIO ACC GPIO 16"),
  534. PINCTRL_PIN(348, "PI TAP TMS"),
  535. PINCTRL_PIN(349, "PI TAP TDI"),
  536. PINCTRL_PIN(350, "PO TAP TDO"),
  537. PINCTRL_PIN(351, "PI TAP RST N"),
  538. /* Pads along the left edge of the chip */
  539. PINCTRL_PIN(352, "PI EMU MODE 0"),
  540. PINCTRL_PIN(353, "PO TAP RET CLK"),
  541. PINCTRL_PIN(354, "PI TAP CLK"),
  542. PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
  543. PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
  544. PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
  545. PINCTRL_PIN(358, "P PAD VDDIO 1"),
  546. PINCTRL_PIN(359, "P PAD VSSIO 1"),
  547. PINCTRL_PIN(360, "P PAD GND 1"),
  548. PINCTRL_PIN(361, "P PAD VDD 1"),
  549. PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
  550. PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
  551. PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
  552. PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
  553. PINCTRL_PIN(366, "PIO EMIF 0 D15"),
  554. PINCTRL_PIN(367, "PO EMIF 0 A15"),
  555. PINCTRL_PIN(368, "PIO EMIF 0 D14"),
  556. PINCTRL_PIN(369, "PO EMIF 0 A14"),
  557. PINCTRL_PIN(370, "PIO EMIF 0 D13"),
  558. PINCTRL_PIN(371, "PO EMIF 0 A13"),
  559. PINCTRL_PIN(372, "P PAD VDDIO 2"),
  560. PINCTRL_PIN(373, "P PAD VSSIO 2"),
  561. PINCTRL_PIN(374, "P PAD GND 2"),
  562. PINCTRL_PIN(375, "P PAD VDD 2"),
  563. PINCTRL_PIN(376, "PIO EMIF 0 D12"),
  564. PINCTRL_PIN(377, "PO EMIF 0 A12"),
  565. PINCTRL_PIN(378, "PIO EMIF 0 D11"),
  566. PINCTRL_PIN(379, "PO EMIF 0 A11"),
  567. PINCTRL_PIN(380, "PIO EMIF 0 D10"),
  568. PINCTRL_PIN(381, "PO EMIF 0 A10"),
  569. PINCTRL_PIN(382, "PIO EMIF 0 D09"),
  570. PINCTRL_PIN(383, "PO EMIF 0 A09"),
  571. PINCTRL_PIN(384, "PIO EMIF 0 D08"),
  572. PINCTRL_PIN(385, "PO EMIF 0 A08"),
  573. PINCTRL_PIN(386, "PIO EMIF 0 D07"),
  574. PINCTRL_PIN(387, "PO EMIF 0 A07"),
  575. PINCTRL_PIN(388, "P PAD VDDIO 3"),
  576. PINCTRL_PIN(389, "P PAD VSSIO 3"),
  577. PINCTRL_PIN(390, "P PAD GND 3"),
  578. PINCTRL_PIN(391, "P PAD VDD 3"),
  579. PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
  580. PINCTRL_PIN(393, "PIO EMIF 0 D06"),
  581. PINCTRL_PIN(394, "PO EMIF 0 A06"),
  582. PINCTRL_PIN(395, "PIO EMIF 0 D05"),
  583. PINCTRL_PIN(396, "PO EMIF 0 A05"),
  584. PINCTRL_PIN(397, "PIO EMIF 0 D04"),
  585. PINCTRL_PIN(398, "PO EMIF 0 A04"),
  586. PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
  587. PINCTRL_PIN(400, "PWR VDDCO AF"),
  588. PINCTRL_PIN(401, "PWR EFUSE HV1"),
  589. PINCTRL_PIN(402, "P PAD VSSIO 4"),
  590. PINCTRL_PIN(403, "P PAD VDDIO 4"),
  591. PINCTRL_PIN(404, "P PAD GND 4"),
  592. PINCTRL_PIN(405, "P PAD VDD 4"),
  593. PINCTRL_PIN(406, "PIO EMIF 0 D03"),
  594. PINCTRL_PIN(407, "PO EMIF 0 A03"),
  595. PINCTRL_PIN(408, "PWR EFUSE HV2"),
  596. PINCTRL_PIN(409, "PWR EFUSE HV3"),
  597. PINCTRL_PIN(410, "PIO EMIF 0 D02"),
  598. PINCTRL_PIN(411, "PO EMIF 0 A02"),
  599. PINCTRL_PIN(412, "PIO EMIF 0 D01"),
  600. PINCTRL_PIN(413, "P PAD VDDIO 5"),
  601. PINCTRL_PIN(414, "P PAD VSSIO 5"),
  602. PINCTRL_PIN(415, "P PAD GND 5"),
  603. PINCTRL_PIN(416, "P PAD VDD 5"),
  604. PINCTRL_PIN(417, "PO EMIF 0 A01"),
  605. PINCTRL_PIN(418, "PIO EMIF 0 D00"),
  606. PINCTRL_PIN(419, "IF 0 SD CLK"),
  607. PINCTRL_PIN(420, "APP SPI CLK"),
  608. PINCTRL_PIN(421, "APP SPI DO"),
  609. PINCTRL_PIN(422, "APP SPI DI"),
  610. PINCTRL_PIN(423, "APP SPI CS0"),
  611. PINCTRL_PIN(424, "APP SPI CS1"),
  612. PINCTRL_PIN(425, "APP SPI CS2"),
  613. PINCTRL_PIN(426, "PIO APP GPIO 10"),
  614. PINCTRL_PIN(427, "P PAD VDDIO 41"),
  615. PINCTRL_PIN(428, "P PAD VSSIO 41"),
  616. PINCTRL_PIN(429, "P PAD GND 6"),
  617. PINCTRL_PIN(430, "P PAD VDD 6"),
  618. PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
  619. PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
  620. PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
  621. PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
  622. PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
  623. PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
  624. PINCTRL_PIN(437, "PIO USB PU"),
  625. PINCTRL_PIN(438, "PIO USB SP"),
  626. PINCTRL_PIN(439, "PIO USB DAT VP"),
  627. PINCTRL_PIN(440, "PIO USB SE0 VM"),
  628. PINCTRL_PIN(441, "PIO USB OE"),
  629. PINCTRL_PIN(442, "PIO USB SUSP"),
  630. PINCTRL_PIN(443, "P PAD VSSIO 6"),
  631. PINCTRL_PIN(444, "P PAD VDDIO 6"),
  632. PINCTRL_PIN(445, "PIO USB PUEN"),
  633. PINCTRL_PIN(446, "PIO ACC UART0 RX"),
  634. PINCTRL_PIN(447, "PIO ACC UART0 TX"),
  635. PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
  636. PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
  637. PINCTRL_PIN(450, "PIO ACC UART3 RX"),
  638. PINCTRL_PIN(451, "PIO ACC UART3 TX"),
  639. PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
  640. PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
  641. PINCTRL_PIN(454, "PIO ACC IRDA TX"),
  642. PINCTRL_PIN(455, "P PAD VDDIO 7"),
  643. PINCTRL_PIN(456, "P PAD VSSIO 7"),
  644. PINCTRL_PIN(457, "P PAD GND 7"),
  645. PINCTRL_PIN(458, "P PAD VDD 7"),
  646. PINCTRL_PIN(459, "PIO ACC IRDA RX"),
  647. PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
  648. PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
  649. PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
  650. PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
  651. PINCTRL_PIN(464, "PO SIM CLK"),
  652. PINCTRL_PIN(465, "PIO ACC IRDA SD"),
  653. PINCTRL_PIN(466, "PIO SIM DATA"),
  654. };
  655. /**
  656. * @dev: a pointer back to containing device
  657. * @virtbase: the offset to the controller in virtual memory
  658. */
  659. struct u300_pmx {
  660. struct device *dev;
  661. struct pinctrl_dev *pctl;
  662. void __iomem *virtbase;
  663. };
  664. /**
  665. * u300_pmx_registers - the array of registers read/written for each pinmux
  666. * shunt setting
  667. */
  668. static const u32 u300_pmx_registers[] = {
  669. U300_SYSCON_PMC1LR,
  670. U300_SYSCON_PMC1HR,
  671. U300_SYSCON_PMC2R,
  672. U300_SYSCON_PMC3R,
  673. U300_SYSCON_PMC4R,
  674. };
  675. /**
  676. * struct u300_pin_group - describes a U300 pin group
  677. * @name: the name of this specific pin group
  678. * @pins: an array of discrete physical pins used in this group, taken
  679. * from the driver-local pin enumeration space
  680. * @num_pins: the number of pins in this group array, i.e. the number of
  681. * elements in .pins so we can iterate over that array
  682. */
  683. struct u300_pin_group {
  684. const char *name;
  685. const unsigned int *pins;
  686. const unsigned num_pins;
  687. };
  688. /**
  689. * struct pmx_onmask - mask bits to enable/disable padmux
  690. * @mask: mask bits to disable
  691. * @val: mask bits to enable
  692. *
  693. * onmask lazy dog:
  694. * onmask = {
  695. * {"PMC1LR" mask, "PMC1LR" value},
  696. * {"PMC1HR" mask, "PMC1HR" value},
  697. * {"PMC2R" mask, "PMC2R" value},
  698. * {"PMC3R" mask, "PMC3R" value},
  699. * {"PMC4R" mask, "PMC4R" value}
  700. * }
  701. */
  702. struct u300_pmx_mask {
  703. u16 mask;
  704. u16 bits;
  705. };
  706. /* The chip power pins are VDD, GND, VDDIO and VSSIO */
  707. static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
  708. 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
  709. 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
  710. 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
  711. 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
  712. 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
  713. 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
  714. 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
  715. 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
  716. 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
  717. static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
  718. 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
  719. 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
  720. 417, 418 };
  721. static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
  722. 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
  723. 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
  724. 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
  725. 304, 305, 306, 307, 308, 313, 314, 315 };
  726. static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
  727. static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
  728. static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
  729. static const struct u300_pmx_mask emif0_mask[] = {
  730. {0, 0},
  731. {0, 0},
  732. {0, 0},
  733. {0, 0},
  734. {0, 0},
  735. };
  736. static const struct u300_pmx_mask emif1_mask[] = {
  737. /*
  738. * This connects the SDRAM to CS2 and a NAND flash to
  739. * CS0 on the EMIF.
  740. */
  741. {
  742. U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
  743. U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
  744. U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
  745. U300_SYSCON_PMC1LR_EMIF_1_MASK,
  746. U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
  747. U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
  748. U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
  749. U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
  750. },
  751. {0, 0},
  752. {0, 0},
  753. {0, 0},
  754. {0, 0},
  755. };
  756. static const struct u300_pmx_mask uart0_mask[] = {
  757. {0, 0},
  758. {
  759. U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
  760. U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
  761. U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
  762. U300_SYSCON_PMC1HR_APP_UART0_2_UART0
  763. },
  764. {0, 0},
  765. {0, 0},
  766. {0, 0},
  767. };
  768. static const struct u300_pmx_mask mmc0_mask[] = {
  769. { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
  770. {0, 0},
  771. {0, 0},
  772. {0, 0},
  773. { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
  774. U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
  775. };
  776. static const struct u300_pmx_mask spi0_mask[] = {
  777. {0, 0},
  778. {
  779. U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
  780. U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
  781. U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
  782. U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
  783. U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
  784. U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
  785. },
  786. {0, 0},
  787. {0, 0},
  788. {0, 0}
  789. };
  790. static const struct u300_pin_group u300_pin_groups[] = {
  791. {
  792. .name = "powergrp",
  793. .pins = power_pins,
  794. .num_pins = ARRAY_SIZE(power_pins),
  795. },
  796. {
  797. .name = "emif0grp",
  798. .pins = emif0_pins,
  799. .num_pins = ARRAY_SIZE(emif0_pins),
  800. },
  801. {
  802. .name = "emif1grp",
  803. .pins = emif1_pins,
  804. .num_pins = ARRAY_SIZE(emif1_pins),
  805. },
  806. {
  807. .name = "uart0grp",
  808. .pins = uart0_pins,
  809. .num_pins = ARRAY_SIZE(uart0_pins),
  810. },
  811. {
  812. .name = "mmc0grp",
  813. .pins = mmc0_pins,
  814. .num_pins = ARRAY_SIZE(mmc0_pins),
  815. },
  816. {
  817. .name = "spi0grp",
  818. .pins = spi0_pins,
  819. .num_pins = ARRAY_SIZE(spi0_pins),
  820. },
  821. };
  822. static int u300_get_groups_count(struct pinctrl_dev *pctldev)
  823. {
  824. return ARRAY_SIZE(u300_pin_groups);
  825. }
  826. static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
  827. unsigned selector)
  828. {
  829. return u300_pin_groups[selector].name;
  830. }
  831. static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  832. const unsigned **pins,
  833. unsigned *num_pins)
  834. {
  835. *pins = u300_pin_groups[selector].pins;
  836. *num_pins = u300_pin_groups[selector].num_pins;
  837. return 0;
  838. }
  839. static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  840. unsigned offset)
  841. {
  842. seq_printf(s, " " DRIVER_NAME);
  843. }
  844. static const struct pinctrl_ops u300_pctrl_ops = {
  845. .get_groups_count = u300_get_groups_count,
  846. .get_group_name = u300_get_group_name,
  847. .get_group_pins = u300_get_group_pins,
  848. .pin_dbg_show = u300_pin_dbg_show,
  849. };
  850. /*
  851. * Here we define the available functions and their corresponding pin groups
  852. */
  853. /**
  854. * struct u300_pmx_func - describes U300 pinmux functions
  855. * @name: the name of this specific function
  856. * @groups: corresponding pin groups
  857. * @onmask: bits to set to enable this when doing pin muxing
  858. */
  859. struct u300_pmx_func {
  860. const char *name;
  861. const char * const *groups;
  862. const unsigned num_groups;
  863. const struct u300_pmx_mask *mask;
  864. };
  865. static const char * const powergrps[] = { "powergrp" };
  866. static const char * const emif0grps[] = { "emif0grp" };
  867. static const char * const emif1grps[] = { "emif1grp" };
  868. static const char * const uart0grps[] = { "uart0grp" };
  869. static const char * const mmc0grps[] = { "mmc0grp" };
  870. static const char * const spi0grps[] = { "spi0grp" };
  871. static const struct u300_pmx_func u300_pmx_functions[] = {
  872. {
  873. .name = "power",
  874. .groups = powergrps,
  875. .num_groups = ARRAY_SIZE(powergrps),
  876. /* Mask is N/A */
  877. },
  878. {
  879. .name = "emif0",
  880. .groups = emif0grps,
  881. .num_groups = ARRAY_SIZE(emif0grps),
  882. .mask = emif0_mask,
  883. },
  884. {
  885. .name = "emif1",
  886. .groups = emif1grps,
  887. .num_groups = ARRAY_SIZE(emif1grps),
  888. .mask = emif1_mask,
  889. },
  890. {
  891. .name = "uart0",
  892. .groups = uart0grps,
  893. .num_groups = ARRAY_SIZE(uart0grps),
  894. .mask = uart0_mask,
  895. },
  896. {
  897. .name = "mmc0",
  898. .groups = mmc0grps,
  899. .num_groups = ARRAY_SIZE(mmc0grps),
  900. .mask = mmc0_mask,
  901. },
  902. {
  903. .name = "spi0",
  904. .groups = spi0grps,
  905. .num_groups = ARRAY_SIZE(spi0grps),
  906. .mask = spi0_mask,
  907. },
  908. };
  909. static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
  910. bool enable)
  911. {
  912. u16 regval, val, mask;
  913. int i;
  914. const struct u300_pmx_mask *upmx_mask;
  915. upmx_mask = u300_pmx_functions[selector].mask;
  916. for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
  917. if (enable)
  918. val = upmx_mask->bits;
  919. else
  920. val = 0;
  921. mask = upmx_mask->mask;
  922. if (mask != 0) {
  923. regval = readw(upmx->virtbase + u300_pmx_registers[i]);
  924. regval &= ~mask;
  925. regval |= val;
  926. writew(regval, upmx->virtbase + u300_pmx_registers[i]);
  927. }
  928. upmx_mask++;
  929. }
  930. }
  931. static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
  932. unsigned group)
  933. {
  934. struct u300_pmx *upmx;
  935. /* There is nothing to do with the power pins */
  936. if (selector == 0)
  937. return 0;
  938. upmx = pinctrl_dev_get_drvdata(pctldev);
  939. u300_pmx_endisable(upmx, selector, true);
  940. return 0;
  941. }
  942. static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
  943. {
  944. return ARRAY_SIZE(u300_pmx_functions);
  945. }
  946. static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
  947. unsigned selector)
  948. {
  949. return u300_pmx_functions[selector].name;
  950. }
  951. static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
  952. const char * const **groups,
  953. unsigned * const num_groups)
  954. {
  955. *groups = u300_pmx_functions[selector].groups;
  956. *num_groups = u300_pmx_functions[selector].num_groups;
  957. return 0;
  958. }
  959. static const struct pinmux_ops u300_pmx_ops = {
  960. .get_functions_count = u300_pmx_get_funcs_count,
  961. .get_function_name = u300_pmx_get_func_name,
  962. .get_function_groups = u300_pmx_get_groups,
  963. .set_mux = u300_pmx_set_mux,
  964. };
  965. static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
  966. unsigned long *config)
  967. {
  968. struct pinctrl_gpio_range *range =
  969. pinctrl_find_gpio_range_from_pin(pctldev, pin);
  970. /* We get config for those pins we CAN get it for and that's it */
  971. if (!range)
  972. return -ENOTSUPP;
  973. return u300_gpio_config_get(range->gc,
  974. (pin - range->pin_base + range->base),
  975. config);
  976. }
  977. static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
  978. unsigned long *configs, unsigned num_configs)
  979. {
  980. struct pinctrl_gpio_range *range =
  981. pinctrl_find_gpio_range_from_pin(pctldev, pin);
  982. int ret, i;
  983. if (!range)
  984. return -EINVAL;
  985. for (i = 0; i < num_configs; i++) {
  986. /* Note: none of these configurations take any argument */
  987. ret = u300_gpio_config_set(range->gc,
  988. (pin - range->pin_base + range->base),
  989. pinconf_to_config_param(configs[i]));
  990. if (ret)
  991. return ret;
  992. } /* for each config */
  993. return 0;
  994. }
  995. static const struct pinconf_ops u300_pconf_ops = {
  996. .is_generic = true,
  997. .pin_config_get = u300_pin_config_get,
  998. .pin_config_set = u300_pin_config_set,
  999. };
  1000. static struct pinctrl_desc u300_pmx_desc = {
  1001. .name = DRIVER_NAME,
  1002. .pins = u300_pads,
  1003. .npins = ARRAY_SIZE(u300_pads),
  1004. .pctlops = &u300_pctrl_ops,
  1005. .pmxops = &u300_pmx_ops,
  1006. .confops = &u300_pconf_ops,
  1007. .owner = THIS_MODULE,
  1008. };
  1009. static int u300_pmx_probe(struct platform_device *pdev)
  1010. {
  1011. struct u300_pmx *upmx;
  1012. /* Create state holders etc for this driver */
  1013. upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
  1014. if (!upmx)
  1015. return -ENOMEM;
  1016. upmx->dev = &pdev->dev;
  1017. upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
  1018. if (IS_ERR(upmx->virtbase))
  1019. return PTR_ERR(upmx->virtbase);
  1020. upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
  1021. if (IS_ERR(upmx->pctl)) {
  1022. dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
  1023. return PTR_ERR(upmx->pctl);
  1024. }
  1025. platform_set_drvdata(pdev, upmx);
  1026. dev_info(&pdev->dev, "initialized U300 pin control driver\n");
  1027. return 0;
  1028. }
  1029. static const struct of_device_id u300_pinctrl_match[] = {
  1030. { .compatible = "stericsson,pinctrl-u300" },
  1031. {},
  1032. };
  1033. static struct platform_driver u300_pmx_driver = {
  1034. .driver = {
  1035. .name = DRIVER_NAME,
  1036. .of_match_table = u300_pinctrl_match,
  1037. },
  1038. .probe = u300_pmx_probe,
  1039. };
  1040. static int __init u300_pmx_init(void)
  1041. {
  1042. return platform_driver_register(&u300_pmx_driver);
  1043. }
  1044. arch_initcall(u300_pmx_init);
  1045. static void __exit u300_pmx_exit(void)
  1046. {
  1047. platform_driver_unregister(&u300_pmx_driver);
  1048. }
  1049. module_exit(u300_pmx_exit);
  1050. MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
  1051. MODULE_DESCRIPTION("U300 pin control driver");
  1052. MODULE_LICENSE("GPL v2");