pinctrl-stmfx.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
  4. *
  5. * Copyright (C) 2019 STMicroelectronics
  6. * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
  7. */
  8. #include <linux/gpio/driver.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/mfd/stmfx.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pinctrl/pinconf.h>
  14. #include <linux/pinctrl/pinmux.h>
  15. #include "core.h"
  16. #include "pinctrl-utils.h"
  17. /* GPIOs expander */
  18. /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
  19. #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */
  20. /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
  21. #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */
  22. /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
  23. #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */
  24. /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
  25. #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */
  26. /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
  27. #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */
  28. /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
  29. #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */
  30. /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
  31. #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */
  32. /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
  33. #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */
  34. /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
  35. #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */
  36. /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
  37. #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */
  38. /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
  39. #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */
  40. #define NR_GPIO_REGS 3
  41. #define NR_GPIOS_PER_REG 8
  42. #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG)
  43. #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG)
  44. #define get_mask(offset) (BIT(get_shift(offset)))
  45. /*
  46. * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
  47. * Pins availability is managed thanks to gpio-ranges property.
  48. */
  49. static const struct pinctrl_pin_desc stmfx_pins[] = {
  50. PINCTRL_PIN(0, "gpio0"),
  51. PINCTRL_PIN(1, "gpio1"),
  52. PINCTRL_PIN(2, "gpio2"),
  53. PINCTRL_PIN(3, "gpio3"),
  54. PINCTRL_PIN(4, "gpio4"),
  55. PINCTRL_PIN(5, "gpio5"),
  56. PINCTRL_PIN(6, "gpio6"),
  57. PINCTRL_PIN(7, "gpio7"),
  58. PINCTRL_PIN(8, "gpio8"),
  59. PINCTRL_PIN(9, "gpio9"),
  60. PINCTRL_PIN(10, "gpio10"),
  61. PINCTRL_PIN(11, "gpio11"),
  62. PINCTRL_PIN(12, "gpio12"),
  63. PINCTRL_PIN(13, "gpio13"),
  64. PINCTRL_PIN(14, "gpio14"),
  65. PINCTRL_PIN(15, "gpio15"),
  66. PINCTRL_PIN(16, "agpio0"),
  67. PINCTRL_PIN(17, "agpio1"),
  68. PINCTRL_PIN(18, "agpio2"),
  69. PINCTRL_PIN(19, "agpio3"),
  70. PINCTRL_PIN(20, "agpio4"),
  71. PINCTRL_PIN(21, "agpio5"),
  72. PINCTRL_PIN(22, "agpio6"),
  73. PINCTRL_PIN(23, "agpio7"),
  74. };
  75. struct stmfx_pinctrl {
  76. struct device *dev;
  77. struct stmfx *stmfx;
  78. struct pinctrl_dev *pctl_dev;
  79. struct pinctrl_desc pctl_desc;
  80. struct gpio_chip gpio_chip;
  81. struct irq_chip irq_chip;
  82. struct mutex lock; /* IRQ bus lock */
  83. unsigned long gpio_valid_mask;
  84. /* Cache of IRQ_GPI_* registers for bus_lock */
  85. u8 irq_gpi_src[NR_GPIO_REGS];
  86. u8 irq_gpi_type[NR_GPIO_REGS];
  87. u8 irq_gpi_evt[NR_GPIO_REGS];
  88. u8 irq_toggle_edge[NR_GPIO_REGS];
  89. #ifdef CONFIG_PM
  90. /* Backup of GPIO_* registers for suspend/resume */
  91. u8 bkp_gpio_state[NR_GPIO_REGS];
  92. u8 bkp_gpio_dir[NR_GPIO_REGS];
  93. u8 bkp_gpio_type[NR_GPIO_REGS];
  94. u8 bkp_gpio_pupd[NR_GPIO_REGS];
  95. #endif
  96. };
  97. static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
  98. {
  99. struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
  100. u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
  101. u32 mask = get_mask(offset);
  102. u32 value;
  103. int ret;
  104. ret = regmap_read(pctl->stmfx->map, reg, &value);
  105. return ret ? ret : !!(value & mask);
  106. }
  107. static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
  108. {
  109. struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
  110. u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
  111. u32 mask = get_mask(offset);
  112. regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
  113. mask, mask);
  114. }
  115. static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
  116. {
  117. struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
  118. u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
  119. u32 mask = get_mask(offset);
  120. u32 val;
  121. int ret;
  122. ret = regmap_read(pctl->stmfx->map, reg, &val);
  123. /*
  124. * On stmfx, gpio pins direction is (0)input, (1)output.
  125. */
  126. if (ret)
  127. return ret;
  128. if (val & mask)
  129. return GPIO_LINE_DIRECTION_OUT;
  130. return GPIO_LINE_DIRECTION_IN;
  131. }
  132. static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
  133. {
  134. struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
  135. u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
  136. u32 mask = get_mask(offset);
  137. return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
  138. }
  139. static int stmfx_gpio_direction_output(struct gpio_chip *gc,
  140. unsigned int offset, int value)
  141. {
  142. struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
  143. u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
  144. u32 mask = get_mask(offset);
  145. stmfx_gpio_set(gc, offset, value);
  146. return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
  147. }
  148. static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
  149. unsigned int offset)
  150. {
  151. u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
  152. u32 pupd, mask = get_mask(offset);
  153. int ret;
  154. ret = regmap_read(pctl->stmfx->map, reg, &pupd);
  155. if (ret)
  156. return ret;
  157. return !!(pupd & mask);
  158. }
  159. static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
  160. unsigned int offset, u32 pupd)
  161. {
  162. u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
  163. u32 mask = get_mask(offset);
  164. return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
  165. }
  166. static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
  167. unsigned int offset)
  168. {
  169. u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
  170. u32 type, mask = get_mask(offset);
  171. int ret;
  172. ret = regmap_read(pctl->stmfx->map, reg, &type);
  173. if (ret)
  174. return ret;
  175. return !!(type & mask);
  176. }
  177. static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
  178. unsigned int offset, u32 type)
  179. {
  180. u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
  181. u32 mask = get_mask(offset);
  182. return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
  183. }
  184. static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
  185. unsigned int pin, unsigned long *config)
  186. {
  187. struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  188. u32 param = pinconf_to_config_param(*config);
  189. struct pinctrl_gpio_range *range;
  190. u32 arg = 0;
  191. int ret, dir, type, pupd;
  192. range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
  193. if (!range)
  194. return -EINVAL;
  195. dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
  196. if (dir < 0)
  197. return dir;
  198. /*
  199. * Currently the gpiolib IN is 1 and OUT is 0 but let's not count
  200. * on it just to be on the safe side also in the future :)
  201. */
  202. dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0;
  203. type = stmfx_pinconf_get_type(pctl, pin);
  204. if (type < 0)
  205. return type;
  206. pupd = stmfx_pinconf_get_pupd(pctl, pin);
  207. if (pupd < 0)
  208. return pupd;
  209. switch (param) {
  210. case PIN_CONFIG_BIAS_DISABLE:
  211. if ((!dir && (!type || !pupd)) || (dir && !type))
  212. arg = 1;
  213. break;
  214. case PIN_CONFIG_BIAS_PULL_DOWN:
  215. if (dir && type && !pupd)
  216. arg = 1;
  217. break;
  218. case PIN_CONFIG_BIAS_PULL_UP:
  219. if (type && pupd)
  220. arg = 1;
  221. break;
  222. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  223. if ((!dir && type) || (dir && !type))
  224. arg = 1;
  225. break;
  226. case PIN_CONFIG_DRIVE_PUSH_PULL:
  227. if ((!dir && !type) || (dir && type))
  228. arg = 1;
  229. break;
  230. case PIN_CONFIG_OUTPUT:
  231. if (dir)
  232. return -EINVAL;
  233. ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
  234. if (ret < 0)
  235. return ret;
  236. arg = ret;
  237. break;
  238. default:
  239. return -ENOTSUPP;
  240. }
  241. *config = pinconf_to_config_packed(param, arg);
  242. return 0;
  243. }
  244. static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  245. unsigned long *configs, unsigned int num_configs)
  246. {
  247. struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  248. struct pinctrl_gpio_range *range;
  249. enum pin_config_param param;
  250. u32 arg;
  251. int i, ret;
  252. range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
  253. if (!range) {
  254. dev_err(pctldev->dev, "pin %d is not available\n", pin);
  255. return -EINVAL;
  256. }
  257. for (i = 0; i < num_configs; i++) {
  258. param = pinconf_to_config_param(configs[i]);
  259. arg = pinconf_to_config_argument(configs[i]);
  260. switch (param) {
  261. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  262. case PIN_CONFIG_BIAS_DISABLE:
  263. case PIN_CONFIG_DRIVE_PUSH_PULL:
  264. ret = stmfx_pinconf_set_type(pctl, pin, 0);
  265. if (ret)
  266. return ret;
  267. break;
  268. case PIN_CONFIG_BIAS_PULL_DOWN:
  269. ret = stmfx_pinconf_set_type(pctl, pin, 1);
  270. if (ret)
  271. return ret;
  272. ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
  273. if (ret)
  274. return ret;
  275. break;
  276. case PIN_CONFIG_BIAS_PULL_UP:
  277. ret = stmfx_pinconf_set_type(pctl, pin, 1);
  278. if (ret)
  279. return ret;
  280. ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
  281. if (ret)
  282. return ret;
  283. break;
  284. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  285. ret = stmfx_pinconf_set_type(pctl, pin, 1);
  286. if (ret)
  287. return ret;
  288. break;
  289. case PIN_CONFIG_OUTPUT:
  290. ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
  291. pin, arg);
  292. if (ret)
  293. return ret;
  294. break;
  295. default:
  296. return -ENOTSUPP;
  297. }
  298. }
  299. return 0;
  300. }
  301. static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  302. struct seq_file *s, unsigned int offset)
  303. {
  304. struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  305. struct pinctrl_gpio_range *range;
  306. int dir, type, pupd, val;
  307. range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
  308. if (!range)
  309. return;
  310. dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
  311. if (dir < 0)
  312. return;
  313. type = stmfx_pinconf_get_type(pctl, offset);
  314. if (type < 0)
  315. return;
  316. pupd = stmfx_pinconf_get_pupd(pctl, offset);
  317. if (pupd < 0)
  318. return;
  319. val = stmfx_gpio_get(&pctl->gpio_chip, offset);
  320. if (val < 0)
  321. return;
  322. if (dir == GPIO_LINE_DIRECTION_OUT) {
  323. seq_printf(s, "output %s ", val ? "high" : "low");
  324. if (type)
  325. seq_printf(s, "open drain %s internal pull-up ",
  326. pupd ? "with" : "without");
  327. else
  328. seq_puts(s, "push pull no pull ");
  329. } else {
  330. seq_printf(s, "input %s ", val ? "high" : "low");
  331. if (type)
  332. seq_printf(s, "with internal pull-%s ",
  333. pupd ? "up" : "down");
  334. else
  335. seq_printf(s, "%s ", pupd ? "floating" : "analog");
  336. }
  337. }
  338. static const struct pinconf_ops stmfx_pinconf_ops = {
  339. .pin_config_get = stmfx_pinconf_get,
  340. .pin_config_set = stmfx_pinconf_set,
  341. .pin_config_dbg_show = stmfx_pinconf_dbg_show,
  342. };
  343. static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  344. {
  345. return 0;
  346. }
  347. static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  348. unsigned int selector)
  349. {
  350. return NULL;
  351. }
  352. static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  353. unsigned int selector,
  354. const unsigned int **pins,
  355. unsigned int *num_pins)
  356. {
  357. return -ENOTSUPP;
  358. }
  359. static const struct pinctrl_ops stmfx_pinctrl_ops = {
  360. .get_groups_count = stmfx_pinctrl_get_groups_count,
  361. .get_group_name = stmfx_pinctrl_get_group_name,
  362. .get_group_pins = stmfx_pinctrl_get_group_pins,
  363. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  364. .dt_free_map = pinctrl_utils_free_map,
  365. };
  366. static void stmfx_pinctrl_irq_mask(struct irq_data *data)
  367. {
  368. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  369. struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
  370. u32 reg = get_reg(data->hwirq);
  371. u32 mask = get_mask(data->hwirq);
  372. pctl->irq_gpi_src[reg] &= ~mask;
  373. }
  374. static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
  375. {
  376. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  377. struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
  378. u32 reg = get_reg(data->hwirq);
  379. u32 mask = get_mask(data->hwirq);
  380. pctl->irq_gpi_src[reg] |= mask;
  381. }
  382. static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
  383. {
  384. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  385. struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
  386. u32 reg = get_reg(data->hwirq);
  387. u32 mask = get_mask(data->hwirq);
  388. if (type == IRQ_TYPE_NONE)
  389. return -EINVAL;
  390. if (type & IRQ_TYPE_EDGE_BOTH) {
  391. pctl->irq_gpi_evt[reg] |= mask;
  392. irq_set_handler_locked(data, handle_edge_irq);
  393. } else {
  394. pctl->irq_gpi_evt[reg] &= ~mask;
  395. irq_set_handler_locked(data, handle_level_irq);
  396. }
  397. if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
  398. pctl->irq_gpi_type[reg] |= mask;
  399. else
  400. pctl->irq_gpi_type[reg] &= ~mask;
  401. /*
  402. * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
  403. * GPIO value to set the right edge trigger. But in atomic context
  404. * here we can't access registers over I2C. That's why (type &
  405. * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
  406. */
  407. if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
  408. pctl->irq_toggle_edge[reg] |= mask;
  409. else
  410. pctl->irq_toggle_edge[reg] &= mask;
  411. return 0;
  412. }
  413. static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
  414. {
  415. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  416. struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
  417. mutex_lock(&pctl->lock);
  418. }
  419. static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
  420. {
  421. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  422. struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
  423. u32 reg = get_reg(data->hwirq);
  424. u32 mask = get_mask(data->hwirq);
  425. /*
  426. * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
  427. * (this couldn't be done in .irq_set_type because of atomic context)
  428. * to set the right irq trigger type.
  429. */
  430. if (pctl->irq_toggle_edge[reg] & mask) {
  431. if (stmfx_gpio_get(gpio_chip, data->hwirq))
  432. pctl->irq_gpi_type[reg] &= ~mask;
  433. else
  434. pctl->irq_gpi_type[reg] |= mask;
  435. }
  436. regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
  437. pctl->irq_gpi_evt, NR_GPIO_REGS);
  438. regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
  439. pctl->irq_gpi_type, NR_GPIO_REGS);
  440. regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
  441. pctl->irq_gpi_src, NR_GPIO_REGS);
  442. mutex_unlock(&pctl->lock);
  443. }
  444. static int stmfx_gpio_irq_request_resources(struct irq_data *data)
  445. {
  446. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  447. int ret;
  448. ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
  449. if (ret)
  450. return ret;
  451. return gpiochip_reqres_irq(gpio_chip, data->hwirq);
  452. }
  453. static void stmfx_gpio_irq_release_resources(struct irq_data *data)
  454. {
  455. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  456. return gpiochip_relres_irq(gpio_chip, data->hwirq);
  457. }
  458. static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
  459. unsigned int offset)
  460. {
  461. u32 reg = get_reg(offset);
  462. u32 mask = get_mask(offset);
  463. int val;
  464. if (!(pctl->irq_toggle_edge[reg] & mask))
  465. return;
  466. val = stmfx_gpio_get(&pctl->gpio_chip, offset);
  467. if (val < 0)
  468. return;
  469. if (val) {
  470. pctl->irq_gpi_type[reg] &= mask;
  471. regmap_write_bits(pctl->stmfx->map,
  472. STMFX_REG_IRQ_GPI_TYPE + reg,
  473. mask, 0);
  474. } else {
  475. pctl->irq_gpi_type[reg] |= mask;
  476. regmap_write_bits(pctl->stmfx->map,
  477. STMFX_REG_IRQ_GPI_TYPE + reg,
  478. mask, mask);
  479. }
  480. }
  481. static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
  482. {
  483. struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
  484. struct gpio_chip *gc = &pctl->gpio_chip;
  485. u8 pending[NR_GPIO_REGS];
  486. u8 src[NR_GPIO_REGS] = {0, 0, 0};
  487. unsigned long n, status;
  488. int i, ret;
  489. ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
  490. &pending, NR_GPIO_REGS);
  491. if (ret)
  492. return IRQ_NONE;
  493. regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
  494. src, NR_GPIO_REGS);
  495. BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
  496. for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
  497. status |= (unsigned long)pending[i] << (i * 8);
  498. for_each_set_bit(n, &status, gc->ngpio) {
  499. handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
  500. stmfx_pinctrl_irq_toggle_trigger(pctl, n);
  501. }
  502. regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
  503. pctl->irq_gpi_src, NR_GPIO_REGS);
  504. return IRQ_HANDLED;
  505. }
  506. static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
  507. {
  508. struct pinctrl_gpio_range *gpio_range;
  509. struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
  510. u32 func = STMFX_FUNC_GPIO;
  511. pctl->gpio_valid_mask = GENMASK(15, 0);
  512. gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
  513. if (gpio_range) {
  514. func |= STMFX_FUNC_ALTGPIO_LOW;
  515. pctl->gpio_valid_mask |= GENMASK(19, 16);
  516. }
  517. gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
  518. if (gpio_range) {
  519. func |= STMFX_FUNC_ALTGPIO_HIGH;
  520. pctl->gpio_valid_mask |= GENMASK(23, 20);
  521. }
  522. return stmfx_function_enable(pctl->stmfx, func);
  523. }
  524. static int stmfx_pinctrl_probe(struct platform_device *pdev)
  525. {
  526. struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
  527. struct device_node *np = pdev->dev.of_node;
  528. struct stmfx_pinctrl *pctl;
  529. struct gpio_irq_chip *girq;
  530. int irq, ret;
  531. pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
  532. if (!pctl)
  533. return -ENOMEM;
  534. platform_set_drvdata(pdev, pctl);
  535. pctl->dev = &pdev->dev;
  536. pctl->stmfx = stmfx;
  537. if (!of_find_property(np, "gpio-ranges", NULL)) {
  538. dev_err(pctl->dev, "missing required gpio-ranges property\n");
  539. return -EINVAL;
  540. }
  541. irq = platform_get_irq(pdev, 0);
  542. if (irq <= 0)
  543. return -ENXIO;
  544. mutex_init(&pctl->lock);
  545. /* Register pin controller */
  546. pctl->pctl_desc.name = "stmfx-pinctrl";
  547. pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
  548. pctl->pctl_desc.confops = &stmfx_pinconf_ops;
  549. pctl->pctl_desc.pins = stmfx_pins;
  550. pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
  551. pctl->pctl_desc.owner = THIS_MODULE;
  552. pctl->pctl_desc.link_consumers = true;
  553. ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
  554. pctl, &pctl->pctl_dev);
  555. if (ret) {
  556. dev_err(pctl->dev, "pinctrl registration failed\n");
  557. return ret;
  558. }
  559. ret = pinctrl_enable(pctl->pctl_dev);
  560. if (ret) {
  561. dev_err(pctl->dev, "pinctrl enable failed\n");
  562. return ret;
  563. }
  564. /* Register gpio controller */
  565. pctl->gpio_chip.label = "stmfx-gpio";
  566. pctl->gpio_chip.parent = pctl->dev;
  567. pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
  568. pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
  569. pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
  570. pctl->gpio_chip.get = stmfx_gpio_get;
  571. pctl->gpio_chip.set = stmfx_gpio_set;
  572. pctl->gpio_chip.set_config = gpiochip_generic_config;
  573. pctl->gpio_chip.base = -1;
  574. pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
  575. pctl->gpio_chip.can_sleep = true;
  576. pctl->gpio_chip.of_node = np;
  577. pctl->irq_chip.name = dev_name(pctl->dev);
  578. pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask;
  579. pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask;
  580. pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type;
  581. pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock;
  582. pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock;
  583. pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources;
  584. pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources;
  585. girq = &pctl->gpio_chip.irq;
  586. girq->chip = &pctl->irq_chip;
  587. /* This will let us handle the parent IRQ in the driver */
  588. girq->parent_handler = NULL;
  589. girq->num_parents = 0;
  590. girq->parents = NULL;
  591. girq->default_type = IRQ_TYPE_NONE;
  592. girq->handler = handle_bad_irq;
  593. girq->threaded = true;
  594. ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
  595. if (ret) {
  596. dev_err(pctl->dev, "gpio_chip registration failed\n");
  597. return ret;
  598. }
  599. ret = stmfx_pinctrl_gpio_function_enable(pctl);
  600. if (ret)
  601. return ret;
  602. ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
  603. stmfx_pinctrl_irq_thread_fn,
  604. IRQF_ONESHOT,
  605. pctl->irq_chip.name, pctl);
  606. if (ret) {
  607. dev_err(pctl->dev, "cannot request irq%d\n", irq);
  608. return ret;
  609. }
  610. dev_info(pctl->dev,
  611. "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
  612. return 0;
  613. }
  614. static int stmfx_pinctrl_remove(struct platform_device *pdev)
  615. {
  616. struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
  617. return stmfx_function_disable(stmfx,
  618. STMFX_FUNC_GPIO |
  619. STMFX_FUNC_ALTGPIO_LOW |
  620. STMFX_FUNC_ALTGPIO_HIGH);
  621. }
  622. #ifdef CONFIG_PM_SLEEP
  623. static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
  624. {
  625. int ret;
  626. ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
  627. &pctl->bkp_gpio_state, NR_GPIO_REGS);
  628. if (ret)
  629. return ret;
  630. ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
  631. &pctl->bkp_gpio_dir, NR_GPIO_REGS);
  632. if (ret)
  633. return ret;
  634. ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
  635. &pctl->bkp_gpio_type, NR_GPIO_REGS);
  636. if (ret)
  637. return ret;
  638. ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
  639. &pctl->bkp_gpio_pupd, NR_GPIO_REGS);
  640. if (ret)
  641. return ret;
  642. return 0;
  643. }
  644. static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
  645. {
  646. int ret;
  647. ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
  648. pctl->bkp_gpio_dir, NR_GPIO_REGS);
  649. if (ret)
  650. return ret;
  651. ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
  652. pctl->bkp_gpio_type, NR_GPIO_REGS);
  653. if (ret)
  654. return ret;
  655. ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
  656. pctl->bkp_gpio_pupd, NR_GPIO_REGS);
  657. if (ret)
  658. return ret;
  659. ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
  660. pctl->bkp_gpio_state, NR_GPIO_REGS);
  661. if (ret)
  662. return ret;
  663. ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
  664. pctl->irq_gpi_evt, NR_GPIO_REGS);
  665. if (ret)
  666. return ret;
  667. ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
  668. pctl->irq_gpi_type, NR_GPIO_REGS);
  669. if (ret)
  670. return ret;
  671. ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
  672. pctl->irq_gpi_src, NR_GPIO_REGS);
  673. if (ret)
  674. return ret;
  675. return 0;
  676. }
  677. static int stmfx_pinctrl_suspend(struct device *dev)
  678. {
  679. struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
  680. int ret;
  681. ret = stmfx_pinctrl_backup_regs(pctl);
  682. if (ret) {
  683. dev_err(pctl->dev, "registers backup failure\n");
  684. return ret;
  685. }
  686. return 0;
  687. }
  688. static int stmfx_pinctrl_resume(struct device *dev)
  689. {
  690. struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
  691. int ret;
  692. ret = stmfx_pinctrl_restore_regs(pctl);
  693. if (ret) {
  694. dev_err(pctl->dev, "registers restoration failure\n");
  695. return ret;
  696. }
  697. return 0;
  698. }
  699. #endif
  700. static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
  701. stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
  702. static const struct of_device_id stmfx_pinctrl_of_match[] = {
  703. { .compatible = "st,stmfx-0300-pinctrl", },
  704. {},
  705. };
  706. MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
  707. static struct platform_driver stmfx_pinctrl_driver = {
  708. .driver = {
  709. .name = "stmfx-pinctrl",
  710. .of_match_table = stmfx_pinctrl_of_match,
  711. .pm = &stmfx_pinctrl_dev_pm_ops,
  712. },
  713. .probe = stmfx_pinctrl_probe,
  714. .remove = stmfx_pinctrl_remove,
  715. };
  716. module_platform_driver(stmfx_pinctrl_driver);
  717. MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
  718. MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
  719. MODULE_LICENSE("GPL v2");