pinctrl-st.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
  4. * Authors:
  5. * Srinivas Kandagatla <srinivas.kandagatla@st.com>
  6. */
  7. #include <linux/init.h>
  8. #include <linux/module.h>
  9. #include <linux/slab.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_gpio.h> /* of_get_named_gpio() */
  15. #include <linux/of_address.h>
  16. #include <linux/gpio/driver.h>
  17. #include <linux/regmap.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/pinctrl/pinctrl.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include <linux/pinctrl/pinconf.h>
  22. #include <linux/platform_device.h>
  23. #include "core.h"
  24. /* PIO Block registers */
  25. /* PIO output */
  26. #define REG_PIO_POUT 0x00
  27. /* Set bits of POUT */
  28. #define REG_PIO_SET_POUT 0x04
  29. /* Clear bits of POUT */
  30. #define REG_PIO_CLR_POUT 0x08
  31. /* PIO input */
  32. #define REG_PIO_PIN 0x10
  33. /* PIO configuration */
  34. #define REG_PIO_PC(n) (0x20 + (n) * 0x10)
  35. /* Set bits of PC[2:0] */
  36. #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
  37. /* Clear bits of PC[2:0] */
  38. #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
  39. /* PIO input comparison */
  40. #define REG_PIO_PCOMP 0x50
  41. /* Set bits of PCOMP */
  42. #define REG_PIO_SET_PCOMP 0x54
  43. /* Clear bits of PCOMP */
  44. #define REG_PIO_CLR_PCOMP 0x58
  45. /* PIO input comparison mask */
  46. #define REG_PIO_PMASK 0x60
  47. /* Set bits of PMASK */
  48. #define REG_PIO_SET_PMASK 0x64
  49. /* Clear bits of PMASK */
  50. #define REG_PIO_CLR_PMASK 0x68
  51. #define ST_GPIO_DIRECTION_BIDIR 0x1
  52. #define ST_GPIO_DIRECTION_OUT 0x2
  53. #define ST_GPIO_DIRECTION_IN 0x4
  54. /**
  55. * Packed style retime configuration.
  56. * There are two registers cfg0 and cfg1 in this style for each bank.
  57. * Each field in this register is 8 bit corresponding to 8 pins in the bank.
  58. */
  59. #define RT_P_CFGS_PER_BANK 2
  60. #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
  61. #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
  62. #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
  63. #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
  64. #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
  65. #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
  66. #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
  67. /**
  68. * Dedicated style retime Configuration register
  69. * each register is dedicated per pin.
  70. */
  71. #define RT_D_CFGS_PER_BANK 8
  72. #define RT_D_CFG_CLK_SHIFT 0
  73. #define RT_D_CFG_CLK_MASK (0x3 << 0)
  74. #define RT_D_CFG_CLKNOTDATA_SHIFT 2
  75. #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
  76. #define RT_D_CFG_DELAY_SHIFT 3
  77. #define RT_D_CFG_DELAY_MASK (0xf << 3)
  78. #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
  79. #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
  80. #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
  81. #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
  82. #define RT_D_CFG_INVERTCLK_SHIFT 9
  83. #define RT_D_CFG_INVERTCLK_MASK BIT(9)
  84. #define RT_D_CFG_RETIME_SHIFT 10
  85. #define RT_D_CFG_RETIME_MASK BIT(10)
  86. /*
  87. * Pinconf is represented in an opaque unsigned long variable.
  88. * Below is the bit allocation details for each possible configuration.
  89. * All the bit fields can be encapsulated into four variables
  90. * (direction, retime-type, retime-clk, retime-delay)
  91. *
  92. * +----------------+
  93. *[31:28]| reserved-3 |
  94. * +----------------+-------------
  95. *[27] | oe | |
  96. * +----------------+ v
  97. *[26] | pu | [Direction ]
  98. * +----------------+ ^
  99. *[25] | od | |
  100. * +----------------+-------------
  101. *[24] | reserved-2 |
  102. * +----------------+-------------
  103. *[23] | retime | |
  104. * +----------------+ |
  105. *[22] | retime-invclk | |
  106. * +----------------+ v
  107. *[21] |retime-clknotdat| [Retime-type ]
  108. * +----------------+ ^
  109. *[20] | retime-de | |
  110. * +----------------+-------------
  111. *[19:18]| retime-clk |------>[Retime-Clk ]
  112. * +----------------+
  113. *[17:16]| reserved-1 |
  114. * +----------------+
  115. *[15..0]| retime-delay |------>[Retime Delay]
  116. * +----------------+
  117. */
  118. #define ST_PINCONF_UNPACK(conf, param)\
  119. ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
  120. & ST_PINCONF_ ##param ##_MASK)
  121. #define ST_PINCONF_PACK(conf, val, param) (conf |=\
  122. ((val & ST_PINCONF_ ##param ##_MASK) << \
  123. ST_PINCONF_ ##param ##_SHIFT))
  124. /* Output enable */
  125. #define ST_PINCONF_OE_MASK 0x1
  126. #define ST_PINCONF_OE_SHIFT 27
  127. #define ST_PINCONF_OE BIT(27)
  128. #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
  129. #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
  130. /* Pull Up */
  131. #define ST_PINCONF_PU_MASK 0x1
  132. #define ST_PINCONF_PU_SHIFT 26
  133. #define ST_PINCONF_PU BIT(26)
  134. #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
  135. #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
  136. /* Open Drain */
  137. #define ST_PINCONF_OD_MASK 0x1
  138. #define ST_PINCONF_OD_SHIFT 25
  139. #define ST_PINCONF_OD BIT(25)
  140. #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
  141. #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
  142. #define ST_PINCONF_RT_MASK 0x1
  143. #define ST_PINCONF_RT_SHIFT 23
  144. #define ST_PINCONF_RT BIT(23)
  145. #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
  146. #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
  147. #define ST_PINCONF_RT_INVERTCLK_MASK 0x1
  148. #define ST_PINCONF_RT_INVERTCLK_SHIFT 22
  149. #define ST_PINCONF_RT_INVERTCLK BIT(22)
  150. #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
  151. ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
  152. #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
  153. ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
  154. #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
  155. #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
  156. #define ST_PINCONF_RT_CLKNOTDATA BIT(21)
  157. #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
  158. ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
  159. #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
  160. ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
  161. #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
  162. #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
  163. #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
  164. #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
  165. ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
  166. #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
  167. ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
  168. #define ST_PINCONF_RT_CLK_MASK 0x3
  169. #define ST_PINCONF_RT_CLK_SHIFT 18
  170. #define ST_PINCONF_RT_CLK BIT(18)
  171. #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
  172. #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
  173. /* RETIME_DELAY in Pico Secs */
  174. #define ST_PINCONF_RT_DELAY_MASK 0xffff
  175. #define ST_PINCONF_RT_DELAY_SHIFT 0
  176. #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
  177. #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
  178. ST_PINCONF_PACK(conf, val, RT_DELAY)
  179. #define ST_GPIO_PINS_PER_BANK (8)
  180. #define OF_GPIO_ARGS_MIN (4)
  181. #define OF_RT_ARGS_MIN (2)
  182. #define gpio_range_to_bank(chip) \
  183. container_of(chip, struct st_gpio_bank, range)
  184. #define pc_to_bank(pc) \
  185. container_of(pc, struct st_gpio_bank, pc)
  186. enum st_retime_style {
  187. st_retime_style_none,
  188. st_retime_style_packed,
  189. st_retime_style_dedicated,
  190. };
  191. struct st_retime_dedicated {
  192. struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
  193. };
  194. struct st_retime_packed {
  195. struct regmap_field *clk1notclk0;
  196. struct regmap_field *delay_0;
  197. struct regmap_field *delay_1;
  198. struct regmap_field *invertclk;
  199. struct regmap_field *retime;
  200. struct regmap_field *clknotdata;
  201. struct regmap_field *double_edge;
  202. };
  203. struct st_pio_control {
  204. u32 rt_pin_mask;
  205. struct regmap_field *alt, *oe, *pu, *od;
  206. /* retiming */
  207. union {
  208. struct st_retime_packed rt_p;
  209. struct st_retime_dedicated rt_d;
  210. } rt;
  211. };
  212. struct st_pctl_data {
  213. const enum st_retime_style rt_style;
  214. const unsigned int *input_delays;
  215. const int ninput_delays;
  216. const unsigned int *output_delays;
  217. const int noutput_delays;
  218. /* register offset information */
  219. const int alt, oe, pu, od, rt;
  220. };
  221. struct st_pinconf {
  222. int pin;
  223. const char *name;
  224. unsigned long config;
  225. int altfunc;
  226. };
  227. struct st_pmx_func {
  228. const char *name;
  229. const char **groups;
  230. unsigned ngroups;
  231. };
  232. struct st_pctl_group {
  233. const char *name;
  234. unsigned int *pins;
  235. unsigned npins;
  236. struct st_pinconf *pin_conf;
  237. };
  238. /*
  239. * Edge triggers are not supported at hardware level, it is supported by
  240. * software by exploiting the level trigger support in hardware.
  241. * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
  242. * of each gpio pin in a GPIO bank.
  243. *
  244. * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
  245. * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
  246. *
  247. * bit allocation per pin is:
  248. * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
  249. * --------------------------------------------------------
  250. * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
  251. * --------------------------------------------------------
  252. *
  253. * A pin can have one of following the values in its edge configuration field.
  254. *
  255. * ------- ----------------------------
  256. * [0-3] - Description
  257. * ------- ----------------------------
  258. * 0000 - No edge IRQ.
  259. * 0001 - Falling edge IRQ.
  260. * 0010 - Rising edge IRQ.
  261. * 0011 - Rising and Falling edge IRQ.
  262. * ------- ----------------------------
  263. */
  264. #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
  265. #define ST_IRQ_EDGE_MASK 0xf
  266. #define ST_IRQ_EDGE_FALLING BIT(0)
  267. #define ST_IRQ_EDGE_RISING BIT(1)
  268. #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
  269. #define ST_IRQ_RISING_EDGE_CONF(pin) \
  270. (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
  271. #define ST_IRQ_FALLING_EDGE_CONF(pin) \
  272. (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
  273. #define ST_IRQ_BOTH_EDGE_CONF(pin) \
  274. (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
  275. #define ST_IRQ_EDGE_CONF(conf, pin) \
  276. (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
  277. struct st_gpio_bank {
  278. struct gpio_chip gpio_chip;
  279. struct pinctrl_gpio_range range;
  280. void __iomem *base;
  281. struct st_pio_control pc;
  282. unsigned long irq_edge_conf;
  283. spinlock_t lock;
  284. };
  285. struct st_pinctrl {
  286. struct device *dev;
  287. struct pinctrl_dev *pctl;
  288. struct st_gpio_bank *banks;
  289. int nbanks;
  290. struct st_pmx_func *functions;
  291. int nfunctions;
  292. struct st_pctl_group *groups;
  293. int ngroups;
  294. struct regmap *regmap;
  295. const struct st_pctl_data *data;
  296. void __iomem *irqmux_base;
  297. };
  298. /* SOC specific data */
  299. static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
  300. 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
  301. static const struct st_pctl_data stih407_data = {
  302. .rt_style = st_retime_style_dedicated,
  303. .input_delays = stih407_delays,
  304. .ninput_delays = ARRAY_SIZE(stih407_delays),
  305. .output_delays = stih407_delays,
  306. .noutput_delays = ARRAY_SIZE(stih407_delays),
  307. .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
  308. };
  309. static const struct st_pctl_data stih407_flashdata = {
  310. .rt_style = st_retime_style_none,
  311. .input_delays = stih407_delays,
  312. .ninput_delays = ARRAY_SIZE(stih407_delays),
  313. .output_delays = stih407_delays,
  314. .noutput_delays = ARRAY_SIZE(stih407_delays),
  315. .alt = 0,
  316. .oe = -1, /* Not Available */
  317. .pu = -1, /* Not Available */
  318. .od = 60,
  319. .rt = 100,
  320. };
  321. static struct st_pio_control *st_get_pio_control(
  322. struct pinctrl_dev *pctldev, int pin)
  323. {
  324. struct pinctrl_gpio_range *range =
  325. pinctrl_find_gpio_range_from_pin(pctldev, pin);
  326. struct st_gpio_bank *bank = gpio_range_to_bank(range);
  327. return &bank->pc;
  328. }
  329. /* Low level functions.. */
  330. static inline int st_gpio_bank(int gpio)
  331. {
  332. return gpio/ST_GPIO_PINS_PER_BANK;
  333. }
  334. static inline int st_gpio_pin(int gpio)
  335. {
  336. return gpio%ST_GPIO_PINS_PER_BANK;
  337. }
  338. static void st_pinconf_set_config(struct st_pio_control *pc,
  339. int pin, unsigned long config)
  340. {
  341. struct regmap_field *output_enable = pc->oe;
  342. struct regmap_field *pull_up = pc->pu;
  343. struct regmap_field *open_drain = pc->od;
  344. unsigned int oe_value, pu_value, od_value;
  345. unsigned long mask = BIT(pin);
  346. if (output_enable) {
  347. regmap_field_read(output_enable, &oe_value);
  348. oe_value &= ~mask;
  349. if (config & ST_PINCONF_OE)
  350. oe_value |= mask;
  351. regmap_field_write(output_enable, oe_value);
  352. }
  353. if (pull_up) {
  354. regmap_field_read(pull_up, &pu_value);
  355. pu_value &= ~mask;
  356. if (config & ST_PINCONF_PU)
  357. pu_value |= mask;
  358. regmap_field_write(pull_up, pu_value);
  359. }
  360. if (open_drain) {
  361. regmap_field_read(open_drain, &od_value);
  362. od_value &= ~mask;
  363. if (config & ST_PINCONF_OD)
  364. od_value |= mask;
  365. regmap_field_write(open_drain, od_value);
  366. }
  367. }
  368. static void st_pctl_set_function(struct st_pio_control *pc,
  369. int pin_id, int function)
  370. {
  371. struct regmap_field *alt = pc->alt;
  372. unsigned int val;
  373. int pin = st_gpio_pin(pin_id);
  374. int offset = pin * 4;
  375. if (!alt)
  376. return;
  377. regmap_field_read(alt, &val);
  378. val &= ~(0xf << offset);
  379. val |= function << offset;
  380. regmap_field_write(alt, val);
  381. }
  382. static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
  383. {
  384. struct regmap_field *alt = pc->alt;
  385. unsigned int val;
  386. int offset = pin * 4;
  387. if (!alt)
  388. return 0;
  389. regmap_field_read(alt, &val);
  390. return (val >> offset) & 0xf;
  391. }
  392. static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
  393. const struct st_pctl_data *data, unsigned long config)
  394. {
  395. const unsigned int *delay_times;
  396. int num_delay_times, i, closest_index = -1;
  397. unsigned int closest_divergence = UINT_MAX;
  398. if (ST_PINCONF_UNPACK_OE(config)) {
  399. delay_times = data->output_delays;
  400. num_delay_times = data->noutput_delays;
  401. } else {
  402. delay_times = data->input_delays;
  403. num_delay_times = data->ninput_delays;
  404. }
  405. for (i = 0; i < num_delay_times; i++) {
  406. unsigned int divergence = abs(delay - delay_times[i]);
  407. if (divergence == 0)
  408. return i;
  409. if (divergence < closest_divergence) {
  410. closest_divergence = divergence;
  411. closest_index = i;
  412. }
  413. }
  414. pr_warn("Attempt to set delay %d, closest available %d\n",
  415. delay, delay_times[closest_index]);
  416. return closest_index;
  417. }
  418. static unsigned long st_pinconf_bit_to_delay(unsigned int index,
  419. const struct st_pctl_data *data, unsigned long output)
  420. {
  421. const unsigned int *delay_times;
  422. int num_delay_times;
  423. if (output) {
  424. delay_times = data->output_delays;
  425. num_delay_times = data->noutput_delays;
  426. } else {
  427. delay_times = data->input_delays;
  428. num_delay_times = data->ninput_delays;
  429. }
  430. if (index < num_delay_times) {
  431. return delay_times[index];
  432. } else {
  433. pr_warn("Delay not found in/out delay list\n");
  434. return 0;
  435. }
  436. }
  437. static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
  438. int enable, int pin)
  439. {
  440. unsigned int val = 0;
  441. regmap_field_read(field, &val);
  442. if (enable)
  443. val |= BIT(pin);
  444. else
  445. val &= ~BIT(pin);
  446. regmap_field_write(field, val);
  447. }
  448. static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
  449. struct st_pio_control *pc, unsigned long config, int pin)
  450. {
  451. const struct st_pctl_data *data = info->data;
  452. struct st_retime_packed *rt_p = &pc->rt.rt_p;
  453. unsigned int delay;
  454. st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
  455. ST_PINCONF_UNPACK_RT_CLK(config), pin);
  456. st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
  457. ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
  458. st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
  459. ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
  460. st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
  461. ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
  462. st_regmap_field_bit_set_clear_pin(rt_p->retime,
  463. ST_PINCONF_UNPACK_RT(config), pin);
  464. delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
  465. data, config);
  466. /* 2 bit delay, lsb */
  467. st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
  468. /* 2 bit delay, msb */
  469. st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
  470. }
  471. static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
  472. struct st_pio_control *pc, unsigned long config, int pin)
  473. {
  474. int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
  475. int clk = ST_PINCONF_UNPACK_RT_CLK(config);
  476. int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
  477. int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
  478. int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
  479. int retime = ST_PINCONF_UNPACK_RT(config);
  480. unsigned long delay = st_pinconf_delay_to_bit(
  481. ST_PINCONF_UNPACK_RT_DELAY(config),
  482. info->data, config);
  483. struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
  484. unsigned long retime_config =
  485. ((clk) << RT_D_CFG_CLK_SHIFT) |
  486. ((delay) << RT_D_CFG_DELAY_SHIFT) |
  487. ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
  488. ((retime) << RT_D_CFG_RETIME_SHIFT) |
  489. ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
  490. ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
  491. ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
  492. regmap_field_write(rt_d->rt[pin], retime_config);
  493. }
  494. static void st_pinconf_get_direction(struct st_pio_control *pc,
  495. int pin, unsigned long *config)
  496. {
  497. unsigned int oe_value, pu_value, od_value;
  498. if (pc->oe) {
  499. regmap_field_read(pc->oe, &oe_value);
  500. if (oe_value & BIT(pin))
  501. ST_PINCONF_PACK_OE(*config);
  502. }
  503. if (pc->pu) {
  504. regmap_field_read(pc->pu, &pu_value);
  505. if (pu_value & BIT(pin))
  506. ST_PINCONF_PACK_PU(*config);
  507. }
  508. if (pc->od) {
  509. regmap_field_read(pc->od, &od_value);
  510. if (od_value & BIT(pin))
  511. ST_PINCONF_PACK_OD(*config);
  512. }
  513. }
  514. static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
  515. struct st_pio_control *pc, int pin, unsigned long *config)
  516. {
  517. const struct st_pctl_data *data = info->data;
  518. struct st_retime_packed *rt_p = &pc->rt.rt_p;
  519. unsigned int delay_bits, delay, delay0, delay1, val;
  520. int output = ST_PINCONF_UNPACK_OE(*config);
  521. if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
  522. ST_PINCONF_PACK_RT(*config);
  523. if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
  524. ST_PINCONF_PACK_RT_CLK(*config, 1);
  525. if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
  526. ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
  527. if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
  528. ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
  529. if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
  530. ST_PINCONF_PACK_RT_INVERTCLK(*config);
  531. regmap_field_read(rt_p->delay_0, &delay0);
  532. regmap_field_read(rt_p->delay_1, &delay1);
  533. delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
  534. (((delay0 & BIT(pin)) ? 1 : 0));
  535. delay = st_pinconf_bit_to_delay(delay_bits, data, output);
  536. ST_PINCONF_PACK_RT_DELAY(*config, delay);
  537. return 0;
  538. }
  539. static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
  540. struct st_pio_control *pc, int pin, unsigned long *config)
  541. {
  542. unsigned int value;
  543. unsigned long delay_bits, delay, rt_clk;
  544. int output = ST_PINCONF_UNPACK_OE(*config);
  545. struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
  546. regmap_field_read(rt_d->rt[pin], &value);
  547. rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
  548. ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
  549. delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
  550. delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
  551. ST_PINCONF_PACK_RT_DELAY(*config, delay);
  552. if (value & RT_D_CFG_CLKNOTDATA_MASK)
  553. ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
  554. if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
  555. ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
  556. if (value & RT_D_CFG_INVERTCLK_MASK)
  557. ST_PINCONF_PACK_RT_INVERTCLK(*config);
  558. if (value & RT_D_CFG_RETIME_MASK)
  559. ST_PINCONF_PACK_RT(*config);
  560. return 0;
  561. }
  562. /* GPIO related functions */
  563. static inline void __st_gpio_set(struct st_gpio_bank *bank,
  564. unsigned offset, int value)
  565. {
  566. if (value)
  567. writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
  568. else
  569. writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
  570. }
  571. static void st_gpio_direction(struct st_gpio_bank *bank,
  572. unsigned int gpio, unsigned int direction)
  573. {
  574. int offset = st_gpio_pin(gpio);
  575. int i = 0;
  576. /**
  577. * There are three configuration registers (PIOn_PC0, PIOn_PC1
  578. * and PIOn_PC2) for each port. These are used to configure the
  579. * PIO port pins. Each pin can be configured as an input, output,
  580. * bidirectional, or alternative function pin. Three bits, one bit
  581. * from each of the three registers, configure the corresponding bit of
  582. * the port. Valid bit settings is:
  583. *
  584. * PC2 PC1 PC0 Direction.
  585. * 0 0 0 [Input Weak pull-up]
  586. * 0 0 or 1 1 [Bidirection]
  587. * 0 1 0 [Output]
  588. * 1 0 0 [Input]
  589. *
  590. * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
  591. * individually.
  592. */
  593. for (i = 0; i <= 2; i++) {
  594. if (direction & BIT(i))
  595. writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
  596. else
  597. writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
  598. }
  599. }
  600. static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
  601. {
  602. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  603. return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
  604. }
  605. static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  606. {
  607. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  608. __st_gpio_set(bank, offset, value);
  609. }
  610. static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  611. {
  612. pinctrl_gpio_direction_input(chip->base + offset);
  613. return 0;
  614. }
  615. static int st_gpio_direction_output(struct gpio_chip *chip,
  616. unsigned offset, int value)
  617. {
  618. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  619. __st_gpio_set(bank, offset, value);
  620. pinctrl_gpio_direction_output(chip->base + offset);
  621. return 0;
  622. }
  623. static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  624. {
  625. struct st_gpio_bank *bank = gpiochip_get_data(chip);
  626. struct st_pio_control pc = bank->pc;
  627. unsigned long config;
  628. unsigned int direction = 0;
  629. unsigned int function;
  630. unsigned int value;
  631. int i = 0;
  632. /* Alternate function direction is handled by Pinctrl */
  633. function = st_pctl_get_pin_function(&pc, offset);
  634. if (function) {
  635. st_pinconf_get_direction(&pc, offset, &config);
  636. if (ST_PINCONF_UNPACK_OE(config))
  637. return GPIO_LINE_DIRECTION_OUT;
  638. return GPIO_LINE_DIRECTION_IN;
  639. }
  640. /*
  641. * GPIO direction is handled differently
  642. * - See st_gpio_direction() above for an explanation
  643. */
  644. for (i = 0; i <= 2; i++) {
  645. value = readl(bank->base + REG_PIO_PC(i));
  646. direction |= ((value >> offset) & 0x1) << i;
  647. }
  648. if (direction == ST_GPIO_DIRECTION_IN)
  649. return GPIO_LINE_DIRECTION_IN;
  650. return GPIO_LINE_DIRECTION_OUT;
  651. }
  652. /* Pinctrl Groups */
  653. static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  654. {
  655. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  656. return info->ngroups;
  657. }
  658. static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
  659. unsigned selector)
  660. {
  661. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  662. return info->groups[selector].name;
  663. }
  664. static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  665. unsigned selector, const unsigned **pins, unsigned *npins)
  666. {
  667. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  668. if (selector >= info->ngroups)
  669. return -EINVAL;
  670. *pins = info->groups[selector].pins;
  671. *npins = info->groups[selector].npins;
  672. return 0;
  673. }
  674. static inline const struct st_pctl_group *st_pctl_find_group_by_name(
  675. const struct st_pinctrl *info, const char *name)
  676. {
  677. int i;
  678. for (i = 0; i < info->ngroups; i++) {
  679. if (!strcmp(info->groups[i].name, name))
  680. return &info->groups[i];
  681. }
  682. return NULL;
  683. }
  684. static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
  685. struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
  686. {
  687. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  688. const struct st_pctl_group *grp;
  689. struct pinctrl_map *new_map;
  690. struct device_node *parent;
  691. int map_num, i;
  692. grp = st_pctl_find_group_by_name(info, np->name);
  693. if (!grp) {
  694. dev_err(info->dev, "unable to find group for node %pOFn\n",
  695. np);
  696. return -EINVAL;
  697. }
  698. map_num = grp->npins + 1;
  699. new_map = devm_kcalloc(pctldev->dev,
  700. map_num, sizeof(*new_map), GFP_KERNEL);
  701. if (!new_map)
  702. return -ENOMEM;
  703. parent = of_get_parent(np);
  704. if (!parent) {
  705. devm_kfree(pctldev->dev, new_map);
  706. return -EINVAL;
  707. }
  708. *map = new_map;
  709. *num_maps = map_num;
  710. new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
  711. new_map[0].data.mux.function = parent->name;
  712. new_map[0].data.mux.group = np->name;
  713. of_node_put(parent);
  714. /* create config map per pin */
  715. new_map++;
  716. for (i = 0; i < grp->npins; i++) {
  717. new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
  718. new_map[i].data.configs.group_or_pin =
  719. pin_get_name(pctldev, grp->pins[i]);
  720. new_map[i].data.configs.configs = &grp->pin_conf[i].config;
  721. new_map[i].data.configs.num_configs = 1;
  722. }
  723. dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
  724. (*map)->data.mux.function, grp->name, map_num);
  725. return 0;
  726. }
  727. static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
  728. struct pinctrl_map *map, unsigned num_maps)
  729. {
  730. }
  731. static const struct pinctrl_ops st_pctlops = {
  732. .get_groups_count = st_pctl_get_groups_count,
  733. .get_group_pins = st_pctl_get_group_pins,
  734. .get_group_name = st_pctl_get_group_name,
  735. .dt_node_to_map = st_pctl_dt_node_to_map,
  736. .dt_free_map = st_pctl_dt_free_map,
  737. };
  738. /* Pinmux */
  739. static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
  740. {
  741. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  742. return info->nfunctions;
  743. }
  744. static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
  745. unsigned selector)
  746. {
  747. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  748. return info->functions[selector].name;
  749. }
  750. static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
  751. unsigned selector, const char * const **grps, unsigned * const ngrps)
  752. {
  753. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  754. *grps = info->functions[selector].groups;
  755. *ngrps = info->functions[selector].ngroups;
  756. return 0;
  757. }
  758. static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
  759. unsigned group)
  760. {
  761. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  762. struct st_pinconf *conf = info->groups[group].pin_conf;
  763. struct st_pio_control *pc;
  764. int i;
  765. for (i = 0; i < info->groups[group].npins; i++) {
  766. pc = st_get_pio_control(pctldev, conf[i].pin);
  767. st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
  768. }
  769. return 0;
  770. }
  771. static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
  772. struct pinctrl_gpio_range *range, unsigned gpio,
  773. bool input)
  774. {
  775. struct st_gpio_bank *bank = gpio_range_to_bank(range);
  776. /*
  777. * When a PIO bank is used in its primary function mode (altfunc = 0)
  778. * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
  779. * for the primary PIO functions are driven by the related PIO block
  780. */
  781. st_pctl_set_function(&bank->pc, gpio, 0);
  782. st_gpio_direction(bank, gpio, input ?
  783. ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
  784. return 0;
  785. }
  786. static const struct pinmux_ops st_pmxops = {
  787. .get_functions_count = st_pmx_get_funcs_count,
  788. .get_function_name = st_pmx_get_fname,
  789. .get_function_groups = st_pmx_get_groups,
  790. .set_mux = st_pmx_set_mux,
  791. .gpio_set_direction = st_pmx_set_gpio_direction,
  792. .strict = true,
  793. };
  794. /* Pinconf */
  795. static void st_pinconf_get_retime(struct st_pinctrl *info,
  796. struct st_pio_control *pc, int pin, unsigned long *config)
  797. {
  798. if (info->data->rt_style == st_retime_style_packed)
  799. st_pinconf_get_retime_packed(info, pc, pin, config);
  800. else if (info->data->rt_style == st_retime_style_dedicated)
  801. if ((BIT(pin) & pc->rt_pin_mask))
  802. st_pinconf_get_retime_dedicated(info, pc,
  803. pin, config);
  804. }
  805. static void st_pinconf_set_retime(struct st_pinctrl *info,
  806. struct st_pio_control *pc, int pin, unsigned long config)
  807. {
  808. if (info->data->rt_style == st_retime_style_packed)
  809. st_pinconf_set_retime_packed(info, pc, config, pin);
  810. else if (info->data->rt_style == st_retime_style_dedicated)
  811. if ((BIT(pin) & pc->rt_pin_mask))
  812. st_pinconf_set_retime_dedicated(info, pc,
  813. config, pin);
  814. }
  815. static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
  816. unsigned long *configs, unsigned num_configs)
  817. {
  818. int pin = st_gpio_pin(pin_id);
  819. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  820. struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
  821. int i;
  822. for (i = 0; i < num_configs; i++) {
  823. st_pinconf_set_config(pc, pin, configs[i]);
  824. st_pinconf_set_retime(info, pc, pin, configs[i]);
  825. } /* for each config */
  826. return 0;
  827. }
  828. static int st_pinconf_get(struct pinctrl_dev *pctldev,
  829. unsigned pin_id, unsigned long *config)
  830. {
  831. int pin = st_gpio_pin(pin_id);
  832. struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  833. struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
  834. *config = 0;
  835. st_pinconf_get_direction(pc, pin, config);
  836. st_pinconf_get_retime(info, pc, pin, config);
  837. return 0;
  838. }
  839. static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  840. struct seq_file *s, unsigned pin_id)
  841. {
  842. struct st_pio_control *pc;
  843. unsigned long config;
  844. unsigned int function;
  845. int offset = st_gpio_pin(pin_id);
  846. char f[16];
  847. int oe;
  848. mutex_unlock(&pctldev->mutex);
  849. pc = st_get_pio_control(pctldev, pin_id);
  850. st_pinconf_get(pctldev, pin_id, &config);
  851. mutex_lock(&pctldev->mutex);
  852. function = st_pctl_get_pin_function(pc, offset);
  853. if (function)
  854. snprintf(f, 10, "Alt Fn %u", function);
  855. else
  856. snprintf(f, 5, "GPIO");
  857. oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
  858. seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
  859. "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
  860. "de:%ld,rt-clk:%ld,rt-delay:%ld]",
  861. (oe == GPIO_LINE_DIRECTION_OUT),
  862. ST_PINCONF_UNPACK_PU(config),
  863. ST_PINCONF_UNPACK_OD(config),
  864. f,
  865. ST_PINCONF_UNPACK_RT(config),
  866. ST_PINCONF_UNPACK_RT_INVERTCLK(config),
  867. ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
  868. ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
  869. ST_PINCONF_UNPACK_RT_CLK(config),
  870. ST_PINCONF_UNPACK_RT_DELAY(config));
  871. }
  872. static const struct pinconf_ops st_confops = {
  873. .pin_config_get = st_pinconf_get,
  874. .pin_config_set = st_pinconf_set,
  875. .pin_config_dbg_show = st_pinconf_dbg_show,
  876. };
  877. static void st_pctl_dt_child_count(struct st_pinctrl *info,
  878. struct device_node *np)
  879. {
  880. struct device_node *child;
  881. for_each_child_of_node(np, child) {
  882. if (of_property_read_bool(child, "gpio-controller")) {
  883. info->nbanks++;
  884. } else {
  885. info->nfunctions++;
  886. info->ngroups += of_get_child_count(child);
  887. }
  888. }
  889. }
  890. static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
  891. int bank, struct st_pio_control *pc)
  892. {
  893. struct device *dev = info->dev;
  894. struct regmap *rm = info->regmap;
  895. const struct st_pctl_data *data = info->data;
  896. /* 2 registers per bank */
  897. int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
  898. struct st_retime_packed *rt_p = &pc->rt.rt_p;
  899. /* cfg0 */
  900. struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
  901. struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
  902. struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
  903. /* cfg1 */
  904. struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
  905. struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
  906. struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
  907. struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
  908. rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
  909. rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
  910. rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
  911. rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
  912. rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
  913. rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
  914. rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
  915. if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
  916. IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
  917. IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
  918. IS_ERR(rt_p->double_edge))
  919. return -EINVAL;
  920. return 0;
  921. }
  922. static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
  923. int bank, struct st_pio_control *pc)
  924. {
  925. struct device *dev = info->dev;
  926. struct regmap *rm = info->regmap;
  927. const struct st_pctl_data *data = info->data;
  928. /* 8 registers per bank */
  929. int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
  930. struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
  931. unsigned int j;
  932. u32 pin_mask = pc->rt_pin_mask;
  933. for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
  934. if (BIT(j) & pin_mask) {
  935. struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
  936. rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
  937. if (IS_ERR(rt_d->rt[j]))
  938. return -EINVAL;
  939. reg_offset += 4;
  940. }
  941. }
  942. return 0;
  943. }
  944. static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
  945. int bank, struct st_pio_control *pc)
  946. {
  947. const struct st_pctl_data *data = info->data;
  948. if (data->rt_style == st_retime_style_packed)
  949. return st_pctl_dt_setup_retime_packed(info, bank, pc);
  950. else if (data->rt_style == st_retime_style_dedicated)
  951. return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
  952. return -EINVAL;
  953. }
  954. static struct regmap_field *st_pc_get_value(struct device *dev,
  955. struct regmap *regmap, int bank,
  956. int data, int lsb, int msb)
  957. {
  958. struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
  959. if (data < 0)
  960. return NULL;
  961. return devm_regmap_field_alloc(dev, regmap, reg);
  962. }
  963. static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
  964. struct device_node *np)
  965. {
  966. const struct st_pctl_data *data = info->data;
  967. /**
  968. * For a given shared register like OE/PU/OD, there are 8 bits per bank
  969. * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
  970. * So each register is shared across 4 banks.
  971. */
  972. int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
  973. int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
  974. struct st_pio_control *pc = &info->banks[bank].pc;
  975. struct device *dev = info->dev;
  976. struct regmap *regmap = info->regmap;
  977. pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
  978. pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
  979. pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
  980. pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
  981. /* retime avaiable for all pins by default */
  982. pc->rt_pin_mask = 0xff;
  983. of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
  984. st_pctl_dt_setup_retime(info, bank, pc);
  985. return;
  986. }
  987. /*
  988. * Each pin is represented in of the below forms.
  989. * <bank offset mux direction rt_type rt_delay rt_clk>
  990. */
  991. static int st_pctl_dt_parse_groups(struct device_node *np,
  992. struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
  993. {
  994. /* bank pad direction val altfunction */
  995. const __be32 *list;
  996. struct property *pp;
  997. struct st_pinconf *conf;
  998. struct device_node *pins;
  999. int i = 0, npins = 0, nr_props, ret = 0;
  1000. pins = of_get_child_by_name(np, "st,pins");
  1001. if (!pins)
  1002. return -ENODATA;
  1003. for_each_property_of_node(pins, pp) {
  1004. /* Skip those we do not want to proceed */
  1005. if (!strcmp(pp->name, "name"))
  1006. continue;
  1007. if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
  1008. npins++;
  1009. } else {
  1010. pr_warn("Invalid st,pins in %pOFn node\n", np);
  1011. ret = -EINVAL;
  1012. goto out_put_node;
  1013. }
  1014. }
  1015. grp->npins = npins;
  1016. grp->name = np->name;
  1017. grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL);
  1018. grp->pin_conf = devm_kcalloc(info->dev,
  1019. npins, sizeof(*conf), GFP_KERNEL);
  1020. if (!grp->pins || !grp->pin_conf) {
  1021. ret = -ENOMEM;
  1022. goto out_put_node;
  1023. }
  1024. /* <bank offset mux direction rt_type rt_delay rt_clk> */
  1025. for_each_property_of_node(pins, pp) {
  1026. if (!strcmp(pp->name, "name"))
  1027. continue;
  1028. nr_props = pp->length/sizeof(u32);
  1029. list = pp->value;
  1030. conf = &grp->pin_conf[i];
  1031. /* bank & offset */
  1032. be32_to_cpup(list++);
  1033. be32_to_cpup(list++);
  1034. conf->pin = of_get_named_gpio(pins, pp->name, 0);
  1035. conf->name = pp->name;
  1036. grp->pins[i] = conf->pin;
  1037. /* mux */
  1038. conf->altfunc = be32_to_cpup(list++);
  1039. conf->config = 0;
  1040. /* direction */
  1041. conf->config |= be32_to_cpup(list++);
  1042. /* rt_type rt_delay rt_clk */
  1043. if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
  1044. /* rt_type */
  1045. conf->config |= be32_to_cpup(list++);
  1046. /* rt_delay */
  1047. conf->config |= be32_to_cpup(list++);
  1048. /* rt_clk */
  1049. if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
  1050. conf->config |= be32_to_cpup(list++);
  1051. }
  1052. i++;
  1053. }
  1054. out_put_node:
  1055. of_node_put(pins);
  1056. return ret;
  1057. }
  1058. static int st_pctl_parse_functions(struct device_node *np,
  1059. struct st_pinctrl *info, u32 index, int *grp_index)
  1060. {
  1061. struct device_node *child;
  1062. struct st_pmx_func *func;
  1063. struct st_pctl_group *grp;
  1064. int ret, i;
  1065. func = &info->functions[index];
  1066. func->name = np->name;
  1067. func->ngroups = of_get_child_count(np);
  1068. if (func->ngroups == 0) {
  1069. dev_err(info->dev, "No groups defined\n");
  1070. return -EINVAL;
  1071. }
  1072. func->groups = devm_kcalloc(info->dev,
  1073. func->ngroups, sizeof(char *), GFP_KERNEL);
  1074. if (!func->groups)
  1075. return -ENOMEM;
  1076. i = 0;
  1077. for_each_child_of_node(np, child) {
  1078. func->groups[i] = child->name;
  1079. grp = &info->groups[*grp_index];
  1080. *grp_index += 1;
  1081. ret = st_pctl_dt_parse_groups(child, grp, info, i++);
  1082. if (ret) {
  1083. of_node_put(child);
  1084. return ret;
  1085. }
  1086. }
  1087. dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
  1088. index, func->name, func->ngroups);
  1089. return 0;
  1090. }
  1091. static void st_gpio_irq_mask(struct irq_data *d)
  1092. {
  1093. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1094. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1095. writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
  1096. }
  1097. static void st_gpio_irq_unmask(struct irq_data *d)
  1098. {
  1099. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1100. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1101. writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
  1102. }
  1103. static int st_gpio_irq_request_resources(struct irq_data *d)
  1104. {
  1105. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1106. st_gpio_direction_input(gc, d->hwirq);
  1107. return gpiochip_lock_as_irq(gc, d->hwirq);
  1108. }
  1109. static void st_gpio_irq_release_resources(struct irq_data *d)
  1110. {
  1111. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1112. gpiochip_unlock_as_irq(gc, d->hwirq);
  1113. }
  1114. static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
  1115. {
  1116. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1117. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1118. unsigned long flags;
  1119. int comp, pin = d->hwirq;
  1120. u32 val;
  1121. u32 pin_edge_conf = 0;
  1122. switch (type) {
  1123. case IRQ_TYPE_LEVEL_HIGH:
  1124. comp = 0;
  1125. break;
  1126. case IRQ_TYPE_EDGE_FALLING:
  1127. comp = 0;
  1128. pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
  1129. break;
  1130. case IRQ_TYPE_LEVEL_LOW:
  1131. comp = 1;
  1132. break;
  1133. case IRQ_TYPE_EDGE_RISING:
  1134. comp = 1;
  1135. pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
  1136. break;
  1137. case IRQ_TYPE_EDGE_BOTH:
  1138. comp = st_gpio_get(&bank->gpio_chip, pin);
  1139. pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
  1140. break;
  1141. default:
  1142. return -EINVAL;
  1143. }
  1144. spin_lock_irqsave(&bank->lock, flags);
  1145. bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
  1146. pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
  1147. bank->irq_edge_conf |= pin_edge_conf;
  1148. spin_unlock_irqrestore(&bank->lock, flags);
  1149. val = readl(bank->base + REG_PIO_PCOMP);
  1150. val &= ~BIT(pin);
  1151. val |= (comp << pin);
  1152. writel(val, bank->base + REG_PIO_PCOMP);
  1153. return 0;
  1154. }
  1155. /*
  1156. * As edge triggers are not supported at hardware level, it is supported by
  1157. * software by exploiting the level trigger support in hardware.
  1158. *
  1159. * Steps for detection raising edge interrupt in software.
  1160. *
  1161. * Step 1: CONFIGURE pin to detect level LOW interrupts.
  1162. *
  1163. * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
  1164. * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
  1165. * IGNORE calling the actual interrupt handler for the pin at this stage.
  1166. *
  1167. * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
  1168. * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
  1169. * DISPATCH the interrupt to the interrupt handler of the pin.
  1170. *
  1171. * step-1 ________ __________
  1172. * | | step - 3
  1173. * | |
  1174. * step -2 |_____|
  1175. *
  1176. * falling edge is also detected int the same way.
  1177. *
  1178. */
  1179. static void __gpio_irq_handler(struct st_gpio_bank *bank)
  1180. {
  1181. unsigned long port_in, port_mask, port_comp, active_irqs;
  1182. unsigned long bank_edge_mask, flags;
  1183. int n, val, ecfg;
  1184. spin_lock_irqsave(&bank->lock, flags);
  1185. bank_edge_mask = bank->irq_edge_conf;
  1186. spin_unlock_irqrestore(&bank->lock, flags);
  1187. for (;;) {
  1188. port_in = readl(bank->base + REG_PIO_PIN);
  1189. port_comp = readl(bank->base + REG_PIO_PCOMP);
  1190. port_mask = readl(bank->base + REG_PIO_PMASK);
  1191. active_irqs = (port_in ^ port_comp) & port_mask;
  1192. if (active_irqs == 0)
  1193. break;
  1194. for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
  1195. /* check if we are detecting fake edges ... */
  1196. ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
  1197. if (ecfg) {
  1198. /* edge detection. */
  1199. val = st_gpio_get(&bank->gpio_chip, n);
  1200. writel(BIT(n),
  1201. val ? bank->base + REG_PIO_SET_PCOMP :
  1202. bank->base + REG_PIO_CLR_PCOMP);
  1203. if (ecfg != ST_IRQ_EDGE_BOTH &&
  1204. !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
  1205. continue;
  1206. }
  1207. generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n));
  1208. }
  1209. }
  1210. }
  1211. static void st_gpio_irq_handler(struct irq_desc *desc)
  1212. {
  1213. /* interrupt dedicated per bank */
  1214. struct irq_chip *chip = irq_desc_get_chip(desc);
  1215. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  1216. struct st_gpio_bank *bank = gpiochip_get_data(gc);
  1217. chained_irq_enter(chip, desc);
  1218. __gpio_irq_handler(bank);
  1219. chained_irq_exit(chip, desc);
  1220. }
  1221. static void st_gpio_irqmux_handler(struct irq_desc *desc)
  1222. {
  1223. struct irq_chip *chip = irq_desc_get_chip(desc);
  1224. struct st_pinctrl *info = irq_desc_get_handler_data(desc);
  1225. unsigned long status;
  1226. int n;
  1227. chained_irq_enter(chip, desc);
  1228. status = readl(info->irqmux_base);
  1229. for_each_set_bit(n, &status, info->nbanks)
  1230. __gpio_irq_handler(&info->banks[n]);
  1231. chained_irq_exit(chip, desc);
  1232. }
  1233. static const struct gpio_chip st_gpio_template = {
  1234. .request = gpiochip_generic_request,
  1235. .free = gpiochip_generic_free,
  1236. .get = st_gpio_get,
  1237. .set = st_gpio_set,
  1238. .direction_input = st_gpio_direction_input,
  1239. .direction_output = st_gpio_direction_output,
  1240. .get_direction = st_gpio_get_direction,
  1241. .ngpio = ST_GPIO_PINS_PER_BANK,
  1242. };
  1243. static struct irq_chip st_gpio_irqchip = {
  1244. .name = "GPIO",
  1245. .irq_request_resources = st_gpio_irq_request_resources,
  1246. .irq_release_resources = st_gpio_irq_release_resources,
  1247. .irq_disable = st_gpio_irq_mask,
  1248. .irq_mask = st_gpio_irq_mask,
  1249. .irq_unmask = st_gpio_irq_unmask,
  1250. .irq_set_type = st_gpio_irq_set_type,
  1251. .flags = IRQCHIP_SKIP_SET_WAKE,
  1252. };
  1253. static int st_gpiolib_register_bank(struct st_pinctrl *info,
  1254. int bank_nr, struct device_node *np)
  1255. {
  1256. struct st_gpio_bank *bank = &info->banks[bank_nr];
  1257. struct pinctrl_gpio_range *range = &bank->range;
  1258. struct device *dev = info->dev;
  1259. int bank_num = of_alias_get_id(np, "gpio");
  1260. struct resource res, irq_res;
  1261. int err;
  1262. if (of_address_to_resource(np, 0, &res))
  1263. return -ENODEV;
  1264. bank->base = devm_ioremap_resource(dev, &res);
  1265. if (IS_ERR(bank->base))
  1266. return PTR_ERR(bank->base);
  1267. bank->gpio_chip = st_gpio_template;
  1268. bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
  1269. bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
  1270. bank->gpio_chip.of_node = np;
  1271. bank->gpio_chip.parent = dev;
  1272. spin_lock_init(&bank->lock);
  1273. of_property_read_string(np, "st,bank-name", &range->name);
  1274. bank->gpio_chip.label = range->name;
  1275. range->id = bank_num;
  1276. range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
  1277. range->npins = bank->gpio_chip.ngpio;
  1278. range->gc = &bank->gpio_chip;
  1279. /**
  1280. * GPIO bank can have one of the two possible types of
  1281. * interrupt-wirings.
  1282. *
  1283. * First type is via irqmux, single interrupt is used by multiple
  1284. * gpio banks. This reduces number of overall interrupts numbers
  1285. * required. All these banks belong to a single pincontroller.
  1286. * _________
  1287. * | |----> [gpio-bank (n) ]
  1288. * | |----> [gpio-bank (n + 1)]
  1289. * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
  1290. * | |----> [gpio-bank (... )]
  1291. * |_________|----> [gpio-bank (n + 7)]
  1292. *
  1293. * Second type has a dedicated interrupt per each gpio bank.
  1294. *
  1295. * [irqN]----> [gpio-bank (n)]
  1296. */
  1297. if (of_irq_to_resource(np, 0, &irq_res) > 0) {
  1298. struct gpio_irq_chip *girq;
  1299. int gpio_irq = irq_res.start;
  1300. /* This is not a valid IRQ */
  1301. if (gpio_irq <= 0) {
  1302. dev_err(dev, "invalid IRQ for %pOF bank\n", np);
  1303. goto skip_irq;
  1304. }
  1305. /* We need to have a mux as well */
  1306. if (!info->irqmux_base) {
  1307. dev_err(dev, "no irqmux for %pOF bank\n", np);
  1308. goto skip_irq;
  1309. }
  1310. girq = &bank->gpio_chip.irq;
  1311. girq->chip = &st_gpio_irqchip;
  1312. girq->parent_handler = st_gpio_irq_handler;
  1313. girq->num_parents = 1;
  1314. girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
  1315. GFP_KERNEL);
  1316. if (!girq->parents)
  1317. return -ENOMEM;
  1318. girq->parents[0] = gpio_irq;
  1319. girq->default_type = IRQ_TYPE_NONE;
  1320. girq->handler = handle_simple_irq;
  1321. }
  1322. skip_irq:
  1323. err = gpiochip_add_data(&bank->gpio_chip, bank);
  1324. if (err) {
  1325. dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
  1326. return err;
  1327. }
  1328. dev_info(dev, "%s bank added.\n", range->name);
  1329. return 0;
  1330. }
  1331. static const struct of_device_id st_pctl_of_match[] = {
  1332. { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
  1333. { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
  1334. { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
  1335. { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
  1336. { /* sentinel */ }
  1337. };
  1338. static int st_pctl_probe_dt(struct platform_device *pdev,
  1339. struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
  1340. {
  1341. int ret = 0;
  1342. int i = 0, j = 0, k = 0, bank;
  1343. struct pinctrl_pin_desc *pdesc;
  1344. struct device_node *np = pdev->dev.of_node;
  1345. struct device_node *child;
  1346. int grp_index = 0;
  1347. int irq = 0;
  1348. struct resource *res;
  1349. st_pctl_dt_child_count(info, np);
  1350. if (!info->nbanks) {
  1351. dev_err(&pdev->dev, "you need atleast one gpio bank\n");
  1352. return -EINVAL;
  1353. }
  1354. dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
  1355. dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
  1356. dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
  1357. info->functions = devm_kcalloc(&pdev->dev,
  1358. info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
  1359. info->groups = devm_kcalloc(&pdev->dev,
  1360. info->ngroups, sizeof(*info->groups),
  1361. GFP_KERNEL);
  1362. info->banks = devm_kcalloc(&pdev->dev,
  1363. info->nbanks, sizeof(*info->banks), GFP_KERNEL);
  1364. if (!info->functions || !info->groups || !info->banks)
  1365. return -ENOMEM;
  1366. info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
  1367. if (IS_ERR(info->regmap)) {
  1368. dev_err(info->dev, "No syscfg phandle specified\n");
  1369. return PTR_ERR(info->regmap);
  1370. }
  1371. info->data = of_match_node(st_pctl_of_match, np)->data;
  1372. irq = platform_get_irq(pdev, 0);
  1373. if (irq > 0) {
  1374. res = platform_get_resource_byname(pdev,
  1375. IORESOURCE_MEM, "irqmux");
  1376. info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
  1377. if (IS_ERR(info->irqmux_base))
  1378. return PTR_ERR(info->irqmux_base);
  1379. irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
  1380. info);
  1381. }
  1382. pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
  1383. pdesc = devm_kcalloc(&pdev->dev,
  1384. pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
  1385. if (!pdesc)
  1386. return -ENOMEM;
  1387. pctl_desc->pins = pdesc;
  1388. bank = 0;
  1389. for_each_child_of_node(np, child) {
  1390. if (of_property_read_bool(child, "gpio-controller")) {
  1391. const char *bank_name = NULL;
  1392. ret = st_gpiolib_register_bank(info, bank, child);
  1393. if (ret) {
  1394. of_node_put(child);
  1395. return ret;
  1396. }
  1397. k = info->banks[bank].range.pin_base;
  1398. bank_name = info->banks[bank].range.name;
  1399. for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
  1400. pdesc->number = k;
  1401. pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
  1402. bank_name, j);
  1403. pdesc++;
  1404. }
  1405. st_parse_syscfgs(info, bank, child);
  1406. bank++;
  1407. } else {
  1408. ret = st_pctl_parse_functions(child, info,
  1409. i++, &grp_index);
  1410. if (ret) {
  1411. dev_err(&pdev->dev, "No functions found.\n");
  1412. of_node_put(child);
  1413. return ret;
  1414. }
  1415. }
  1416. }
  1417. return 0;
  1418. }
  1419. static int st_pctl_probe(struct platform_device *pdev)
  1420. {
  1421. struct st_pinctrl *info;
  1422. struct pinctrl_desc *pctl_desc;
  1423. int ret, i;
  1424. if (!pdev->dev.of_node) {
  1425. dev_err(&pdev->dev, "device node not found.\n");
  1426. return -EINVAL;
  1427. }
  1428. pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
  1429. if (!pctl_desc)
  1430. return -ENOMEM;
  1431. info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
  1432. if (!info)
  1433. return -ENOMEM;
  1434. info->dev = &pdev->dev;
  1435. platform_set_drvdata(pdev, info);
  1436. ret = st_pctl_probe_dt(pdev, pctl_desc, info);
  1437. if (ret)
  1438. return ret;
  1439. pctl_desc->owner = THIS_MODULE;
  1440. pctl_desc->pctlops = &st_pctlops;
  1441. pctl_desc->pmxops = &st_pmxops;
  1442. pctl_desc->confops = &st_confops;
  1443. pctl_desc->name = dev_name(&pdev->dev);
  1444. info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info);
  1445. if (IS_ERR(info->pctl)) {
  1446. dev_err(&pdev->dev, "Failed pinctrl registration\n");
  1447. return PTR_ERR(info->pctl);
  1448. }
  1449. for (i = 0; i < info->nbanks; i++)
  1450. pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
  1451. return 0;
  1452. }
  1453. static struct platform_driver st_pctl_driver = {
  1454. .driver = {
  1455. .name = "st-pinctrl",
  1456. .of_match_table = st_pctl_of_match,
  1457. },
  1458. .probe = st_pctl_probe,
  1459. };
  1460. static int __init st_pctl_init(void)
  1461. {
  1462. return platform_driver_register(&st_pctl_driver);
  1463. }
  1464. arch_initcall(st_pctl_init);