pinctrl-single.c 48 KB

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  1. /*
  2. * Generic device tree based pinctrl driver for one register per pin
  3. * type pinmux controllers
  4. *
  5. * Copyright (C) 2012 Texas Instruments, Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/io.h>
  14. #include <linux/slab.h>
  15. #include <linux/err.h>
  16. #include <linux/list.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irqchip/chained_irq.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/pinctrl/pinctrl.h>
  24. #include <linux/pinctrl/pinmux.h>
  25. #include <linux/pinctrl/pinconf-generic.h>
  26. #include <linux/platform_data/pinctrl-single.h>
  27. #include "core.h"
  28. #include "devicetree.h"
  29. #include "pinconf.h"
  30. #include "pinmux.h"
  31. #define DRIVER_NAME "pinctrl-single"
  32. #define PCS_OFF_DISABLED ~0U
  33. /**
  34. * struct pcs_func_vals - mux function register offset and value pair
  35. * @reg: register virtual address
  36. * @val: register value
  37. * @mask: mask
  38. */
  39. struct pcs_func_vals {
  40. void __iomem *reg;
  41. unsigned val;
  42. unsigned mask;
  43. };
  44. /**
  45. * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  46. * and value, enable, disable, mask
  47. * @param: config parameter
  48. * @val: user input bits in the pinconf register
  49. * @enable: enable bits in the pinconf register
  50. * @disable: disable bits in the pinconf register
  51. * @mask: mask bits in the register value
  52. */
  53. struct pcs_conf_vals {
  54. enum pin_config_param param;
  55. unsigned val;
  56. unsigned enable;
  57. unsigned disable;
  58. unsigned mask;
  59. };
  60. /**
  61. * struct pcs_conf_type - pinconf property name, pinconf param pair
  62. * @name: property name in DTS file
  63. * @param: config parameter
  64. */
  65. struct pcs_conf_type {
  66. const char *name;
  67. enum pin_config_param param;
  68. };
  69. /**
  70. * struct pcs_function - pinctrl function
  71. * @name: pinctrl function name
  72. * @vals: register and vals array
  73. * @nvals: number of entries in vals array
  74. * @pgnames: array of pingroup names the function uses
  75. * @npgnames: number of pingroup names the function uses
  76. * @conf: array of pin configurations
  77. * @nconfs: number of pin configurations available
  78. * @node: list node
  79. */
  80. struct pcs_function {
  81. const char *name;
  82. struct pcs_func_vals *vals;
  83. unsigned nvals;
  84. const char **pgnames;
  85. int npgnames;
  86. struct pcs_conf_vals *conf;
  87. int nconfs;
  88. struct list_head node;
  89. };
  90. /**
  91. * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
  92. * @offset: offset base of pins
  93. * @npins: number pins with the same mux value of gpio function
  94. * @gpiofunc: mux value of gpio function
  95. * @node: list node
  96. */
  97. struct pcs_gpiofunc_range {
  98. unsigned offset;
  99. unsigned npins;
  100. unsigned gpiofunc;
  101. struct list_head node;
  102. };
  103. /**
  104. * struct pcs_data - wrapper for data needed by pinctrl framework
  105. * @pa: pindesc array
  106. * @cur: index to current element
  107. *
  108. * REVISIT: We should be able to drop this eventually by adding
  109. * support for registering pins individually in the pinctrl
  110. * framework for those drivers that don't need a static array.
  111. */
  112. struct pcs_data {
  113. struct pinctrl_pin_desc *pa;
  114. int cur;
  115. };
  116. /**
  117. * struct pcs_soc_data - SoC specific settings
  118. * @flags: initial SoC specific PCS_FEAT_xxx values
  119. * @irq: optional interrupt for the controller
  120. * @irq_enable_mask: optional SoC specific interrupt enable mask
  121. * @irq_status_mask: optional SoC specific interrupt status mask
  122. * @rearm: optional SoC specific wake-up rearm function
  123. */
  124. struct pcs_soc_data {
  125. unsigned flags;
  126. int irq;
  127. unsigned irq_enable_mask;
  128. unsigned irq_status_mask;
  129. void (*rearm)(void);
  130. };
  131. /**
  132. * struct pcs_device - pinctrl device instance
  133. * @res: resources
  134. * @base: virtual address of the controller
  135. * @saved_vals: saved values for the controller
  136. * @size: size of the ioremapped area
  137. * @dev: device entry
  138. * @np: device tree node
  139. * @pctl: pin controller device
  140. * @flags: mask of PCS_FEAT_xxx values
  141. * @missing_nr_pinctrl_cells: for legacy binding, may go away
  142. * @socdata: soc specific data
  143. * @lock: spinlock for register access
  144. * @mutex: mutex protecting the lists
  145. * @width: bits per mux register
  146. * @fmask: function register mask
  147. * @fshift: function register shift
  148. * @foff: value to turn mux off
  149. * @fmax: max number of functions in fmask
  150. * @bits_per_mux: number of bits per mux
  151. * @bits_per_pin: number of bits per pin
  152. * @pins: physical pins on the SoC
  153. * @gpiofuncs: list of gpio functions
  154. * @irqs: list of interrupt registers
  155. * @chip: chip container for this instance
  156. * @domain: IRQ domain for this instance
  157. * @desc: pin controller descriptor
  158. * @read: register read function to use
  159. * @write: register write function to use
  160. */
  161. struct pcs_device {
  162. struct resource *res;
  163. void __iomem *base;
  164. void *saved_vals;
  165. unsigned size;
  166. struct device *dev;
  167. struct device_node *np;
  168. struct pinctrl_dev *pctl;
  169. unsigned flags;
  170. #define PCS_CONTEXT_LOSS_OFF (1 << 3)
  171. #define PCS_QUIRK_SHARED_IRQ (1 << 2)
  172. #define PCS_FEAT_IRQ (1 << 1)
  173. #define PCS_FEAT_PINCONF (1 << 0)
  174. struct property *missing_nr_pinctrl_cells;
  175. struct pcs_soc_data socdata;
  176. raw_spinlock_t lock;
  177. struct mutex mutex;
  178. unsigned width;
  179. unsigned fmask;
  180. unsigned fshift;
  181. unsigned foff;
  182. unsigned fmax;
  183. bool bits_per_mux;
  184. unsigned bits_per_pin;
  185. struct pcs_data pins;
  186. struct list_head gpiofuncs;
  187. struct list_head irqs;
  188. struct irq_chip chip;
  189. struct irq_domain *domain;
  190. struct pinctrl_desc desc;
  191. unsigned (*read)(void __iomem *reg);
  192. void (*write)(unsigned val, void __iomem *reg);
  193. };
  194. #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
  195. #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
  196. #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
  197. static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
  198. unsigned long *config);
  199. static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
  200. unsigned long *configs, unsigned num_configs);
  201. static enum pin_config_param pcs_bias[] = {
  202. PIN_CONFIG_BIAS_PULL_DOWN,
  203. PIN_CONFIG_BIAS_PULL_UP,
  204. };
  205. /*
  206. * This lock class tells lockdep that irqchip core that this single
  207. * pinctrl can be in a different category than its parents, so it won't
  208. * report false recursion.
  209. */
  210. static struct lock_class_key pcs_lock_class;
  211. /* Class for the IRQ request mutex */
  212. static struct lock_class_key pcs_request_class;
  213. /*
  214. * REVISIT: Reads and writes could eventually use regmap or something
  215. * generic. But at least on omaps, some mux registers are performance
  216. * critical as they may need to be remuxed every time before and after
  217. * idle. Adding tests for register access width for every read and
  218. * write like regmap is doing is not desired, and caching the registers
  219. * does not help in this case.
  220. */
  221. static unsigned __maybe_unused pcs_readb(void __iomem *reg)
  222. {
  223. return readb(reg);
  224. }
  225. static unsigned __maybe_unused pcs_readw(void __iomem *reg)
  226. {
  227. return readw(reg);
  228. }
  229. static unsigned __maybe_unused pcs_readl(void __iomem *reg)
  230. {
  231. return readl(reg);
  232. }
  233. static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
  234. {
  235. writeb(val, reg);
  236. }
  237. static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
  238. {
  239. writew(val, reg);
  240. }
  241. static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
  242. {
  243. writel(val, reg);
  244. }
  245. static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
  246. unsigned int pin)
  247. {
  248. unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
  249. if (pcs->bits_per_mux) {
  250. unsigned int pin_offset_bytes;
  251. pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
  252. return (pin_offset_bytes / mux_bytes) * mux_bytes;
  253. }
  254. return pin * mux_bytes;
  255. }
  256. static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
  257. unsigned int pin)
  258. {
  259. return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
  260. }
  261. static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
  262. struct seq_file *s,
  263. unsigned pin)
  264. {
  265. struct pcs_device *pcs;
  266. unsigned int val;
  267. unsigned long offset;
  268. size_t pa;
  269. pcs = pinctrl_dev_get_drvdata(pctldev);
  270. offset = pcs_pin_reg_offset_get(pcs, pin);
  271. val = pcs->read(pcs->base + offset);
  272. if (pcs->bits_per_mux)
  273. val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
  274. pa = pcs->res->start + offset;
  275. seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
  276. }
  277. static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
  278. struct pinctrl_map *map, unsigned num_maps)
  279. {
  280. struct pcs_device *pcs;
  281. pcs = pinctrl_dev_get_drvdata(pctldev);
  282. devm_kfree(pcs->dev, map);
  283. }
  284. static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
  285. struct device_node *np_config,
  286. struct pinctrl_map **map, unsigned *num_maps);
  287. static const struct pinctrl_ops pcs_pinctrl_ops = {
  288. .get_groups_count = pinctrl_generic_get_group_count,
  289. .get_group_name = pinctrl_generic_get_group_name,
  290. .get_group_pins = pinctrl_generic_get_group_pins,
  291. .pin_dbg_show = pcs_pin_dbg_show,
  292. .dt_node_to_map = pcs_dt_node_to_map,
  293. .dt_free_map = pcs_dt_free_map,
  294. };
  295. static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
  296. struct pcs_function **func)
  297. {
  298. struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
  299. struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
  300. const struct pinctrl_setting_mux *setting;
  301. struct function_desc *function;
  302. unsigned fselector;
  303. /* If pin is not described in DTS & enabled, mux_setting is NULL. */
  304. setting = pdesc->mux_setting;
  305. if (!setting)
  306. return -ENOTSUPP;
  307. fselector = setting->func;
  308. function = pinmux_generic_get_function(pctldev, fselector);
  309. *func = function->data;
  310. if (!(*func)) {
  311. dev_err(pcs->dev, "%s could not find function%i\n",
  312. __func__, fselector);
  313. return -ENOTSUPP;
  314. }
  315. return 0;
  316. }
  317. static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
  318. unsigned group)
  319. {
  320. struct pcs_device *pcs;
  321. struct function_desc *function;
  322. struct pcs_function *func;
  323. int i;
  324. pcs = pinctrl_dev_get_drvdata(pctldev);
  325. /* If function mask is null, needn't enable it. */
  326. if (!pcs->fmask)
  327. return 0;
  328. function = pinmux_generic_get_function(pctldev, fselector);
  329. func = function->data;
  330. if (!func)
  331. return -EINVAL;
  332. dev_dbg(pcs->dev, "enabling %s function%i\n",
  333. func->name, fselector);
  334. for (i = 0; i < func->nvals; i++) {
  335. struct pcs_func_vals *vals;
  336. unsigned long flags;
  337. unsigned val, mask;
  338. vals = &func->vals[i];
  339. raw_spin_lock_irqsave(&pcs->lock, flags);
  340. val = pcs->read(vals->reg);
  341. if (pcs->bits_per_mux)
  342. mask = vals->mask;
  343. else
  344. mask = pcs->fmask;
  345. val &= ~mask;
  346. val |= (vals->val & mask);
  347. pcs->write(val, vals->reg);
  348. raw_spin_unlock_irqrestore(&pcs->lock, flags);
  349. }
  350. return 0;
  351. }
  352. static int pcs_request_gpio(struct pinctrl_dev *pctldev,
  353. struct pinctrl_gpio_range *range, unsigned pin)
  354. {
  355. struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
  356. struct pcs_gpiofunc_range *frange = NULL;
  357. struct list_head *pos, *tmp;
  358. unsigned data;
  359. /* If function mask is null, return directly. */
  360. if (!pcs->fmask)
  361. return -ENOTSUPP;
  362. list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
  363. u32 offset;
  364. frange = list_entry(pos, struct pcs_gpiofunc_range, node);
  365. if (pin >= frange->offset + frange->npins
  366. || pin < frange->offset)
  367. continue;
  368. offset = pcs_pin_reg_offset_get(pcs, pin);
  369. if (pcs->bits_per_mux) {
  370. int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
  371. data = pcs->read(pcs->base + offset);
  372. data &= ~(pcs->fmask << pin_shift);
  373. data |= frange->gpiofunc << pin_shift;
  374. pcs->write(data, pcs->base + offset);
  375. } else {
  376. data = pcs->read(pcs->base + offset);
  377. data &= ~pcs->fmask;
  378. data |= frange->gpiofunc;
  379. pcs->write(data, pcs->base + offset);
  380. }
  381. break;
  382. }
  383. return 0;
  384. }
  385. static const struct pinmux_ops pcs_pinmux_ops = {
  386. .get_functions_count = pinmux_generic_get_function_count,
  387. .get_function_name = pinmux_generic_get_function_name,
  388. .get_function_groups = pinmux_generic_get_function_groups,
  389. .set_mux = pcs_set_mux,
  390. .gpio_request_enable = pcs_request_gpio,
  391. };
  392. /* Clear BIAS value */
  393. static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
  394. {
  395. unsigned long config;
  396. int i;
  397. for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
  398. config = pinconf_to_config_packed(pcs_bias[i], 0);
  399. pcs_pinconf_set(pctldev, pin, &config, 1);
  400. }
  401. }
  402. /*
  403. * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
  404. * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
  405. */
  406. static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
  407. {
  408. unsigned long config;
  409. int i;
  410. for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
  411. config = pinconf_to_config_packed(pcs_bias[i], 0);
  412. if (!pcs_pinconf_get(pctldev, pin, &config))
  413. goto out;
  414. }
  415. return true;
  416. out:
  417. return false;
  418. }
  419. static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
  420. unsigned pin, unsigned long *config)
  421. {
  422. struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
  423. struct pcs_function *func;
  424. enum pin_config_param param;
  425. unsigned offset = 0, data = 0, i, j, ret;
  426. ret = pcs_get_function(pctldev, pin, &func);
  427. if (ret)
  428. return ret;
  429. for (i = 0; i < func->nconfs; i++) {
  430. param = pinconf_to_config_param(*config);
  431. if (param == PIN_CONFIG_BIAS_DISABLE) {
  432. if (pcs_pinconf_bias_disable(pctldev, pin)) {
  433. *config = 0;
  434. return 0;
  435. } else {
  436. return -ENOTSUPP;
  437. }
  438. } else if (param != func->conf[i].param) {
  439. continue;
  440. }
  441. offset = pin * (pcs->width / BITS_PER_BYTE);
  442. data = pcs->read(pcs->base + offset) & func->conf[i].mask;
  443. switch (func->conf[i].param) {
  444. /* 4 parameters */
  445. case PIN_CONFIG_BIAS_PULL_DOWN:
  446. case PIN_CONFIG_BIAS_PULL_UP:
  447. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  448. if ((data != func->conf[i].enable) ||
  449. (data == func->conf[i].disable))
  450. return -ENOTSUPP;
  451. *config = 0;
  452. break;
  453. /* 2 parameters */
  454. case PIN_CONFIG_INPUT_SCHMITT:
  455. for (j = 0; j < func->nconfs; j++) {
  456. switch (func->conf[j].param) {
  457. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  458. if (data != func->conf[j].enable)
  459. return -ENOTSUPP;
  460. break;
  461. default:
  462. break;
  463. }
  464. }
  465. *config = data;
  466. break;
  467. case PIN_CONFIG_DRIVE_STRENGTH:
  468. case PIN_CONFIG_SLEW_RATE:
  469. case PIN_CONFIG_LOW_POWER_MODE:
  470. default:
  471. *config = data;
  472. break;
  473. }
  474. return 0;
  475. }
  476. return -ENOTSUPP;
  477. }
  478. static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
  479. unsigned pin, unsigned long *configs,
  480. unsigned num_configs)
  481. {
  482. struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
  483. struct pcs_function *func;
  484. unsigned offset = 0, shift = 0, i, data, ret;
  485. u32 arg;
  486. int j;
  487. ret = pcs_get_function(pctldev, pin, &func);
  488. if (ret)
  489. return ret;
  490. for (j = 0; j < num_configs; j++) {
  491. for (i = 0; i < func->nconfs; i++) {
  492. if (pinconf_to_config_param(configs[j])
  493. != func->conf[i].param)
  494. continue;
  495. offset = pin * (pcs->width / BITS_PER_BYTE);
  496. data = pcs->read(pcs->base + offset);
  497. arg = pinconf_to_config_argument(configs[j]);
  498. switch (func->conf[i].param) {
  499. /* 2 parameters */
  500. case PIN_CONFIG_INPUT_SCHMITT:
  501. case PIN_CONFIG_DRIVE_STRENGTH:
  502. case PIN_CONFIG_SLEW_RATE:
  503. case PIN_CONFIG_LOW_POWER_MODE:
  504. shift = ffs(func->conf[i].mask) - 1;
  505. data &= ~func->conf[i].mask;
  506. data |= (arg << shift) & func->conf[i].mask;
  507. break;
  508. /* 4 parameters */
  509. case PIN_CONFIG_BIAS_DISABLE:
  510. pcs_pinconf_clear_bias(pctldev, pin);
  511. break;
  512. case PIN_CONFIG_BIAS_PULL_DOWN:
  513. case PIN_CONFIG_BIAS_PULL_UP:
  514. if (arg)
  515. pcs_pinconf_clear_bias(pctldev, pin);
  516. fallthrough;
  517. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  518. data &= ~func->conf[i].mask;
  519. if (arg)
  520. data |= func->conf[i].enable;
  521. else
  522. data |= func->conf[i].disable;
  523. break;
  524. default:
  525. return -ENOTSUPP;
  526. }
  527. pcs->write(data, pcs->base + offset);
  528. break;
  529. }
  530. if (i >= func->nconfs)
  531. return -ENOTSUPP;
  532. } /* for each config */
  533. return 0;
  534. }
  535. static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
  536. unsigned group, unsigned long *config)
  537. {
  538. const unsigned *pins;
  539. unsigned npins, old = 0;
  540. int i, ret;
  541. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  542. if (ret)
  543. return ret;
  544. for (i = 0; i < npins; i++) {
  545. if (pcs_pinconf_get(pctldev, pins[i], config))
  546. return -ENOTSUPP;
  547. /* configs do not match between two pins */
  548. if (i && (old != *config))
  549. return -ENOTSUPP;
  550. old = *config;
  551. }
  552. return 0;
  553. }
  554. static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
  555. unsigned group, unsigned long *configs,
  556. unsigned num_configs)
  557. {
  558. const unsigned *pins;
  559. unsigned npins;
  560. int i, ret;
  561. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  562. if (ret)
  563. return ret;
  564. for (i = 0; i < npins; i++) {
  565. if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
  566. return -ENOTSUPP;
  567. }
  568. return 0;
  569. }
  570. static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  571. struct seq_file *s, unsigned pin)
  572. {
  573. }
  574. static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
  575. struct seq_file *s, unsigned selector)
  576. {
  577. }
  578. static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
  579. struct seq_file *s,
  580. unsigned long config)
  581. {
  582. pinconf_generic_dump_config(pctldev, s, config);
  583. }
  584. static const struct pinconf_ops pcs_pinconf_ops = {
  585. .pin_config_get = pcs_pinconf_get,
  586. .pin_config_set = pcs_pinconf_set,
  587. .pin_config_group_get = pcs_pinconf_group_get,
  588. .pin_config_group_set = pcs_pinconf_group_set,
  589. .pin_config_dbg_show = pcs_pinconf_dbg_show,
  590. .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
  591. .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
  592. .is_generic = true,
  593. };
  594. /**
  595. * pcs_add_pin() - add a pin to the static per controller pin array
  596. * @pcs: pcs driver instance
  597. * @offset: register offset from base
  598. */
  599. static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
  600. {
  601. struct pcs_soc_data *pcs_soc = &pcs->socdata;
  602. struct pinctrl_pin_desc *pin;
  603. int i;
  604. i = pcs->pins.cur;
  605. if (i >= pcs->desc.npins) {
  606. dev_err(pcs->dev, "too many pins, max %i\n",
  607. pcs->desc.npins);
  608. return -ENOMEM;
  609. }
  610. if (pcs_soc->irq_enable_mask) {
  611. unsigned val;
  612. val = pcs->read(pcs->base + offset);
  613. if (val & pcs_soc->irq_enable_mask) {
  614. dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
  615. (unsigned long)pcs->res->start + offset, val);
  616. val &= ~pcs_soc->irq_enable_mask;
  617. pcs->write(val, pcs->base + offset);
  618. }
  619. }
  620. pin = &pcs->pins.pa[i];
  621. pin->number = i;
  622. pcs->pins.cur++;
  623. return i;
  624. }
  625. /**
  626. * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
  627. * @pcs: pcs driver instance
  628. *
  629. * In case of errors, resources are freed in pcs_free_resources.
  630. *
  631. * If your hardware needs holes in the address space, then just set
  632. * up multiple driver instances.
  633. */
  634. static int pcs_allocate_pin_table(struct pcs_device *pcs)
  635. {
  636. int mux_bytes, nr_pins, i;
  637. int num_pins_in_register = 0;
  638. mux_bytes = pcs->width / BITS_PER_BYTE;
  639. if (pcs->bits_per_mux) {
  640. pcs->bits_per_pin = fls(pcs->fmask);
  641. nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
  642. num_pins_in_register = pcs->width / pcs->bits_per_pin;
  643. } else {
  644. nr_pins = pcs->size / mux_bytes;
  645. }
  646. dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
  647. pcs->pins.pa = devm_kcalloc(pcs->dev,
  648. nr_pins, sizeof(*pcs->pins.pa),
  649. GFP_KERNEL);
  650. if (!pcs->pins.pa)
  651. return -ENOMEM;
  652. pcs->desc.pins = pcs->pins.pa;
  653. pcs->desc.npins = nr_pins;
  654. for (i = 0; i < pcs->desc.npins; i++) {
  655. unsigned offset;
  656. int res;
  657. offset = pcs_pin_reg_offset_get(pcs, i);
  658. res = pcs_add_pin(pcs, offset);
  659. if (res < 0) {
  660. dev_err(pcs->dev, "error adding pins: %i\n", res);
  661. return res;
  662. }
  663. }
  664. return 0;
  665. }
  666. /**
  667. * pcs_add_function() - adds a new function to the function list
  668. * @pcs: pcs driver instance
  669. * @fcn: new function allocated
  670. * @name: name of the function
  671. * @vals: array of mux register value pairs used by the function
  672. * @nvals: number of mux register value pairs
  673. * @pgnames: array of pingroup names for the function
  674. * @npgnames: number of pingroup names
  675. *
  676. * Caller must take care of locking.
  677. */
  678. static int pcs_add_function(struct pcs_device *pcs,
  679. struct pcs_function **fcn,
  680. const char *name,
  681. struct pcs_func_vals *vals,
  682. unsigned int nvals,
  683. const char **pgnames,
  684. unsigned int npgnames)
  685. {
  686. struct pcs_function *function;
  687. int selector;
  688. function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
  689. if (!function)
  690. return -ENOMEM;
  691. function->vals = vals;
  692. function->nvals = nvals;
  693. selector = pinmux_generic_add_function(pcs->pctl, name,
  694. pgnames, npgnames,
  695. function);
  696. if (selector < 0) {
  697. devm_kfree(pcs->dev, function);
  698. *fcn = NULL;
  699. } else {
  700. *fcn = function;
  701. }
  702. return selector;
  703. }
  704. /**
  705. * pcs_get_pin_by_offset() - get a pin index based on the register offset
  706. * @pcs: pcs driver instance
  707. * @offset: register offset from the base
  708. *
  709. * Note that this is OK as long as the pins are in a static array.
  710. */
  711. static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
  712. {
  713. unsigned index;
  714. if (offset >= pcs->size) {
  715. dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
  716. offset, pcs->size);
  717. return -EINVAL;
  718. }
  719. if (pcs->bits_per_mux)
  720. index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
  721. else
  722. index = offset / (pcs->width / BITS_PER_BYTE);
  723. return index;
  724. }
  725. /*
  726. * check whether data matches enable bits or disable bits
  727. * Return value: 1 for matching enable bits, 0 for matching disable bits,
  728. * and negative value for matching failure.
  729. */
  730. static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
  731. {
  732. int ret = -EINVAL;
  733. if (data == enable)
  734. ret = 1;
  735. else if (data == disable)
  736. ret = 0;
  737. return ret;
  738. }
  739. static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
  740. unsigned value, unsigned enable, unsigned disable,
  741. unsigned mask)
  742. {
  743. (*conf)->param = param;
  744. (*conf)->val = value;
  745. (*conf)->enable = enable;
  746. (*conf)->disable = disable;
  747. (*conf)->mask = mask;
  748. (*conf)++;
  749. }
  750. static void add_setting(unsigned long **setting, enum pin_config_param param,
  751. unsigned arg)
  752. {
  753. **setting = pinconf_to_config_packed(param, arg);
  754. (*setting)++;
  755. }
  756. /* add pinconf setting with 2 parameters */
  757. static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
  758. const char *name, enum pin_config_param param,
  759. struct pcs_conf_vals **conf, unsigned long **settings)
  760. {
  761. unsigned value[2], shift;
  762. int ret;
  763. ret = of_property_read_u32_array(np, name, value, 2);
  764. if (ret)
  765. return;
  766. /* set value & mask */
  767. value[0] &= value[1];
  768. shift = ffs(value[1]) - 1;
  769. /* skip enable & disable */
  770. add_config(conf, param, value[0], 0, 0, value[1]);
  771. add_setting(settings, param, value[0] >> shift);
  772. }
  773. /* add pinconf setting with 4 parameters */
  774. static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
  775. const char *name, enum pin_config_param param,
  776. struct pcs_conf_vals **conf, unsigned long **settings)
  777. {
  778. unsigned value[4];
  779. int ret;
  780. /* value to set, enable, disable, mask */
  781. ret = of_property_read_u32_array(np, name, value, 4);
  782. if (ret)
  783. return;
  784. if (!value[3]) {
  785. dev_err(pcs->dev, "mask field of the property can't be 0\n");
  786. return;
  787. }
  788. value[0] &= value[3];
  789. value[1] &= value[3];
  790. value[2] &= value[3];
  791. ret = pcs_config_match(value[0], value[1], value[2]);
  792. if (ret < 0)
  793. dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
  794. add_config(conf, param, value[0], value[1], value[2], value[3]);
  795. add_setting(settings, param, ret);
  796. }
  797. static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
  798. struct pcs_function *func,
  799. struct pinctrl_map **map)
  800. {
  801. struct pinctrl_map *m = *map;
  802. int i = 0, nconfs = 0;
  803. unsigned long *settings = NULL, *s = NULL;
  804. struct pcs_conf_vals *conf = NULL;
  805. static const struct pcs_conf_type prop2[] = {
  806. { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
  807. { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
  808. { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
  809. { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
  810. };
  811. static const struct pcs_conf_type prop4[] = {
  812. { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
  813. { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
  814. { "pinctrl-single,input-schmitt-enable",
  815. PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
  816. };
  817. /* If pinconf isn't supported, don't parse properties in below. */
  818. if (!PCS_HAS_PINCONF)
  819. return -ENOTSUPP;
  820. /* cacluate how much properties are supported in current node */
  821. for (i = 0; i < ARRAY_SIZE(prop2); i++) {
  822. if (of_find_property(np, prop2[i].name, NULL))
  823. nconfs++;
  824. }
  825. for (i = 0; i < ARRAY_SIZE(prop4); i++) {
  826. if (of_find_property(np, prop4[i].name, NULL))
  827. nconfs++;
  828. }
  829. if (!nconfs)
  830. return -ENOTSUPP;
  831. func->conf = devm_kcalloc(pcs->dev,
  832. nconfs, sizeof(struct pcs_conf_vals),
  833. GFP_KERNEL);
  834. if (!func->conf)
  835. return -ENOMEM;
  836. func->nconfs = nconfs;
  837. conf = &(func->conf[0]);
  838. m++;
  839. settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
  840. GFP_KERNEL);
  841. if (!settings)
  842. return -ENOMEM;
  843. s = &settings[0];
  844. for (i = 0; i < ARRAY_SIZE(prop2); i++)
  845. pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
  846. &conf, &s);
  847. for (i = 0; i < ARRAY_SIZE(prop4); i++)
  848. pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
  849. &conf, &s);
  850. m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
  851. m->data.configs.group_or_pin = np->name;
  852. m->data.configs.configs = settings;
  853. m->data.configs.num_configs = nconfs;
  854. return 0;
  855. }
  856. /**
  857. * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
  858. * @pcs: pinctrl driver instance
  859. * @np: device node of the mux entry
  860. * @map: map entry
  861. * @num_maps: number of map
  862. * @pgnames: pingroup names
  863. *
  864. * Note that this binding currently supports only sets of one register + value.
  865. *
  866. * Also note that this driver tries to avoid understanding pin and function
  867. * names because of the extra bloat they would cause especially in the case of
  868. * a large number of pins. This driver just sets what is specified for the board
  869. * in the .dts file. Further user space debugging tools can be developed to
  870. * decipher the pin and function names using debugfs.
  871. *
  872. * If you are concerned about the boot time, set up the static pins in
  873. * the bootloader, and only set up selected pins as device tree entries.
  874. */
  875. static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
  876. struct device_node *np,
  877. struct pinctrl_map **map,
  878. unsigned *num_maps,
  879. const char **pgnames)
  880. {
  881. const char *name = "pinctrl-single,pins";
  882. struct pcs_func_vals *vals;
  883. int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
  884. struct pcs_function *function = NULL;
  885. rows = pinctrl_count_index_with_args(np, name);
  886. if (rows <= 0) {
  887. dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
  888. return -EINVAL;
  889. }
  890. vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
  891. if (!vals)
  892. return -ENOMEM;
  893. pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
  894. if (!pins)
  895. goto free_vals;
  896. for (i = 0; i < rows; i++) {
  897. struct of_phandle_args pinctrl_spec;
  898. unsigned int offset;
  899. int pin;
  900. res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
  901. if (res)
  902. return res;
  903. if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
  904. dev_err(pcs->dev, "invalid args_count for spec: %i\n",
  905. pinctrl_spec.args_count);
  906. break;
  907. }
  908. offset = pinctrl_spec.args[0];
  909. vals[found].reg = pcs->base + offset;
  910. switch (pinctrl_spec.args_count) {
  911. case 2:
  912. vals[found].val = pinctrl_spec.args[1];
  913. break;
  914. case 3:
  915. vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
  916. break;
  917. }
  918. dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
  919. pinctrl_spec.np, offset, vals[found].val);
  920. pin = pcs_get_pin_by_offset(pcs, offset);
  921. if (pin < 0) {
  922. dev_err(pcs->dev,
  923. "could not add functions for %pOFn %ux\n",
  924. np, offset);
  925. break;
  926. }
  927. pins[found++] = pin;
  928. }
  929. pgnames[0] = np->name;
  930. mutex_lock(&pcs->mutex);
  931. fsel = pcs_add_function(pcs, &function, np->name, vals, found,
  932. pgnames, 1);
  933. if (fsel < 0) {
  934. res = fsel;
  935. goto free_pins;
  936. }
  937. gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
  938. if (gsel < 0) {
  939. res = gsel;
  940. goto free_function;
  941. }
  942. (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
  943. (*map)->data.mux.group = np->name;
  944. (*map)->data.mux.function = np->name;
  945. if (PCS_HAS_PINCONF && function) {
  946. res = pcs_parse_pinconf(pcs, np, function, map);
  947. if (res == 0)
  948. *num_maps = 2;
  949. else if (res == -ENOTSUPP)
  950. *num_maps = 1;
  951. else
  952. goto free_pingroups;
  953. } else {
  954. *num_maps = 1;
  955. }
  956. mutex_unlock(&pcs->mutex);
  957. return 0;
  958. free_pingroups:
  959. pinctrl_generic_remove_group(pcs->pctl, gsel);
  960. *num_maps = 1;
  961. free_function:
  962. pinmux_generic_remove_function(pcs->pctl, fsel);
  963. free_pins:
  964. mutex_unlock(&pcs->mutex);
  965. devm_kfree(pcs->dev, pins);
  966. free_vals:
  967. devm_kfree(pcs->dev, vals);
  968. return res;
  969. }
  970. static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
  971. struct device_node *np,
  972. struct pinctrl_map **map,
  973. unsigned *num_maps,
  974. const char **pgnames)
  975. {
  976. const char *name = "pinctrl-single,bits";
  977. struct pcs_func_vals *vals;
  978. int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
  979. int npins_in_row;
  980. struct pcs_function *function = NULL;
  981. rows = pinctrl_count_index_with_args(np, name);
  982. if (rows <= 0) {
  983. dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
  984. return -EINVAL;
  985. }
  986. npins_in_row = pcs->width / pcs->bits_per_pin;
  987. vals = devm_kzalloc(pcs->dev,
  988. array3_size(rows, npins_in_row, sizeof(*vals)),
  989. GFP_KERNEL);
  990. if (!vals)
  991. return -ENOMEM;
  992. pins = devm_kzalloc(pcs->dev,
  993. array3_size(rows, npins_in_row, sizeof(*pins)),
  994. GFP_KERNEL);
  995. if (!pins)
  996. goto free_vals;
  997. for (i = 0; i < rows; i++) {
  998. struct of_phandle_args pinctrl_spec;
  999. unsigned offset, val;
  1000. unsigned mask, bit_pos, val_pos, mask_pos, submask;
  1001. unsigned pin_num_from_lsb;
  1002. int pin;
  1003. res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
  1004. if (res)
  1005. return res;
  1006. if (pinctrl_spec.args_count < 3) {
  1007. dev_err(pcs->dev, "invalid args_count for spec: %i\n",
  1008. pinctrl_spec.args_count);
  1009. break;
  1010. }
  1011. /* Index plus two value cells */
  1012. offset = pinctrl_spec.args[0];
  1013. val = pinctrl_spec.args[1];
  1014. mask = pinctrl_spec.args[2];
  1015. dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
  1016. pinctrl_spec.np, offset, val, mask);
  1017. /* Parse pins in each row from LSB */
  1018. while (mask) {
  1019. bit_pos = __ffs(mask);
  1020. pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
  1021. mask_pos = ((pcs->fmask) << bit_pos);
  1022. val_pos = val & mask_pos;
  1023. submask = mask & mask_pos;
  1024. if ((mask & mask_pos) == 0) {
  1025. dev_err(pcs->dev,
  1026. "Invalid mask for %pOFn at 0x%x\n",
  1027. np, offset);
  1028. break;
  1029. }
  1030. mask &= ~mask_pos;
  1031. if (submask != mask_pos) {
  1032. dev_warn(pcs->dev,
  1033. "Invalid submask 0x%x for %pOFn at 0x%x\n",
  1034. submask, np, offset);
  1035. continue;
  1036. }
  1037. vals[found].mask = submask;
  1038. vals[found].reg = pcs->base + offset;
  1039. vals[found].val = val_pos;
  1040. pin = pcs_get_pin_by_offset(pcs, offset);
  1041. if (pin < 0) {
  1042. dev_err(pcs->dev,
  1043. "could not add functions for %pOFn %ux\n",
  1044. np, offset);
  1045. break;
  1046. }
  1047. pins[found++] = pin + pin_num_from_lsb;
  1048. }
  1049. }
  1050. pgnames[0] = np->name;
  1051. mutex_lock(&pcs->mutex);
  1052. fsel = pcs_add_function(pcs, &function, np->name, vals, found,
  1053. pgnames, 1);
  1054. if (fsel < 0) {
  1055. res = fsel;
  1056. goto free_pins;
  1057. }
  1058. gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
  1059. if (gsel < 0) {
  1060. res = gsel;
  1061. goto free_function;
  1062. }
  1063. (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
  1064. (*map)->data.mux.group = np->name;
  1065. (*map)->data.mux.function = np->name;
  1066. if (PCS_HAS_PINCONF) {
  1067. dev_err(pcs->dev, "pinconf not supported\n");
  1068. res = -ENOTSUPP;
  1069. goto free_pingroups;
  1070. }
  1071. *num_maps = 1;
  1072. mutex_unlock(&pcs->mutex);
  1073. return 0;
  1074. free_pingroups:
  1075. pinctrl_generic_remove_group(pcs->pctl, gsel);
  1076. *num_maps = 1;
  1077. free_function:
  1078. pinmux_generic_remove_function(pcs->pctl, fsel);
  1079. free_pins:
  1080. mutex_unlock(&pcs->mutex);
  1081. devm_kfree(pcs->dev, pins);
  1082. free_vals:
  1083. devm_kfree(pcs->dev, vals);
  1084. return res;
  1085. }
  1086. /**
  1087. * pcs_dt_node_to_map() - allocates and parses pinctrl maps
  1088. * @pctldev: pinctrl instance
  1089. * @np_config: device tree pinmux entry
  1090. * @map: array of map entries
  1091. * @num_maps: number of maps
  1092. */
  1093. static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
  1094. struct device_node *np_config,
  1095. struct pinctrl_map **map, unsigned *num_maps)
  1096. {
  1097. struct pcs_device *pcs;
  1098. const char **pgnames;
  1099. int ret;
  1100. pcs = pinctrl_dev_get_drvdata(pctldev);
  1101. /* create 2 maps. One is for pinmux, and the other is for pinconf. */
  1102. *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
  1103. if (!*map)
  1104. return -ENOMEM;
  1105. *num_maps = 0;
  1106. pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
  1107. if (!pgnames) {
  1108. ret = -ENOMEM;
  1109. goto free_map;
  1110. }
  1111. if (pcs->bits_per_mux) {
  1112. ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
  1113. num_maps, pgnames);
  1114. if (ret < 0) {
  1115. dev_err(pcs->dev, "no pins entries for %pOFn\n",
  1116. np_config);
  1117. goto free_pgnames;
  1118. }
  1119. } else {
  1120. ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
  1121. num_maps, pgnames);
  1122. if (ret < 0) {
  1123. dev_err(pcs->dev, "no pins entries for %pOFn\n",
  1124. np_config);
  1125. goto free_pgnames;
  1126. }
  1127. }
  1128. return 0;
  1129. free_pgnames:
  1130. devm_kfree(pcs->dev, pgnames);
  1131. free_map:
  1132. devm_kfree(pcs->dev, *map);
  1133. return ret;
  1134. }
  1135. /**
  1136. * pcs_irq_free() - free interrupt
  1137. * @pcs: pcs driver instance
  1138. */
  1139. static void pcs_irq_free(struct pcs_device *pcs)
  1140. {
  1141. struct pcs_soc_data *pcs_soc = &pcs->socdata;
  1142. if (pcs_soc->irq < 0)
  1143. return;
  1144. if (pcs->domain)
  1145. irq_domain_remove(pcs->domain);
  1146. if (PCS_QUIRK_HAS_SHARED_IRQ)
  1147. free_irq(pcs_soc->irq, pcs_soc);
  1148. else
  1149. irq_set_chained_handler(pcs_soc->irq, NULL);
  1150. }
  1151. /**
  1152. * pcs_free_resources() - free memory used by this driver
  1153. * @pcs: pcs driver instance
  1154. */
  1155. static void pcs_free_resources(struct pcs_device *pcs)
  1156. {
  1157. pcs_irq_free(pcs);
  1158. pinctrl_unregister(pcs->pctl);
  1159. #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
  1160. if (pcs->missing_nr_pinctrl_cells)
  1161. of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
  1162. #endif
  1163. }
  1164. static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
  1165. {
  1166. const char *propname = "pinctrl-single,gpio-range";
  1167. const char *cellname = "#pinctrl-single,gpio-range-cells";
  1168. struct of_phandle_args gpiospec;
  1169. struct pcs_gpiofunc_range *range;
  1170. int ret, i;
  1171. for (i = 0; ; i++) {
  1172. ret = of_parse_phandle_with_args(node, propname, cellname,
  1173. i, &gpiospec);
  1174. /* Do not treat it as error. Only treat it as end condition. */
  1175. if (ret) {
  1176. ret = 0;
  1177. break;
  1178. }
  1179. range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
  1180. if (!range) {
  1181. ret = -ENOMEM;
  1182. break;
  1183. }
  1184. range->offset = gpiospec.args[0];
  1185. range->npins = gpiospec.args[1];
  1186. range->gpiofunc = gpiospec.args[2];
  1187. mutex_lock(&pcs->mutex);
  1188. list_add_tail(&range->node, &pcs->gpiofuncs);
  1189. mutex_unlock(&pcs->mutex);
  1190. }
  1191. return ret;
  1192. }
  1193. /**
  1194. * struct pcs_interrupt
  1195. * @reg: virtual address of interrupt register
  1196. * @hwirq: hardware irq number
  1197. * @irq: virtual irq number
  1198. * @node: list node
  1199. */
  1200. struct pcs_interrupt {
  1201. void __iomem *reg;
  1202. irq_hw_number_t hwirq;
  1203. unsigned int irq;
  1204. struct list_head node;
  1205. };
  1206. /**
  1207. * pcs_irq_set() - enables or disables an interrupt
  1208. * @pcs_soc: SoC specific settings
  1209. * @irq: interrupt
  1210. * @enable: enable or disable the interrupt
  1211. *
  1212. * Note that this currently assumes one interrupt per pinctrl
  1213. * register that is typically used for wake-up events.
  1214. */
  1215. static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
  1216. int irq, const bool enable)
  1217. {
  1218. struct pcs_device *pcs;
  1219. struct list_head *pos;
  1220. unsigned mask;
  1221. pcs = container_of(pcs_soc, struct pcs_device, socdata);
  1222. list_for_each(pos, &pcs->irqs) {
  1223. struct pcs_interrupt *pcswi;
  1224. unsigned soc_mask;
  1225. pcswi = list_entry(pos, struct pcs_interrupt, node);
  1226. if (irq != pcswi->irq)
  1227. continue;
  1228. soc_mask = pcs_soc->irq_enable_mask;
  1229. raw_spin_lock(&pcs->lock);
  1230. mask = pcs->read(pcswi->reg);
  1231. if (enable)
  1232. mask |= soc_mask;
  1233. else
  1234. mask &= ~soc_mask;
  1235. pcs->write(mask, pcswi->reg);
  1236. /* flush posted write */
  1237. mask = pcs->read(pcswi->reg);
  1238. raw_spin_unlock(&pcs->lock);
  1239. }
  1240. if (pcs_soc->rearm)
  1241. pcs_soc->rearm();
  1242. }
  1243. /**
  1244. * pcs_irq_mask() - mask pinctrl interrupt
  1245. * @d: interrupt data
  1246. */
  1247. static void pcs_irq_mask(struct irq_data *d)
  1248. {
  1249. struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
  1250. pcs_irq_set(pcs_soc, d->irq, false);
  1251. }
  1252. /**
  1253. * pcs_irq_unmask() - unmask pinctrl interrupt
  1254. * @d: interrupt data
  1255. */
  1256. static void pcs_irq_unmask(struct irq_data *d)
  1257. {
  1258. struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
  1259. pcs_irq_set(pcs_soc, d->irq, true);
  1260. }
  1261. /**
  1262. * pcs_irq_set_wake() - toggle the suspend and resume wake up
  1263. * @d: interrupt data
  1264. * @state: wake-up state
  1265. *
  1266. * Note that this should be called only for suspend and resume.
  1267. * For runtime PM, the wake-up events should be enabled by default.
  1268. */
  1269. static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
  1270. {
  1271. if (state)
  1272. pcs_irq_unmask(d);
  1273. else
  1274. pcs_irq_mask(d);
  1275. return 0;
  1276. }
  1277. /**
  1278. * pcs_irq_handle() - common interrupt handler
  1279. * @pcs_soc: SoC specific settings
  1280. *
  1281. * Note that this currently assumes we have one interrupt bit per
  1282. * mux register. This interrupt is typically used for wake-up events.
  1283. * For more complex interrupts different handlers can be specified.
  1284. */
  1285. static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
  1286. {
  1287. struct pcs_device *pcs;
  1288. struct list_head *pos;
  1289. int count = 0;
  1290. pcs = container_of(pcs_soc, struct pcs_device, socdata);
  1291. list_for_each(pos, &pcs->irqs) {
  1292. struct pcs_interrupt *pcswi;
  1293. unsigned mask;
  1294. pcswi = list_entry(pos, struct pcs_interrupt, node);
  1295. raw_spin_lock(&pcs->lock);
  1296. mask = pcs->read(pcswi->reg);
  1297. raw_spin_unlock(&pcs->lock);
  1298. if (mask & pcs_soc->irq_status_mask) {
  1299. generic_handle_irq(irq_find_mapping(pcs->domain,
  1300. pcswi->hwirq));
  1301. count++;
  1302. }
  1303. }
  1304. return count;
  1305. }
  1306. /**
  1307. * pcs_irq_handler() - handler for the shared interrupt case
  1308. * @irq: interrupt
  1309. * @d: data
  1310. *
  1311. * Use this for cases where multiple instances of
  1312. * pinctrl-single share a single interrupt like on omaps.
  1313. */
  1314. static irqreturn_t pcs_irq_handler(int irq, void *d)
  1315. {
  1316. struct pcs_soc_data *pcs_soc = d;
  1317. return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
  1318. }
  1319. /**
  1320. * pcs_irq_handle() - handler for the dedicated chained interrupt case
  1321. * @desc: interrupt descriptor
  1322. *
  1323. * Use this if you have a separate interrupt for each
  1324. * pinctrl-single instance.
  1325. */
  1326. static void pcs_irq_chain_handler(struct irq_desc *desc)
  1327. {
  1328. struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
  1329. struct irq_chip *chip;
  1330. chip = irq_desc_get_chip(desc);
  1331. chained_irq_enter(chip, desc);
  1332. pcs_irq_handle(pcs_soc);
  1333. /* REVISIT: export and add handle_bad_irq(irq, desc)? */
  1334. chained_irq_exit(chip, desc);
  1335. }
  1336. static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
  1337. irq_hw_number_t hwirq)
  1338. {
  1339. struct pcs_soc_data *pcs_soc = d->host_data;
  1340. struct pcs_device *pcs;
  1341. struct pcs_interrupt *pcswi;
  1342. pcs = container_of(pcs_soc, struct pcs_device, socdata);
  1343. pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
  1344. if (!pcswi)
  1345. return -ENOMEM;
  1346. pcswi->reg = pcs->base + hwirq;
  1347. pcswi->hwirq = hwirq;
  1348. pcswi->irq = irq;
  1349. mutex_lock(&pcs->mutex);
  1350. list_add_tail(&pcswi->node, &pcs->irqs);
  1351. mutex_unlock(&pcs->mutex);
  1352. irq_set_chip_data(irq, pcs_soc);
  1353. irq_set_chip_and_handler(irq, &pcs->chip,
  1354. handle_level_irq);
  1355. irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
  1356. irq_set_noprobe(irq);
  1357. return 0;
  1358. }
  1359. static const struct irq_domain_ops pcs_irqdomain_ops = {
  1360. .map = pcs_irqdomain_map,
  1361. .xlate = irq_domain_xlate_onecell,
  1362. };
  1363. /**
  1364. * pcs_irq_init_chained_handler() - set up a chained interrupt handler
  1365. * @pcs: pcs driver instance
  1366. * @np: device node pointer
  1367. */
  1368. static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
  1369. struct device_node *np)
  1370. {
  1371. struct pcs_soc_data *pcs_soc = &pcs->socdata;
  1372. const char *name = "pinctrl";
  1373. int num_irqs;
  1374. if (!pcs_soc->irq_enable_mask ||
  1375. !pcs_soc->irq_status_mask) {
  1376. pcs_soc->irq = -1;
  1377. return -EINVAL;
  1378. }
  1379. INIT_LIST_HEAD(&pcs->irqs);
  1380. pcs->chip.name = name;
  1381. pcs->chip.irq_ack = pcs_irq_mask;
  1382. pcs->chip.irq_mask = pcs_irq_mask;
  1383. pcs->chip.irq_unmask = pcs_irq_unmask;
  1384. pcs->chip.irq_set_wake = pcs_irq_set_wake;
  1385. if (PCS_QUIRK_HAS_SHARED_IRQ) {
  1386. int res;
  1387. res = request_irq(pcs_soc->irq, pcs_irq_handler,
  1388. IRQF_SHARED | IRQF_NO_SUSPEND |
  1389. IRQF_NO_THREAD,
  1390. name, pcs_soc);
  1391. if (res) {
  1392. pcs_soc->irq = -1;
  1393. return res;
  1394. }
  1395. } else {
  1396. irq_set_chained_handler_and_data(pcs_soc->irq,
  1397. pcs_irq_chain_handler,
  1398. pcs_soc);
  1399. }
  1400. /*
  1401. * We can use the register offset as the hardirq
  1402. * number as irq_domain_add_simple maps them lazily.
  1403. * This way we can easily support more than one
  1404. * interrupt per function if needed.
  1405. */
  1406. num_irqs = pcs->size;
  1407. pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
  1408. &pcs_irqdomain_ops,
  1409. pcs_soc);
  1410. if (!pcs->domain) {
  1411. irq_set_chained_handler(pcs_soc->irq, NULL);
  1412. return -EINVAL;
  1413. }
  1414. return 0;
  1415. }
  1416. #ifdef CONFIG_PM
  1417. static int pcs_save_context(struct pcs_device *pcs)
  1418. {
  1419. int i, mux_bytes;
  1420. u64 *regsl;
  1421. u32 *regsw;
  1422. u16 *regshw;
  1423. mux_bytes = pcs->width / BITS_PER_BYTE;
  1424. if (!pcs->saved_vals) {
  1425. pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
  1426. if (!pcs->saved_vals)
  1427. return -ENOMEM;
  1428. }
  1429. switch (pcs->width) {
  1430. case 64:
  1431. regsl = pcs->saved_vals;
  1432. for (i = 0; i < pcs->size; i += mux_bytes)
  1433. *regsl++ = pcs->read(pcs->base + i);
  1434. break;
  1435. case 32:
  1436. regsw = pcs->saved_vals;
  1437. for (i = 0; i < pcs->size; i += mux_bytes)
  1438. *regsw++ = pcs->read(pcs->base + i);
  1439. break;
  1440. case 16:
  1441. regshw = pcs->saved_vals;
  1442. for (i = 0; i < pcs->size; i += mux_bytes)
  1443. *regshw++ = pcs->read(pcs->base + i);
  1444. break;
  1445. }
  1446. return 0;
  1447. }
  1448. static void pcs_restore_context(struct pcs_device *pcs)
  1449. {
  1450. int i, mux_bytes;
  1451. u64 *regsl;
  1452. u32 *regsw;
  1453. u16 *regshw;
  1454. mux_bytes = pcs->width / BITS_PER_BYTE;
  1455. switch (pcs->width) {
  1456. case 64:
  1457. regsl = pcs->saved_vals;
  1458. for (i = 0; i < pcs->size; i += mux_bytes)
  1459. pcs->write(*regsl++, pcs->base + i);
  1460. break;
  1461. case 32:
  1462. regsw = pcs->saved_vals;
  1463. for (i = 0; i < pcs->size; i += mux_bytes)
  1464. pcs->write(*regsw++, pcs->base + i);
  1465. break;
  1466. case 16:
  1467. regshw = pcs->saved_vals;
  1468. for (i = 0; i < pcs->size; i += mux_bytes)
  1469. pcs->write(*regshw++, pcs->base + i);
  1470. break;
  1471. }
  1472. }
  1473. static int pinctrl_single_suspend(struct platform_device *pdev,
  1474. pm_message_t state)
  1475. {
  1476. struct pcs_device *pcs;
  1477. pcs = platform_get_drvdata(pdev);
  1478. if (!pcs)
  1479. return -EINVAL;
  1480. if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
  1481. int ret;
  1482. ret = pcs_save_context(pcs);
  1483. if (ret < 0)
  1484. return ret;
  1485. }
  1486. return pinctrl_force_sleep(pcs->pctl);
  1487. }
  1488. static int pinctrl_single_resume(struct platform_device *pdev)
  1489. {
  1490. struct pcs_device *pcs;
  1491. pcs = platform_get_drvdata(pdev);
  1492. if (!pcs)
  1493. return -EINVAL;
  1494. if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
  1495. pcs_restore_context(pcs);
  1496. return pinctrl_force_default(pcs->pctl);
  1497. }
  1498. #endif
  1499. /**
  1500. * pcs_quirk_missing_pinctrl_cells - handle legacy binding
  1501. * @pcs: pinctrl driver instance
  1502. * @np: device tree node
  1503. * @cells: number of cells
  1504. *
  1505. * Handle legacy binding with no #pinctrl-cells. This should be
  1506. * always two pinctrl-single,bit-per-mux and one for others.
  1507. * At some point we may want to consider removing this.
  1508. */
  1509. static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
  1510. struct device_node *np,
  1511. int cells)
  1512. {
  1513. struct property *p;
  1514. const char *name = "#pinctrl-cells";
  1515. int error;
  1516. u32 val;
  1517. error = of_property_read_u32(np, name, &val);
  1518. if (!error)
  1519. return 0;
  1520. dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
  1521. name, cells);
  1522. p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
  1523. if (!p)
  1524. return -ENOMEM;
  1525. p->length = sizeof(__be32);
  1526. p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
  1527. if (!p->value)
  1528. return -ENOMEM;
  1529. *(__be32 *)p->value = cpu_to_be32(cells);
  1530. p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
  1531. if (!p->name)
  1532. return -ENOMEM;
  1533. pcs->missing_nr_pinctrl_cells = p;
  1534. #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
  1535. error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
  1536. #endif
  1537. return error;
  1538. }
  1539. static int pcs_probe(struct platform_device *pdev)
  1540. {
  1541. struct device_node *np = pdev->dev.of_node;
  1542. struct pcs_pdata *pdata;
  1543. struct resource *res;
  1544. struct pcs_device *pcs;
  1545. const struct pcs_soc_data *soc;
  1546. int ret;
  1547. soc = of_device_get_match_data(&pdev->dev);
  1548. if (WARN_ON(!soc))
  1549. return -EINVAL;
  1550. pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
  1551. if (!pcs)
  1552. return -ENOMEM;
  1553. pcs->dev = &pdev->dev;
  1554. pcs->np = np;
  1555. raw_spin_lock_init(&pcs->lock);
  1556. mutex_init(&pcs->mutex);
  1557. INIT_LIST_HEAD(&pcs->gpiofuncs);
  1558. pcs->flags = soc->flags;
  1559. memcpy(&pcs->socdata, soc, sizeof(*soc));
  1560. ret = of_property_read_u32(np, "pinctrl-single,register-width",
  1561. &pcs->width);
  1562. if (ret) {
  1563. dev_err(pcs->dev, "register width not specified\n");
  1564. return ret;
  1565. }
  1566. ret = of_property_read_u32(np, "pinctrl-single,function-mask",
  1567. &pcs->fmask);
  1568. if (!ret) {
  1569. pcs->fshift = __ffs(pcs->fmask);
  1570. pcs->fmax = pcs->fmask >> pcs->fshift;
  1571. } else {
  1572. /* If mask property doesn't exist, function mux is invalid. */
  1573. pcs->fmask = 0;
  1574. pcs->fshift = 0;
  1575. pcs->fmax = 0;
  1576. }
  1577. ret = of_property_read_u32(np, "pinctrl-single,function-off",
  1578. &pcs->foff);
  1579. if (ret)
  1580. pcs->foff = PCS_OFF_DISABLED;
  1581. pcs->bits_per_mux = of_property_read_bool(np,
  1582. "pinctrl-single,bit-per-mux");
  1583. ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
  1584. pcs->bits_per_mux ? 2 : 1);
  1585. if (ret) {
  1586. dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
  1587. return ret;
  1588. }
  1589. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1590. if (!res) {
  1591. dev_err(pcs->dev, "could not get resource\n");
  1592. return -ENODEV;
  1593. }
  1594. pcs->res = devm_request_mem_region(pcs->dev, res->start,
  1595. resource_size(res), DRIVER_NAME);
  1596. if (!pcs->res) {
  1597. dev_err(pcs->dev, "could not get mem_region\n");
  1598. return -EBUSY;
  1599. }
  1600. pcs->size = resource_size(pcs->res);
  1601. pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
  1602. if (!pcs->base) {
  1603. dev_err(pcs->dev, "could not ioremap\n");
  1604. return -ENODEV;
  1605. }
  1606. platform_set_drvdata(pdev, pcs);
  1607. switch (pcs->width) {
  1608. case 8:
  1609. pcs->read = pcs_readb;
  1610. pcs->write = pcs_writeb;
  1611. break;
  1612. case 16:
  1613. pcs->read = pcs_readw;
  1614. pcs->write = pcs_writew;
  1615. break;
  1616. case 32:
  1617. pcs->read = pcs_readl;
  1618. pcs->write = pcs_writel;
  1619. break;
  1620. default:
  1621. break;
  1622. }
  1623. pcs->desc.name = DRIVER_NAME;
  1624. pcs->desc.pctlops = &pcs_pinctrl_ops;
  1625. pcs->desc.pmxops = &pcs_pinmux_ops;
  1626. if (PCS_HAS_PINCONF)
  1627. pcs->desc.confops = &pcs_pinconf_ops;
  1628. pcs->desc.owner = THIS_MODULE;
  1629. ret = pcs_allocate_pin_table(pcs);
  1630. if (ret < 0)
  1631. goto free;
  1632. ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
  1633. if (ret) {
  1634. dev_err(pcs->dev, "could not register single pinctrl driver\n");
  1635. goto free;
  1636. }
  1637. ret = pcs_add_gpio_func(np, pcs);
  1638. if (ret < 0)
  1639. goto free;
  1640. pcs->socdata.irq = irq_of_parse_and_map(np, 0);
  1641. if (pcs->socdata.irq)
  1642. pcs->flags |= PCS_FEAT_IRQ;
  1643. /* We still need auxdata for some omaps for PRM interrupts */
  1644. pdata = dev_get_platdata(&pdev->dev);
  1645. if (pdata) {
  1646. if (pdata->rearm)
  1647. pcs->socdata.rearm = pdata->rearm;
  1648. if (pdata->irq) {
  1649. pcs->socdata.irq = pdata->irq;
  1650. pcs->flags |= PCS_FEAT_IRQ;
  1651. }
  1652. }
  1653. if (PCS_HAS_IRQ) {
  1654. ret = pcs_irq_init_chained_handler(pcs, np);
  1655. if (ret < 0)
  1656. dev_warn(pcs->dev, "initialized with no interrupts\n");
  1657. }
  1658. dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
  1659. return pinctrl_enable(pcs->pctl);
  1660. free:
  1661. pcs_free_resources(pcs);
  1662. return ret;
  1663. }
  1664. static int pcs_remove(struct platform_device *pdev)
  1665. {
  1666. struct pcs_device *pcs = platform_get_drvdata(pdev);
  1667. if (!pcs)
  1668. return 0;
  1669. pcs_free_resources(pcs);
  1670. return 0;
  1671. }
  1672. static const struct pcs_soc_data pinctrl_single_omap_wkup = {
  1673. .flags = PCS_QUIRK_SHARED_IRQ,
  1674. .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
  1675. .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
  1676. };
  1677. static const struct pcs_soc_data pinctrl_single_dra7 = {
  1678. .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
  1679. .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
  1680. };
  1681. static const struct pcs_soc_data pinctrl_single_am437x = {
  1682. .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
  1683. .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
  1684. .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
  1685. };
  1686. static const struct pcs_soc_data pinctrl_single = {
  1687. };
  1688. static const struct pcs_soc_data pinconf_single = {
  1689. .flags = PCS_FEAT_PINCONF,
  1690. };
  1691. static const struct of_device_id pcs_of_match[] = {
  1692. { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
  1693. { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
  1694. { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
  1695. { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
  1696. { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
  1697. { .compatible = "pinctrl-single", .data = &pinctrl_single },
  1698. { .compatible = "pinconf-single", .data = &pinconf_single },
  1699. { },
  1700. };
  1701. MODULE_DEVICE_TABLE(of, pcs_of_match);
  1702. static struct platform_driver pcs_driver = {
  1703. .probe = pcs_probe,
  1704. .remove = pcs_remove,
  1705. .driver = {
  1706. .name = DRIVER_NAME,
  1707. .of_match_table = pcs_of_match,
  1708. },
  1709. #ifdef CONFIG_PM
  1710. .suspend = pinctrl_single_suspend,
  1711. .resume = pinctrl_single_resume,
  1712. #endif
  1713. };
  1714. module_platform_driver(pcs_driver);
  1715. MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
  1716. MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
  1717. MODULE_LICENSE("GPL v2");