pinctrl-rockchip.c 103 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Pinctrl driver for Rockchip SoCs
  4. *
  5. * Copyright (c) 2013 MundoReader S.L.
  6. * Author: Heiko Stuebner <heiko@sntech.de>
  7. *
  8. * With some ideas taken from pinctrl-samsung:
  9. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10. * http://www.samsung.com
  11. * Copyright (c) 2012 Linaro Ltd
  12. * https://www.linaro.org
  13. *
  14. * and pinctrl-at91:
  15. * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16. */
  17. #include <linux/init.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/io.h>
  20. #include <linux/bitops.h>
  21. #include <linux/gpio/driver.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/pinctrl/machine.h>
  25. #include <linux/pinctrl/pinconf.h>
  26. #include <linux/pinctrl/pinctrl.h>
  27. #include <linux/pinctrl/pinmux.h>
  28. #include <linux/pinctrl/pinconf-generic.h>
  29. #include <linux/irqchip/chained_irq.h>
  30. #include <linux/clk.h>
  31. #include <linux/regmap.h>
  32. #include <linux/mfd/syscon.h>
  33. #include <dt-bindings/pinctrl/rockchip.h>
  34. #include "core.h"
  35. #include "pinconf.h"
  36. /* GPIO control registers */
  37. #define GPIO_SWPORT_DR 0x00
  38. #define GPIO_SWPORT_DDR 0x04
  39. #define GPIO_INTEN 0x30
  40. #define GPIO_INTMASK 0x34
  41. #define GPIO_INTTYPE_LEVEL 0x38
  42. #define GPIO_INT_POLARITY 0x3c
  43. #define GPIO_INT_STATUS 0x40
  44. #define GPIO_INT_RAWSTATUS 0x44
  45. #define GPIO_DEBOUNCE 0x48
  46. #define GPIO_PORTS_EOI 0x4c
  47. #define GPIO_EXT_PORT 0x50
  48. #define GPIO_LS_SYNC 0x60
  49. enum rockchip_pinctrl_type {
  50. PX30,
  51. RV1108,
  52. RK2928,
  53. RK3066B,
  54. RK3128,
  55. RK3188,
  56. RK3288,
  57. RK3308,
  58. RK3368,
  59. RK3399,
  60. };
  61. /*
  62. * Encode variants of iomux registers into a type variable
  63. */
  64. #define IOMUX_GPIO_ONLY BIT(0)
  65. #define IOMUX_WIDTH_4BIT BIT(1)
  66. #define IOMUX_SOURCE_PMU BIT(2)
  67. #define IOMUX_UNROUTED BIT(3)
  68. #define IOMUX_WIDTH_3BIT BIT(4)
  69. #define IOMUX_WIDTH_2BIT BIT(5)
  70. /**
  71. * struct rockchip_iomux
  72. * @type: iomux variant using IOMUX_* constants
  73. * @offset: if initialized to -1 it will be autocalculated, by specifying
  74. * an initial offset value the relevant source offset can be reset
  75. * to a new value for autocalculating the following iomux registers.
  76. */
  77. struct rockchip_iomux {
  78. int type;
  79. int offset;
  80. };
  81. /*
  82. * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  83. */
  84. enum rockchip_pin_drv_type {
  85. DRV_TYPE_IO_DEFAULT = 0,
  86. DRV_TYPE_IO_1V8_OR_3V0,
  87. DRV_TYPE_IO_1V8_ONLY,
  88. DRV_TYPE_IO_1V8_3V0_AUTO,
  89. DRV_TYPE_IO_3V3_ONLY,
  90. DRV_TYPE_MAX
  91. };
  92. /*
  93. * enum type index corresponding to rockchip_pull_list arrays index.
  94. */
  95. enum rockchip_pin_pull_type {
  96. PULL_TYPE_IO_DEFAULT = 0,
  97. PULL_TYPE_IO_1V8_ONLY,
  98. PULL_TYPE_MAX
  99. };
  100. /**
  101. * struct rockchip_drv
  102. * @drv_type: drive strength variant using rockchip_perpin_drv_type
  103. * @offset: if initialized to -1 it will be autocalculated, by specifying
  104. * an initial offset value the relevant source offset can be reset
  105. * to a new value for autocalculating the following drive strength
  106. * registers. if used chips own cal_drv func instead to calculate
  107. * registers offset, the variant could be ignored.
  108. */
  109. struct rockchip_drv {
  110. enum rockchip_pin_drv_type drv_type;
  111. int offset;
  112. };
  113. /**
  114. * struct rockchip_pin_bank
  115. * @reg_base: register base of the gpio bank
  116. * @regmap_pull: optional separate register for additional pull settings
  117. * @clk: clock of the gpio bank
  118. * @irq: interrupt of the gpio bank
  119. * @saved_masks: Saved content of GPIO_INTEN at suspend time.
  120. * @pin_base: first pin number
  121. * @nr_pins: number of pins in this bank
  122. * @name: name of the bank
  123. * @bank_num: number of the bank, to account for holes
  124. * @iomux: array describing the 4 iomux sources of the bank
  125. * @drv: array describing the 4 drive strength sources of the bank
  126. * @pull_type: array describing the 4 pull type sources of the bank
  127. * @valid: is all necessary information present
  128. * @of_node: dt node of this bank
  129. * @drvdata: common pinctrl basedata
  130. * @domain: irqdomain of the gpio bank
  131. * @gpio_chip: gpiolib chip
  132. * @grange: gpio range
  133. * @slock: spinlock for the gpio bank
  134. * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
  135. * @recalced_mask: bit mask to indicate a need to recalulate the mask
  136. * @route_mask: bits describing the routing pins of per bank
  137. */
  138. struct rockchip_pin_bank {
  139. void __iomem *reg_base;
  140. struct regmap *regmap_pull;
  141. struct clk *clk;
  142. int irq;
  143. u32 saved_masks;
  144. u32 pin_base;
  145. u8 nr_pins;
  146. char *name;
  147. u8 bank_num;
  148. struct rockchip_iomux iomux[4];
  149. struct rockchip_drv drv[4];
  150. enum rockchip_pin_pull_type pull_type[4];
  151. bool valid;
  152. struct device_node *of_node;
  153. struct rockchip_pinctrl *drvdata;
  154. struct irq_domain *domain;
  155. struct gpio_chip gpio_chip;
  156. struct pinctrl_gpio_range grange;
  157. raw_spinlock_t slock;
  158. u32 toggle_edge_mode;
  159. u32 recalced_mask;
  160. u32 route_mask;
  161. };
  162. #define PIN_BANK(id, pins, label) \
  163. { \
  164. .bank_num = id, \
  165. .nr_pins = pins, \
  166. .name = label, \
  167. .iomux = { \
  168. { .offset = -1 }, \
  169. { .offset = -1 }, \
  170. { .offset = -1 }, \
  171. { .offset = -1 }, \
  172. }, \
  173. }
  174. #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
  175. { \
  176. .bank_num = id, \
  177. .nr_pins = pins, \
  178. .name = label, \
  179. .iomux = { \
  180. { .type = iom0, .offset = -1 }, \
  181. { .type = iom1, .offset = -1 }, \
  182. { .type = iom2, .offset = -1 }, \
  183. { .type = iom3, .offset = -1 }, \
  184. }, \
  185. }
  186. #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
  187. { \
  188. .bank_num = id, \
  189. .nr_pins = pins, \
  190. .name = label, \
  191. .iomux = { \
  192. { .offset = -1 }, \
  193. { .offset = -1 }, \
  194. { .offset = -1 }, \
  195. { .offset = -1 }, \
  196. }, \
  197. .drv = { \
  198. { .drv_type = type0, .offset = -1 }, \
  199. { .drv_type = type1, .offset = -1 }, \
  200. { .drv_type = type2, .offset = -1 }, \
  201. { .drv_type = type3, .offset = -1 }, \
  202. }, \
  203. }
  204. #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
  205. drv2, drv3, pull0, pull1, \
  206. pull2, pull3) \
  207. { \
  208. .bank_num = id, \
  209. .nr_pins = pins, \
  210. .name = label, \
  211. .iomux = { \
  212. { .offset = -1 }, \
  213. { .offset = -1 }, \
  214. { .offset = -1 }, \
  215. { .offset = -1 }, \
  216. }, \
  217. .drv = { \
  218. { .drv_type = drv0, .offset = -1 }, \
  219. { .drv_type = drv1, .offset = -1 }, \
  220. { .drv_type = drv2, .offset = -1 }, \
  221. { .drv_type = drv3, .offset = -1 }, \
  222. }, \
  223. .pull_type[0] = pull0, \
  224. .pull_type[1] = pull1, \
  225. .pull_type[2] = pull2, \
  226. .pull_type[3] = pull3, \
  227. }
  228. #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
  229. iom2, iom3, drv0, drv1, drv2, \
  230. drv3, offset0, offset1, \
  231. offset2, offset3) \
  232. { \
  233. .bank_num = id, \
  234. .nr_pins = pins, \
  235. .name = label, \
  236. .iomux = { \
  237. { .type = iom0, .offset = -1 }, \
  238. { .type = iom1, .offset = -1 }, \
  239. { .type = iom2, .offset = -1 }, \
  240. { .type = iom3, .offset = -1 }, \
  241. }, \
  242. .drv = { \
  243. { .drv_type = drv0, .offset = offset0 }, \
  244. { .drv_type = drv1, .offset = offset1 }, \
  245. { .drv_type = drv2, .offset = offset2 }, \
  246. { .drv_type = drv3, .offset = offset3 }, \
  247. }, \
  248. }
  249. #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
  250. label, iom0, iom1, iom2, \
  251. iom3, drv0, drv1, drv2, \
  252. drv3, offset0, offset1, \
  253. offset2, offset3, pull0, \
  254. pull1, pull2, pull3) \
  255. { \
  256. .bank_num = id, \
  257. .nr_pins = pins, \
  258. .name = label, \
  259. .iomux = { \
  260. { .type = iom0, .offset = -1 }, \
  261. { .type = iom1, .offset = -1 }, \
  262. { .type = iom2, .offset = -1 }, \
  263. { .type = iom3, .offset = -1 }, \
  264. }, \
  265. .drv = { \
  266. { .drv_type = drv0, .offset = offset0 }, \
  267. { .drv_type = drv1, .offset = offset1 }, \
  268. { .drv_type = drv2, .offset = offset2 }, \
  269. { .drv_type = drv3, .offset = offset3 }, \
  270. }, \
  271. .pull_type[0] = pull0, \
  272. .pull_type[1] = pull1, \
  273. .pull_type[2] = pull2, \
  274. .pull_type[3] = pull3, \
  275. }
  276. /**
  277. * struct rockchip_mux_recalced_data: represent a pin iomux data.
  278. * @num: bank number.
  279. * @pin: pin number.
  280. * @bit: index at register.
  281. * @reg: register offset.
  282. * @mask: mask bit
  283. */
  284. struct rockchip_mux_recalced_data {
  285. u8 num;
  286. u8 pin;
  287. u32 reg;
  288. u8 bit;
  289. u8 mask;
  290. };
  291. enum rockchip_mux_route_location {
  292. ROCKCHIP_ROUTE_SAME = 0,
  293. ROCKCHIP_ROUTE_PMU,
  294. ROCKCHIP_ROUTE_GRF,
  295. };
  296. /**
  297. * struct rockchip_mux_recalced_data: represent a pin iomux data.
  298. * @bank_num: bank number.
  299. * @pin: index at register or used to calc index.
  300. * @func: the min pin.
  301. * @route_location: the mux route location (same, pmu, grf).
  302. * @route_offset: the max pin.
  303. * @route_val: the register offset.
  304. */
  305. struct rockchip_mux_route_data {
  306. u8 bank_num;
  307. u8 pin;
  308. u8 func;
  309. enum rockchip_mux_route_location route_location;
  310. u32 route_offset;
  311. u32 route_val;
  312. };
  313. struct rockchip_pin_ctrl {
  314. struct rockchip_pin_bank *pin_banks;
  315. u32 nr_banks;
  316. u32 nr_pins;
  317. char *label;
  318. enum rockchip_pinctrl_type type;
  319. int grf_mux_offset;
  320. int pmu_mux_offset;
  321. int grf_drv_offset;
  322. int pmu_drv_offset;
  323. struct rockchip_mux_recalced_data *iomux_recalced;
  324. u32 niomux_recalced;
  325. struct rockchip_mux_route_data *iomux_routes;
  326. u32 niomux_routes;
  327. void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
  328. int pin_num, struct regmap **regmap,
  329. int *reg, u8 *bit);
  330. void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
  331. int pin_num, struct regmap **regmap,
  332. int *reg, u8 *bit);
  333. int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
  334. int pin_num, struct regmap **regmap,
  335. int *reg, u8 *bit);
  336. };
  337. struct rockchip_pin_config {
  338. unsigned int func;
  339. unsigned long *configs;
  340. unsigned int nconfigs;
  341. };
  342. /**
  343. * struct rockchip_pin_group: represent group of pins of a pinmux function.
  344. * @name: name of the pin group, used to lookup the group.
  345. * @pins: the pins included in this group.
  346. * @npins: number of pins included in this group.
  347. * @data: local pin configuration
  348. */
  349. struct rockchip_pin_group {
  350. const char *name;
  351. unsigned int npins;
  352. unsigned int *pins;
  353. struct rockchip_pin_config *data;
  354. };
  355. /**
  356. * struct rockchip_pmx_func: represent a pin function.
  357. * @name: name of the pin function, used to lookup the function.
  358. * @groups: one or more names of pin groups that provide this function.
  359. * @ngroups: number of groups included in @groups.
  360. */
  361. struct rockchip_pmx_func {
  362. const char *name;
  363. const char **groups;
  364. u8 ngroups;
  365. };
  366. struct rockchip_pinctrl {
  367. struct regmap *regmap_base;
  368. int reg_size;
  369. struct regmap *regmap_pull;
  370. struct regmap *regmap_pmu;
  371. struct device *dev;
  372. struct rockchip_pin_ctrl *ctrl;
  373. struct pinctrl_desc pctl;
  374. struct pinctrl_dev *pctl_dev;
  375. struct rockchip_pin_group *groups;
  376. unsigned int ngroups;
  377. struct rockchip_pmx_func *functions;
  378. unsigned int nfunctions;
  379. };
  380. static struct regmap_config rockchip_regmap_config = {
  381. .reg_bits = 32,
  382. .val_bits = 32,
  383. .reg_stride = 4,
  384. };
  385. static inline const struct rockchip_pin_group *pinctrl_name_to_group(
  386. const struct rockchip_pinctrl *info,
  387. const char *name)
  388. {
  389. int i;
  390. for (i = 0; i < info->ngroups; i++) {
  391. if (!strcmp(info->groups[i].name, name))
  392. return &info->groups[i];
  393. }
  394. return NULL;
  395. }
  396. /*
  397. * given a pin number that is local to a pin controller, find out the pin bank
  398. * and the register base of the pin bank.
  399. */
  400. static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
  401. unsigned pin)
  402. {
  403. struct rockchip_pin_bank *b = info->ctrl->pin_banks;
  404. while (pin >= (b->pin_base + b->nr_pins))
  405. b++;
  406. return b;
  407. }
  408. static struct rockchip_pin_bank *bank_num_to_bank(
  409. struct rockchip_pinctrl *info,
  410. unsigned num)
  411. {
  412. struct rockchip_pin_bank *b = info->ctrl->pin_banks;
  413. int i;
  414. for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
  415. if (b->bank_num == num)
  416. return b;
  417. }
  418. return ERR_PTR(-EINVAL);
  419. }
  420. /*
  421. * Pinctrl_ops handling
  422. */
  423. static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
  424. {
  425. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  426. return info->ngroups;
  427. }
  428. static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
  429. unsigned selector)
  430. {
  431. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  432. return info->groups[selector].name;
  433. }
  434. static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
  435. unsigned selector, const unsigned **pins,
  436. unsigned *npins)
  437. {
  438. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  439. if (selector >= info->ngroups)
  440. return -EINVAL;
  441. *pins = info->groups[selector].pins;
  442. *npins = info->groups[selector].npins;
  443. return 0;
  444. }
  445. static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
  446. struct device_node *np,
  447. struct pinctrl_map **map, unsigned *num_maps)
  448. {
  449. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  450. const struct rockchip_pin_group *grp;
  451. struct pinctrl_map *new_map;
  452. struct device_node *parent;
  453. int map_num = 1;
  454. int i;
  455. /*
  456. * first find the group of this node and check if we need to create
  457. * config maps for pins
  458. */
  459. grp = pinctrl_name_to_group(info, np->name);
  460. if (!grp) {
  461. dev_err(info->dev, "unable to find group for node %pOFn\n",
  462. np);
  463. return -EINVAL;
  464. }
  465. map_num += grp->npins;
  466. new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
  467. if (!new_map)
  468. return -ENOMEM;
  469. *map = new_map;
  470. *num_maps = map_num;
  471. /* create mux map */
  472. parent = of_get_parent(np);
  473. if (!parent) {
  474. kfree(new_map);
  475. return -EINVAL;
  476. }
  477. new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
  478. new_map[0].data.mux.function = parent->name;
  479. new_map[0].data.mux.group = np->name;
  480. of_node_put(parent);
  481. /* create config map */
  482. new_map++;
  483. for (i = 0; i < grp->npins; i++) {
  484. new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
  485. new_map[i].data.configs.group_or_pin =
  486. pin_get_name(pctldev, grp->pins[i]);
  487. new_map[i].data.configs.configs = grp->data[i].configs;
  488. new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
  489. }
  490. dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
  491. (*map)->data.mux.function, (*map)->data.mux.group, map_num);
  492. return 0;
  493. }
  494. static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
  495. struct pinctrl_map *map, unsigned num_maps)
  496. {
  497. kfree(map);
  498. }
  499. static const struct pinctrl_ops rockchip_pctrl_ops = {
  500. .get_groups_count = rockchip_get_groups_count,
  501. .get_group_name = rockchip_get_group_name,
  502. .get_group_pins = rockchip_get_group_pins,
  503. .dt_node_to_map = rockchip_dt_node_to_map,
  504. .dt_free_map = rockchip_dt_free_map,
  505. };
  506. /*
  507. * Hardware access
  508. */
  509. static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
  510. {
  511. .num = 1,
  512. .pin = 0,
  513. .reg = 0x418,
  514. .bit = 0,
  515. .mask = 0x3
  516. }, {
  517. .num = 1,
  518. .pin = 1,
  519. .reg = 0x418,
  520. .bit = 2,
  521. .mask = 0x3
  522. }, {
  523. .num = 1,
  524. .pin = 2,
  525. .reg = 0x418,
  526. .bit = 4,
  527. .mask = 0x3
  528. }, {
  529. .num = 1,
  530. .pin = 3,
  531. .reg = 0x418,
  532. .bit = 6,
  533. .mask = 0x3
  534. }, {
  535. .num = 1,
  536. .pin = 4,
  537. .reg = 0x418,
  538. .bit = 8,
  539. .mask = 0x3
  540. }, {
  541. .num = 1,
  542. .pin = 5,
  543. .reg = 0x418,
  544. .bit = 10,
  545. .mask = 0x3
  546. }, {
  547. .num = 1,
  548. .pin = 6,
  549. .reg = 0x418,
  550. .bit = 12,
  551. .mask = 0x3
  552. }, {
  553. .num = 1,
  554. .pin = 7,
  555. .reg = 0x418,
  556. .bit = 14,
  557. .mask = 0x3
  558. }, {
  559. .num = 1,
  560. .pin = 8,
  561. .reg = 0x41c,
  562. .bit = 0,
  563. .mask = 0x3
  564. }, {
  565. .num = 1,
  566. .pin = 9,
  567. .reg = 0x41c,
  568. .bit = 2,
  569. .mask = 0x3
  570. },
  571. };
  572. static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
  573. {
  574. .num = 2,
  575. .pin = 20,
  576. .reg = 0xe8,
  577. .bit = 0,
  578. .mask = 0x7
  579. }, {
  580. .num = 2,
  581. .pin = 21,
  582. .reg = 0xe8,
  583. .bit = 4,
  584. .mask = 0x7
  585. }, {
  586. .num = 2,
  587. .pin = 22,
  588. .reg = 0xe8,
  589. .bit = 8,
  590. .mask = 0x7
  591. }, {
  592. .num = 2,
  593. .pin = 23,
  594. .reg = 0xe8,
  595. .bit = 12,
  596. .mask = 0x7
  597. }, {
  598. .num = 2,
  599. .pin = 24,
  600. .reg = 0xd4,
  601. .bit = 12,
  602. .mask = 0x7
  603. },
  604. };
  605. static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
  606. {
  607. .num = 1,
  608. .pin = 14,
  609. .reg = 0x28,
  610. .bit = 12,
  611. .mask = 0xf
  612. }, {
  613. .num = 1,
  614. .pin = 15,
  615. .reg = 0x2c,
  616. .bit = 0,
  617. .mask = 0x3
  618. }, {
  619. .num = 1,
  620. .pin = 18,
  621. .reg = 0x30,
  622. .bit = 4,
  623. .mask = 0xf
  624. }, {
  625. .num = 1,
  626. .pin = 19,
  627. .reg = 0x30,
  628. .bit = 8,
  629. .mask = 0xf
  630. }, {
  631. .num = 1,
  632. .pin = 20,
  633. .reg = 0x30,
  634. .bit = 12,
  635. .mask = 0xf
  636. }, {
  637. .num = 1,
  638. .pin = 21,
  639. .reg = 0x34,
  640. .bit = 0,
  641. .mask = 0xf
  642. }, {
  643. .num = 1,
  644. .pin = 22,
  645. .reg = 0x34,
  646. .bit = 4,
  647. .mask = 0xf
  648. }, {
  649. .num = 1,
  650. .pin = 23,
  651. .reg = 0x34,
  652. .bit = 8,
  653. .mask = 0xf
  654. }, {
  655. .num = 3,
  656. .pin = 12,
  657. .reg = 0x68,
  658. .bit = 8,
  659. .mask = 0xf
  660. }, {
  661. .num = 3,
  662. .pin = 13,
  663. .reg = 0x68,
  664. .bit = 12,
  665. .mask = 0xf
  666. }, {
  667. .num = 2,
  668. .pin = 2,
  669. .reg = 0x608,
  670. .bit = 0,
  671. .mask = 0x7
  672. }, {
  673. .num = 2,
  674. .pin = 3,
  675. .reg = 0x608,
  676. .bit = 4,
  677. .mask = 0x7
  678. }, {
  679. .num = 2,
  680. .pin = 16,
  681. .reg = 0x610,
  682. .bit = 8,
  683. .mask = 0x7
  684. }, {
  685. .num = 3,
  686. .pin = 10,
  687. .reg = 0x610,
  688. .bit = 0,
  689. .mask = 0x7
  690. }, {
  691. .num = 3,
  692. .pin = 11,
  693. .reg = 0x610,
  694. .bit = 4,
  695. .mask = 0x7
  696. },
  697. };
  698. static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
  699. {
  700. .num = 2,
  701. .pin = 12,
  702. .reg = 0x24,
  703. .bit = 8,
  704. .mask = 0x3
  705. }, {
  706. .num = 2,
  707. .pin = 15,
  708. .reg = 0x28,
  709. .bit = 0,
  710. .mask = 0x7
  711. }, {
  712. .num = 2,
  713. .pin = 23,
  714. .reg = 0x30,
  715. .bit = 14,
  716. .mask = 0x3
  717. },
  718. };
  719. static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
  720. int *reg, u8 *bit, int *mask)
  721. {
  722. struct rockchip_pinctrl *info = bank->drvdata;
  723. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  724. struct rockchip_mux_recalced_data *data;
  725. int i;
  726. for (i = 0; i < ctrl->niomux_recalced; i++) {
  727. data = &ctrl->iomux_recalced[i];
  728. if (data->num == bank->bank_num &&
  729. data->pin == pin)
  730. break;
  731. }
  732. if (i >= ctrl->niomux_recalced)
  733. return;
  734. *reg = data->reg;
  735. *mask = data->mask;
  736. *bit = data->bit;
  737. }
  738. static struct rockchip_mux_route_data px30_mux_route_data[] = {
  739. {
  740. /* cif-d2m0 */
  741. .bank_num = 2,
  742. .pin = 0,
  743. .func = 1,
  744. .route_offset = 0x184,
  745. .route_val = BIT(16 + 7),
  746. }, {
  747. /* cif-d2m1 */
  748. .bank_num = 3,
  749. .pin = 3,
  750. .func = 3,
  751. .route_offset = 0x184,
  752. .route_val = BIT(16 + 7) | BIT(7),
  753. }, {
  754. /* pdm-m0 */
  755. .bank_num = 3,
  756. .pin = 22,
  757. .func = 2,
  758. .route_offset = 0x184,
  759. .route_val = BIT(16 + 8),
  760. }, {
  761. /* pdm-m1 */
  762. .bank_num = 2,
  763. .pin = 22,
  764. .func = 1,
  765. .route_offset = 0x184,
  766. .route_val = BIT(16 + 8) | BIT(8),
  767. }, {
  768. /* uart2-rxm0 */
  769. .bank_num = 1,
  770. .pin = 27,
  771. .func = 2,
  772. .route_offset = 0x184,
  773. .route_val = BIT(16 + 10),
  774. }, {
  775. /* uart2-rxm1 */
  776. .bank_num = 2,
  777. .pin = 14,
  778. .func = 2,
  779. .route_offset = 0x184,
  780. .route_val = BIT(16 + 10) | BIT(10),
  781. }, {
  782. /* uart3-rxm0 */
  783. .bank_num = 0,
  784. .pin = 17,
  785. .func = 2,
  786. .route_offset = 0x184,
  787. .route_val = BIT(16 + 9),
  788. }, {
  789. /* uart3-rxm1 */
  790. .bank_num = 1,
  791. .pin = 15,
  792. .func = 2,
  793. .route_offset = 0x184,
  794. .route_val = BIT(16 + 9) | BIT(9),
  795. },
  796. };
  797. static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
  798. {
  799. /* spi-0 */
  800. .bank_num = 1,
  801. .pin = 10,
  802. .func = 1,
  803. .route_offset = 0x144,
  804. .route_val = BIT(16 + 3) | BIT(16 + 4),
  805. }, {
  806. /* spi-1 */
  807. .bank_num = 1,
  808. .pin = 27,
  809. .func = 3,
  810. .route_offset = 0x144,
  811. .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
  812. }, {
  813. /* spi-2 */
  814. .bank_num = 0,
  815. .pin = 13,
  816. .func = 2,
  817. .route_offset = 0x144,
  818. .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
  819. }, {
  820. /* i2s-0 */
  821. .bank_num = 1,
  822. .pin = 5,
  823. .func = 1,
  824. .route_offset = 0x144,
  825. .route_val = BIT(16 + 5),
  826. }, {
  827. /* i2s-1 */
  828. .bank_num = 0,
  829. .pin = 14,
  830. .func = 1,
  831. .route_offset = 0x144,
  832. .route_val = BIT(16 + 5) | BIT(5),
  833. }, {
  834. /* emmc-0 */
  835. .bank_num = 1,
  836. .pin = 22,
  837. .func = 2,
  838. .route_offset = 0x144,
  839. .route_val = BIT(16 + 6),
  840. }, {
  841. /* emmc-1 */
  842. .bank_num = 2,
  843. .pin = 4,
  844. .func = 2,
  845. .route_offset = 0x144,
  846. .route_val = BIT(16 + 6) | BIT(6),
  847. },
  848. };
  849. static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
  850. {
  851. /* non-iomuxed emmc/flash pins on flash-dqs */
  852. .bank_num = 0,
  853. .pin = 24,
  854. .func = 1,
  855. .route_location = ROCKCHIP_ROUTE_GRF,
  856. .route_offset = 0xa0,
  857. .route_val = BIT(16 + 11),
  858. }, {
  859. /* non-iomuxed emmc/flash pins on emmc-clk */
  860. .bank_num = 0,
  861. .pin = 24,
  862. .func = 2,
  863. .route_location = ROCKCHIP_ROUTE_GRF,
  864. .route_offset = 0xa0,
  865. .route_val = BIT(16 + 11) | BIT(11),
  866. },
  867. };
  868. static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
  869. {
  870. /* pwm0-0 */
  871. .bank_num = 0,
  872. .pin = 26,
  873. .func = 1,
  874. .route_offset = 0x50,
  875. .route_val = BIT(16),
  876. }, {
  877. /* pwm0-1 */
  878. .bank_num = 3,
  879. .pin = 21,
  880. .func = 1,
  881. .route_offset = 0x50,
  882. .route_val = BIT(16) | BIT(0),
  883. }, {
  884. /* pwm1-0 */
  885. .bank_num = 0,
  886. .pin = 27,
  887. .func = 1,
  888. .route_offset = 0x50,
  889. .route_val = BIT(16 + 1),
  890. }, {
  891. /* pwm1-1 */
  892. .bank_num = 0,
  893. .pin = 30,
  894. .func = 2,
  895. .route_offset = 0x50,
  896. .route_val = BIT(16 + 1) | BIT(1),
  897. }, {
  898. /* pwm2-0 */
  899. .bank_num = 0,
  900. .pin = 28,
  901. .func = 1,
  902. .route_offset = 0x50,
  903. .route_val = BIT(16 + 2),
  904. }, {
  905. /* pwm2-1 */
  906. .bank_num = 1,
  907. .pin = 12,
  908. .func = 2,
  909. .route_offset = 0x50,
  910. .route_val = BIT(16 + 2) | BIT(2),
  911. }, {
  912. /* pwm3-0 */
  913. .bank_num = 3,
  914. .pin = 26,
  915. .func = 1,
  916. .route_offset = 0x50,
  917. .route_val = BIT(16 + 3),
  918. }, {
  919. /* pwm3-1 */
  920. .bank_num = 1,
  921. .pin = 11,
  922. .func = 2,
  923. .route_offset = 0x50,
  924. .route_val = BIT(16 + 3) | BIT(3),
  925. }, {
  926. /* sdio-0_d0 */
  927. .bank_num = 1,
  928. .pin = 1,
  929. .func = 1,
  930. .route_offset = 0x50,
  931. .route_val = BIT(16 + 4),
  932. }, {
  933. /* sdio-1_d0 */
  934. .bank_num = 3,
  935. .pin = 2,
  936. .func = 1,
  937. .route_offset = 0x50,
  938. .route_val = BIT(16 + 4) | BIT(4),
  939. }, {
  940. /* spi-0_rx */
  941. .bank_num = 0,
  942. .pin = 13,
  943. .func = 2,
  944. .route_offset = 0x50,
  945. .route_val = BIT(16 + 5),
  946. }, {
  947. /* spi-1_rx */
  948. .bank_num = 2,
  949. .pin = 0,
  950. .func = 2,
  951. .route_offset = 0x50,
  952. .route_val = BIT(16 + 5) | BIT(5),
  953. }, {
  954. /* emmc-0_cmd */
  955. .bank_num = 1,
  956. .pin = 22,
  957. .func = 2,
  958. .route_offset = 0x50,
  959. .route_val = BIT(16 + 7),
  960. }, {
  961. /* emmc-1_cmd */
  962. .bank_num = 2,
  963. .pin = 4,
  964. .func = 2,
  965. .route_offset = 0x50,
  966. .route_val = BIT(16 + 7) | BIT(7),
  967. }, {
  968. /* uart2-0_rx */
  969. .bank_num = 1,
  970. .pin = 19,
  971. .func = 2,
  972. .route_offset = 0x50,
  973. .route_val = BIT(16 + 8),
  974. }, {
  975. /* uart2-1_rx */
  976. .bank_num = 1,
  977. .pin = 10,
  978. .func = 2,
  979. .route_offset = 0x50,
  980. .route_val = BIT(16 + 8) | BIT(8),
  981. }, {
  982. /* uart1-0_rx */
  983. .bank_num = 1,
  984. .pin = 10,
  985. .func = 1,
  986. .route_offset = 0x50,
  987. .route_val = BIT(16 + 11),
  988. }, {
  989. /* uart1-1_rx */
  990. .bank_num = 3,
  991. .pin = 13,
  992. .func = 1,
  993. .route_offset = 0x50,
  994. .route_val = BIT(16 + 11) | BIT(11),
  995. },
  996. };
  997. static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
  998. {
  999. /* edphdmi_cecinoutt1 */
  1000. .bank_num = 7,
  1001. .pin = 16,
  1002. .func = 2,
  1003. .route_offset = 0x264,
  1004. .route_val = BIT(16 + 12) | BIT(12),
  1005. }, {
  1006. /* edphdmi_cecinout */
  1007. .bank_num = 7,
  1008. .pin = 23,
  1009. .func = 4,
  1010. .route_offset = 0x264,
  1011. .route_val = BIT(16 + 12),
  1012. },
  1013. };
  1014. static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
  1015. {
  1016. /* rtc_clk */
  1017. .bank_num = 0,
  1018. .pin = 19,
  1019. .func = 1,
  1020. .route_offset = 0x314,
  1021. .route_val = BIT(16 + 0) | BIT(0),
  1022. }, {
  1023. /* uart2_rxm0 */
  1024. .bank_num = 1,
  1025. .pin = 22,
  1026. .func = 2,
  1027. .route_offset = 0x314,
  1028. .route_val = BIT(16 + 2) | BIT(16 + 3),
  1029. }, {
  1030. /* uart2_rxm1 */
  1031. .bank_num = 4,
  1032. .pin = 26,
  1033. .func = 2,
  1034. .route_offset = 0x314,
  1035. .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
  1036. }, {
  1037. /* i2c3_sdam0 */
  1038. .bank_num = 0,
  1039. .pin = 15,
  1040. .func = 2,
  1041. .route_offset = 0x608,
  1042. .route_val = BIT(16 + 8) | BIT(16 + 9),
  1043. }, {
  1044. /* i2c3_sdam1 */
  1045. .bank_num = 3,
  1046. .pin = 12,
  1047. .func = 2,
  1048. .route_offset = 0x608,
  1049. .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
  1050. }, {
  1051. /* i2c3_sdam2 */
  1052. .bank_num = 2,
  1053. .pin = 0,
  1054. .func = 3,
  1055. .route_offset = 0x608,
  1056. .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
  1057. }, {
  1058. /* i2s-8ch-1-sclktxm0 */
  1059. .bank_num = 1,
  1060. .pin = 3,
  1061. .func = 2,
  1062. .route_offset = 0x308,
  1063. .route_val = BIT(16 + 3),
  1064. }, {
  1065. /* i2s-8ch-1-sclkrxm0 */
  1066. .bank_num = 1,
  1067. .pin = 4,
  1068. .func = 2,
  1069. .route_offset = 0x308,
  1070. .route_val = BIT(16 + 3),
  1071. }, {
  1072. /* i2s-8ch-1-sclktxm1 */
  1073. .bank_num = 1,
  1074. .pin = 13,
  1075. .func = 2,
  1076. .route_offset = 0x308,
  1077. .route_val = BIT(16 + 3) | BIT(3),
  1078. }, {
  1079. /* i2s-8ch-1-sclkrxm1 */
  1080. .bank_num = 1,
  1081. .pin = 14,
  1082. .func = 2,
  1083. .route_offset = 0x308,
  1084. .route_val = BIT(16 + 3) | BIT(3),
  1085. }, {
  1086. /* pdm-clkm0 */
  1087. .bank_num = 1,
  1088. .pin = 4,
  1089. .func = 3,
  1090. .route_offset = 0x308,
  1091. .route_val = BIT(16 + 12) | BIT(16 + 13),
  1092. }, {
  1093. /* pdm-clkm1 */
  1094. .bank_num = 1,
  1095. .pin = 14,
  1096. .func = 4,
  1097. .route_offset = 0x308,
  1098. .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
  1099. }, {
  1100. /* pdm-clkm2 */
  1101. .bank_num = 2,
  1102. .pin = 6,
  1103. .func = 2,
  1104. .route_offset = 0x308,
  1105. .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
  1106. }, {
  1107. /* pdm-clkm-m2 */
  1108. .bank_num = 2,
  1109. .pin = 4,
  1110. .func = 3,
  1111. .route_offset = 0x600,
  1112. .route_val = BIT(16 + 2) | BIT(2),
  1113. }, {
  1114. /* spi1_miso */
  1115. .bank_num = 3,
  1116. .pin = 10,
  1117. .func = 3,
  1118. .route_offset = 0x314,
  1119. .route_val = BIT(16 + 9),
  1120. }, {
  1121. /* spi1_miso_m1 */
  1122. .bank_num = 2,
  1123. .pin = 4,
  1124. .func = 2,
  1125. .route_offset = 0x314,
  1126. .route_val = BIT(16 + 9) | BIT(9),
  1127. }, {
  1128. /* owire_m0 */
  1129. .bank_num = 0,
  1130. .pin = 11,
  1131. .func = 3,
  1132. .route_offset = 0x314,
  1133. .route_val = BIT(16 + 10) | BIT(16 + 11),
  1134. }, {
  1135. /* owire_m1 */
  1136. .bank_num = 1,
  1137. .pin = 22,
  1138. .func = 7,
  1139. .route_offset = 0x314,
  1140. .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
  1141. }, {
  1142. /* owire_m2 */
  1143. .bank_num = 2,
  1144. .pin = 2,
  1145. .func = 5,
  1146. .route_offset = 0x314,
  1147. .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
  1148. }, {
  1149. /* can_rxd_m0 */
  1150. .bank_num = 0,
  1151. .pin = 11,
  1152. .func = 2,
  1153. .route_offset = 0x314,
  1154. .route_val = BIT(16 + 12) | BIT(16 + 13),
  1155. }, {
  1156. /* can_rxd_m1 */
  1157. .bank_num = 1,
  1158. .pin = 22,
  1159. .func = 5,
  1160. .route_offset = 0x314,
  1161. .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
  1162. }, {
  1163. /* can_rxd_m2 */
  1164. .bank_num = 2,
  1165. .pin = 2,
  1166. .func = 4,
  1167. .route_offset = 0x314,
  1168. .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
  1169. }, {
  1170. /* mac_rxd0_m0 */
  1171. .bank_num = 1,
  1172. .pin = 20,
  1173. .func = 3,
  1174. .route_offset = 0x314,
  1175. .route_val = BIT(16 + 14),
  1176. }, {
  1177. /* mac_rxd0_m1 */
  1178. .bank_num = 4,
  1179. .pin = 2,
  1180. .func = 2,
  1181. .route_offset = 0x314,
  1182. .route_val = BIT(16 + 14) | BIT(14),
  1183. }, {
  1184. /* uart3_rx */
  1185. .bank_num = 3,
  1186. .pin = 12,
  1187. .func = 4,
  1188. .route_offset = 0x314,
  1189. .route_val = BIT(16 + 15),
  1190. }, {
  1191. /* uart3_rx_m1 */
  1192. .bank_num = 0,
  1193. .pin = 17,
  1194. .func = 3,
  1195. .route_offset = 0x314,
  1196. .route_val = BIT(16 + 15) | BIT(15),
  1197. },
  1198. };
  1199. static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
  1200. {
  1201. /* uart2dbg_rxm0 */
  1202. .bank_num = 1,
  1203. .pin = 1,
  1204. .func = 2,
  1205. .route_offset = 0x50,
  1206. .route_val = BIT(16) | BIT(16 + 1),
  1207. }, {
  1208. /* uart2dbg_rxm1 */
  1209. .bank_num = 2,
  1210. .pin = 1,
  1211. .func = 1,
  1212. .route_offset = 0x50,
  1213. .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
  1214. }, {
  1215. /* gmac-m1_rxd0 */
  1216. .bank_num = 1,
  1217. .pin = 11,
  1218. .func = 2,
  1219. .route_offset = 0x50,
  1220. .route_val = BIT(16 + 2) | BIT(2),
  1221. }, {
  1222. /* gmac-m1-optimized_rxd3 */
  1223. .bank_num = 1,
  1224. .pin = 14,
  1225. .func = 2,
  1226. .route_offset = 0x50,
  1227. .route_val = BIT(16 + 10) | BIT(10),
  1228. }, {
  1229. /* pdm_sdi0m0 */
  1230. .bank_num = 2,
  1231. .pin = 19,
  1232. .func = 2,
  1233. .route_offset = 0x50,
  1234. .route_val = BIT(16 + 3),
  1235. }, {
  1236. /* pdm_sdi0m1 */
  1237. .bank_num = 1,
  1238. .pin = 23,
  1239. .func = 3,
  1240. .route_offset = 0x50,
  1241. .route_val = BIT(16 + 3) | BIT(3),
  1242. }, {
  1243. /* spi_rxdm2 */
  1244. .bank_num = 3,
  1245. .pin = 2,
  1246. .func = 4,
  1247. .route_offset = 0x50,
  1248. .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
  1249. }, {
  1250. /* i2s2_sdim0 */
  1251. .bank_num = 1,
  1252. .pin = 24,
  1253. .func = 1,
  1254. .route_offset = 0x50,
  1255. .route_val = BIT(16 + 6),
  1256. }, {
  1257. /* i2s2_sdim1 */
  1258. .bank_num = 3,
  1259. .pin = 2,
  1260. .func = 6,
  1261. .route_offset = 0x50,
  1262. .route_val = BIT(16 + 6) | BIT(6),
  1263. }, {
  1264. /* card_iom1 */
  1265. .bank_num = 2,
  1266. .pin = 22,
  1267. .func = 3,
  1268. .route_offset = 0x50,
  1269. .route_val = BIT(16 + 7) | BIT(7),
  1270. }, {
  1271. /* tsp_d5m1 */
  1272. .bank_num = 2,
  1273. .pin = 16,
  1274. .func = 3,
  1275. .route_offset = 0x50,
  1276. .route_val = BIT(16 + 8) | BIT(8),
  1277. }, {
  1278. /* cif_data5m1 */
  1279. .bank_num = 2,
  1280. .pin = 16,
  1281. .func = 4,
  1282. .route_offset = 0x50,
  1283. .route_val = BIT(16 + 9) | BIT(9),
  1284. },
  1285. };
  1286. static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
  1287. {
  1288. /* uart2dbga_rx */
  1289. .bank_num = 4,
  1290. .pin = 8,
  1291. .func = 2,
  1292. .route_offset = 0xe21c,
  1293. .route_val = BIT(16 + 10) | BIT(16 + 11),
  1294. }, {
  1295. /* uart2dbgb_rx */
  1296. .bank_num = 4,
  1297. .pin = 16,
  1298. .func = 2,
  1299. .route_offset = 0xe21c,
  1300. .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
  1301. }, {
  1302. /* uart2dbgc_rx */
  1303. .bank_num = 4,
  1304. .pin = 19,
  1305. .func = 1,
  1306. .route_offset = 0xe21c,
  1307. .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
  1308. }, {
  1309. /* pcie_clkreqn */
  1310. .bank_num = 2,
  1311. .pin = 26,
  1312. .func = 2,
  1313. .route_offset = 0xe21c,
  1314. .route_val = BIT(16 + 14),
  1315. }, {
  1316. /* pcie_clkreqnb */
  1317. .bank_num = 4,
  1318. .pin = 24,
  1319. .func = 1,
  1320. .route_offset = 0xe21c,
  1321. .route_val = BIT(16 + 14) | BIT(14),
  1322. },
  1323. };
  1324. static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
  1325. int mux, u32 *loc, u32 *reg, u32 *value)
  1326. {
  1327. struct rockchip_pinctrl *info = bank->drvdata;
  1328. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  1329. struct rockchip_mux_route_data *data;
  1330. int i;
  1331. for (i = 0; i < ctrl->niomux_routes; i++) {
  1332. data = &ctrl->iomux_routes[i];
  1333. if ((data->bank_num == bank->bank_num) &&
  1334. (data->pin == pin) && (data->func == mux))
  1335. break;
  1336. }
  1337. if (i >= ctrl->niomux_routes)
  1338. return false;
  1339. *loc = data->route_location;
  1340. *reg = data->route_offset;
  1341. *value = data->route_val;
  1342. return true;
  1343. }
  1344. static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
  1345. {
  1346. struct rockchip_pinctrl *info = bank->drvdata;
  1347. int iomux_num = (pin / 8);
  1348. struct regmap *regmap;
  1349. unsigned int val;
  1350. int reg, ret, mask, mux_type;
  1351. u8 bit;
  1352. if (iomux_num > 3)
  1353. return -EINVAL;
  1354. if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
  1355. dev_err(info->dev, "pin %d is unrouted\n", pin);
  1356. return -EINVAL;
  1357. }
  1358. if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
  1359. return RK_FUNC_GPIO;
  1360. regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  1361. ? info->regmap_pmu : info->regmap_base;
  1362. /* get basic quadrupel of mux registers and the correct reg inside */
  1363. mux_type = bank->iomux[iomux_num].type;
  1364. reg = bank->iomux[iomux_num].offset;
  1365. if (mux_type & IOMUX_WIDTH_4BIT) {
  1366. if ((pin % 8) >= 4)
  1367. reg += 0x4;
  1368. bit = (pin % 4) * 4;
  1369. mask = 0xf;
  1370. } else if (mux_type & IOMUX_WIDTH_3BIT) {
  1371. if ((pin % 8) >= 5)
  1372. reg += 0x4;
  1373. bit = (pin % 8 % 5) * 3;
  1374. mask = 0x7;
  1375. } else {
  1376. bit = (pin % 8) * 2;
  1377. mask = 0x3;
  1378. }
  1379. if (bank->recalced_mask & BIT(pin))
  1380. rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
  1381. ret = regmap_read(regmap, reg, &val);
  1382. if (ret)
  1383. return ret;
  1384. return ((val >> bit) & mask);
  1385. }
  1386. static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
  1387. int pin, int mux)
  1388. {
  1389. struct rockchip_pinctrl *info = bank->drvdata;
  1390. int iomux_num = (pin / 8);
  1391. if (iomux_num > 3)
  1392. return -EINVAL;
  1393. if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
  1394. dev_err(info->dev, "pin %d is unrouted\n", pin);
  1395. return -EINVAL;
  1396. }
  1397. if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
  1398. if (mux != RK_FUNC_GPIO) {
  1399. dev_err(info->dev,
  1400. "pin %d only supports a gpio mux\n", pin);
  1401. return -ENOTSUPP;
  1402. }
  1403. }
  1404. return 0;
  1405. }
  1406. /*
  1407. * Set a new mux function for a pin.
  1408. *
  1409. * The register is divided into the upper and lower 16 bit. When changing
  1410. * a value, the previous register value is not read and changed. Instead
  1411. * it seems the changed bits are marked in the upper 16 bit, while the
  1412. * changed value gets set in the same offset in the lower 16 bit.
  1413. * All pin settings seem to be 2 bit wide in both the upper and lower
  1414. * parts.
  1415. * @bank: pin bank to change
  1416. * @pin: pin to change
  1417. * @mux: new mux function to set
  1418. */
  1419. static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  1420. {
  1421. struct rockchip_pinctrl *info = bank->drvdata;
  1422. int iomux_num = (pin / 8);
  1423. struct regmap *regmap;
  1424. int reg, ret, mask, mux_type;
  1425. u8 bit;
  1426. u32 data, rmask, route_location, route_reg, route_val;
  1427. ret = rockchip_verify_mux(bank, pin, mux);
  1428. if (ret < 0)
  1429. return ret;
  1430. if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
  1431. return 0;
  1432. dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
  1433. bank->bank_num, pin, mux);
  1434. regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  1435. ? info->regmap_pmu : info->regmap_base;
  1436. /* get basic quadrupel of mux registers and the correct reg inside */
  1437. mux_type = bank->iomux[iomux_num].type;
  1438. reg = bank->iomux[iomux_num].offset;
  1439. if (mux_type & IOMUX_WIDTH_4BIT) {
  1440. if ((pin % 8) >= 4)
  1441. reg += 0x4;
  1442. bit = (pin % 4) * 4;
  1443. mask = 0xf;
  1444. } else if (mux_type & IOMUX_WIDTH_3BIT) {
  1445. if ((pin % 8) >= 5)
  1446. reg += 0x4;
  1447. bit = (pin % 8 % 5) * 3;
  1448. mask = 0x7;
  1449. } else {
  1450. bit = (pin % 8) * 2;
  1451. mask = 0x3;
  1452. }
  1453. if (bank->recalced_mask & BIT(pin))
  1454. rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
  1455. if (bank->route_mask & BIT(pin)) {
  1456. if (rockchip_get_mux_route(bank, pin, mux, &route_location,
  1457. &route_reg, &route_val)) {
  1458. struct regmap *route_regmap = regmap;
  1459. /* handle special locations */
  1460. switch (route_location) {
  1461. case ROCKCHIP_ROUTE_PMU:
  1462. route_regmap = info->regmap_pmu;
  1463. break;
  1464. case ROCKCHIP_ROUTE_GRF:
  1465. route_regmap = info->regmap_base;
  1466. break;
  1467. }
  1468. ret = regmap_write(route_regmap, route_reg, route_val);
  1469. if (ret)
  1470. return ret;
  1471. }
  1472. }
  1473. data = (mask << (bit + 16));
  1474. rmask = data | (data >> 16);
  1475. data |= (mux & mask) << bit;
  1476. ret = regmap_update_bits(regmap, reg, rmask, data);
  1477. return ret;
  1478. }
  1479. #define PX30_PULL_PMU_OFFSET 0x10
  1480. #define PX30_PULL_GRF_OFFSET 0x60
  1481. #define PX30_PULL_BITS_PER_PIN 2
  1482. #define PX30_PULL_PINS_PER_REG 8
  1483. #define PX30_PULL_BANK_STRIDE 16
  1484. static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1485. int pin_num, struct regmap **regmap,
  1486. int *reg, u8 *bit)
  1487. {
  1488. struct rockchip_pinctrl *info = bank->drvdata;
  1489. /* The first 32 pins of the first bank are located in PMU */
  1490. if (bank->bank_num == 0) {
  1491. *regmap = info->regmap_pmu;
  1492. *reg = PX30_PULL_PMU_OFFSET;
  1493. } else {
  1494. *regmap = info->regmap_base;
  1495. *reg = PX30_PULL_GRF_OFFSET;
  1496. /* correct the offset, as we're starting with the 2nd bank */
  1497. *reg -= 0x10;
  1498. *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
  1499. }
  1500. *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
  1501. *bit = (pin_num % PX30_PULL_PINS_PER_REG);
  1502. *bit *= PX30_PULL_BITS_PER_PIN;
  1503. }
  1504. #define PX30_DRV_PMU_OFFSET 0x20
  1505. #define PX30_DRV_GRF_OFFSET 0xf0
  1506. #define PX30_DRV_BITS_PER_PIN 2
  1507. #define PX30_DRV_PINS_PER_REG 8
  1508. #define PX30_DRV_BANK_STRIDE 16
  1509. static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  1510. int pin_num, struct regmap **regmap,
  1511. int *reg, u8 *bit)
  1512. {
  1513. struct rockchip_pinctrl *info = bank->drvdata;
  1514. /* The first 32 pins of the first bank are located in PMU */
  1515. if (bank->bank_num == 0) {
  1516. *regmap = info->regmap_pmu;
  1517. *reg = PX30_DRV_PMU_OFFSET;
  1518. } else {
  1519. *regmap = info->regmap_base;
  1520. *reg = PX30_DRV_GRF_OFFSET;
  1521. /* correct the offset, as we're starting with the 2nd bank */
  1522. *reg -= 0x10;
  1523. *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
  1524. }
  1525. *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
  1526. *bit = (pin_num % PX30_DRV_PINS_PER_REG);
  1527. *bit *= PX30_DRV_BITS_PER_PIN;
  1528. }
  1529. #define PX30_SCHMITT_PMU_OFFSET 0x38
  1530. #define PX30_SCHMITT_GRF_OFFSET 0xc0
  1531. #define PX30_SCHMITT_PINS_PER_PMU_REG 16
  1532. #define PX30_SCHMITT_BANK_STRIDE 16
  1533. #define PX30_SCHMITT_PINS_PER_GRF_REG 8
  1534. static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
  1535. int pin_num,
  1536. struct regmap **regmap,
  1537. int *reg, u8 *bit)
  1538. {
  1539. struct rockchip_pinctrl *info = bank->drvdata;
  1540. int pins_per_reg;
  1541. if (bank->bank_num == 0) {
  1542. *regmap = info->regmap_pmu;
  1543. *reg = PX30_SCHMITT_PMU_OFFSET;
  1544. pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
  1545. } else {
  1546. *regmap = info->regmap_base;
  1547. *reg = PX30_SCHMITT_GRF_OFFSET;
  1548. pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
  1549. *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
  1550. }
  1551. *reg += ((pin_num / pins_per_reg) * 4);
  1552. *bit = pin_num % pins_per_reg;
  1553. return 0;
  1554. }
  1555. #define RV1108_PULL_PMU_OFFSET 0x10
  1556. #define RV1108_PULL_OFFSET 0x110
  1557. #define RV1108_PULL_PINS_PER_REG 8
  1558. #define RV1108_PULL_BITS_PER_PIN 2
  1559. #define RV1108_PULL_BANK_STRIDE 16
  1560. static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1561. int pin_num, struct regmap **regmap,
  1562. int *reg, u8 *bit)
  1563. {
  1564. struct rockchip_pinctrl *info = bank->drvdata;
  1565. /* The first 24 pins of the first bank are located in PMU */
  1566. if (bank->bank_num == 0) {
  1567. *regmap = info->regmap_pmu;
  1568. *reg = RV1108_PULL_PMU_OFFSET;
  1569. } else {
  1570. *reg = RV1108_PULL_OFFSET;
  1571. *regmap = info->regmap_base;
  1572. /* correct the offset, as we're starting with the 2nd bank */
  1573. *reg -= 0x10;
  1574. *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
  1575. }
  1576. *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
  1577. *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
  1578. *bit *= RV1108_PULL_BITS_PER_PIN;
  1579. }
  1580. #define RV1108_DRV_PMU_OFFSET 0x20
  1581. #define RV1108_DRV_GRF_OFFSET 0x210
  1582. #define RV1108_DRV_BITS_PER_PIN 2
  1583. #define RV1108_DRV_PINS_PER_REG 8
  1584. #define RV1108_DRV_BANK_STRIDE 16
  1585. static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  1586. int pin_num, struct regmap **regmap,
  1587. int *reg, u8 *bit)
  1588. {
  1589. struct rockchip_pinctrl *info = bank->drvdata;
  1590. /* The first 24 pins of the first bank are located in PMU */
  1591. if (bank->bank_num == 0) {
  1592. *regmap = info->regmap_pmu;
  1593. *reg = RV1108_DRV_PMU_OFFSET;
  1594. } else {
  1595. *regmap = info->regmap_base;
  1596. *reg = RV1108_DRV_GRF_OFFSET;
  1597. /* correct the offset, as we're starting with the 2nd bank */
  1598. *reg -= 0x10;
  1599. *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
  1600. }
  1601. *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
  1602. *bit = pin_num % RV1108_DRV_PINS_PER_REG;
  1603. *bit *= RV1108_DRV_BITS_PER_PIN;
  1604. }
  1605. #define RV1108_SCHMITT_PMU_OFFSET 0x30
  1606. #define RV1108_SCHMITT_GRF_OFFSET 0x388
  1607. #define RV1108_SCHMITT_BANK_STRIDE 8
  1608. #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
  1609. #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
  1610. static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
  1611. int pin_num,
  1612. struct regmap **regmap,
  1613. int *reg, u8 *bit)
  1614. {
  1615. struct rockchip_pinctrl *info = bank->drvdata;
  1616. int pins_per_reg;
  1617. if (bank->bank_num == 0) {
  1618. *regmap = info->regmap_pmu;
  1619. *reg = RV1108_SCHMITT_PMU_OFFSET;
  1620. pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
  1621. } else {
  1622. *regmap = info->regmap_base;
  1623. *reg = RV1108_SCHMITT_GRF_OFFSET;
  1624. pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
  1625. *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
  1626. }
  1627. *reg += ((pin_num / pins_per_reg) * 4);
  1628. *bit = pin_num % pins_per_reg;
  1629. return 0;
  1630. }
  1631. #define RK3308_SCHMITT_PINS_PER_REG 8
  1632. #define RK3308_SCHMITT_BANK_STRIDE 16
  1633. #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
  1634. static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
  1635. int pin_num, struct regmap **regmap,
  1636. int *reg, u8 *bit)
  1637. {
  1638. struct rockchip_pinctrl *info = bank->drvdata;
  1639. *regmap = info->regmap_base;
  1640. *reg = RK3308_SCHMITT_GRF_OFFSET;
  1641. *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
  1642. *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
  1643. *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
  1644. return 0;
  1645. }
  1646. #define RK2928_PULL_OFFSET 0x118
  1647. #define RK2928_PULL_PINS_PER_REG 16
  1648. #define RK2928_PULL_BANK_STRIDE 8
  1649. static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1650. int pin_num, struct regmap **regmap,
  1651. int *reg, u8 *bit)
  1652. {
  1653. struct rockchip_pinctrl *info = bank->drvdata;
  1654. *regmap = info->regmap_base;
  1655. *reg = RK2928_PULL_OFFSET;
  1656. *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
  1657. *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
  1658. *bit = pin_num % RK2928_PULL_PINS_PER_REG;
  1659. };
  1660. #define RK3128_PULL_OFFSET 0x118
  1661. static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1662. int pin_num, struct regmap **regmap,
  1663. int *reg, u8 *bit)
  1664. {
  1665. struct rockchip_pinctrl *info = bank->drvdata;
  1666. *regmap = info->regmap_base;
  1667. *reg = RK3128_PULL_OFFSET;
  1668. *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
  1669. *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
  1670. *bit = pin_num % RK2928_PULL_PINS_PER_REG;
  1671. }
  1672. #define RK3188_PULL_OFFSET 0x164
  1673. #define RK3188_PULL_BITS_PER_PIN 2
  1674. #define RK3188_PULL_PINS_PER_REG 8
  1675. #define RK3188_PULL_BANK_STRIDE 16
  1676. #define RK3188_PULL_PMU_OFFSET 0x64
  1677. static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1678. int pin_num, struct regmap **regmap,
  1679. int *reg, u8 *bit)
  1680. {
  1681. struct rockchip_pinctrl *info = bank->drvdata;
  1682. /* The first 12 pins of the first bank are located elsewhere */
  1683. if (bank->bank_num == 0 && pin_num < 12) {
  1684. *regmap = info->regmap_pmu ? info->regmap_pmu
  1685. : bank->regmap_pull;
  1686. *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
  1687. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1688. *bit = pin_num % RK3188_PULL_PINS_PER_REG;
  1689. *bit *= RK3188_PULL_BITS_PER_PIN;
  1690. } else {
  1691. *regmap = info->regmap_pull ? info->regmap_pull
  1692. : info->regmap_base;
  1693. *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
  1694. /* correct the offset, as it is the 2nd pull register */
  1695. *reg -= 4;
  1696. *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
  1697. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1698. /*
  1699. * The bits in these registers have an inverse ordering
  1700. * with the lowest pin being in bits 15:14 and the highest
  1701. * pin in bits 1:0
  1702. */
  1703. *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
  1704. *bit *= RK3188_PULL_BITS_PER_PIN;
  1705. }
  1706. }
  1707. #define RK3288_PULL_OFFSET 0x140
  1708. static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1709. int pin_num, struct regmap **regmap,
  1710. int *reg, u8 *bit)
  1711. {
  1712. struct rockchip_pinctrl *info = bank->drvdata;
  1713. /* The first 24 pins of the first bank are located in PMU */
  1714. if (bank->bank_num == 0) {
  1715. *regmap = info->regmap_pmu;
  1716. *reg = RK3188_PULL_PMU_OFFSET;
  1717. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1718. *bit = pin_num % RK3188_PULL_PINS_PER_REG;
  1719. *bit *= RK3188_PULL_BITS_PER_PIN;
  1720. } else {
  1721. *regmap = info->regmap_base;
  1722. *reg = RK3288_PULL_OFFSET;
  1723. /* correct the offset, as we're starting with the 2nd bank */
  1724. *reg -= 0x10;
  1725. *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
  1726. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1727. *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
  1728. *bit *= RK3188_PULL_BITS_PER_PIN;
  1729. }
  1730. }
  1731. #define RK3288_DRV_PMU_OFFSET 0x70
  1732. #define RK3288_DRV_GRF_OFFSET 0x1c0
  1733. #define RK3288_DRV_BITS_PER_PIN 2
  1734. #define RK3288_DRV_PINS_PER_REG 8
  1735. #define RK3288_DRV_BANK_STRIDE 16
  1736. static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  1737. int pin_num, struct regmap **regmap,
  1738. int *reg, u8 *bit)
  1739. {
  1740. struct rockchip_pinctrl *info = bank->drvdata;
  1741. /* The first 24 pins of the first bank are located in PMU */
  1742. if (bank->bank_num == 0) {
  1743. *regmap = info->regmap_pmu;
  1744. *reg = RK3288_DRV_PMU_OFFSET;
  1745. *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
  1746. *bit = pin_num % RK3288_DRV_PINS_PER_REG;
  1747. *bit *= RK3288_DRV_BITS_PER_PIN;
  1748. } else {
  1749. *regmap = info->regmap_base;
  1750. *reg = RK3288_DRV_GRF_OFFSET;
  1751. /* correct the offset, as we're starting with the 2nd bank */
  1752. *reg -= 0x10;
  1753. *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
  1754. *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
  1755. *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
  1756. *bit *= RK3288_DRV_BITS_PER_PIN;
  1757. }
  1758. }
  1759. #define RK3228_PULL_OFFSET 0x100
  1760. static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1761. int pin_num, struct regmap **regmap,
  1762. int *reg, u8 *bit)
  1763. {
  1764. struct rockchip_pinctrl *info = bank->drvdata;
  1765. *regmap = info->regmap_base;
  1766. *reg = RK3228_PULL_OFFSET;
  1767. *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
  1768. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1769. *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
  1770. *bit *= RK3188_PULL_BITS_PER_PIN;
  1771. }
  1772. #define RK3228_DRV_GRF_OFFSET 0x200
  1773. static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  1774. int pin_num, struct regmap **regmap,
  1775. int *reg, u8 *bit)
  1776. {
  1777. struct rockchip_pinctrl *info = bank->drvdata;
  1778. *regmap = info->regmap_base;
  1779. *reg = RK3228_DRV_GRF_OFFSET;
  1780. *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
  1781. *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
  1782. *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
  1783. *bit *= RK3288_DRV_BITS_PER_PIN;
  1784. }
  1785. #define RK3308_PULL_OFFSET 0xa0
  1786. static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1787. int pin_num, struct regmap **regmap,
  1788. int *reg, u8 *bit)
  1789. {
  1790. struct rockchip_pinctrl *info = bank->drvdata;
  1791. *regmap = info->regmap_base;
  1792. *reg = RK3308_PULL_OFFSET;
  1793. *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
  1794. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1795. *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
  1796. *bit *= RK3188_PULL_BITS_PER_PIN;
  1797. }
  1798. #define RK3308_DRV_GRF_OFFSET 0x100
  1799. static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  1800. int pin_num, struct regmap **regmap,
  1801. int *reg, u8 *bit)
  1802. {
  1803. struct rockchip_pinctrl *info = bank->drvdata;
  1804. *regmap = info->regmap_base;
  1805. *reg = RK3308_DRV_GRF_OFFSET;
  1806. *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
  1807. *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
  1808. *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
  1809. *bit *= RK3288_DRV_BITS_PER_PIN;
  1810. }
  1811. #define RK3368_PULL_GRF_OFFSET 0x100
  1812. #define RK3368_PULL_PMU_OFFSET 0x10
  1813. static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1814. int pin_num, struct regmap **regmap,
  1815. int *reg, u8 *bit)
  1816. {
  1817. struct rockchip_pinctrl *info = bank->drvdata;
  1818. /* The first 32 pins of the first bank are located in PMU */
  1819. if (bank->bank_num == 0) {
  1820. *regmap = info->regmap_pmu;
  1821. *reg = RK3368_PULL_PMU_OFFSET;
  1822. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1823. *bit = pin_num % RK3188_PULL_PINS_PER_REG;
  1824. *bit *= RK3188_PULL_BITS_PER_PIN;
  1825. } else {
  1826. *regmap = info->regmap_base;
  1827. *reg = RK3368_PULL_GRF_OFFSET;
  1828. /* correct the offset, as we're starting with the 2nd bank */
  1829. *reg -= 0x10;
  1830. *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
  1831. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1832. *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
  1833. *bit *= RK3188_PULL_BITS_PER_PIN;
  1834. }
  1835. }
  1836. #define RK3368_DRV_PMU_OFFSET 0x20
  1837. #define RK3368_DRV_GRF_OFFSET 0x200
  1838. static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  1839. int pin_num, struct regmap **regmap,
  1840. int *reg, u8 *bit)
  1841. {
  1842. struct rockchip_pinctrl *info = bank->drvdata;
  1843. /* The first 32 pins of the first bank are located in PMU */
  1844. if (bank->bank_num == 0) {
  1845. *regmap = info->regmap_pmu;
  1846. *reg = RK3368_DRV_PMU_OFFSET;
  1847. *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
  1848. *bit = pin_num % RK3288_DRV_PINS_PER_REG;
  1849. *bit *= RK3288_DRV_BITS_PER_PIN;
  1850. } else {
  1851. *regmap = info->regmap_base;
  1852. *reg = RK3368_DRV_GRF_OFFSET;
  1853. /* correct the offset, as we're starting with the 2nd bank */
  1854. *reg -= 0x10;
  1855. *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
  1856. *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
  1857. *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
  1858. *bit *= RK3288_DRV_BITS_PER_PIN;
  1859. }
  1860. }
  1861. #define RK3399_PULL_GRF_OFFSET 0xe040
  1862. #define RK3399_PULL_PMU_OFFSET 0x40
  1863. #define RK3399_DRV_3BITS_PER_PIN 3
  1864. static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  1865. int pin_num, struct regmap **regmap,
  1866. int *reg, u8 *bit)
  1867. {
  1868. struct rockchip_pinctrl *info = bank->drvdata;
  1869. /* The bank0:16 and bank1:32 pins are located in PMU */
  1870. if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
  1871. *regmap = info->regmap_pmu;
  1872. *reg = RK3399_PULL_PMU_OFFSET;
  1873. *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
  1874. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1875. *bit = pin_num % RK3188_PULL_PINS_PER_REG;
  1876. *bit *= RK3188_PULL_BITS_PER_PIN;
  1877. } else {
  1878. *regmap = info->regmap_base;
  1879. *reg = RK3399_PULL_GRF_OFFSET;
  1880. /* correct the offset, as we're starting with the 3rd bank */
  1881. *reg -= 0x20;
  1882. *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
  1883. *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
  1884. *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
  1885. *bit *= RK3188_PULL_BITS_PER_PIN;
  1886. }
  1887. }
  1888. static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  1889. int pin_num, struct regmap **regmap,
  1890. int *reg, u8 *bit)
  1891. {
  1892. struct rockchip_pinctrl *info = bank->drvdata;
  1893. int drv_num = (pin_num / 8);
  1894. /* The bank0:16 and bank1:32 pins are located in PMU */
  1895. if ((bank->bank_num == 0) || (bank->bank_num == 1))
  1896. *regmap = info->regmap_pmu;
  1897. else
  1898. *regmap = info->regmap_base;
  1899. *reg = bank->drv[drv_num].offset;
  1900. if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
  1901. (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
  1902. *bit = (pin_num % 8) * 3;
  1903. else
  1904. *bit = (pin_num % 8) * 2;
  1905. }
  1906. static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
  1907. { 2, 4, 8, 12, -1, -1, -1, -1 },
  1908. { 3, 6, 9, 12, -1, -1, -1, -1 },
  1909. { 5, 10, 15, 20, -1, -1, -1, -1 },
  1910. { 4, 6, 8, 10, 12, 14, 16, 18 },
  1911. { 4, 7, 10, 13, 16, 19, 22, 26 }
  1912. };
  1913. static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
  1914. int pin_num)
  1915. {
  1916. struct rockchip_pinctrl *info = bank->drvdata;
  1917. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  1918. struct regmap *regmap;
  1919. int reg, ret;
  1920. u32 data, temp, rmask_bits;
  1921. u8 bit;
  1922. int drv_type = bank->drv[pin_num / 8].drv_type;
  1923. ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
  1924. switch (drv_type) {
  1925. case DRV_TYPE_IO_1V8_3V0_AUTO:
  1926. case DRV_TYPE_IO_3V3_ONLY:
  1927. rmask_bits = RK3399_DRV_3BITS_PER_PIN;
  1928. switch (bit) {
  1929. case 0 ... 12:
  1930. /* regular case, nothing to do */
  1931. break;
  1932. case 15:
  1933. /*
  1934. * drive-strength offset is special, as it is
  1935. * spread over 2 registers
  1936. */
  1937. ret = regmap_read(regmap, reg, &data);
  1938. if (ret)
  1939. return ret;
  1940. ret = regmap_read(regmap, reg + 0x4, &temp);
  1941. if (ret)
  1942. return ret;
  1943. /*
  1944. * the bit data[15] contains bit 0 of the value
  1945. * while temp[1:0] contains bits 2 and 1
  1946. */
  1947. data >>= 15;
  1948. temp &= 0x3;
  1949. temp <<= 1;
  1950. data |= temp;
  1951. return rockchip_perpin_drv_list[drv_type][data];
  1952. case 18 ... 21:
  1953. /* setting fully enclosed in the second register */
  1954. reg += 4;
  1955. bit -= 16;
  1956. break;
  1957. default:
  1958. dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
  1959. bit, drv_type);
  1960. return -EINVAL;
  1961. }
  1962. break;
  1963. case DRV_TYPE_IO_DEFAULT:
  1964. case DRV_TYPE_IO_1V8_OR_3V0:
  1965. case DRV_TYPE_IO_1V8_ONLY:
  1966. rmask_bits = RK3288_DRV_BITS_PER_PIN;
  1967. break;
  1968. default:
  1969. dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
  1970. drv_type);
  1971. return -EINVAL;
  1972. }
  1973. ret = regmap_read(regmap, reg, &data);
  1974. if (ret)
  1975. return ret;
  1976. data >>= bit;
  1977. data &= (1 << rmask_bits) - 1;
  1978. return rockchip_perpin_drv_list[drv_type][data];
  1979. }
  1980. static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
  1981. int pin_num, int strength)
  1982. {
  1983. struct rockchip_pinctrl *info = bank->drvdata;
  1984. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  1985. struct regmap *regmap;
  1986. int reg, ret, i;
  1987. u32 data, rmask, rmask_bits, temp;
  1988. u8 bit;
  1989. int drv_type = bank->drv[pin_num / 8].drv_type;
  1990. dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
  1991. bank->bank_num, pin_num, strength);
  1992. ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
  1993. ret = -EINVAL;
  1994. for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
  1995. if (rockchip_perpin_drv_list[drv_type][i] == strength) {
  1996. ret = i;
  1997. break;
  1998. } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
  1999. ret = rockchip_perpin_drv_list[drv_type][i];
  2000. break;
  2001. }
  2002. }
  2003. if (ret < 0) {
  2004. dev_err(info->dev, "unsupported driver strength %d\n",
  2005. strength);
  2006. return ret;
  2007. }
  2008. switch (drv_type) {
  2009. case DRV_TYPE_IO_1V8_3V0_AUTO:
  2010. case DRV_TYPE_IO_3V3_ONLY:
  2011. rmask_bits = RK3399_DRV_3BITS_PER_PIN;
  2012. switch (bit) {
  2013. case 0 ... 12:
  2014. /* regular case, nothing to do */
  2015. break;
  2016. case 15:
  2017. /*
  2018. * drive-strength offset is special, as it is spread
  2019. * over 2 registers, the bit data[15] contains bit 0
  2020. * of the value while temp[1:0] contains bits 2 and 1
  2021. */
  2022. data = (ret & 0x1) << 15;
  2023. temp = (ret >> 0x1) & 0x3;
  2024. rmask = BIT(15) | BIT(31);
  2025. data |= BIT(31);
  2026. ret = regmap_update_bits(regmap, reg, rmask, data);
  2027. if (ret)
  2028. return ret;
  2029. rmask = 0x3 | (0x3 << 16);
  2030. temp |= (0x3 << 16);
  2031. reg += 0x4;
  2032. ret = regmap_update_bits(regmap, reg, rmask, temp);
  2033. return ret;
  2034. case 18 ... 21:
  2035. /* setting fully enclosed in the second register */
  2036. reg += 4;
  2037. bit -= 16;
  2038. break;
  2039. default:
  2040. dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
  2041. bit, drv_type);
  2042. return -EINVAL;
  2043. }
  2044. break;
  2045. case DRV_TYPE_IO_DEFAULT:
  2046. case DRV_TYPE_IO_1V8_OR_3V0:
  2047. case DRV_TYPE_IO_1V8_ONLY:
  2048. rmask_bits = RK3288_DRV_BITS_PER_PIN;
  2049. break;
  2050. default:
  2051. dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
  2052. drv_type);
  2053. return -EINVAL;
  2054. }
  2055. /* enable the write to the equivalent lower bits */
  2056. data = ((1 << rmask_bits) - 1) << (bit + 16);
  2057. rmask = data | (data >> 16);
  2058. data |= (ret << bit);
  2059. ret = regmap_update_bits(regmap, reg, rmask, data);
  2060. return ret;
  2061. }
  2062. static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
  2063. {
  2064. PIN_CONFIG_BIAS_DISABLE,
  2065. PIN_CONFIG_BIAS_PULL_UP,
  2066. PIN_CONFIG_BIAS_PULL_DOWN,
  2067. PIN_CONFIG_BIAS_BUS_HOLD
  2068. },
  2069. {
  2070. PIN_CONFIG_BIAS_DISABLE,
  2071. PIN_CONFIG_BIAS_PULL_DOWN,
  2072. PIN_CONFIG_BIAS_DISABLE,
  2073. PIN_CONFIG_BIAS_PULL_UP
  2074. },
  2075. };
  2076. static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
  2077. {
  2078. struct rockchip_pinctrl *info = bank->drvdata;
  2079. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  2080. struct regmap *regmap;
  2081. int reg, ret, pull_type;
  2082. u8 bit;
  2083. u32 data;
  2084. /* rk3066b does support any pulls */
  2085. if (ctrl->type == RK3066B)
  2086. return PIN_CONFIG_BIAS_DISABLE;
  2087. ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
  2088. ret = regmap_read(regmap, reg, &data);
  2089. if (ret)
  2090. return ret;
  2091. switch (ctrl->type) {
  2092. case RK2928:
  2093. case RK3128:
  2094. return !(data & BIT(bit))
  2095. ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
  2096. : PIN_CONFIG_BIAS_DISABLE;
  2097. case PX30:
  2098. case RV1108:
  2099. case RK3188:
  2100. case RK3288:
  2101. case RK3308:
  2102. case RK3368:
  2103. case RK3399:
  2104. pull_type = bank->pull_type[pin_num / 8];
  2105. data >>= bit;
  2106. data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
  2107. return rockchip_pull_list[pull_type][data];
  2108. default:
  2109. dev_err(info->dev, "unsupported pinctrl type\n");
  2110. return -EINVAL;
  2111. };
  2112. }
  2113. static int rockchip_set_pull(struct rockchip_pin_bank *bank,
  2114. int pin_num, int pull)
  2115. {
  2116. struct rockchip_pinctrl *info = bank->drvdata;
  2117. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  2118. struct regmap *regmap;
  2119. int reg, ret, i, pull_type;
  2120. u8 bit;
  2121. u32 data, rmask;
  2122. dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
  2123. bank->bank_num, pin_num, pull);
  2124. /* rk3066b does support any pulls */
  2125. if (ctrl->type == RK3066B)
  2126. return pull ? -EINVAL : 0;
  2127. ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
  2128. switch (ctrl->type) {
  2129. case RK2928:
  2130. case RK3128:
  2131. data = BIT(bit + 16);
  2132. if (pull == PIN_CONFIG_BIAS_DISABLE)
  2133. data |= BIT(bit);
  2134. ret = regmap_write(regmap, reg, data);
  2135. break;
  2136. case PX30:
  2137. case RV1108:
  2138. case RK3188:
  2139. case RK3288:
  2140. case RK3308:
  2141. case RK3368:
  2142. case RK3399:
  2143. pull_type = bank->pull_type[pin_num / 8];
  2144. ret = -EINVAL;
  2145. for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
  2146. i++) {
  2147. if (rockchip_pull_list[pull_type][i] == pull) {
  2148. ret = i;
  2149. break;
  2150. }
  2151. }
  2152. if (ret < 0) {
  2153. dev_err(info->dev, "unsupported pull setting %d\n",
  2154. pull);
  2155. return ret;
  2156. }
  2157. /* enable the write to the equivalent lower bits */
  2158. data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
  2159. rmask = data | (data >> 16);
  2160. data |= (ret << bit);
  2161. ret = regmap_update_bits(regmap, reg, rmask, data);
  2162. break;
  2163. default:
  2164. dev_err(info->dev, "unsupported pinctrl type\n");
  2165. return -EINVAL;
  2166. }
  2167. return ret;
  2168. }
  2169. #define RK3328_SCHMITT_BITS_PER_PIN 1
  2170. #define RK3328_SCHMITT_PINS_PER_REG 16
  2171. #define RK3328_SCHMITT_BANK_STRIDE 8
  2172. #define RK3328_SCHMITT_GRF_OFFSET 0x380
  2173. static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
  2174. int pin_num,
  2175. struct regmap **regmap,
  2176. int *reg, u8 *bit)
  2177. {
  2178. struct rockchip_pinctrl *info = bank->drvdata;
  2179. *regmap = info->regmap_base;
  2180. *reg = RK3328_SCHMITT_GRF_OFFSET;
  2181. *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
  2182. *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
  2183. *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
  2184. return 0;
  2185. }
  2186. static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
  2187. {
  2188. struct rockchip_pinctrl *info = bank->drvdata;
  2189. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  2190. struct regmap *regmap;
  2191. int reg, ret;
  2192. u8 bit;
  2193. u32 data;
  2194. ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
  2195. if (ret)
  2196. return ret;
  2197. ret = regmap_read(regmap, reg, &data);
  2198. if (ret)
  2199. return ret;
  2200. data >>= bit;
  2201. return data & 0x1;
  2202. }
  2203. static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
  2204. int pin_num, int enable)
  2205. {
  2206. struct rockchip_pinctrl *info = bank->drvdata;
  2207. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  2208. struct regmap *regmap;
  2209. int reg, ret;
  2210. u8 bit;
  2211. u32 data, rmask;
  2212. dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
  2213. bank->bank_num, pin_num, enable);
  2214. ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
  2215. if (ret)
  2216. return ret;
  2217. /* enable the write to the equivalent lower bits */
  2218. data = BIT(bit + 16) | (enable << bit);
  2219. rmask = BIT(bit + 16) | BIT(bit);
  2220. return regmap_update_bits(regmap, reg, rmask, data);
  2221. }
  2222. /*
  2223. * Pinmux_ops handling
  2224. */
  2225. static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
  2226. {
  2227. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  2228. return info->nfunctions;
  2229. }
  2230. static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
  2231. unsigned selector)
  2232. {
  2233. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  2234. return info->functions[selector].name;
  2235. }
  2236. static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
  2237. unsigned selector, const char * const **groups,
  2238. unsigned * const num_groups)
  2239. {
  2240. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  2241. *groups = info->functions[selector].groups;
  2242. *num_groups = info->functions[selector].ngroups;
  2243. return 0;
  2244. }
  2245. static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
  2246. unsigned group)
  2247. {
  2248. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  2249. const unsigned int *pins = info->groups[group].pins;
  2250. const struct rockchip_pin_config *data = info->groups[group].data;
  2251. struct rockchip_pin_bank *bank;
  2252. int cnt, ret = 0;
  2253. dev_dbg(info->dev, "enable function %s group %s\n",
  2254. info->functions[selector].name, info->groups[group].name);
  2255. /*
  2256. * for each pin in the pin group selected, program the corresponding
  2257. * pin function number in the config register.
  2258. */
  2259. for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
  2260. bank = pin_to_bank(info, pins[cnt]);
  2261. ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
  2262. data[cnt].func);
  2263. if (ret)
  2264. break;
  2265. }
  2266. if (ret) {
  2267. /* revert the already done pin settings */
  2268. for (cnt--; cnt >= 0; cnt--)
  2269. rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
  2270. return ret;
  2271. }
  2272. return 0;
  2273. }
  2274. static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  2275. {
  2276. struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
  2277. u32 data;
  2278. int ret;
  2279. ret = clk_enable(bank->clk);
  2280. if (ret < 0) {
  2281. dev_err(bank->drvdata->dev,
  2282. "failed to enable clock for bank %s\n", bank->name);
  2283. return ret;
  2284. }
  2285. data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
  2286. clk_disable(bank->clk);
  2287. if (data & BIT(offset))
  2288. return GPIO_LINE_DIRECTION_OUT;
  2289. return GPIO_LINE_DIRECTION_IN;
  2290. }
  2291. /*
  2292. * The calls to gpio_direction_output() and gpio_direction_input()
  2293. * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
  2294. * function called from the gpiolib interface).
  2295. */
  2296. static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
  2297. int pin, bool input)
  2298. {
  2299. struct rockchip_pin_bank *bank;
  2300. int ret;
  2301. unsigned long flags;
  2302. u32 data;
  2303. bank = gpiochip_get_data(chip);
  2304. ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
  2305. if (ret < 0)
  2306. return ret;
  2307. clk_enable(bank->clk);
  2308. raw_spin_lock_irqsave(&bank->slock, flags);
  2309. data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
  2310. /* set bit to 1 for output, 0 for input */
  2311. if (!input)
  2312. data |= BIT(pin);
  2313. else
  2314. data &= ~BIT(pin);
  2315. writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
  2316. raw_spin_unlock_irqrestore(&bank->slock, flags);
  2317. clk_disable(bank->clk);
  2318. return 0;
  2319. }
  2320. static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  2321. struct pinctrl_gpio_range *range,
  2322. unsigned offset, bool input)
  2323. {
  2324. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  2325. struct gpio_chip *chip;
  2326. int pin;
  2327. chip = range->gc;
  2328. pin = offset - chip->base;
  2329. dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
  2330. offset, range->name, pin, input ? "input" : "output");
  2331. return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
  2332. input);
  2333. }
  2334. static const struct pinmux_ops rockchip_pmx_ops = {
  2335. .get_functions_count = rockchip_pmx_get_funcs_count,
  2336. .get_function_name = rockchip_pmx_get_func_name,
  2337. .get_function_groups = rockchip_pmx_get_groups,
  2338. .set_mux = rockchip_pmx_set,
  2339. .gpio_set_direction = rockchip_pmx_gpio_set_direction,
  2340. };
  2341. /*
  2342. * Pinconf_ops handling
  2343. */
  2344. static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
  2345. enum pin_config_param pull)
  2346. {
  2347. switch (ctrl->type) {
  2348. case RK2928:
  2349. case RK3128:
  2350. return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
  2351. pull == PIN_CONFIG_BIAS_DISABLE);
  2352. case RK3066B:
  2353. return pull ? false : true;
  2354. case PX30:
  2355. case RV1108:
  2356. case RK3188:
  2357. case RK3288:
  2358. case RK3308:
  2359. case RK3368:
  2360. case RK3399:
  2361. return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
  2362. }
  2363. return false;
  2364. }
  2365. static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
  2366. static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
  2367. /* set the pin config settings for a specified pin */
  2368. static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  2369. unsigned long *configs, unsigned num_configs)
  2370. {
  2371. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  2372. struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
  2373. enum pin_config_param param;
  2374. u32 arg;
  2375. int i;
  2376. int rc;
  2377. for (i = 0; i < num_configs; i++) {
  2378. param = pinconf_to_config_param(configs[i]);
  2379. arg = pinconf_to_config_argument(configs[i]);
  2380. switch (param) {
  2381. case PIN_CONFIG_BIAS_DISABLE:
  2382. rc = rockchip_set_pull(bank, pin - bank->pin_base,
  2383. param);
  2384. if (rc)
  2385. return rc;
  2386. break;
  2387. case PIN_CONFIG_BIAS_PULL_UP:
  2388. case PIN_CONFIG_BIAS_PULL_DOWN:
  2389. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  2390. case PIN_CONFIG_BIAS_BUS_HOLD:
  2391. if (!rockchip_pinconf_pull_valid(info->ctrl, param))
  2392. return -ENOTSUPP;
  2393. if (!arg)
  2394. return -EINVAL;
  2395. rc = rockchip_set_pull(bank, pin - bank->pin_base,
  2396. param);
  2397. if (rc)
  2398. return rc;
  2399. break;
  2400. case PIN_CONFIG_OUTPUT:
  2401. rockchip_gpio_set(&bank->gpio_chip,
  2402. pin - bank->pin_base, arg);
  2403. rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
  2404. pin - bank->pin_base, false);
  2405. if (rc)
  2406. return rc;
  2407. break;
  2408. case PIN_CONFIG_DRIVE_STRENGTH:
  2409. /* rk3288 is the first with per-pin drive-strength */
  2410. if (!info->ctrl->drv_calc_reg)
  2411. return -ENOTSUPP;
  2412. rc = rockchip_set_drive_perpin(bank,
  2413. pin - bank->pin_base, arg);
  2414. if (rc < 0)
  2415. return rc;
  2416. break;
  2417. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  2418. if (!info->ctrl->schmitt_calc_reg)
  2419. return -ENOTSUPP;
  2420. rc = rockchip_set_schmitt(bank,
  2421. pin - bank->pin_base, arg);
  2422. if (rc < 0)
  2423. return rc;
  2424. break;
  2425. default:
  2426. return -ENOTSUPP;
  2427. break;
  2428. }
  2429. } /* for each config */
  2430. return 0;
  2431. }
  2432. /* get the pin config settings for a specified pin */
  2433. static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
  2434. unsigned long *config)
  2435. {
  2436. struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  2437. struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
  2438. enum pin_config_param param = pinconf_to_config_param(*config);
  2439. u16 arg;
  2440. int rc;
  2441. switch (param) {
  2442. case PIN_CONFIG_BIAS_DISABLE:
  2443. if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
  2444. return -EINVAL;
  2445. arg = 0;
  2446. break;
  2447. case PIN_CONFIG_BIAS_PULL_UP:
  2448. case PIN_CONFIG_BIAS_PULL_DOWN:
  2449. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  2450. case PIN_CONFIG_BIAS_BUS_HOLD:
  2451. if (!rockchip_pinconf_pull_valid(info->ctrl, param))
  2452. return -ENOTSUPP;
  2453. if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
  2454. return -EINVAL;
  2455. arg = 1;
  2456. break;
  2457. case PIN_CONFIG_OUTPUT:
  2458. rc = rockchip_get_mux(bank, pin - bank->pin_base);
  2459. if (rc != RK_FUNC_GPIO)
  2460. return -EINVAL;
  2461. rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
  2462. if (rc < 0)
  2463. return rc;
  2464. arg = rc ? 1 : 0;
  2465. break;
  2466. case PIN_CONFIG_DRIVE_STRENGTH:
  2467. /* rk3288 is the first with per-pin drive-strength */
  2468. if (!info->ctrl->drv_calc_reg)
  2469. return -ENOTSUPP;
  2470. rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
  2471. if (rc < 0)
  2472. return rc;
  2473. arg = rc;
  2474. break;
  2475. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  2476. if (!info->ctrl->schmitt_calc_reg)
  2477. return -ENOTSUPP;
  2478. rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
  2479. if (rc < 0)
  2480. return rc;
  2481. arg = rc;
  2482. break;
  2483. default:
  2484. return -ENOTSUPP;
  2485. break;
  2486. }
  2487. *config = pinconf_to_config_packed(param, arg);
  2488. return 0;
  2489. }
  2490. static const struct pinconf_ops rockchip_pinconf_ops = {
  2491. .pin_config_get = rockchip_pinconf_get,
  2492. .pin_config_set = rockchip_pinconf_set,
  2493. .is_generic = true,
  2494. };
  2495. static const struct of_device_id rockchip_bank_match[] = {
  2496. { .compatible = "rockchip,gpio-bank" },
  2497. { .compatible = "rockchip,rk3188-gpio-bank0" },
  2498. {},
  2499. };
  2500. static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
  2501. struct device_node *np)
  2502. {
  2503. struct device_node *child;
  2504. for_each_child_of_node(np, child) {
  2505. if (of_match_node(rockchip_bank_match, child))
  2506. continue;
  2507. info->nfunctions++;
  2508. info->ngroups += of_get_child_count(child);
  2509. }
  2510. }
  2511. static int rockchip_pinctrl_parse_groups(struct device_node *np,
  2512. struct rockchip_pin_group *grp,
  2513. struct rockchip_pinctrl *info,
  2514. u32 index)
  2515. {
  2516. struct rockchip_pin_bank *bank;
  2517. int size;
  2518. const __be32 *list;
  2519. int num;
  2520. int i, j;
  2521. int ret;
  2522. dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
  2523. /* Initialise group */
  2524. grp->name = np->name;
  2525. /*
  2526. * the binding format is rockchip,pins = <bank pin mux CONFIG>,
  2527. * do sanity check and calculate pins number
  2528. */
  2529. list = of_get_property(np, "rockchip,pins", &size);
  2530. /* we do not check return since it's safe node passed down */
  2531. size /= sizeof(*list);
  2532. if (!size || size % 4) {
  2533. dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
  2534. return -EINVAL;
  2535. }
  2536. grp->npins = size / 4;
  2537. grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
  2538. GFP_KERNEL);
  2539. grp->data = devm_kcalloc(info->dev,
  2540. grp->npins,
  2541. sizeof(struct rockchip_pin_config),
  2542. GFP_KERNEL);
  2543. if (!grp->pins || !grp->data)
  2544. return -ENOMEM;
  2545. for (i = 0, j = 0; i < size; i += 4, j++) {
  2546. const __be32 *phandle;
  2547. struct device_node *np_config;
  2548. num = be32_to_cpu(*list++);
  2549. bank = bank_num_to_bank(info, num);
  2550. if (IS_ERR(bank))
  2551. return PTR_ERR(bank);
  2552. grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
  2553. grp->data[j].func = be32_to_cpu(*list++);
  2554. phandle = list++;
  2555. if (!phandle)
  2556. return -EINVAL;
  2557. np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
  2558. ret = pinconf_generic_parse_dt_config(np_config, NULL,
  2559. &grp->data[j].configs, &grp->data[j].nconfigs);
  2560. if (ret)
  2561. return ret;
  2562. }
  2563. return 0;
  2564. }
  2565. static int rockchip_pinctrl_parse_functions(struct device_node *np,
  2566. struct rockchip_pinctrl *info,
  2567. u32 index)
  2568. {
  2569. struct device_node *child;
  2570. struct rockchip_pmx_func *func;
  2571. struct rockchip_pin_group *grp;
  2572. int ret;
  2573. static u32 grp_index;
  2574. u32 i = 0;
  2575. dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
  2576. func = &info->functions[index];
  2577. /* Initialise function */
  2578. func->name = np->name;
  2579. func->ngroups = of_get_child_count(np);
  2580. if (func->ngroups <= 0)
  2581. return 0;
  2582. func->groups = devm_kcalloc(info->dev,
  2583. func->ngroups, sizeof(char *), GFP_KERNEL);
  2584. if (!func->groups)
  2585. return -ENOMEM;
  2586. for_each_child_of_node(np, child) {
  2587. func->groups[i] = child->name;
  2588. grp = &info->groups[grp_index++];
  2589. ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
  2590. if (ret) {
  2591. of_node_put(child);
  2592. return ret;
  2593. }
  2594. }
  2595. return 0;
  2596. }
  2597. static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
  2598. struct rockchip_pinctrl *info)
  2599. {
  2600. struct device *dev = &pdev->dev;
  2601. struct device_node *np = dev->of_node;
  2602. struct device_node *child;
  2603. int ret;
  2604. int i;
  2605. rockchip_pinctrl_child_count(info, np);
  2606. dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
  2607. dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
  2608. info->functions = devm_kcalloc(dev,
  2609. info->nfunctions,
  2610. sizeof(struct rockchip_pmx_func),
  2611. GFP_KERNEL);
  2612. if (!info->functions)
  2613. return -ENOMEM;
  2614. info->groups = devm_kcalloc(dev,
  2615. info->ngroups,
  2616. sizeof(struct rockchip_pin_group),
  2617. GFP_KERNEL);
  2618. if (!info->groups)
  2619. return -ENOMEM;
  2620. i = 0;
  2621. for_each_child_of_node(np, child) {
  2622. if (of_match_node(rockchip_bank_match, child))
  2623. continue;
  2624. ret = rockchip_pinctrl_parse_functions(child, info, i++);
  2625. if (ret) {
  2626. dev_err(&pdev->dev, "failed to parse function\n");
  2627. of_node_put(child);
  2628. return ret;
  2629. }
  2630. }
  2631. return 0;
  2632. }
  2633. static int rockchip_pinctrl_register(struct platform_device *pdev,
  2634. struct rockchip_pinctrl *info)
  2635. {
  2636. struct pinctrl_desc *ctrldesc = &info->pctl;
  2637. struct pinctrl_pin_desc *pindesc, *pdesc;
  2638. struct rockchip_pin_bank *pin_bank;
  2639. int pin, bank, ret;
  2640. int k;
  2641. ctrldesc->name = "rockchip-pinctrl";
  2642. ctrldesc->owner = THIS_MODULE;
  2643. ctrldesc->pctlops = &rockchip_pctrl_ops;
  2644. ctrldesc->pmxops = &rockchip_pmx_ops;
  2645. ctrldesc->confops = &rockchip_pinconf_ops;
  2646. pindesc = devm_kcalloc(&pdev->dev,
  2647. info->ctrl->nr_pins, sizeof(*pindesc),
  2648. GFP_KERNEL);
  2649. if (!pindesc)
  2650. return -ENOMEM;
  2651. ctrldesc->pins = pindesc;
  2652. ctrldesc->npins = info->ctrl->nr_pins;
  2653. pdesc = pindesc;
  2654. for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
  2655. pin_bank = &info->ctrl->pin_banks[bank];
  2656. for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
  2657. pdesc->number = k;
  2658. pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
  2659. pin_bank->name, pin);
  2660. pdesc++;
  2661. }
  2662. }
  2663. ret = rockchip_pinctrl_parse_dt(pdev, info);
  2664. if (ret)
  2665. return ret;
  2666. info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
  2667. if (IS_ERR(info->pctl_dev)) {
  2668. dev_err(&pdev->dev, "could not register pinctrl driver\n");
  2669. return PTR_ERR(info->pctl_dev);
  2670. }
  2671. for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
  2672. pin_bank = &info->ctrl->pin_banks[bank];
  2673. pin_bank->grange.name = pin_bank->name;
  2674. pin_bank->grange.id = bank;
  2675. pin_bank->grange.pin_base = pin_bank->pin_base;
  2676. pin_bank->grange.base = pin_bank->gpio_chip.base;
  2677. pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
  2678. pin_bank->grange.gc = &pin_bank->gpio_chip;
  2679. pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
  2680. }
  2681. return 0;
  2682. }
  2683. /*
  2684. * GPIO handling
  2685. */
  2686. static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
  2687. {
  2688. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  2689. void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
  2690. unsigned long flags;
  2691. u32 data;
  2692. clk_enable(bank->clk);
  2693. raw_spin_lock_irqsave(&bank->slock, flags);
  2694. data = readl(reg);
  2695. data &= ~BIT(offset);
  2696. if (value)
  2697. data |= BIT(offset);
  2698. writel(data, reg);
  2699. raw_spin_unlock_irqrestore(&bank->slock, flags);
  2700. clk_disable(bank->clk);
  2701. }
  2702. /*
  2703. * Returns the level of the pin for input direction and setting of the DR
  2704. * register for output gpios.
  2705. */
  2706. static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
  2707. {
  2708. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  2709. u32 data;
  2710. clk_enable(bank->clk);
  2711. data = readl(bank->reg_base + GPIO_EXT_PORT);
  2712. clk_disable(bank->clk);
  2713. data >>= offset;
  2714. data &= 1;
  2715. return data;
  2716. }
  2717. /*
  2718. * gpiolib gpio_direction_input callback function. The setting of the pin
  2719. * mux function as 'gpio input' will be handled by the pinctrl subsystem
  2720. * interface.
  2721. */
  2722. static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  2723. {
  2724. return pinctrl_gpio_direction_input(gc->base + offset);
  2725. }
  2726. /*
  2727. * gpiolib gpio_direction_output callback function. The setting of the pin
  2728. * mux function as 'gpio output' will be handled by the pinctrl subsystem
  2729. * interface.
  2730. */
  2731. static int rockchip_gpio_direction_output(struct gpio_chip *gc,
  2732. unsigned offset, int value)
  2733. {
  2734. rockchip_gpio_set(gc, offset, value);
  2735. return pinctrl_gpio_direction_output(gc->base + offset);
  2736. }
  2737. static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
  2738. unsigned int offset, bool enable)
  2739. {
  2740. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  2741. void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
  2742. unsigned long flags;
  2743. u32 data;
  2744. clk_enable(bank->clk);
  2745. raw_spin_lock_irqsave(&bank->slock, flags);
  2746. data = readl(reg);
  2747. if (enable)
  2748. data |= BIT(offset);
  2749. else
  2750. data &= ~BIT(offset);
  2751. writel(data, reg);
  2752. raw_spin_unlock_irqrestore(&bank->slock, flags);
  2753. clk_disable(bank->clk);
  2754. }
  2755. /*
  2756. * gpiolib set_config callback function. The setting of the pin
  2757. * mux function as 'gpio output' will be handled by the pinctrl subsystem
  2758. * interface.
  2759. */
  2760. static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
  2761. unsigned long config)
  2762. {
  2763. enum pin_config_param param = pinconf_to_config_param(config);
  2764. switch (param) {
  2765. case PIN_CONFIG_INPUT_DEBOUNCE:
  2766. rockchip_gpio_set_debounce(gc, offset, true);
  2767. /*
  2768. * Rockchip's gpio could only support up to one period
  2769. * of the debounce clock(pclk), which is far away from
  2770. * satisftying the requirement, as pclk is usually near
  2771. * 100MHz shared by all peripherals. So the fact is it
  2772. * has crippled debounce capability could only be useful
  2773. * to prevent any spurious glitches from waking up the system
  2774. * if the gpio is conguired as wakeup interrupt source. Let's
  2775. * still return -ENOTSUPP as before, to make sure the caller
  2776. * of gpiod_set_debounce won't change its behaviour.
  2777. */
  2778. return -ENOTSUPP;
  2779. default:
  2780. return -ENOTSUPP;
  2781. }
  2782. }
  2783. /*
  2784. * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
  2785. * and a virtual IRQ, if not already present.
  2786. */
  2787. static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
  2788. {
  2789. struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
  2790. unsigned int virq;
  2791. if (!bank->domain)
  2792. return -ENXIO;
  2793. clk_enable(bank->clk);
  2794. virq = irq_create_mapping(bank->domain, offset);
  2795. clk_disable(bank->clk);
  2796. return (virq) ? : -ENXIO;
  2797. }
  2798. static const struct gpio_chip rockchip_gpiolib_chip = {
  2799. .request = gpiochip_generic_request,
  2800. .free = gpiochip_generic_free,
  2801. .set = rockchip_gpio_set,
  2802. .get = rockchip_gpio_get,
  2803. .get_direction = rockchip_gpio_get_direction,
  2804. .direction_input = rockchip_gpio_direction_input,
  2805. .direction_output = rockchip_gpio_direction_output,
  2806. .set_config = rockchip_gpio_set_config,
  2807. .to_irq = rockchip_gpio_to_irq,
  2808. .owner = THIS_MODULE,
  2809. };
  2810. /*
  2811. * Interrupt handling
  2812. */
  2813. static void rockchip_irq_demux(struct irq_desc *desc)
  2814. {
  2815. struct irq_chip *chip = irq_desc_get_chip(desc);
  2816. struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
  2817. u32 pend;
  2818. dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
  2819. chained_irq_enter(chip, desc);
  2820. pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
  2821. while (pend) {
  2822. unsigned int irq, virq;
  2823. irq = __ffs(pend);
  2824. pend &= ~BIT(irq);
  2825. virq = irq_find_mapping(bank->domain, irq);
  2826. if (!virq) {
  2827. dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
  2828. continue;
  2829. }
  2830. dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
  2831. /*
  2832. * Triggering IRQ on both rising and falling edge
  2833. * needs manual intervention.
  2834. */
  2835. if (bank->toggle_edge_mode & BIT(irq)) {
  2836. u32 data, data_old, polarity;
  2837. unsigned long flags;
  2838. data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
  2839. do {
  2840. raw_spin_lock_irqsave(&bank->slock, flags);
  2841. polarity = readl_relaxed(bank->reg_base +
  2842. GPIO_INT_POLARITY);
  2843. if (data & BIT(irq))
  2844. polarity &= ~BIT(irq);
  2845. else
  2846. polarity |= BIT(irq);
  2847. writel(polarity,
  2848. bank->reg_base + GPIO_INT_POLARITY);
  2849. raw_spin_unlock_irqrestore(&bank->slock, flags);
  2850. data_old = data;
  2851. data = readl_relaxed(bank->reg_base +
  2852. GPIO_EXT_PORT);
  2853. } while ((data & BIT(irq)) != (data_old & BIT(irq)));
  2854. }
  2855. generic_handle_irq(virq);
  2856. }
  2857. chained_irq_exit(chip, desc);
  2858. }
  2859. static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
  2860. {
  2861. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  2862. struct rockchip_pin_bank *bank = gc->private;
  2863. u32 mask = BIT(d->hwirq);
  2864. u32 polarity;
  2865. u32 level;
  2866. u32 data;
  2867. unsigned long flags;
  2868. int ret;
  2869. /* make sure the pin is configured as gpio input */
  2870. ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
  2871. if (ret < 0)
  2872. return ret;
  2873. clk_enable(bank->clk);
  2874. raw_spin_lock_irqsave(&bank->slock, flags);
  2875. data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
  2876. data &= ~mask;
  2877. writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
  2878. raw_spin_unlock_irqrestore(&bank->slock, flags);
  2879. if (type & IRQ_TYPE_EDGE_BOTH)
  2880. irq_set_handler_locked(d, handle_edge_irq);
  2881. else
  2882. irq_set_handler_locked(d, handle_level_irq);
  2883. raw_spin_lock_irqsave(&bank->slock, flags);
  2884. irq_gc_lock(gc);
  2885. level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
  2886. polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
  2887. switch (type) {
  2888. case IRQ_TYPE_EDGE_BOTH:
  2889. bank->toggle_edge_mode |= mask;
  2890. level |= mask;
  2891. /*
  2892. * Determine gpio state. If 1 next interrupt should be falling
  2893. * otherwise rising.
  2894. */
  2895. data = readl(bank->reg_base + GPIO_EXT_PORT);
  2896. if (data & mask)
  2897. polarity &= ~mask;
  2898. else
  2899. polarity |= mask;
  2900. break;
  2901. case IRQ_TYPE_EDGE_RISING:
  2902. bank->toggle_edge_mode &= ~mask;
  2903. level |= mask;
  2904. polarity |= mask;
  2905. break;
  2906. case IRQ_TYPE_EDGE_FALLING:
  2907. bank->toggle_edge_mode &= ~mask;
  2908. level |= mask;
  2909. polarity &= ~mask;
  2910. break;
  2911. case IRQ_TYPE_LEVEL_HIGH:
  2912. bank->toggle_edge_mode &= ~mask;
  2913. level &= ~mask;
  2914. polarity |= mask;
  2915. break;
  2916. case IRQ_TYPE_LEVEL_LOW:
  2917. bank->toggle_edge_mode &= ~mask;
  2918. level &= ~mask;
  2919. polarity &= ~mask;
  2920. break;
  2921. default:
  2922. irq_gc_unlock(gc);
  2923. raw_spin_unlock_irqrestore(&bank->slock, flags);
  2924. clk_disable(bank->clk);
  2925. return -EINVAL;
  2926. }
  2927. writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
  2928. writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
  2929. irq_gc_unlock(gc);
  2930. raw_spin_unlock_irqrestore(&bank->slock, flags);
  2931. clk_disable(bank->clk);
  2932. return 0;
  2933. }
  2934. static void rockchip_irq_suspend(struct irq_data *d)
  2935. {
  2936. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  2937. struct rockchip_pin_bank *bank = gc->private;
  2938. clk_enable(bank->clk);
  2939. bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
  2940. irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
  2941. clk_disable(bank->clk);
  2942. }
  2943. static void rockchip_irq_resume(struct irq_data *d)
  2944. {
  2945. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  2946. struct rockchip_pin_bank *bank = gc->private;
  2947. clk_enable(bank->clk);
  2948. irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
  2949. clk_disable(bank->clk);
  2950. }
  2951. static void rockchip_irq_enable(struct irq_data *d)
  2952. {
  2953. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  2954. struct rockchip_pin_bank *bank = gc->private;
  2955. clk_enable(bank->clk);
  2956. irq_gc_mask_clr_bit(d);
  2957. }
  2958. static void rockchip_irq_disable(struct irq_data *d)
  2959. {
  2960. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  2961. struct rockchip_pin_bank *bank = gc->private;
  2962. irq_gc_mask_set_bit(d);
  2963. clk_disable(bank->clk);
  2964. }
  2965. static int rockchip_interrupts_register(struct platform_device *pdev,
  2966. struct rockchip_pinctrl *info)
  2967. {
  2968. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  2969. struct rockchip_pin_bank *bank = ctrl->pin_banks;
  2970. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  2971. struct irq_chip_generic *gc;
  2972. int ret;
  2973. int i;
  2974. for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
  2975. if (!bank->valid) {
  2976. dev_warn(&pdev->dev, "bank %s is not valid\n",
  2977. bank->name);
  2978. continue;
  2979. }
  2980. ret = clk_enable(bank->clk);
  2981. if (ret) {
  2982. dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
  2983. bank->name);
  2984. continue;
  2985. }
  2986. bank->domain = irq_domain_add_linear(bank->of_node, 32,
  2987. &irq_generic_chip_ops, NULL);
  2988. if (!bank->domain) {
  2989. dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
  2990. bank->name);
  2991. clk_disable(bank->clk);
  2992. continue;
  2993. }
  2994. ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
  2995. "rockchip_gpio_irq", handle_level_irq,
  2996. clr, 0, 0);
  2997. if (ret) {
  2998. dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
  2999. bank->name);
  3000. irq_domain_remove(bank->domain);
  3001. clk_disable(bank->clk);
  3002. continue;
  3003. }
  3004. gc = irq_get_domain_generic_chip(bank->domain, 0);
  3005. gc->reg_base = bank->reg_base;
  3006. gc->private = bank;
  3007. gc->chip_types[0].regs.mask = GPIO_INTMASK;
  3008. gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
  3009. gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
  3010. gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
  3011. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
  3012. gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
  3013. gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
  3014. gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
  3015. gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
  3016. gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
  3017. gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
  3018. gc->wake_enabled = IRQ_MSK(bank->nr_pins);
  3019. /*
  3020. * Linux assumes that all interrupts start out disabled/masked.
  3021. * Our driver only uses the concept of masked and always keeps
  3022. * things enabled, so for us that's all masked and all enabled.
  3023. */
  3024. writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
  3025. writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
  3026. gc->mask_cache = 0xffffffff;
  3027. irq_set_chained_handler_and_data(bank->irq,
  3028. rockchip_irq_demux, bank);
  3029. clk_disable(bank->clk);
  3030. }
  3031. return 0;
  3032. }
  3033. static int rockchip_gpiolib_register(struct platform_device *pdev,
  3034. struct rockchip_pinctrl *info)
  3035. {
  3036. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  3037. struct rockchip_pin_bank *bank = ctrl->pin_banks;
  3038. struct gpio_chip *gc;
  3039. int ret;
  3040. int i;
  3041. for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
  3042. if (!bank->valid) {
  3043. dev_warn(&pdev->dev, "bank %s is not valid\n",
  3044. bank->name);
  3045. continue;
  3046. }
  3047. bank->gpio_chip = rockchip_gpiolib_chip;
  3048. gc = &bank->gpio_chip;
  3049. gc->base = bank->pin_base;
  3050. gc->ngpio = bank->nr_pins;
  3051. gc->parent = &pdev->dev;
  3052. gc->of_node = bank->of_node;
  3053. gc->label = bank->name;
  3054. ret = gpiochip_add_data(gc, bank);
  3055. if (ret) {
  3056. dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
  3057. gc->label, ret);
  3058. goto fail;
  3059. }
  3060. }
  3061. rockchip_interrupts_register(pdev, info);
  3062. return 0;
  3063. fail:
  3064. for (--i, --bank; i >= 0; --i, --bank) {
  3065. if (!bank->valid)
  3066. continue;
  3067. gpiochip_remove(&bank->gpio_chip);
  3068. }
  3069. return ret;
  3070. }
  3071. static int rockchip_gpiolib_unregister(struct platform_device *pdev,
  3072. struct rockchip_pinctrl *info)
  3073. {
  3074. struct rockchip_pin_ctrl *ctrl = info->ctrl;
  3075. struct rockchip_pin_bank *bank = ctrl->pin_banks;
  3076. int i;
  3077. for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
  3078. if (!bank->valid)
  3079. continue;
  3080. gpiochip_remove(&bank->gpio_chip);
  3081. }
  3082. return 0;
  3083. }
  3084. static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
  3085. struct rockchip_pinctrl *info)
  3086. {
  3087. struct resource res;
  3088. void __iomem *base;
  3089. if (of_address_to_resource(bank->of_node, 0, &res)) {
  3090. dev_err(info->dev, "cannot find IO resource for bank\n");
  3091. return -ENOENT;
  3092. }
  3093. bank->reg_base = devm_ioremap_resource(info->dev, &res);
  3094. if (IS_ERR(bank->reg_base))
  3095. return PTR_ERR(bank->reg_base);
  3096. /*
  3097. * special case, where parts of the pull setting-registers are
  3098. * part of the PMU register space
  3099. */
  3100. if (of_device_is_compatible(bank->of_node,
  3101. "rockchip,rk3188-gpio-bank0")) {
  3102. struct device_node *node;
  3103. node = of_parse_phandle(bank->of_node->parent,
  3104. "rockchip,pmu", 0);
  3105. if (!node) {
  3106. if (of_address_to_resource(bank->of_node, 1, &res)) {
  3107. dev_err(info->dev, "cannot find IO resource for bank\n");
  3108. return -ENOENT;
  3109. }
  3110. base = devm_ioremap_resource(info->dev, &res);
  3111. if (IS_ERR(base))
  3112. return PTR_ERR(base);
  3113. rockchip_regmap_config.max_register =
  3114. resource_size(&res) - 4;
  3115. rockchip_regmap_config.name =
  3116. "rockchip,rk3188-gpio-bank0-pull";
  3117. bank->regmap_pull = devm_regmap_init_mmio(info->dev,
  3118. base,
  3119. &rockchip_regmap_config);
  3120. }
  3121. of_node_put(node);
  3122. }
  3123. bank->irq = irq_of_parse_and_map(bank->of_node, 0);
  3124. bank->clk = of_clk_get(bank->of_node, 0);
  3125. if (IS_ERR(bank->clk))
  3126. return PTR_ERR(bank->clk);
  3127. return clk_prepare(bank->clk);
  3128. }
  3129. static const struct of_device_id rockchip_pinctrl_dt_match[];
  3130. /* retrieve the soc specific data */
  3131. static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
  3132. struct rockchip_pinctrl *d,
  3133. struct platform_device *pdev)
  3134. {
  3135. const struct of_device_id *match;
  3136. struct device_node *node = pdev->dev.of_node;
  3137. struct device_node *np;
  3138. struct rockchip_pin_ctrl *ctrl;
  3139. struct rockchip_pin_bank *bank;
  3140. int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
  3141. match = of_match_node(rockchip_pinctrl_dt_match, node);
  3142. ctrl = (struct rockchip_pin_ctrl *)match->data;
  3143. for_each_child_of_node(node, np) {
  3144. if (!of_find_property(np, "gpio-controller", NULL))
  3145. continue;
  3146. bank = ctrl->pin_banks;
  3147. for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
  3148. if (!strcmp(bank->name, np->name)) {
  3149. bank->of_node = np;
  3150. if (!rockchip_get_bank_data(bank, d))
  3151. bank->valid = true;
  3152. break;
  3153. }
  3154. }
  3155. }
  3156. grf_offs = ctrl->grf_mux_offset;
  3157. pmu_offs = ctrl->pmu_mux_offset;
  3158. drv_pmu_offs = ctrl->pmu_drv_offset;
  3159. drv_grf_offs = ctrl->grf_drv_offset;
  3160. bank = ctrl->pin_banks;
  3161. for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
  3162. int bank_pins = 0;
  3163. raw_spin_lock_init(&bank->slock);
  3164. bank->drvdata = d;
  3165. bank->pin_base = ctrl->nr_pins;
  3166. ctrl->nr_pins += bank->nr_pins;
  3167. /* calculate iomux and drv offsets */
  3168. for (j = 0; j < 4; j++) {
  3169. struct rockchip_iomux *iom = &bank->iomux[j];
  3170. struct rockchip_drv *drv = &bank->drv[j];
  3171. int inc;
  3172. if (bank_pins >= bank->nr_pins)
  3173. break;
  3174. /* preset iomux offset value, set new start value */
  3175. if (iom->offset >= 0) {
  3176. if (iom->type & IOMUX_SOURCE_PMU)
  3177. pmu_offs = iom->offset;
  3178. else
  3179. grf_offs = iom->offset;
  3180. } else { /* set current iomux offset */
  3181. iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
  3182. pmu_offs : grf_offs;
  3183. }
  3184. /* preset drv offset value, set new start value */
  3185. if (drv->offset >= 0) {
  3186. if (iom->type & IOMUX_SOURCE_PMU)
  3187. drv_pmu_offs = drv->offset;
  3188. else
  3189. drv_grf_offs = drv->offset;
  3190. } else { /* set current drv offset */
  3191. drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
  3192. drv_pmu_offs : drv_grf_offs;
  3193. }
  3194. dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
  3195. i, j, iom->offset, drv->offset);
  3196. /*
  3197. * Increase offset according to iomux width.
  3198. * 4bit iomux'es are spread over two registers.
  3199. */
  3200. inc = (iom->type & (IOMUX_WIDTH_4BIT |
  3201. IOMUX_WIDTH_3BIT |
  3202. IOMUX_WIDTH_2BIT)) ? 8 : 4;
  3203. if (iom->type & IOMUX_SOURCE_PMU)
  3204. pmu_offs += inc;
  3205. else
  3206. grf_offs += inc;
  3207. /*
  3208. * Increase offset according to drv width.
  3209. * 3bit drive-strenth'es are spread over two registers.
  3210. */
  3211. if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
  3212. (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
  3213. inc = 8;
  3214. else
  3215. inc = 4;
  3216. if (iom->type & IOMUX_SOURCE_PMU)
  3217. drv_pmu_offs += inc;
  3218. else
  3219. drv_grf_offs += inc;
  3220. bank_pins += 8;
  3221. }
  3222. /* calculate the per-bank recalced_mask */
  3223. for (j = 0; j < ctrl->niomux_recalced; j++) {
  3224. int pin = 0;
  3225. if (ctrl->iomux_recalced[j].num == bank->bank_num) {
  3226. pin = ctrl->iomux_recalced[j].pin;
  3227. bank->recalced_mask |= BIT(pin);
  3228. }
  3229. }
  3230. /* calculate the per-bank route_mask */
  3231. for (j = 0; j < ctrl->niomux_routes; j++) {
  3232. int pin = 0;
  3233. if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
  3234. pin = ctrl->iomux_routes[j].pin;
  3235. bank->route_mask |= BIT(pin);
  3236. }
  3237. }
  3238. }
  3239. return ctrl;
  3240. }
  3241. #define RK3288_GRF_GPIO6C_IOMUX 0x64
  3242. #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
  3243. static u32 rk3288_grf_gpio6c_iomux;
  3244. static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
  3245. {
  3246. struct rockchip_pinctrl *info = dev_get_drvdata(dev);
  3247. int ret = pinctrl_force_sleep(info->pctl_dev);
  3248. if (ret)
  3249. return ret;
  3250. /*
  3251. * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
  3252. * the setting here, and restore it at resume.
  3253. */
  3254. if (info->ctrl->type == RK3288) {
  3255. ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
  3256. &rk3288_grf_gpio6c_iomux);
  3257. if (ret) {
  3258. pinctrl_force_default(info->pctl_dev);
  3259. return ret;
  3260. }
  3261. }
  3262. return 0;
  3263. }
  3264. static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
  3265. {
  3266. struct rockchip_pinctrl *info = dev_get_drvdata(dev);
  3267. int ret;
  3268. if (info->ctrl->type == RK3288) {
  3269. ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
  3270. rk3288_grf_gpio6c_iomux |
  3271. GPIO6C6_SEL_WRITE_ENABLE);
  3272. if (ret)
  3273. return ret;
  3274. }
  3275. return pinctrl_force_default(info->pctl_dev);
  3276. }
  3277. static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
  3278. rockchip_pinctrl_resume);
  3279. static int rockchip_pinctrl_probe(struct platform_device *pdev)
  3280. {
  3281. struct rockchip_pinctrl *info;
  3282. struct device *dev = &pdev->dev;
  3283. struct rockchip_pin_ctrl *ctrl;
  3284. struct device_node *np = pdev->dev.of_node, *node;
  3285. struct resource *res;
  3286. void __iomem *base;
  3287. int ret;
  3288. if (!dev->of_node) {
  3289. dev_err(dev, "device tree node not found\n");
  3290. return -ENODEV;
  3291. }
  3292. info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
  3293. if (!info)
  3294. return -ENOMEM;
  3295. info->dev = dev;
  3296. ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
  3297. if (!ctrl) {
  3298. dev_err(dev, "driver data not available\n");
  3299. return -EINVAL;
  3300. }
  3301. info->ctrl = ctrl;
  3302. node = of_parse_phandle(np, "rockchip,grf", 0);
  3303. if (node) {
  3304. info->regmap_base = syscon_node_to_regmap(node);
  3305. of_node_put(node);
  3306. if (IS_ERR(info->regmap_base))
  3307. return PTR_ERR(info->regmap_base);
  3308. } else {
  3309. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3310. base = devm_ioremap_resource(&pdev->dev, res);
  3311. if (IS_ERR(base))
  3312. return PTR_ERR(base);
  3313. rockchip_regmap_config.max_register = resource_size(res) - 4;
  3314. rockchip_regmap_config.name = "rockchip,pinctrl";
  3315. info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
  3316. &rockchip_regmap_config);
  3317. /* to check for the old dt-bindings */
  3318. info->reg_size = resource_size(res);
  3319. /* Honor the old binding, with pull registers as 2nd resource */
  3320. if (ctrl->type == RK3188 && info->reg_size < 0x200) {
  3321. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  3322. base = devm_ioremap_resource(&pdev->dev, res);
  3323. if (IS_ERR(base))
  3324. return PTR_ERR(base);
  3325. rockchip_regmap_config.max_register =
  3326. resource_size(res) - 4;
  3327. rockchip_regmap_config.name = "rockchip,pinctrl-pull";
  3328. info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
  3329. base,
  3330. &rockchip_regmap_config);
  3331. }
  3332. }
  3333. /* try to find the optional reference to the pmu syscon */
  3334. node = of_parse_phandle(np, "rockchip,pmu", 0);
  3335. if (node) {
  3336. info->regmap_pmu = syscon_node_to_regmap(node);
  3337. of_node_put(node);
  3338. if (IS_ERR(info->regmap_pmu))
  3339. return PTR_ERR(info->regmap_pmu);
  3340. }
  3341. ret = rockchip_gpiolib_register(pdev, info);
  3342. if (ret)
  3343. return ret;
  3344. ret = rockchip_pinctrl_register(pdev, info);
  3345. if (ret) {
  3346. rockchip_gpiolib_unregister(pdev, info);
  3347. return ret;
  3348. }
  3349. platform_set_drvdata(pdev, info);
  3350. return 0;
  3351. }
  3352. static struct rockchip_pin_bank px30_pin_banks[] = {
  3353. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
  3354. IOMUX_SOURCE_PMU,
  3355. IOMUX_SOURCE_PMU,
  3356. IOMUX_SOURCE_PMU
  3357. ),
  3358. PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
  3359. IOMUX_WIDTH_4BIT,
  3360. IOMUX_WIDTH_4BIT,
  3361. IOMUX_WIDTH_4BIT
  3362. ),
  3363. PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
  3364. IOMUX_WIDTH_4BIT,
  3365. IOMUX_WIDTH_4BIT,
  3366. IOMUX_WIDTH_4BIT
  3367. ),
  3368. PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
  3369. IOMUX_WIDTH_4BIT,
  3370. IOMUX_WIDTH_4BIT,
  3371. IOMUX_WIDTH_4BIT
  3372. ),
  3373. };
  3374. static struct rockchip_pin_ctrl px30_pin_ctrl = {
  3375. .pin_banks = px30_pin_banks,
  3376. .nr_banks = ARRAY_SIZE(px30_pin_banks),
  3377. .label = "PX30-GPIO",
  3378. .type = PX30,
  3379. .grf_mux_offset = 0x0,
  3380. .pmu_mux_offset = 0x0,
  3381. .iomux_routes = px30_mux_route_data,
  3382. .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
  3383. .pull_calc_reg = px30_calc_pull_reg_and_bit,
  3384. .drv_calc_reg = px30_calc_drv_reg_and_bit,
  3385. .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
  3386. };
  3387. static struct rockchip_pin_bank rv1108_pin_banks[] = {
  3388. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
  3389. IOMUX_SOURCE_PMU,
  3390. IOMUX_SOURCE_PMU,
  3391. IOMUX_SOURCE_PMU),
  3392. PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
  3393. PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
  3394. PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
  3395. };
  3396. static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
  3397. .pin_banks = rv1108_pin_banks,
  3398. .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
  3399. .label = "RV1108-GPIO",
  3400. .type = RV1108,
  3401. .grf_mux_offset = 0x10,
  3402. .pmu_mux_offset = 0x0,
  3403. .iomux_recalced = rv1108_mux_recalced_data,
  3404. .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
  3405. .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
  3406. .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
  3407. .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
  3408. };
  3409. static struct rockchip_pin_bank rk2928_pin_banks[] = {
  3410. PIN_BANK(0, 32, "gpio0"),
  3411. PIN_BANK(1, 32, "gpio1"),
  3412. PIN_BANK(2, 32, "gpio2"),
  3413. PIN_BANK(3, 32, "gpio3"),
  3414. };
  3415. static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
  3416. .pin_banks = rk2928_pin_banks,
  3417. .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
  3418. .label = "RK2928-GPIO",
  3419. .type = RK2928,
  3420. .grf_mux_offset = 0xa8,
  3421. .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
  3422. };
  3423. static struct rockchip_pin_bank rk3036_pin_banks[] = {
  3424. PIN_BANK(0, 32, "gpio0"),
  3425. PIN_BANK(1, 32, "gpio1"),
  3426. PIN_BANK(2, 32, "gpio2"),
  3427. };
  3428. static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
  3429. .pin_banks = rk3036_pin_banks,
  3430. .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
  3431. .label = "RK3036-GPIO",
  3432. .type = RK2928,
  3433. .grf_mux_offset = 0xa8,
  3434. .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
  3435. };
  3436. static struct rockchip_pin_bank rk3066a_pin_banks[] = {
  3437. PIN_BANK(0, 32, "gpio0"),
  3438. PIN_BANK(1, 32, "gpio1"),
  3439. PIN_BANK(2, 32, "gpio2"),
  3440. PIN_BANK(3, 32, "gpio3"),
  3441. PIN_BANK(4, 32, "gpio4"),
  3442. PIN_BANK(6, 16, "gpio6"),
  3443. };
  3444. static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
  3445. .pin_banks = rk3066a_pin_banks,
  3446. .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
  3447. .label = "RK3066a-GPIO",
  3448. .type = RK2928,
  3449. .grf_mux_offset = 0xa8,
  3450. .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
  3451. };
  3452. static struct rockchip_pin_bank rk3066b_pin_banks[] = {
  3453. PIN_BANK(0, 32, "gpio0"),
  3454. PIN_BANK(1, 32, "gpio1"),
  3455. PIN_BANK(2, 32, "gpio2"),
  3456. PIN_BANK(3, 32, "gpio3"),
  3457. };
  3458. static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
  3459. .pin_banks = rk3066b_pin_banks,
  3460. .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
  3461. .label = "RK3066b-GPIO",
  3462. .type = RK3066B,
  3463. .grf_mux_offset = 0x60,
  3464. };
  3465. static struct rockchip_pin_bank rk3128_pin_banks[] = {
  3466. PIN_BANK(0, 32, "gpio0"),
  3467. PIN_BANK(1, 32, "gpio1"),
  3468. PIN_BANK(2, 32, "gpio2"),
  3469. PIN_BANK(3, 32, "gpio3"),
  3470. };
  3471. static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
  3472. .pin_banks = rk3128_pin_banks,
  3473. .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
  3474. .label = "RK3128-GPIO",
  3475. .type = RK3128,
  3476. .grf_mux_offset = 0xa8,
  3477. .iomux_recalced = rk3128_mux_recalced_data,
  3478. .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
  3479. .iomux_routes = rk3128_mux_route_data,
  3480. .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
  3481. .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
  3482. };
  3483. static struct rockchip_pin_bank rk3188_pin_banks[] = {
  3484. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
  3485. PIN_BANK(1, 32, "gpio1"),
  3486. PIN_BANK(2, 32, "gpio2"),
  3487. PIN_BANK(3, 32, "gpio3"),
  3488. };
  3489. static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
  3490. .pin_banks = rk3188_pin_banks,
  3491. .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
  3492. .label = "RK3188-GPIO",
  3493. .type = RK3188,
  3494. .grf_mux_offset = 0x60,
  3495. .iomux_routes = rk3188_mux_route_data,
  3496. .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
  3497. .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
  3498. };
  3499. static struct rockchip_pin_bank rk3228_pin_banks[] = {
  3500. PIN_BANK(0, 32, "gpio0"),
  3501. PIN_BANK(1, 32, "gpio1"),
  3502. PIN_BANK(2, 32, "gpio2"),
  3503. PIN_BANK(3, 32, "gpio3"),
  3504. };
  3505. static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
  3506. .pin_banks = rk3228_pin_banks,
  3507. .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
  3508. .label = "RK3228-GPIO",
  3509. .type = RK3288,
  3510. .grf_mux_offset = 0x0,
  3511. .iomux_routes = rk3228_mux_route_data,
  3512. .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
  3513. .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
  3514. .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
  3515. };
  3516. static struct rockchip_pin_bank rk3288_pin_banks[] = {
  3517. PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
  3518. IOMUX_SOURCE_PMU,
  3519. IOMUX_SOURCE_PMU,
  3520. IOMUX_UNROUTED
  3521. ),
  3522. PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
  3523. IOMUX_UNROUTED,
  3524. IOMUX_UNROUTED,
  3525. 0
  3526. ),
  3527. PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
  3528. PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
  3529. PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
  3530. IOMUX_WIDTH_4BIT,
  3531. 0,
  3532. 0
  3533. ),
  3534. PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
  3535. 0,
  3536. 0,
  3537. IOMUX_UNROUTED
  3538. ),
  3539. PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
  3540. PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
  3541. 0,
  3542. IOMUX_WIDTH_4BIT,
  3543. IOMUX_UNROUTED
  3544. ),
  3545. PIN_BANK(8, 16, "gpio8"),
  3546. };
  3547. static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
  3548. .pin_banks = rk3288_pin_banks,
  3549. .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
  3550. .label = "RK3288-GPIO",
  3551. .type = RK3288,
  3552. .grf_mux_offset = 0x0,
  3553. .pmu_mux_offset = 0x84,
  3554. .iomux_routes = rk3288_mux_route_data,
  3555. .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
  3556. .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
  3557. .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
  3558. };
  3559. static struct rockchip_pin_bank rk3308_pin_banks[] = {
  3560. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
  3561. IOMUX_WIDTH_2BIT,
  3562. IOMUX_WIDTH_2BIT,
  3563. IOMUX_WIDTH_2BIT),
  3564. PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
  3565. IOMUX_WIDTH_2BIT,
  3566. IOMUX_WIDTH_2BIT,
  3567. IOMUX_WIDTH_2BIT),
  3568. PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
  3569. IOMUX_WIDTH_2BIT,
  3570. IOMUX_WIDTH_2BIT,
  3571. IOMUX_WIDTH_2BIT),
  3572. PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
  3573. IOMUX_WIDTH_2BIT,
  3574. IOMUX_WIDTH_2BIT,
  3575. IOMUX_WIDTH_2BIT),
  3576. PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
  3577. IOMUX_WIDTH_2BIT,
  3578. IOMUX_WIDTH_2BIT,
  3579. IOMUX_WIDTH_2BIT),
  3580. };
  3581. static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
  3582. .pin_banks = rk3308_pin_banks,
  3583. .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
  3584. .label = "RK3308-GPIO",
  3585. .type = RK3308,
  3586. .grf_mux_offset = 0x0,
  3587. .iomux_recalced = rk3308_mux_recalced_data,
  3588. .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
  3589. .iomux_routes = rk3308_mux_route_data,
  3590. .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
  3591. .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
  3592. .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
  3593. .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
  3594. };
  3595. static struct rockchip_pin_bank rk3328_pin_banks[] = {
  3596. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
  3597. PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
  3598. PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
  3599. IOMUX_WIDTH_3BIT,
  3600. IOMUX_WIDTH_3BIT,
  3601. 0),
  3602. PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
  3603. IOMUX_WIDTH_3BIT,
  3604. IOMUX_WIDTH_3BIT,
  3605. 0,
  3606. 0),
  3607. };
  3608. static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
  3609. .pin_banks = rk3328_pin_banks,
  3610. .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
  3611. .label = "RK3328-GPIO",
  3612. .type = RK3288,
  3613. .grf_mux_offset = 0x0,
  3614. .iomux_recalced = rk3328_mux_recalced_data,
  3615. .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
  3616. .iomux_routes = rk3328_mux_route_data,
  3617. .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
  3618. .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
  3619. .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
  3620. .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
  3621. };
  3622. static struct rockchip_pin_bank rk3368_pin_banks[] = {
  3623. PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
  3624. IOMUX_SOURCE_PMU,
  3625. IOMUX_SOURCE_PMU,
  3626. IOMUX_SOURCE_PMU
  3627. ),
  3628. PIN_BANK(1, 32, "gpio1"),
  3629. PIN_BANK(2, 32, "gpio2"),
  3630. PIN_BANK(3, 32, "gpio3"),
  3631. };
  3632. static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
  3633. .pin_banks = rk3368_pin_banks,
  3634. .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
  3635. .label = "RK3368-GPIO",
  3636. .type = RK3368,
  3637. .grf_mux_offset = 0x0,
  3638. .pmu_mux_offset = 0x0,
  3639. .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
  3640. .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
  3641. };
  3642. static struct rockchip_pin_bank rk3399_pin_banks[] = {
  3643. PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
  3644. IOMUX_SOURCE_PMU,
  3645. IOMUX_SOURCE_PMU,
  3646. IOMUX_SOURCE_PMU,
  3647. IOMUX_SOURCE_PMU,
  3648. DRV_TYPE_IO_1V8_ONLY,
  3649. DRV_TYPE_IO_1V8_ONLY,
  3650. DRV_TYPE_IO_DEFAULT,
  3651. DRV_TYPE_IO_DEFAULT,
  3652. 0x80,
  3653. 0x88,
  3654. -1,
  3655. -1,
  3656. PULL_TYPE_IO_1V8_ONLY,
  3657. PULL_TYPE_IO_1V8_ONLY,
  3658. PULL_TYPE_IO_DEFAULT,
  3659. PULL_TYPE_IO_DEFAULT
  3660. ),
  3661. PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
  3662. IOMUX_SOURCE_PMU,
  3663. IOMUX_SOURCE_PMU,
  3664. IOMUX_SOURCE_PMU,
  3665. DRV_TYPE_IO_1V8_OR_3V0,
  3666. DRV_TYPE_IO_1V8_OR_3V0,
  3667. DRV_TYPE_IO_1V8_OR_3V0,
  3668. DRV_TYPE_IO_1V8_OR_3V0,
  3669. 0xa0,
  3670. 0xa8,
  3671. 0xb0,
  3672. 0xb8
  3673. ),
  3674. PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
  3675. DRV_TYPE_IO_1V8_OR_3V0,
  3676. DRV_TYPE_IO_1V8_ONLY,
  3677. DRV_TYPE_IO_1V8_ONLY,
  3678. PULL_TYPE_IO_DEFAULT,
  3679. PULL_TYPE_IO_DEFAULT,
  3680. PULL_TYPE_IO_1V8_ONLY,
  3681. PULL_TYPE_IO_1V8_ONLY
  3682. ),
  3683. PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
  3684. DRV_TYPE_IO_3V3_ONLY,
  3685. DRV_TYPE_IO_3V3_ONLY,
  3686. DRV_TYPE_IO_1V8_OR_3V0
  3687. ),
  3688. PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
  3689. DRV_TYPE_IO_1V8_3V0_AUTO,
  3690. DRV_TYPE_IO_1V8_OR_3V0,
  3691. DRV_TYPE_IO_1V8_OR_3V0
  3692. ),
  3693. };
  3694. static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
  3695. .pin_banks = rk3399_pin_banks,
  3696. .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
  3697. .label = "RK3399-GPIO",
  3698. .type = RK3399,
  3699. .grf_mux_offset = 0xe000,
  3700. .pmu_mux_offset = 0x0,
  3701. .grf_drv_offset = 0xe100,
  3702. .pmu_drv_offset = 0x80,
  3703. .iomux_routes = rk3399_mux_route_data,
  3704. .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
  3705. .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
  3706. .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
  3707. };
  3708. static const struct of_device_id rockchip_pinctrl_dt_match[] = {
  3709. { .compatible = "rockchip,px30-pinctrl",
  3710. .data = &px30_pin_ctrl },
  3711. { .compatible = "rockchip,rv1108-pinctrl",
  3712. .data = &rv1108_pin_ctrl },
  3713. { .compatible = "rockchip,rk2928-pinctrl",
  3714. .data = &rk2928_pin_ctrl },
  3715. { .compatible = "rockchip,rk3036-pinctrl",
  3716. .data = &rk3036_pin_ctrl },
  3717. { .compatible = "rockchip,rk3066a-pinctrl",
  3718. .data = &rk3066a_pin_ctrl },
  3719. { .compatible = "rockchip,rk3066b-pinctrl",
  3720. .data = &rk3066b_pin_ctrl },
  3721. { .compatible = "rockchip,rk3128-pinctrl",
  3722. .data = (void *)&rk3128_pin_ctrl },
  3723. { .compatible = "rockchip,rk3188-pinctrl",
  3724. .data = &rk3188_pin_ctrl },
  3725. { .compatible = "rockchip,rk3228-pinctrl",
  3726. .data = &rk3228_pin_ctrl },
  3727. { .compatible = "rockchip,rk3288-pinctrl",
  3728. .data = &rk3288_pin_ctrl },
  3729. { .compatible = "rockchip,rk3308-pinctrl",
  3730. .data = &rk3308_pin_ctrl },
  3731. { .compatible = "rockchip,rk3328-pinctrl",
  3732. .data = &rk3328_pin_ctrl },
  3733. { .compatible = "rockchip,rk3368-pinctrl",
  3734. .data = &rk3368_pin_ctrl },
  3735. { .compatible = "rockchip,rk3399-pinctrl",
  3736. .data = &rk3399_pin_ctrl },
  3737. {},
  3738. };
  3739. static struct platform_driver rockchip_pinctrl_driver = {
  3740. .probe = rockchip_pinctrl_probe,
  3741. .driver = {
  3742. .name = "rockchip-pinctrl",
  3743. .pm = &rockchip_pinctrl_dev_pm_ops,
  3744. .of_match_table = rockchip_pinctrl_dt_match,
  3745. },
  3746. };
  3747. static int __init rockchip_pinctrl_drv_register(void)
  3748. {
  3749. return platform_driver_register(&rockchip_pinctrl_driver);
  3750. }
  3751. postcore_initcall(rockchip_pinctrl_drv_register);