pinctrl-oxnas.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Oxford Semiconductor OXNAS SoC Family pinctrl driver
  4. *
  5. * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
  6. *
  7. * Based on pinctrl-pic32.c
  8. * Joshua Henderson, <joshua.henderson@microchip.com>
  9. * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
  10. */
  11. #include <linux/gpio/driver.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/pinctrl/pinconf.h>
  18. #include <linux/pinctrl/pinconf-generic.h>
  19. #include <linux/pinctrl/pinctrl.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/regmap.h>
  24. #include <linux/mfd/syscon.h>
  25. #include "pinctrl-utils.h"
  26. #define PINS_PER_BANK 32
  27. #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
  28. /* OX810 Regmap Offsets */
  29. #define PINMUX_810_PRIMARY_SEL0 0x0c
  30. #define PINMUX_810_SECONDARY_SEL0 0x14
  31. #define PINMUX_810_TERTIARY_SEL0 0x8c
  32. #define PINMUX_810_PRIMARY_SEL1 0x10
  33. #define PINMUX_810_SECONDARY_SEL1 0x18
  34. #define PINMUX_810_TERTIARY_SEL1 0x90
  35. #define PINMUX_810_PULLUP_CTRL0 0xac
  36. #define PINMUX_810_PULLUP_CTRL1 0xb0
  37. /* OX820 Regmap Offsets */
  38. #define PINMUX_820_BANK_OFFSET 0x100000
  39. #define PINMUX_820_SECONDARY_SEL 0x14
  40. #define PINMUX_820_TERTIARY_SEL 0x8c
  41. #define PINMUX_820_QUATERNARY_SEL 0x94
  42. #define PINMUX_820_DEBUG_SEL 0x9c
  43. #define PINMUX_820_ALTERNATIVE_SEL 0xa4
  44. #define PINMUX_820_PULLUP_CTRL 0xac
  45. /* GPIO Registers */
  46. #define INPUT_VALUE 0x00
  47. #define OUTPUT_EN 0x04
  48. #define IRQ_PENDING 0x0c
  49. #define OUTPUT_SET 0x14
  50. #define OUTPUT_CLEAR 0x18
  51. #define OUTPUT_EN_SET 0x1c
  52. #define OUTPUT_EN_CLEAR 0x20
  53. #define RE_IRQ_ENABLE 0x28
  54. #define FE_IRQ_ENABLE 0x2c
  55. struct oxnas_function {
  56. const char *name;
  57. const char * const *groups;
  58. unsigned int ngroups;
  59. };
  60. struct oxnas_pin_group {
  61. const char *name;
  62. unsigned int pin;
  63. unsigned int bank;
  64. struct oxnas_desc_function *functions;
  65. };
  66. struct oxnas_desc_function {
  67. const char *name;
  68. unsigned int fct;
  69. };
  70. struct oxnas_gpio_bank {
  71. void __iomem *reg_base;
  72. struct gpio_chip gpio_chip;
  73. struct irq_chip irq_chip;
  74. unsigned int id;
  75. };
  76. struct oxnas_pinctrl {
  77. struct regmap *regmap;
  78. struct device *dev;
  79. struct pinctrl_dev *pctldev;
  80. const struct oxnas_function *functions;
  81. unsigned int nfunctions;
  82. const struct oxnas_pin_group *groups;
  83. unsigned int ngroups;
  84. struct oxnas_gpio_bank *gpio_banks;
  85. unsigned int nbanks;
  86. };
  87. struct oxnas_pinctrl_data {
  88. struct pinctrl_desc *desc;
  89. struct oxnas_pinctrl *pctl;
  90. };
  91. static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
  92. PINCTRL_PIN(0, "gpio0"),
  93. PINCTRL_PIN(1, "gpio1"),
  94. PINCTRL_PIN(2, "gpio2"),
  95. PINCTRL_PIN(3, "gpio3"),
  96. PINCTRL_PIN(4, "gpio4"),
  97. PINCTRL_PIN(5, "gpio5"),
  98. PINCTRL_PIN(6, "gpio6"),
  99. PINCTRL_PIN(7, "gpio7"),
  100. PINCTRL_PIN(8, "gpio8"),
  101. PINCTRL_PIN(9, "gpio9"),
  102. PINCTRL_PIN(10, "gpio10"),
  103. PINCTRL_PIN(11, "gpio11"),
  104. PINCTRL_PIN(12, "gpio12"),
  105. PINCTRL_PIN(13, "gpio13"),
  106. PINCTRL_PIN(14, "gpio14"),
  107. PINCTRL_PIN(15, "gpio15"),
  108. PINCTRL_PIN(16, "gpio16"),
  109. PINCTRL_PIN(17, "gpio17"),
  110. PINCTRL_PIN(18, "gpio18"),
  111. PINCTRL_PIN(19, "gpio19"),
  112. PINCTRL_PIN(20, "gpio20"),
  113. PINCTRL_PIN(21, "gpio21"),
  114. PINCTRL_PIN(22, "gpio22"),
  115. PINCTRL_PIN(23, "gpio23"),
  116. PINCTRL_PIN(24, "gpio24"),
  117. PINCTRL_PIN(25, "gpio25"),
  118. PINCTRL_PIN(26, "gpio26"),
  119. PINCTRL_PIN(27, "gpio27"),
  120. PINCTRL_PIN(28, "gpio28"),
  121. PINCTRL_PIN(29, "gpio29"),
  122. PINCTRL_PIN(30, "gpio30"),
  123. PINCTRL_PIN(31, "gpio31"),
  124. PINCTRL_PIN(32, "gpio32"),
  125. PINCTRL_PIN(33, "gpio33"),
  126. PINCTRL_PIN(34, "gpio34"),
  127. };
  128. static const struct pinctrl_pin_desc oxnas_ox820_pins[] = {
  129. PINCTRL_PIN(0, "gpio0"),
  130. PINCTRL_PIN(1, "gpio1"),
  131. PINCTRL_PIN(2, "gpio2"),
  132. PINCTRL_PIN(3, "gpio3"),
  133. PINCTRL_PIN(4, "gpio4"),
  134. PINCTRL_PIN(5, "gpio5"),
  135. PINCTRL_PIN(6, "gpio6"),
  136. PINCTRL_PIN(7, "gpio7"),
  137. PINCTRL_PIN(8, "gpio8"),
  138. PINCTRL_PIN(9, "gpio9"),
  139. PINCTRL_PIN(10, "gpio10"),
  140. PINCTRL_PIN(11, "gpio11"),
  141. PINCTRL_PIN(12, "gpio12"),
  142. PINCTRL_PIN(13, "gpio13"),
  143. PINCTRL_PIN(14, "gpio14"),
  144. PINCTRL_PIN(15, "gpio15"),
  145. PINCTRL_PIN(16, "gpio16"),
  146. PINCTRL_PIN(17, "gpio17"),
  147. PINCTRL_PIN(18, "gpio18"),
  148. PINCTRL_PIN(19, "gpio19"),
  149. PINCTRL_PIN(20, "gpio20"),
  150. PINCTRL_PIN(21, "gpio21"),
  151. PINCTRL_PIN(22, "gpio22"),
  152. PINCTRL_PIN(23, "gpio23"),
  153. PINCTRL_PIN(24, "gpio24"),
  154. PINCTRL_PIN(25, "gpio25"),
  155. PINCTRL_PIN(26, "gpio26"),
  156. PINCTRL_PIN(27, "gpio27"),
  157. PINCTRL_PIN(28, "gpio28"),
  158. PINCTRL_PIN(29, "gpio29"),
  159. PINCTRL_PIN(30, "gpio30"),
  160. PINCTRL_PIN(31, "gpio31"),
  161. PINCTRL_PIN(32, "gpio32"),
  162. PINCTRL_PIN(33, "gpio33"),
  163. PINCTRL_PIN(34, "gpio34"),
  164. PINCTRL_PIN(35, "gpio35"),
  165. PINCTRL_PIN(36, "gpio36"),
  166. PINCTRL_PIN(37, "gpio37"),
  167. PINCTRL_PIN(38, "gpio38"),
  168. PINCTRL_PIN(39, "gpio39"),
  169. PINCTRL_PIN(40, "gpio40"),
  170. PINCTRL_PIN(41, "gpio41"),
  171. PINCTRL_PIN(42, "gpio42"),
  172. PINCTRL_PIN(43, "gpio43"),
  173. PINCTRL_PIN(44, "gpio44"),
  174. PINCTRL_PIN(45, "gpio45"),
  175. PINCTRL_PIN(46, "gpio46"),
  176. PINCTRL_PIN(47, "gpio47"),
  177. PINCTRL_PIN(48, "gpio48"),
  178. PINCTRL_PIN(49, "gpio49"),
  179. };
  180. static const char * const oxnas_ox810se_fct0_group[] = {
  181. "gpio0", "gpio1", "gpio2", "gpio3",
  182. "gpio4", "gpio5", "gpio6", "gpio7",
  183. "gpio8", "gpio9", "gpio10", "gpio11",
  184. "gpio12", "gpio13", "gpio14", "gpio15",
  185. "gpio16", "gpio17", "gpio18", "gpio19",
  186. "gpio20", "gpio21", "gpio22", "gpio23",
  187. "gpio24", "gpio25", "gpio26", "gpio27",
  188. "gpio28", "gpio29", "gpio30", "gpio31",
  189. "gpio32", "gpio33", "gpio34"
  190. };
  191. static const char * const oxnas_ox810se_fct3_group[] = {
  192. "gpio0", "gpio1", "gpio2", "gpio3",
  193. "gpio4", "gpio5", "gpio6", "gpio7",
  194. "gpio8", "gpio9",
  195. "gpio20",
  196. "gpio22", "gpio23", "gpio24", "gpio25",
  197. "gpio26", "gpio27", "gpio28", "gpio29",
  198. "gpio30", "gpio31", "gpio32", "gpio33",
  199. "gpio34"
  200. };
  201. static const char * const oxnas_ox820_fct0_group[] = {
  202. "gpio0", "gpio1", "gpio2", "gpio3",
  203. "gpio4", "gpio5", "gpio6", "gpio7",
  204. "gpio8", "gpio9", "gpio10", "gpio11",
  205. "gpio12", "gpio13", "gpio14", "gpio15",
  206. "gpio16", "gpio17", "gpio18", "gpio19",
  207. "gpio20", "gpio21", "gpio22", "gpio23",
  208. "gpio24", "gpio25", "gpio26", "gpio27",
  209. "gpio28", "gpio29", "gpio30", "gpio31",
  210. "gpio32", "gpio33", "gpio34", "gpio35",
  211. "gpio36", "gpio37", "gpio38", "gpio39",
  212. "gpio40", "gpio41", "gpio42", "gpio43",
  213. "gpio44", "gpio45", "gpio46", "gpio47",
  214. "gpio48", "gpio49"
  215. };
  216. static const char * const oxnas_ox820_fct1_group[] = {
  217. "gpio3", "gpio4",
  218. "gpio12", "gpio13", "gpio14", "gpio15",
  219. "gpio16", "gpio17", "gpio18", "gpio19",
  220. "gpio20", "gpio21", "gpio22", "gpio23",
  221. "gpio24"
  222. };
  223. static const char * const oxnas_ox820_fct4_group[] = {
  224. "gpio5", "gpio6", "gpio7", "gpio8",
  225. "gpio24", "gpio25", "gpio26", "gpio27",
  226. "gpio40", "gpio41", "gpio42", "gpio43"
  227. };
  228. static const char * const oxnas_ox820_fct5_group[] = {
  229. "gpio28", "gpio29", "gpio30", "gpio31"
  230. };
  231. #define FUNCTION(_name, _gr) \
  232. { \
  233. .name = #_name, \
  234. .groups = oxnas_##_gr##_group, \
  235. .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \
  236. }
  237. static const struct oxnas_function oxnas_ox810se_functions[] = {
  238. FUNCTION(gpio, ox810se_fct0),
  239. FUNCTION(fct3, ox810se_fct3),
  240. };
  241. static const struct oxnas_function oxnas_ox820_functions[] = {
  242. FUNCTION(gpio, ox820_fct0),
  243. FUNCTION(fct1, ox820_fct1),
  244. FUNCTION(fct4, ox820_fct4),
  245. FUNCTION(fct5, ox820_fct5),
  246. };
  247. #define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \
  248. { \
  249. .name = #_name, \
  250. .pin = _pin, \
  251. .bank = _pin / PINS_PER_BANK, \
  252. .functions = (struct oxnas_desc_function[]){ \
  253. __VA_ARGS__, { } }, \
  254. }
  255. #define OXNAS_PINCTRL_FUNCTION(_name, _fct) \
  256. { \
  257. .name = #_name, \
  258. .fct = _fct, \
  259. }
  260. static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
  261. OXNAS_PINCTRL_GROUP(0, gpio0,
  262. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  263. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  264. OXNAS_PINCTRL_GROUP(1, gpio1,
  265. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  266. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  267. OXNAS_PINCTRL_GROUP(2, gpio2,
  268. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  269. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  270. OXNAS_PINCTRL_GROUP(3, gpio3,
  271. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  272. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  273. OXNAS_PINCTRL_GROUP(4, gpio4,
  274. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  275. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  276. OXNAS_PINCTRL_GROUP(5, gpio5,
  277. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  278. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  279. OXNAS_PINCTRL_GROUP(6, gpio6,
  280. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  281. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  282. OXNAS_PINCTRL_GROUP(7, gpio7,
  283. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  284. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  285. OXNAS_PINCTRL_GROUP(8, gpio8,
  286. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  287. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  288. OXNAS_PINCTRL_GROUP(9, gpio9,
  289. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  290. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  291. OXNAS_PINCTRL_GROUP(10, gpio10,
  292. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  293. OXNAS_PINCTRL_GROUP(11, gpio11,
  294. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  295. OXNAS_PINCTRL_GROUP(12, gpio12,
  296. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  297. OXNAS_PINCTRL_GROUP(13, gpio13,
  298. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  299. OXNAS_PINCTRL_GROUP(14, gpio14,
  300. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  301. OXNAS_PINCTRL_GROUP(15, gpio15,
  302. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  303. OXNAS_PINCTRL_GROUP(16, gpio16,
  304. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  305. OXNAS_PINCTRL_GROUP(17, gpio17,
  306. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  307. OXNAS_PINCTRL_GROUP(18, gpio18,
  308. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  309. OXNAS_PINCTRL_GROUP(19, gpio19,
  310. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  311. OXNAS_PINCTRL_GROUP(20, gpio20,
  312. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  313. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  314. OXNAS_PINCTRL_GROUP(21, gpio21,
  315. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  316. OXNAS_PINCTRL_GROUP(22, gpio22,
  317. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  318. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  319. OXNAS_PINCTRL_GROUP(23, gpio23,
  320. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  321. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  322. OXNAS_PINCTRL_GROUP(24, gpio24,
  323. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  324. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  325. OXNAS_PINCTRL_GROUP(25, gpio25,
  326. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  327. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  328. OXNAS_PINCTRL_GROUP(26, gpio26,
  329. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  330. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  331. OXNAS_PINCTRL_GROUP(27, gpio27,
  332. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  333. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  334. OXNAS_PINCTRL_GROUP(28, gpio28,
  335. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  336. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  337. OXNAS_PINCTRL_GROUP(29, gpio29,
  338. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  339. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  340. OXNAS_PINCTRL_GROUP(30, gpio30,
  341. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  342. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  343. OXNAS_PINCTRL_GROUP(31, gpio31,
  344. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  345. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  346. OXNAS_PINCTRL_GROUP(32, gpio32,
  347. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  348. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  349. OXNAS_PINCTRL_GROUP(33, gpio33,
  350. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  351. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  352. OXNAS_PINCTRL_GROUP(34, gpio34,
  353. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  354. OXNAS_PINCTRL_FUNCTION(fct3, 3)),
  355. };
  356. static const struct oxnas_pin_group oxnas_ox820_groups[] = {
  357. OXNAS_PINCTRL_GROUP(0, gpio0,
  358. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  359. OXNAS_PINCTRL_GROUP(1, gpio1,
  360. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  361. OXNAS_PINCTRL_GROUP(2, gpio2,
  362. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  363. OXNAS_PINCTRL_GROUP(3, gpio3,
  364. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  365. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  366. OXNAS_PINCTRL_GROUP(4, gpio4,
  367. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  368. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  369. OXNAS_PINCTRL_GROUP(5, gpio5,
  370. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  371. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  372. OXNAS_PINCTRL_GROUP(6, gpio6,
  373. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  374. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  375. OXNAS_PINCTRL_GROUP(7, gpio7,
  376. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  377. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  378. OXNAS_PINCTRL_GROUP(8, gpio8,
  379. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  380. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  381. OXNAS_PINCTRL_GROUP(9, gpio9,
  382. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  383. OXNAS_PINCTRL_GROUP(10, gpio10,
  384. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  385. OXNAS_PINCTRL_GROUP(11, gpio11,
  386. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  387. OXNAS_PINCTRL_GROUP(12, gpio12,
  388. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  389. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  390. OXNAS_PINCTRL_GROUP(13, gpio13,
  391. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  392. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  393. OXNAS_PINCTRL_GROUP(14, gpio14,
  394. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  395. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  396. OXNAS_PINCTRL_GROUP(15, gpio15,
  397. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  398. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  399. OXNAS_PINCTRL_GROUP(16, gpio16,
  400. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  401. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  402. OXNAS_PINCTRL_GROUP(17, gpio17,
  403. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  404. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  405. OXNAS_PINCTRL_GROUP(18, gpio18,
  406. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  407. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  408. OXNAS_PINCTRL_GROUP(19, gpio19,
  409. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  410. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  411. OXNAS_PINCTRL_GROUP(20, gpio20,
  412. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  413. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  414. OXNAS_PINCTRL_GROUP(21, gpio21,
  415. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  416. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  417. OXNAS_PINCTRL_GROUP(22, gpio22,
  418. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  419. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  420. OXNAS_PINCTRL_GROUP(23, gpio23,
  421. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  422. OXNAS_PINCTRL_FUNCTION(fct1, 1)),
  423. OXNAS_PINCTRL_GROUP(24, gpio24,
  424. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  425. OXNAS_PINCTRL_FUNCTION(fct1, 1),
  426. OXNAS_PINCTRL_FUNCTION(fct4, 5)),
  427. OXNAS_PINCTRL_GROUP(25, gpio25,
  428. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  429. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  430. OXNAS_PINCTRL_GROUP(26, gpio26,
  431. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  432. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  433. OXNAS_PINCTRL_GROUP(27, gpio27,
  434. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  435. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  436. OXNAS_PINCTRL_GROUP(28, gpio28,
  437. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  438. OXNAS_PINCTRL_FUNCTION(fct5, 5)),
  439. OXNAS_PINCTRL_GROUP(29, gpio29,
  440. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  441. OXNAS_PINCTRL_FUNCTION(fct5, 5)),
  442. OXNAS_PINCTRL_GROUP(30, gpio30,
  443. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  444. OXNAS_PINCTRL_FUNCTION(fct5, 5)),
  445. OXNAS_PINCTRL_GROUP(31, gpio31,
  446. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  447. OXNAS_PINCTRL_FUNCTION(fct5, 5)),
  448. OXNAS_PINCTRL_GROUP(32, gpio32,
  449. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  450. OXNAS_PINCTRL_GROUP(33, gpio33,
  451. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  452. OXNAS_PINCTRL_GROUP(34, gpio34,
  453. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  454. OXNAS_PINCTRL_GROUP(35, gpio35,
  455. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  456. OXNAS_PINCTRL_GROUP(36, gpio36,
  457. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  458. OXNAS_PINCTRL_GROUP(37, gpio37,
  459. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  460. OXNAS_PINCTRL_GROUP(38, gpio38,
  461. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  462. OXNAS_PINCTRL_GROUP(39, gpio39,
  463. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  464. OXNAS_PINCTRL_GROUP(40, gpio40,
  465. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  466. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  467. OXNAS_PINCTRL_GROUP(41, gpio41,
  468. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  469. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  470. OXNAS_PINCTRL_GROUP(42, gpio42,
  471. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  472. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  473. OXNAS_PINCTRL_GROUP(43, gpio43,
  474. OXNAS_PINCTRL_FUNCTION(gpio, 0),
  475. OXNAS_PINCTRL_FUNCTION(fct4, 4)),
  476. OXNAS_PINCTRL_GROUP(44, gpio44,
  477. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  478. OXNAS_PINCTRL_GROUP(45, gpio45,
  479. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  480. OXNAS_PINCTRL_GROUP(46, gpio46,
  481. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  482. OXNAS_PINCTRL_GROUP(47, gpio47,
  483. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  484. OXNAS_PINCTRL_GROUP(48, gpio48,
  485. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  486. OXNAS_PINCTRL_GROUP(49, gpio49,
  487. OXNAS_PINCTRL_FUNCTION(gpio, 0)),
  488. };
  489. static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
  490. unsigned int pin)
  491. {
  492. return &pctl->gpio_banks[pin / PINS_PER_BANK];
  493. }
  494. static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  495. {
  496. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  497. return pctl->ngroups;
  498. }
  499. static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  500. unsigned int group)
  501. {
  502. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  503. return pctl->groups[group].name;
  504. }
  505. static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  506. unsigned int group,
  507. const unsigned int **pins,
  508. unsigned int *num_pins)
  509. {
  510. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  511. *pins = &pctl->groups[group].pin;
  512. *num_pins = 1;
  513. return 0;
  514. }
  515. static const struct pinctrl_ops oxnas_pinctrl_ops = {
  516. .get_groups_count = oxnas_pinctrl_get_groups_count,
  517. .get_group_name = oxnas_pinctrl_get_group_name,
  518. .get_group_pins = oxnas_pinctrl_get_group_pins,
  519. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  520. .dt_free_map = pinctrl_utils_free_map,
  521. };
  522. static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
  523. {
  524. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  525. return pctl->nfunctions;
  526. }
  527. static const char *
  528. oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
  529. {
  530. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  531. return pctl->functions[func].name;
  532. }
  533. static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
  534. unsigned int func,
  535. const char * const **groups,
  536. unsigned int * const num_groups)
  537. {
  538. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  539. *groups = pctl->functions[func].groups;
  540. *num_groups = pctl->functions[func].ngroups;
  541. return 0;
  542. }
  543. static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
  544. unsigned int func, unsigned int group)
  545. {
  546. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  547. const struct oxnas_pin_group *pg = &pctl->groups[group];
  548. const struct oxnas_function *pf = &pctl->functions[func];
  549. const char *fname = pf->name;
  550. struct oxnas_desc_function *functions = pg->functions;
  551. u32 mask = BIT(pg->pin);
  552. while (functions->name) {
  553. if (!strcmp(functions->name, fname)) {
  554. dev_dbg(pctl->dev,
  555. "setting function %s bank %d pin %d fct %d mask %x\n",
  556. fname, pg->bank, pg->pin,
  557. functions->fct, mask);
  558. regmap_write_bits(pctl->regmap,
  559. (pg->bank ?
  560. PINMUX_810_PRIMARY_SEL1 :
  561. PINMUX_810_PRIMARY_SEL0),
  562. mask,
  563. (functions->fct == 1 ?
  564. mask : 0));
  565. regmap_write_bits(pctl->regmap,
  566. (pg->bank ?
  567. PINMUX_810_SECONDARY_SEL1 :
  568. PINMUX_810_SECONDARY_SEL0),
  569. mask,
  570. (functions->fct == 2 ?
  571. mask : 0));
  572. regmap_write_bits(pctl->regmap,
  573. (pg->bank ?
  574. PINMUX_810_TERTIARY_SEL1 :
  575. PINMUX_810_TERTIARY_SEL0),
  576. mask,
  577. (functions->fct == 3 ?
  578. mask : 0));
  579. return 0;
  580. }
  581. functions++;
  582. }
  583. dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
  584. return -EINVAL;
  585. }
  586. static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev,
  587. unsigned int func, unsigned int group)
  588. {
  589. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  590. const struct oxnas_pin_group *pg = &pctl->groups[group];
  591. const struct oxnas_function *pf = &pctl->functions[func];
  592. const char *fname = pf->name;
  593. struct oxnas_desc_function *functions = pg->functions;
  594. unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);
  595. u32 mask = BIT(pg->pin);
  596. while (functions->name) {
  597. if (!strcmp(functions->name, fname)) {
  598. dev_dbg(pctl->dev,
  599. "setting function %s bank %d pin %d fct %d mask %x\n",
  600. fname, pg->bank, pg->pin,
  601. functions->fct, mask);
  602. regmap_write_bits(pctl->regmap,
  603. offset + PINMUX_820_SECONDARY_SEL,
  604. mask,
  605. (functions->fct == 1 ?
  606. mask : 0));
  607. regmap_write_bits(pctl->regmap,
  608. offset + PINMUX_820_TERTIARY_SEL,
  609. mask,
  610. (functions->fct == 2 ?
  611. mask : 0));
  612. regmap_write_bits(pctl->regmap,
  613. offset + PINMUX_820_QUATERNARY_SEL,
  614. mask,
  615. (functions->fct == 3 ?
  616. mask : 0));
  617. regmap_write_bits(pctl->regmap,
  618. offset + PINMUX_820_DEBUG_SEL,
  619. mask,
  620. (functions->fct == 4 ?
  621. mask : 0));
  622. regmap_write_bits(pctl->regmap,
  623. offset + PINMUX_820_ALTERNATIVE_SEL,
  624. mask,
  625. (functions->fct == 5 ?
  626. mask : 0));
  627. return 0;
  628. }
  629. functions++;
  630. }
  631. dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
  632. return -EINVAL;
  633. }
  634. static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
  635. struct pinctrl_gpio_range *range,
  636. unsigned int offset)
  637. {
  638. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  639. struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
  640. u32 mask = BIT(offset - bank->gpio_chip.base);
  641. dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
  642. offset, bank->gpio_chip.base, bank->id, mask);
  643. regmap_write_bits(pctl->regmap,
  644. (bank->id ?
  645. PINMUX_810_PRIMARY_SEL1 :
  646. PINMUX_810_PRIMARY_SEL0),
  647. mask, 0);
  648. regmap_write_bits(pctl->regmap,
  649. (bank->id ?
  650. PINMUX_810_SECONDARY_SEL1 :
  651. PINMUX_810_SECONDARY_SEL0),
  652. mask, 0);
  653. regmap_write_bits(pctl->regmap,
  654. (bank->id ?
  655. PINMUX_810_TERTIARY_SEL1 :
  656. PINMUX_810_TERTIARY_SEL0),
  657. mask, 0);
  658. return 0;
  659. }
  660. static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev,
  661. struct pinctrl_gpio_range *range,
  662. unsigned int offset)
  663. {
  664. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  665. struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
  666. unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
  667. u32 mask = BIT(offset - bank->gpio_chip.base);
  668. dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
  669. offset, bank->gpio_chip.base, bank->id, mask);
  670. regmap_write_bits(pctl->regmap,
  671. bank_offset + PINMUX_820_SECONDARY_SEL,
  672. mask, 0);
  673. regmap_write_bits(pctl->regmap,
  674. bank_offset + PINMUX_820_TERTIARY_SEL,
  675. mask, 0);
  676. regmap_write_bits(pctl->regmap,
  677. bank_offset + PINMUX_820_QUATERNARY_SEL,
  678. mask, 0);
  679. regmap_write_bits(pctl->regmap,
  680. bank_offset + PINMUX_820_DEBUG_SEL,
  681. mask, 0);
  682. regmap_write_bits(pctl->regmap,
  683. bank_offset + PINMUX_820_ALTERNATIVE_SEL,
  684. mask, 0);
  685. return 0;
  686. }
  687. static int oxnas_gpio_get_direction(struct gpio_chip *chip,
  688. unsigned int offset)
  689. {
  690. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  691. u32 mask = BIT(offset);
  692. if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask)
  693. return GPIO_LINE_DIRECTION_OUT;
  694. return GPIO_LINE_DIRECTION_IN;
  695. }
  696. static int oxnas_gpio_direction_input(struct gpio_chip *chip,
  697. unsigned int offset)
  698. {
  699. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  700. u32 mask = BIT(offset);
  701. writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);
  702. return 0;
  703. }
  704. static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset)
  705. {
  706. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  707. u32 mask = BIT(offset);
  708. return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;
  709. }
  710. static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset,
  711. int value)
  712. {
  713. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  714. u32 mask = BIT(offset);
  715. if (value)
  716. writel_relaxed(mask, bank->reg_base + OUTPUT_SET);
  717. else
  718. writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);
  719. }
  720. static int oxnas_gpio_direction_output(struct gpio_chip *chip,
  721. unsigned int offset, int value)
  722. {
  723. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  724. u32 mask = BIT(offset);
  725. oxnas_gpio_set(chip, offset, value);
  726. writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);
  727. return 0;
  728. }
  729. static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
  730. struct pinctrl_gpio_range *range,
  731. unsigned int offset, bool input)
  732. {
  733. struct gpio_chip *chip = range->gc;
  734. if (input)
  735. oxnas_gpio_direction_input(chip, offset);
  736. else
  737. oxnas_gpio_direction_output(chip, offset, 0);
  738. return 0;
  739. }
  740. static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
  741. .get_functions_count = oxnas_pinmux_get_functions_count,
  742. .get_function_name = oxnas_pinmux_get_function_name,
  743. .get_function_groups = oxnas_pinmux_get_function_groups,
  744. .set_mux = oxnas_ox810se_pinmux_enable,
  745. .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
  746. .gpio_set_direction = oxnas_gpio_set_direction,
  747. };
  748. static const struct pinmux_ops oxnas_ox820_pinmux_ops = {
  749. .get_functions_count = oxnas_pinmux_get_functions_count,
  750. .get_function_name = oxnas_pinmux_get_function_name,
  751. .get_function_groups = oxnas_pinmux_get_function_groups,
  752. .set_mux = oxnas_ox820_pinmux_enable,
  753. .gpio_request_enable = oxnas_ox820_gpio_request_enable,
  754. .gpio_set_direction = oxnas_gpio_set_direction,
  755. };
  756. static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
  757. unsigned int pin, unsigned long *config)
  758. {
  759. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  760. struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
  761. unsigned int param = pinconf_to_config_param(*config);
  762. u32 mask = BIT(pin - bank->gpio_chip.base);
  763. int ret;
  764. u32 arg;
  765. switch (param) {
  766. case PIN_CONFIG_BIAS_PULL_UP:
  767. ret = regmap_read(pctl->regmap,
  768. (bank->id ?
  769. PINMUX_810_PULLUP_CTRL1 :
  770. PINMUX_810_PULLUP_CTRL0),
  771. &arg);
  772. if (ret)
  773. return ret;
  774. arg = !!(arg & mask);
  775. break;
  776. default:
  777. return -ENOTSUPP;
  778. }
  779. *config = pinconf_to_config_packed(param, arg);
  780. return 0;
  781. }
  782. static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev,
  783. unsigned int pin, unsigned long *config)
  784. {
  785. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  786. struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
  787. unsigned int param = pinconf_to_config_param(*config);
  788. unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
  789. u32 mask = BIT(pin - bank->gpio_chip.base);
  790. int ret;
  791. u32 arg;
  792. switch (param) {
  793. case PIN_CONFIG_BIAS_PULL_UP:
  794. ret = regmap_read(pctl->regmap,
  795. bank_offset + PINMUX_820_PULLUP_CTRL,
  796. &arg);
  797. if (ret)
  798. return ret;
  799. arg = !!(arg & mask);
  800. break;
  801. default:
  802. return -ENOTSUPP;
  803. }
  804. *config = pinconf_to_config_packed(param, arg);
  805. return 0;
  806. }
  807. static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
  808. unsigned int pin, unsigned long *configs,
  809. unsigned int num_configs)
  810. {
  811. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  812. struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
  813. unsigned int param;
  814. unsigned int i;
  815. u32 offset = pin - bank->gpio_chip.base;
  816. u32 mask = BIT(offset);
  817. dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
  818. pin, bank->gpio_chip.base, mask);
  819. for (i = 0; i < num_configs; i++) {
  820. param = pinconf_to_config_param(configs[i]);
  821. switch (param) {
  822. case PIN_CONFIG_BIAS_PULL_UP:
  823. dev_dbg(pctl->dev, " pullup\n");
  824. regmap_write_bits(pctl->regmap,
  825. (bank->id ?
  826. PINMUX_810_PULLUP_CTRL1 :
  827. PINMUX_810_PULLUP_CTRL0),
  828. mask, mask);
  829. break;
  830. default:
  831. dev_err(pctl->dev, "Property %u not supported\n",
  832. param);
  833. return -ENOTSUPP;
  834. }
  835. }
  836. return 0;
  837. }
  838. static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
  839. unsigned int pin, unsigned long *configs,
  840. unsigned int num_configs)
  841. {
  842. struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  843. struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
  844. unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
  845. unsigned int param;
  846. unsigned int i;
  847. u32 offset = pin - bank->gpio_chip.base;
  848. u32 mask = BIT(offset);
  849. dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
  850. pin, bank->gpio_chip.base, mask);
  851. for (i = 0; i < num_configs; i++) {
  852. param = pinconf_to_config_param(configs[i]);
  853. switch (param) {
  854. case PIN_CONFIG_BIAS_PULL_UP:
  855. dev_dbg(pctl->dev, " pullup\n");
  856. regmap_write_bits(pctl->regmap,
  857. bank_offset + PINMUX_820_PULLUP_CTRL,
  858. mask, mask);
  859. break;
  860. default:
  861. dev_err(pctl->dev, "Property %u not supported\n",
  862. param);
  863. return -ENOTSUPP;
  864. }
  865. }
  866. return 0;
  867. }
  868. static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
  869. .pin_config_get = oxnas_ox810se_pinconf_get,
  870. .pin_config_set = oxnas_ox810se_pinconf_set,
  871. .is_generic = true,
  872. };
  873. static const struct pinconf_ops oxnas_ox820_pinconf_ops = {
  874. .pin_config_get = oxnas_ox820_pinconf_get,
  875. .pin_config_set = oxnas_ox820_pinconf_set,
  876. .is_generic = true,
  877. };
  878. static void oxnas_gpio_irq_ack(struct irq_data *data)
  879. {
  880. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  881. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  882. u32 mask = BIT(data->hwirq);
  883. writel(mask, bank->reg_base + IRQ_PENDING);
  884. }
  885. static void oxnas_gpio_irq_mask(struct irq_data *data)
  886. {
  887. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  888. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  889. unsigned int type = irqd_get_trigger_type(data);
  890. u32 mask = BIT(data->hwirq);
  891. if (type & IRQ_TYPE_EDGE_RISING)
  892. writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,
  893. bank->reg_base + RE_IRQ_ENABLE);
  894. if (type & IRQ_TYPE_EDGE_FALLING)
  895. writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,
  896. bank->reg_base + FE_IRQ_ENABLE);
  897. }
  898. static void oxnas_gpio_irq_unmask(struct irq_data *data)
  899. {
  900. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  901. struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
  902. unsigned int type = irqd_get_trigger_type(data);
  903. u32 mask = BIT(data->hwirq);
  904. if (type & IRQ_TYPE_EDGE_RISING)
  905. writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,
  906. bank->reg_base + RE_IRQ_ENABLE);
  907. if (type & IRQ_TYPE_EDGE_FALLING)
  908. writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,
  909. bank->reg_base + FE_IRQ_ENABLE);
  910. }
  911. static unsigned int oxnas_gpio_irq_startup(struct irq_data *data)
  912. {
  913. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  914. oxnas_gpio_direction_input(chip, data->hwirq);
  915. oxnas_gpio_irq_unmask(data);
  916. return 0;
  917. }
  918. static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type)
  919. {
  920. if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0)
  921. return -EINVAL;
  922. irq_set_handler_locked(data, handle_edge_irq);
  923. return 0;
  924. }
  925. static void oxnas_gpio_irq_handler(struct irq_desc *desc)
  926. {
  927. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  928. struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
  929. struct irq_chip *chip = irq_desc_get_chip(desc);
  930. unsigned long stat;
  931. unsigned int pin;
  932. chained_irq_enter(chip, desc);
  933. stat = readl(bank->reg_base + IRQ_PENDING);
  934. for_each_set_bit(pin, &stat, BITS_PER_LONG)
  935. generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
  936. chained_irq_exit(chip, desc);
  937. }
  938. #define GPIO_BANK(_bank) \
  939. { \
  940. .gpio_chip = { \
  941. .label = "GPIO" #_bank, \
  942. .request = gpiochip_generic_request, \
  943. .free = gpiochip_generic_free, \
  944. .get_direction = oxnas_gpio_get_direction, \
  945. .direction_input = oxnas_gpio_direction_input, \
  946. .direction_output = oxnas_gpio_direction_output, \
  947. .get = oxnas_gpio_get, \
  948. .set = oxnas_gpio_set, \
  949. .ngpio = PINS_PER_BANK, \
  950. .base = GPIO_BANK_START(_bank), \
  951. .owner = THIS_MODULE, \
  952. .can_sleep = 0, \
  953. }, \
  954. .irq_chip = { \
  955. .name = "GPIO" #_bank, \
  956. .irq_startup = oxnas_gpio_irq_startup, \
  957. .irq_ack = oxnas_gpio_irq_ack, \
  958. .irq_mask = oxnas_gpio_irq_mask, \
  959. .irq_unmask = oxnas_gpio_irq_unmask, \
  960. .irq_set_type = oxnas_gpio_irq_set_type, \
  961. }, \
  962. }
  963. static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
  964. GPIO_BANK(0),
  965. GPIO_BANK(1),
  966. };
  967. static struct oxnas_pinctrl ox810se_pinctrl = {
  968. .functions = oxnas_ox810se_functions,
  969. .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
  970. .groups = oxnas_ox810se_groups,
  971. .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
  972. .gpio_banks = oxnas_gpio_banks,
  973. .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
  974. };
  975. static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
  976. .name = "oxnas-pinctrl",
  977. .pins = oxnas_ox810se_pins,
  978. .npins = ARRAY_SIZE(oxnas_ox810se_pins),
  979. .pctlops = &oxnas_pinctrl_ops,
  980. .pmxops = &oxnas_ox810se_pinmux_ops,
  981. .confops = &oxnas_ox810se_pinconf_ops,
  982. .owner = THIS_MODULE,
  983. };
  984. static struct oxnas_pinctrl ox820_pinctrl = {
  985. .functions = oxnas_ox820_functions,
  986. .nfunctions = ARRAY_SIZE(oxnas_ox820_functions),
  987. .groups = oxnas_ox820_groups,
  988. .ngroups = ARRAY_SIZE(oxnas_ox820_groups),
  989. .gpio_banks = oxnas_gpio_banks,
  990. .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
  991. };
  992. static struct pinctrl_desc oxnas_ox820_pinctrl_desc = {
  993. .name = "oxnas-pinctrl",
  994. .pins = oxnas_ox820_pins,
  995. .npins = ARRAY_SIZE(oxnas_ox820_pins),
  996. .pctlops = &oxnas_pinctrl_ops,
  997. .pmxops = &oxnas_ox820_pinmux_ops,
  998. .confops = &oxnas_ox820_pinconf_ops,
  999. .owner = THIS_MODULE,
  1000. };
  1001. static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
  1002. .desc = &oxnas_ox810se_pinctrl_desc,
  1003. .pctl = &ox810se_pinctrl,
  1004. };
  1005. static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = {
  1006. .desc = &oxnas_ox820_pinctrl_desc,
  1007. .pctl = &ox820_pinctrl,
  1008. };
  1009. static const struct of_device_id oxnas_pinctrl_of_match[] = {
  1010. { .compatible = "oxsemi,ox810se-pinctrl",
  1011. .data = &oxnas_ox810se_pinctrl_data
  1012. },
  1013. { .compatible = "oxsemi,ox820-pinctrl",
  1014. .data = &oxnas_ox820_pinctrl_data,
  1015. },
  1016. { },
  1017. };
  1018. static int oxnas_pinctrl_probe(struct platform_device *pdev)
  1019. {
  1020. const struct of_device_id *id;
  1021. const struct oxnas_pinctrl_data *data;
  1022. struct oxnas_pinctrl *pctl;
  1023. id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
  1024. if (!id)
  1025. return -ENODEV;
  1026. data = id->data;
  1027. if (!data || !data->pctl || !data->desc)
  1028. return -EINVAL;
  1029. pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
  1030. if (!pctl)
  1031. return -ENOMEM;
  1032. pctl->dev = &pdev->dev;
  1033. dev_set_drvdata(&pdev->dev, pctl);
  1034. pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  1035. "oxsemi,sys-ctrl");
  1036. if (IS_ERR(pctl->regmap)) {
  1037. dev_err(&pdev->dev, "failed to get sys ctrl regmap\n");
  1038. return -ENODEV;
  1039. }
  1040. pctl->functions = data->pctl->functions;
  1041. pctl->nfunctions = data->pctl->nfunctions;
  1042. pctl->groups = data->pctl->groups;
  1043. pctl->ngroups = data->pctl->ngroups;
  1044. pctl->gpio_banks = data->pctl->gpio_banks;
  1045. pctl->nbanks = data->pctl->nbanks;
  1046. pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
  1047. if (IS_ERR(pctl->pctldev)) {
  1048. dev_err(&pdev->dev, "Failed to register pinctrl device\n");
  1049. return PTR_ERR(pctl->pctldev);
  1050. }
  1051. return 0;
  1052. }
  1053. static int oxnas_gpio_probe(struct platform_device *pdev)
  1054. {
  1055. struct device_node *np = pdev->dev.of_node;
  1056. struct of_phandle_args pinspec;
  1057. struct oxnas_gpio_bank *bank;
  1058. unsigned int id, ngpios;
  1059. int irq, ret;
  1060. struct gpio_irq_chip *girq;
  1061. if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
  1062. 3, 0, &pinspec)) {
  1063. dev_err(&pdev->dev, "gpio-ranges property not found\n");
  1064. return -EINVAL;
  1065. }
  1066. id = pinspec.args[1] / PINS_PER_BANK;
  1067. ngpios = pinspec.args[2];
  1068. if (id >= ARRAY_SIZE(oxnas_gpio_banks)) {
  1069. dev_err(&pdev->dev, "invalid gpio-ranges base arg\n");
  1070. return -EINVAL;
  1071. }
  1072. if (ngpios > PINS_PER_BANK) {
  1073. dev_err(&pdev->dev, "invalid gpio-ranges count arg\n");
  1074. return -EINVAL;
  1075. }
  1076. bank = &oxnas_gpio_banks[id];
  1077. bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
  1078. if (IS_ERR(bank->reg_base))
  1079. return PTR_ERR(bank->reg_base);
  1080. irq = platform_get_irq(pdev, 0);
  1081. if (irq < 0)
  1082. return irq;
  1083. bank->id = id;
  1084. bank->gpio_chip.parent = &pdev->dev;
  1085. bank->gpio_chip.of_node = np;
  1086. bank->gpio_chip.ngpio = ngpios;
  1087. girq = &bank->gpio_chip.irq;
  1088. girq->chip = &bank->irq_chip;
  1089. girq->parent_handler = oxnas_gpio_irq_handler;
  1090. girq->num_parents = 1;
  1091. girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
  1092. GFP_KERNEL);
  1093. if (!girq->parents)
  1094. return -ENOMEM;
  1095. girq->parents[0] = irq;
  1096. girq->default_type = IRQ_TYPE_NONE;
  1097. girq->handler = handle_level_irq;
  1098. ret = gpiochip_add_data(&bank->gpio_chip, bank);
  1099. if (ret < 0) {
  1100. dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
  1101. id, ret);
  1102. return ret;
  1103. }
  1104. return 0;
  1105. }
  1106. static struct platform_driver oxnas_pinctrl_driver = {
  1107. .driver = {
  1108. .name = "oxnas-pinctrl",
  1109. .of_match_table = oxnas_pinctrl_of_match,
  1110. .suppress_bind_attrs = true,
  1111. },
  1112. .probe = oxnas_pinctrl_probe,
  1113. };
  1114. static const struct of_device_id oxnas_gpio_of_match[] = {
  1115. { .compatible = "oxsemi,ox810se-gpio", },
  1116. { .compatible = "oxsemi,ox820-gpio", },
  1117. { },
  1118. };
  1119. static struct platform_driver oxnas_gpio_driver = {
  1120. .driver = {
  1121. .name = "oxnas-gpio",
  1122. .of_match_table = oxnas_gpio_of_match,
  1123. .suppress_bind_attrs = true,
  1124. },
  1125. .probe = oxnas_gpio_probe,
  1126. };
  1127. static int __init oxnas_gpio_register(void)
  1128. {
  1129. return platform_driver_register(&oxnas_gpio_driver);
  1130. }
  1131. arch_initcall(oxnas_gpio_register);
  1132. static int __init oxnas_pinctrl_register(void)
  1133. {
  1134. return platform_driver_register(&oxnas_pinctrl_driver);
  1135. }
  1136. arch_initcall(oxnas_pinctrl_register);