pinctrl-mcp23s08.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* MCP23S08 SPI/I2C GPIO driver */
  3. #include <linux/bitops.h>
  4. #include <linux/kernel.h>
  5. #include <linux/device.h>
  6. #include <linux/mutex.h>
  7. #include <linux/mod_devicetable.h>
  8. #include <linux/module.h>
  9. #include <linux/export.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/slab.h>
  12. #include <asm/byteorder.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/regmap.h>
  15. #include <linux/pinctrl/pinctrl.h>
  16. #include <linux/pinctrl/pinconf.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include "pinctrl-mcp23s08.h"
  19. /* Registers are all 8 bits wide.
  20. *
  21. * The mcp23s17 has twice as many bits, and can be configured to work
  22. * with either 16 bit registers or with two adjacent 8 bit banks.
  23. */
  24. #define MCP_IODIR 0x00 /* init/reset: all ones */
  25. #define MCP_IPOL 0x01
  26. #define MCP_GPINTEN 0x02
  27. #define MCP_DEFVAL 0x03
  28. #define MCP_INTCON 0x04
  29. #define MCP_IOCON 0x05
  30. # define IOCON_MIRROR (1 << 6)
  31. # define IOCON_SEQOP (1 << 5)
  32. # define IOCON_HAEN (1 << 3)
  33. # define IOCON_ODR (1 << 2)
  34. # define IOCON_INTPOL (1 << 1)
  35. # define IOCON_INTCC (1)
  36. #define MCP_GPPU 0x06
  37. #define MCP_INTF 0x07
  38. #define MCP_INTCAP 0x08
  39. #define MCP_GPIO 0x09
  40. #define MCP_OLAT 0x0a
  41. static const struct reg_default mcp23x08_defaults[] = {
  42. {.reg = MCP_IODIR, .def = 0xff},
  43. {.reg = MCP_IPOL, .def = 0x00},
  44. {.reg = MCP_GPINTEN, .def = 0x00},
  45. {.reg = MCP_DEFVAL, .def = 0x00},
  46. {.reg = MCP_INTCON, .def = 0x00},
  47. {.reg = MCP_IOCON, .def = 0x00},
  48. {.reg = MCP_GPPU, .def = 0x00},
  49. {.reg = MCP_OLAT, .def = 0x00},
  50. };
  51. static const struct regmap_range mcp23x08_volatile_range = {
  52. .range_min = MCP_INTF,
  53. .range_max = MCP_GPIO,
  54. };
  55. static const struct regmap_access_table mcp23x08_volatile_table = {
  56. .yes_ranges = &mcp23x08_volatile_range,
  57. .n_yes_ranges = 1,
  58. };
  59. static const struct regmap_range mcp23x08_precious_range = {
  60. .range_min = MCP_GPIO,
  61. .range_max = MCP_GPIO,
  62. };
  63. static const struct regmap_access_table mcp23x08_precious_table = {
  64. .yes_ranges = &mcp23x08_precious_range,
  65. .n_yes_ranges = 1,
  66. };
  67. const struct regmap_config mcp23x08_regmap = {
  68. .reg_bits = 8,
  69. .val_bits = 8,
  70. .reg_stride = 1,
  71. .volatile_table = &mcp23x08_volatile_table,
  72. .precious_table = &mcp23x08_precious_table,
  73. .reg_defaults = mcp23x08_defaults,
  74. .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
  75. .cache_type = REGCACHE_FLAT,
  76. .max_register = MCP_OLAT,
  77. };
  78. EXPORT_SYMBOL_GPL(mcp23x08_regmap);
  79. static const struct reg_default mcp23x17_defaults[] = {
  80. {.reg = MCP_IODIR << 1, .def = 0xffff},
  81. {.reg = MCP_IPOL << 1, .def = 0x0000},
  82. {.reg = MCP_GPINTEN << 1, .def = 0x0000},
  83. {.reg = MCP_DEFVAL << 1, .def = 0x0000},
  84. {.reg = MCP_INTCON << 1, .def = 0x0000},
  85. {.reg = MCP_IOCON << 1, .def = 0x0000},
  86. {.reg = MCP_GPPU << 1, .def = 0x0000},
  87. {.reg = MCP_OLAT << 1, .def = 0x0000},
  88. };
  89. static const struct regmap_range mcp23x17_volatile_range = {
  90. .range_min = MCP_INTF << 1,
  91. .range_max = MCP_GPIO << 1,
  92. };
  93. static const struct regmap_access_table mcp23x17_volatile_table = {
  94. .yes_ranges = &mcp23x17_volatile_range,
  95. .n_yes_ranges = 1,
  96. };
  97. static const struct regmap_range mcp23x17_precious_range = {
  98. .range_min = MCP_INTCAP << 1,
  99. .range_max = MCP_GPIO << 1,
  100. };
  101. static const struct regmap_access_table mcp23x17_precious_table = {
  102. .yes_ranges = &mcp23x17_precious_range,
  103. .n_yes_ranges = 1,
  104. };
  105. const struct regmap_config mcp23x17_regmap = {
  106. .reg_bits = 8,
  107. .val_bits = 16,
  108. .reg_stride = 2,
  109. .max_register = MCP_OLAT << 1,
  110. .volatile_table = &mcp23x17_volatile_table,
  111. .precious_table = &mcp23x17_precious_table,
  112. .reg_defaults = mcp23x17_defaults,
  113. .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
  114. .cache_type = REGCACHE_FLAT,
  115. .val_format_endian = REGMAP_ENDIAN_LITTLE,
  116. };
  117. EXPORT_SYMBOL_GPL(mcp23x17_regmap);
  118. static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
  119. {
  120. return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
  121. }
  122. static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
  123. {
  124. return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
  125. }
  126. static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
  127. unsigned int mask, bool enabled)
  128. {
  129. u16 val = enabled ? 0xffff : 0x0000;
  130. return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
  131. mask, val);
  132. }
  133. static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
  134. unsigned int pin, bool enabled)
  135. {
  136. u16 mask = BIT(pin);
  137. return mcp_set_mask(mcp, reg, mask, enabled);
  138. }
  139. static const struct pinctrl_pin_desc mcp23x08_pins[] = {
  140. PINCTRL_PIN(0, "gpio0"),
  141. PINCTRL_PIN(1, "gpio1"),
  142. PINCTRL_PIN(2, "gpio2"),
  143. PINCTRL_PIN(3, "gpio3"),
  144. PINCTRL_PIN(4, "gpio4"),
  145. PINCTRL_PIN(5, "gpio5"),
  146. PINCTRL_PIN(6, "gpio6"),
  147. PINCTRL_PIN(7, "gpio7"),
  148. };
  149. static const struct pinctrl_pin_desc mcp23x17_pins[] = {
  150. PINCTRL_PIN(0, "gpio0"),
  151. PINCTRL_PIN(1, "gpio1"),
  152. PINCTRL_PIN(2, "gpio2"),
  153. PINCTRL_PIN(3, "gpio3"),
  154. PINCTRL_PIN(4, "gpio4"),
  155. PINCTRL_PIN(5, "gpio5"),
  156. PINCTRL_PIN(6, "gpio6"),
  157. PINCTRL_PIN(7, "gpio7"),
  158. PINCTRL_PIN(8, "gpio8"),
  159. PINCTRL_PIN(9, "gpio9"),
  160. PINCTRL_PIN(10, "gpio10"),
  161. PINCTRL_PIN(11, "gpio11"),
  162. PINCTRL_PIN(12, "gpio12"),
  163. PINCTRL_PIN(13, "gpio13"),
  164. PINCTRL_PIN(14, "gpio14"),
  165. PINCTRL_PIN(15, "gpio15"),
  166. };
  167. static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  168. {
  169. return 0;
  170. }
  171. static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  172. unsigned int group)
  173. {
  174. return NULL;
  175. }
  176. static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  177. unsigned int group,
  178. const unsigned int **pins,
  179. unsigned int *num_pins)
  180. {
  181. return -ENOTSUPP;
  182. }
  183. static const struct pinctrl_ops mcp_pinctrl_ops = {
  184. .get_groups_count = mcp_pinctrl_get_groups_count,
  185. .get_group_name = mcp_pinctrl_get_group_name,
  186. .get_group_pins = mcp_pinctrl_get_group_pins,
  187. #ifdef CONFIG_OF
  188. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  189. .dt_free_map = pinconf_generic_dt_free_map,
  190. #endif
  191. };
  192. static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
  193. unsigned long *config)
  194. {
  195. struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
  196. enum pin_config_param param = pinconf_to_config_param(*config);
  197. unsigned int data, status;
  198. int ret;
  199. switch (param) {
  200. case PIN_CONFIG_BIAS_PULL_UP:
  201. ret = mcp_read(mcp, MCP_GPPU, &data);
  202. if (ret < 0)
  203. return ret;
  204. status = (data & BIT(pin)) ? 1 : 0;
  205. break;
  206. default:
  207. return -ENOTSUPP;
  208. }
  209. *config = 0;
  210. return status ? 0 : -EINVAL;
  211. }
  212. static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  213. unsigned long *configs, unsigned int num_configs)
  214. {
  215. struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
  216. enum pin_config_param param;
  217. u32 arg;
  218. int ret = 0;
  219. int i;
  220. for (i = 0; i < num_configs; i++) {
  221. param = pinconf_to_config_param(configs[i]);
  222. arg = pinconf_to_config_argument(configs[i]);
  223. switch (param) {
  224. case PIN_CONFIG_BIAS_PULL_UP:
  225. ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
  226. break;
  227. default:
  228. dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
  229. return -ENOTSUPP;
  230. }
  231. }
  232. return ret;
  233. }
  234. static const struct pinconf_ops mcp_pinconf_ops = {
  235. .pin_config_get = mcp_pinconf_get,
  236. .pin_config_set = mcp_pinconf_set,
  237. .is_generic = true,
  238. };
  239. /*----------------------------------------------------------------------*/
  240. static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
  241. {
  242. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  243. int status;
  244. mutex_lock(&mcp->lock);
  245. status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
  246. mutex_unlock(&mcp->lock);
  247. return status;
  248. }
  249. static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
  250. {
  251. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  252. int status, ret;
  253. mutex_lock(&mcp->lock);
  254. /* REVISIT reading this clears any IRQ ... */
  255. ret = mcp_read(mcp, MCP_GPIO, &status);
  256. if (ret < 0)
  257. status = 0;
  258. else {
  259. mcp->cached_gpio = status;
  260. status = !!(status & (1 << offset));
  261. }
  262. mutex_unlock(&mcp->lock);
  263. return status;
  264. }
  265. static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
  266. {
  267. return mcp_set_mask(mcp, MCP_OLAT, mask, value);
  268. }
  269. static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
  270. {
  271. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  272. unsigned mask = BIT(offset);
  273. mutex_lock(&mcp->lock);
  274. __mcp23s08_set(mcp, mask, !!value);
  275. mutex_unlock(&mcp->lock);
  276. }
  277. static int
  278. mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
  279. {
  280. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  281. unsigned mask = BIT(offset);
  282. int status;
  283. mutex_lock(&mcp->lock);
  284. status = __mcp23s08_set(mcp, mask, value);
  285. if (status == 0) {
  286. status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
  287. }
  288. mutex_unlock(&mcp->lock);
  289. return status;
  290. }
  291. /*----------------------------------------------------------------------*/
  292. static irqreturn_t mcp23s08_irq(int irq, void *data)
  293. {
  294. struct mcp23s08 *mcp = data;
  295. int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
  296. unsigned int child_irq;
  297. bool intf_set, intcap_changed, gpio_bit_changed,
  298. defval_changed, gpio_set;
  299. mutex_lock(&mcp->lock);
  300. if (mcp_read(mcp, MCP_INTF, &intf))
  301. goto unlock;
  302. if (intf == 0) {
  303. /* There is no interrupt pending */
  304. goto unlock;
  305. }
  306. if (mcp_read(mcp, MCP_INTCAP, &intcap))
  307. goto unlock;
  308. if (mcp_read(mcp, MCP_INTCON, &intcon))
  309. goto unlock;
  310. if (mcp_read(mcp, MCP_DEFVAL, &defval))
  311. goto unlock;
  312. /* This clears the interrupt(configurable on S18) */
  313. if (mcp_read(mcp, MCP_GPIO, &gpio))
  314. goto unlock;
  315. gpio_orig = mcp->cached_gpio;
  316. mcp->cached_gpio = gpio;
  317. mutex_unlock(&mcp->lock);
  318. dev_dbg(mcp->chip.parent,
  319. "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
  320. intcap, intf, gpio_orig, gpio);
  321. for (i = 0; i < mcp->chip.ngpio; i++) {
  322. /* We must check all of the inputs on the chip,
  323. * otherwise we may not notice a change on >=2 pins.
  324. *
  325. * On at least the mcp23s17, INTCAP is only updated
  326. * one byte at a time(INTCAPA and INTCAPB are
  327. * not written to at the same time - only on a per-bank
  328. * basis).
  329. *
  330. * INTF only contains the single bit that caused the
  331. * interrupt per-bank. On the mcp23s17, there is
  332. * INTFA and INTFB. If two pins are changed on the A
  333. * side at the same time, INTF will only have one bit
  334. * set. If one pin on the A side and one pin on the B
  335. * side are changed at the same time, INTF will have
  336. * two bits set. Thus, INTF can't be the only check
  337. * to see if the input has changed.
  338. */
  339. intf_set = intf & BIT(i);
  340. if (i < 8 && intf_set)
  341. intcap_mask = 0x00FF;
  342. else if (i >= 8 && intf_set)
  343. intcap_mask = 0xFF00;
  344. else
  345. intcap_mask = 0x00;
  346. intcap_changed = (intcap_mask &
  347. (intcap & BIT(i))) !=
  348. (intcap_mask & (BIT(i) & gpio_orig));
  349. gpio_set = BIT(i) & gpio;
  350. gpio_bit_changed = (BIT(i) & gpio_orig) !=
  351. (BIT(i) & gpio);
  352. defval_changed = (BIT(i) & intcon) &&
  353. ((BIT(i) & gpio) !=
  354. (BIT(i) & defval));
  355. if (((gpio_bit_changed || intcap_changed) &&
  356. (BIT(i) & mcp->irq_rise) && gpio_set) ||
  357. ((gpio_bit_changed || intcap_changed) &&
  358. (BIT(i) & mcp->irq_fall) && !gpio_set) ||
  359. defval_changed) {
  360. child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
  361. handle_nested_irq(child_irq);
  362. }
  363. }
  364. return IRQ_HANDLED;
  365. unlock:
  366. mutex_unlock(&mcp->lock);
  367. return IRQ_HANDLED;
  368. }
  369. static void mcp23s08_irq_mask(struct irq_data *data)
  370. {
  371. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  372. struct mcp23s08 *mcp = gpiochip_get_data(gc);
  373. unsigned int pos = data->hwirq;
  374. mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
  375. }
  376. static void mcp23s08_irq_unmask(struct irq_data *data)
  377. {
  378. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  379. struct mcp23s08 *mcp = gpiochip_get_data(gc);
  380. unsigned int pos = data->hwirq;
  381. mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
  382. }
  383. static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
  384. {
  385. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  386. struct mcp23s08 *mcp = gpiochip_get_data(gc);
  387. unsigned int pos = data->hwirq;
  388. if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  389. mcp_set_bit(mcp, MCP_INTCON, pos, false);
  390. mcp->irq_rise |= BIT(pos);
  391. mcp->irq_fall |= BIT(pos);
  392. } else if (type & IRQ_TYPE_EDGE_RISING) {
  393. mcp_set_bit(mcp, MCP_INTCON, pos, false);
  394. mcp->irq_rise |= BIT(pos);
  395. mcp->irq_fall &= ~BIT(pos);
  396. } else if (type & IRQ_TYPE_EDGE_FALLING) {
  397. mcp_set_bit(mcp, MCP_INTCON, pos, false);
  398. mcp->irq_rise &= ~BIT(pos);
  399. mcp->irq_fall |= BIT(pos);
  400. } else if (type & IRQ_TYPE_LEVEL_HIGH) {
  401. mcp_set_bit(mcp, MCP_INTCON, pos, true);
  402. mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
  403. } else if (type & IRQ_TYPE_LEVEL_LOW) {
  404. mcp_set_bit(mcp, MCP_INTCON, pos, true);
  405. mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
  406. } else
  407. return -EINVAL;
  408. return 0;
  409. }
  410. static void mcp23s08_irq_bus_lock(struct irq_data *data)
  411. {
  412. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  413. struct mcp23s08 *mcp = gpiochip_get_data(gc);
  414. mutex_lock(&mcp->lock);
  415. regcache_cache_only(mcp->regmap, true);
  416. }
  417. static void mcp23s08_irq_bus_unlock(struct irq_data *data)
  418. {
  419. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  420. struct mcp23s08 *mcp = gpiochip_get_data(gc);
  421. regcache_cache_only(mcp->regmap, false);
  422. regcache_sync(mcp->regmap);
  423. mutex_unlock(&mcp->lock);
  424. }
  425. static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
  426. {
  427. struct gpio_chip *chip = &mcp->chip;
  428. int err;
  429. unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
  430. if (mcp->irq_active_high)
  431. irqflags |= IRQF_TRIGGER_HIGH;
  432. else
  433. irqflags |= IRQF_TRIGGER_LOW;
  434. err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
  435. mcp23s08_irq,
  436. irqflags, dev_name(chip->parent), mcp);
  437. if (err != 0) {
  438. dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
  439. mcp->irq, err);
  440. return err;
  441. }
  442. return 0;
  443. }
  444. /*----------------------------------------------------------------------*/
  445. int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
  446. unsigned int addr, unsigned int type, unsigned int base)
  447. {
  448. int status, ret;
  449. bool mirror = false;
  450. bool open_drain = false;
  451. mutex_init(&mcp->lock);
  452. mcp->dev = dev;
  453. mcp->addr = addr;
  454. mcp->irq_active_high = false;
  455. mcp->irq_chip.name = dev_name(dev);
  456. mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
  457. mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
  458. mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
  459. mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
  460. mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
  461. mcp->chip.direction_input = mcp23s08_direction_input;
  462. mcp->chip.get = mcp23s08_get;
  463. mcp->chip.direction_output = mcp23s08_direction_output;
  464. mcp->chip.set = mcp23s08_set;
  465. #ifdef CONFIG_OF_GPIO
  466. mcp->chip.of_gpio_n_cells = 2;
  467. mcp->chip.of_node = dev->of_node;
  468. #endif
  469. mcp->chip.base = base;
  470. mcp->chip.can_sleep = true;
  471. mcp->chip.parent = dev;
  472. mcp->chip.owner = THIS_MODULE;
  473. /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
  474. * and MCP_IOCON.HAEN = 1, so we work with all chips.
  475. */
  476. ret = mcp_read(mcp, MCP_IOCON, &status);
  477. if (ret < 0)
  478. return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
  479. mcp->irq_controller =
  480. device_property_read_bool(dev, "interrupt-controller");
  481. if (mcp->irq && mcp->irq_controller) {
  482. mcp->irq_active_high =
  483. device_property_read_bool(dev,
  484. "microchip,irq-active-high");
  485. mirror = device_property_read_bool(dev, "microchip,irq-mirror");
  486. open_drain = device_property_read_bool(dev, "drive-open-drain");
  487. }
  488. if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
  489. mcp->irq_active_high || open_drain) {
  490. /* mcp23s17 has IOCON twice, make sure they are in sync */
  491. status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
  492. status |= IOCON_HAEN | (IOCON_HAEN << 8);
  493. if (mcp->irq_active_high)
  494. status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
  495. else
  496. status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
  497. if (mirror)
  498. status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
  499. if (open_drain)
  500. status |= IOCON_ODR | (IOCON_ODR << 8);
  501. if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
  502. status |= IOCON_INTCC | (IOCON_INTCC << 8);
  503. ret = mcp_write(mcp, MCP_IOCON, status);
  504. if (ret < 0)
  505. return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
  506. }
  507. if (mcp->irq && mcp->irq_controller) {
  508. struct gpio_irq_chip *girq = &mcp->chip.irq;
  509. girq->chip = &mcp->irq_chip;
  510. /* This will let us handle the parent IRQ in the driver */
  511. girq->parent_handler = NULL;
  512. girq->num_parents = 0;
  513. girq->parents = NULL;
  514. girq->default_type = IRQ_TYPE_NONE;
  515. girq->handler = handle_simple_irq;
  516. girq->threaded = true;
  517. }
  518. ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
  519. if (ret < 0)
  520. return dev_err_probe(dev, ret, "can't add GPIO chip\n");
  521. mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
  522. mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
  523. mcp->pinctrl_desc.npins = mcp->chip.ngpio;
  524. if (mcp->pinctrl_desc.npins == 8)
  525. mcp->pinctrl_desc.pins = mcp23x08_pins;
  526. else if (mcp->pinctrl_desc.npins == 16)
  527. mcp->pinctrl_desc.pins = mcp23x17_pins;
  528. mcp->pinctrl_desc.owner = THIS_MODULE;
  529. mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
  530. if (IS_ERR(mcp->pctldev))
  531. return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
  532. if (mcp->irq) {
  533. ret = mcp23s08_irq_setup(mcp);
  534. if (ret)
  535. return dev_err_probe(dev, ret, "can't setup IRQ\n");
  536. }
  537. return 0;
  538. }
  539. EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
  540. MODULE_LICENSE("GPL");