pinctrl-max77620.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MAX77620 pin control driver.
  4. *
  5. * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * Author:
  8. * Chaitanya Bandi <bandik@nvidia.com>
  9. * Laxman Dewangan <ldewangan@nvidia.com>
  10. */
  11. #include <linux/mfd/max77620.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/pinctrl/pinctrl.h>
  15. #include <linux/pinctrl/pinconf-generic.h>
  16. #include <linux/pinctrl/pinconf.h>
  17. #include <linux/pinctrl/pinmux.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. #include "core.h"
  21. #include "pinconf.h"
  22. #include "pinctrl-utils.h"
  23. #define MAX77620_PIN_NUM 8
  24. enum max77620_pin_ppdrv {
  25. MAX77620_PIN_UNCONFIG_DRV,
  26. MAX77620_PIN_OD_DRV,
  27. MAX77620_PIN_PP_DRV,
  28. };
  29. #define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
  30. #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
  31. #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
  32. #define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
  33. #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
  34. #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
  35. struct max77620_pin_function {
  36. const char *name;
  37. const char * const *groups;
  38. unsigned int ngroups;
  39. int mux_option;
  40. };
  41. static const struct pinconf_generic_params max77620_cfg_params[] = {
  42. {
  43. .property = "maxim,active-fps-source",
  44. .param = MAX77620_ACTIVE_FPS_SOURCE,
  45. }, {
  46. .property = "maxim,active-fps-power-up-slot",
  47. .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
  48. }, {
  49. .property = "maxim,active-fps-power-down-slot",
  50. .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
  51. }, {
  52. .property = "maxim,suspend-fps-source",
  53. .param = MAX77620_SUSPEND_FPS_SOURCE,
  54. }, {
  55. .property = "maxim,suspend-fps-power-up-slot",
  56. .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
  57. }, {
  58. .property = "maxim,suspend-fps-power-down-slot",
  59. .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
  60. },
  61. };
  62. enum max77620_alternate_pinmux_option {
  63. MAX77620_PINMUX_GPIO = 0,
  64. MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
  65. MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
  66. MAX77620_PINMUX_32K_OUT1 = 3,
  67. MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
  68. MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
  69. MAX77620_PINMUX_REFERENCE_OUT = 6,
  70. };
  71. struct max77620_pingroup {
  72. const char *name;
  73. const unsigned int pins[1];
  74. unsigned int npins;
  75. enum max77620_alternate_pinmux_option alt_option;
  76. };
  77. struct max77620_pin_info {
  78. enum max77620_pin_ppdrv drv_type;
  79. int pull_config;
  80. };
  81. struct max77620_fps_config {
  82. int active_fps_src;
  83. int active_power_up_slots;
  84. int active_power_down_slots;
  85. int suspend_fps_src;
  86. int suspend_power_up_slots;
  87. int suspend_power_down_slots;
  88. };
  89. struct max77620_pctrl_info {
  90. struct device *dev;
  91. struct pinctrl_dev *pctl;
  92. struct regmap *rmap;
  93. int pins_current_opt[MAX77620_GPIO_NR];
  94. const struct max77620_pin_function *functions;
  95. unsigned int num_functions;
  96. const struct max77620_pingroup *pin_groups;
  97. int num_pin_groups;
  98. const struct pinctrl_pin_desc *pins;
  99. unsigned int num_pins;
  100. struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
  101. struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
  102. };
  103. static const struct pinctrl_pin_desc max77620_pins_desc[] = {
  104. PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
  105. PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
  106. PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
  107. PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
  108. PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
  109. PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
  110. PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
  111. PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
  112. };
  113. static const char * const gpio_groups[] = {
  114. "gpio0",
  115. "gpio1",
  116. "gpio2",
  117. "gpio3",
  118. "gpio4",
  119. "gpio5",
  120. "gpio6",
  121. "gpio7",
  122. };
  123. #define FUNCTION_GROUP(fname, mux) \
  124. { \
  125. .name = fname, \
  126. .groups = gpio_groups, \
  127. .ngroups = ARRAY_SIZE(gpio_groups), \
  128. .mux_option = MAX77620_PINMUX_##mux, \
  129. }
  130. static const struct max77620_pin_function max77620_pin_function[] = {
  131. FUNCTION_GROUP("gpio", GPIO),
  132. FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
  133. FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
  134. FUNCTION_GROUP("32k-out1", 32K_OUT1),
  135. FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
  136. FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
  137. FUNCTION_GROUP("reference-out", REFERENCE_OUT),
  138. };
  139. #define MAX77620_PINGROUP(pg_name, pin_id, option) \
  140. { \
  141. .name = #pg_name, \
  142. .pins = {MAX77620_##pin_id}, \
  143. .npins = 1, \
  144. .alt_option = MAX77620_PINMUX_##option, \
  145. }
  146. static const struct max77620_pingroup max77620_pingroups[] = {
  147. MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
  148. MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
  149. MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
  150. MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
  151. MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
  152. MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
  153. MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
  154. MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
  155. };
  156. static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  157. {
  158. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  159. return mpci->num_pin_groups;
  160. }
  161. static const char *max77620_pinctrl_get_group_name(
  162. struct pinctrl_dev *pctldev, unsigned int group)
  163. {
  164. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  165. return mpci->pin_groups[group].name;
  166. }
  167. static int max77620_pinctrl_get_group_pins(
  168. struct pinctrl_dev *pctldev, unsigned int group,
  169. const unsigned int **pins, unsigned int *num_pins)
  170. {
  171. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  172. *pins = mpci->pin_groups[group].pins;
  173. *num_pins = mpci->pin_groups[group].npins;
  174. return 0;
  175. }
  176. static const struct pinctrl_ops max77620_pinctrl_ops = {
  177. .get_groups_count = max77620_pinctrl_get_groups_count,
  178. .get_group_name = max77620_pinctrl_get_group_name,
  179. .get_group_pins = max77620_pinctrl_get_group_pins,
  180. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  181. .dt_free_map = pinctrl_utils_free_map,
  182. };
  183. static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
  184. {
  185. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  186. return mpci->num_functions;
  187. }
  188. static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
  189. unsigned int function)
  190. {
  191. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  192. return mpci->functions[function].name;
  193. }
  194. static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
  195. unsigned int function,
  196. const char * const **groups,
  197. unsigned int * const num_groups)
  198. {
  199. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  200. *groups = mpci->functions[function].groups;
  201. *num_groups = mpci->functions[function].ngroups;
  202. return 0;
  203. }
  204. static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
  205. unsigned int function, unsigned int group)
  206. {
  207. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  208. u8 val;
  209. int ret;
  210. if (function == MAX77620_PINMUX_GPIO) {
  211. val = 0;
  212. } else if (function == mpci->pin_groups[group].alt_option) {
  213. val = 1 << group;
  214. } else {
  215. dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
  216. group, function);
  217. return -EINVAL;
  218. }
  219. ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
  220. BIT(group), val);
  221. if (ret < 0)
  222. dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
  223. return ret;
  224. }
  225. static const struct pinmux_ops max77620_pinmux_ops = {
  226. .get_functions_count = max77620_pinctrl_get_funcs_count,
  227. .get_function_name = max77620_pinctrl_get_func_name,
  228. .get_function_groups = max77620_pinctrl_get_func_groups,
  229. .set_mux = max77620_pinctrl_enable,
  230. };
  231. static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
  232. unsigned int pin, unsigned long *config)
  233. {
  234. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  235. struct device *dev = mpci->dev;
  236. enum pin_config_param param = pinconf_to_config_param(*config);
  237. unsigned int val;
  238. int arg = 0;
  239. int ret;
  240. switch (param) {
  241. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  242. if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
  243. arg = 1;
  244. break;
  245. case PIN_CONFIG_DRIVE_PUSH_PULL:
  246. if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
  247. arg = 1;
  248. break;
  249. case PIN_CONFIG_BIAS_PULL_UP:
  250. ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
  251. if (ret < 0) {
  252. dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
  253. return ret;
  254. }
  255. if (val & BIT(pin))
  256. arg = 1;
  257. break;
  258. case PIN_CONFIG_BIAS_PULL_DOWN:
  259. ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
  260. if (ret < 0) {
  261. dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
  262. return ret;
  263. }
  264. if (val & BIT(pin))
  265. arg = 1;
  266. break;
  267. default:
  268. dev_err(dev, "Properties not supported\n");
  269. return -ENOTSUPP;
  270. }
  271. *config = pinconf_to_config_packed(param, (u16)arg);
  272. return 0;
  273. }
  274. static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
  275. int addr, int *fps)
  276. {
  277. unsigned int val;
  278. int ret;
  279. ret = regmap_read(mpci->rmap, addr, &val);
  280. if (ret < 0) {
  281. dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
  282. return ret;
  283. }
  284. *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
  285. return 0;
  286. }
  287. static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
  288. int pin, int param)
  289. {
  290. struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
  291. int addr, ret;
  292. int param_val;
  293. int mask, shift;
  294. if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
  295. return 0;
  296. addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
  297. switch (param) {
  298. case MAX77620_ACTIVE_FPS_SOURCE:
  299. case MAX77620_SUSPEND_FPS_SOURCE:
  300. mask = MAX77620_FPS_SRC_MASK;
  301. shift = MAX77620_FPS_SRC_SHIFT;
  302. param_val = fps_config->active_fps_src;
  303. if (param == MAX77620_SUSPEND_FPS_SOURCE)
  304. param_val = fps_config->suspend_fps_src;
  305. break;
  306. case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
  307. case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
  308. mask = MAX77620_FPS_PU_PERIOD_MASK;
  309. shift = MAX77620_FPS_PU_PERIOD_SHIFT;
  310. param_val = fps_config->active_power_up_slots;
  311. if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
  312. param_val = fps_config->suspend_power_up_slots;
  313. break;
  314. case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
  315. case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
  316. mask = MAX77620_FPS_PD_PERIOD_MASK;
  317. shift = MAX77620_FPS_PD_PERIOD_SHIFT;
  318. param_val = fps_config->active_power_down_slots;
  319. if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
  320. param_val = fps_config->suspend_power_down_slots;
  321. break;
  322. default:
  323. dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
  324. param, pin);
  325. return -EINVAL;
  326. }
  327. if (param_val < 0)
  328. return 0;
  329. ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
  330. if (ret < 0)
  331. dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
  332. return ret;
  333. }
  334. static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
  335. unsigned int pin, unsigned long *configs,
  336. unsigned int num_configs)
  337. {
  338. struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
  339. struct device *dev = mpci->dev;
  340. struct max77620_fps_config *fps_config;
  341. int param;
  342. u32 param_val;
  343. unsigned int val;
  344. unsigned int pu_val;
  345. unsigned int pd_val;
  346. int addr, ret;
  347. int i;
  348. for (i = 0; i < num_configs; i++) {
  349. param = pinconf_to_config_param(configs[i]);
  350. param_val = pinconf_to_config_argument(configs[i]);
  351. switch (param) {
  352. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  353. val = param_val ? 0 : 1;
  354. ret = regmap_update_bits(mpci->rmap,
  355. MAX77620_REG_GPIO0 + pin,
  356. MAX77620_CNFG_GPIO_DRV_MASK,
  357. val);
  358. if (ret)
  359. goto report_update_failure;
  360. mpci->pin_info[pin].drv_type = val ?
  361. MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
  362. break;
  363. case PIN_CONFIG_DRIVE_PUSH_PULL:
  364. val = param_val ? 1 : 0;
  365. ret = regmap_update_bits(mpci->rmap,
  366. MAX77620_REG_GPIO0 + pin,
  367. MAX77620_CNFG_GPIO_DRV_MASK,
  368. val);
  369. if (ret)
  370. goto report_update_failure;
  371. mpci->pin_info[pin].drv_type = val ?
  372. MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
  373. break;
  374. case MAX77620_ACTIVE_FPS_SOURCE:
  375. case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
  376. case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
  377. if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
  378. return -EINVAL;
  379. fps_config = &mpci->fps_config[pin];
  380. if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
  381. (param_val == MAX77620_FPS_SRC_DEF)) {
  382. addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
  383. ret = max77620_get_default_fps(
  384. mpci, addr,
  385. &fps_config->active_fps_src);
  386. if (ret < 0)
  387. return ret;
  388. break;
  389. }
  390. if (param == MAX77620_ACTIVE_FPS_SOURCE)
  391. fps_config->active_fps_src = param_val;
  392. else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
  393. fps_config->active_power_up_slots = param_val;
  394. else
  395. fps_config->active_power_down_slots = param_val;
  396. ret = max77620_set_fps_param(mpci, pin, param);
  397. if (ret < 0)
  398. return ret;
  399. break;
  400. case MAX77620_SUSPEND_FPS_SOURCE:
  401. case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
  402. case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
  403. if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
  404. return -EINVAL;
  405. fps_config = &mpci->fps_config[pin];
  406. if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
  407. (param_val == MAX77620_FPS_SRC_DEF)) {
  408. addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
  409. ret = max77620_get_default_fps(
  410. mpci, addr,
  411. &fps_config->suspend_fps_src);
  412. if (ret < 0)
  413. return ret;
  414. break;
  415. }
  416. if (param == MAX77620_SUSPEND_FPS_SOURCE)
  417. fps_config->suspend_fps_src = param_val;
  418. else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
  419. fps_config->suspend_power_up_slots = param_val;
  420. else
  421. fps_config->suspend_power_down_slots =
  422. param_val;
  423. break;
  424. case PIN_CONFIG_BIAS_PULL_UP:
  425. case PIN_CONFIG_BIAS_PULL_DOWN:
  426. pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
  427. BIT(pin) : 0;
  428. pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
  429. BIT(pin) : 0;
  430. ret = regmap_update_bits(mpci->rmap,
  431. MAX77620_REG_PUE_GPIO,
  432. BIT(pin), pu_val);
  433. if (ret < 0) {
  434. dev_err(dev, "PUE_GPIO update failed: %d\n",
  435. ret);
  436. return ret;
  437. }
  438. ret = regmap_update_bits(mpci->rmap,
  439. MAX77620_REG_PDE_GPIO,
  440. BIT(pin), pd_val);
  441. if (ret < 0) {
  442. dev_err(dev, "PDE_GPIO update failed: %d\n",
  443. ret);
  444. return ret;
  445. }
  446. break;
  447. default:
  448. dev_err(dev, "Properties not supported\n");
  449. return -ENOTSUPP;
  450. }
  451. }
  452. return 0;
  453. report_update_failure:
  454. dev_err(dev, "Reg 0x%02x update failed %d\n",
  455. MAX77620_REG_GPIO0 + pin, ret);
  456. return ret;
  457. }
  458. static const struct pinconf_ops max77620_pinconf_ops = {
  459. .pin_config_get = max77620_pinconf_get,
  460. .pin_config_set = max77620_pinconf_set,
  461. };
  462. static struct pinctrl_desc max77620_pinctrl_desc = {
  463. .pctlops = &max77620_pinctrl_ops,
  464. .pmxops = &max77620_pinmux_ops,
  465. .confops = &max77620_pinconf_ops,
  466. };
  467. static int max77620_pinctrl_probe(struct platform_device *pdev)
  468. {
  469. struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
  470. struct max77620_pctrl_info *mpci;
  471. int i;
  472. mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
  473. if (!mpci)
  474. return -ENOMEM;
  475. mpci->dev = &pdev->dev;
  476. mpci->dev->of_node = pdev->dev.parent->of_node;
  477. mpci->rmap = max77620->rmap;
  478. mpci->pins = max77620_pins_desc;
  479. mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
  480. mpci->functions = max77620_pin_function;
  481. mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
  482. mpci->pin_groups = max77620_pingroups;
  483. mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
  484. platform_set_drvdata(pdev, mpci);
  485. max77620_pinctrl_desc.name = dev_name(&pdev->dev);
  486. max77620_pinctrl_desc.pins = max77620_pins_desc;
  487. max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
  488. max77620_pinctrl_desc.num_custom_params =
  489. ARRAY_SIZE(max77620_cfg_params);
  490. max77620_pinctrl_desc.custom_params = max77620_cfg_params;
  491. for (i = 0; i < MAX77620_PIN_NUM; ++i) {
  492. mpci->fps_config[i].active_fps_src = -1;
  493. mpci->fps_config[i].active_power_up_slots = -1;
  494. mpci->fps_config[i].active_power_down_slots = -1;
  495. mpci->fps_config[i].suspend_fps_src = -1;
  496. mpci->fps_config[i].suspend_power_up_slots = -1;
  497. mpci->fps_config[i].suspend_power_down_slots = -1;
  498. }
  499. mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
  500. mpci);
  501. if (IS_ERR(mpci->pctl)) {
  502. dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
  503. return PTR_ERR(mpci->pctl);
  504. }
  505. return 0;
  506. }
  507. #ifdef CONFIG_PM_SLEEP
  508. static int max77620_suspend_fps_param[] = {
  509. MAX77620_SUSPEND_FPS_SOURCE,
  510. MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
  511. MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
  512. };
  513. static int max77620_active_fps_param[] = {
  514. MAX77620_ACTIVE_FPS_SOURCE,
  515. MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
  516. MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
  517. };
  518. static int max77620_pinctrl_suspend(struct device *dev)
  519. {
  520. struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
  521. int pin, p;
  522. for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
  523. if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
  524. continue;
  525. for (p = 0; p < 3; ++p)
  526. max77620_set_fps_param(
  527. mpci, pin, max77620_suspend_fps_param[p]);
  528. }
  529. return 0;
  530. };
  531. static int max77620_pinctrl_resume(struct device *dev)
  532. {
  533. struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
  534. int pin, p;
  535. for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
  536. if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
  537. continue;
  538. for (p = 0; p < 3; ++p)
  539. max77620_set_fps_param(
  540. mpci, pin, max77620_active_fps_param[p]);
  541. }
  542. return 0;
  543. }
  544. #endif
  545. static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
  546. SET_SYSTEM_SLEEP_PM_OPS(
  547. max77620_pinctrl_suspend, max77620_pinctrl_resume)
  548. };
  549. static const struct platform_device_id max77620_pinctrl_devtype[] = {
  550. { .name = "max77620-pinctrl", },
  551. { .name = "max20024-pinctrl", },
  552. {},
  553. };
  554. MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
  555. static struct platform_driver max77620_pinctrl_driver = {
  556. .driver = {
  557. .name = "max77620-pinctrl",
  558. .pm = &max77620_pinctrl_pm_ops,
  559. },
  560. .probe = max77620_pinctrl_probe,
  561. .id_table = max77620_pinctrl_devtype,
  562. };
  563. module_platform_driver(max77620_pinctrl_driver);
  564. MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
  565. MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
  566. MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
  567. MODULE_ALIAS("platform:max77620-pinctrl");
  568. MODULE_LICENSE("GPL v2");