pinctrl-lantiq.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/drivers/pinctrl/pinctrl-lantiq.h
  4. * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
  5. *
  6. * Copyright (C) 2012 John Crispin <john@phrozen.org>
  7. */
  8. #ifndef __PINCTRL_LANTIQ_H
  9. #define __PINCTRL_LANTIQ_H
  10. #include <linux/clkdev.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include <linux/pinctrl/pinconf.h>
  13. #include <linux/pinctrl/pinmux.h>
  14. #include <linux/pinctrl/consumer.h>
  15. #include <linux/pinctrl/machine.h>
  16. #include "core.h"
  17. #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
  18. #define LTQ_MAX_MUX 4
  19. #define MFPR_FUNC_MASK 0x3
  20. #define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg))
  21. #define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)
  22. #define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)
  23. enum ltq_pinconf_param {
  24. LTQ_PINCONF_PARAM_PULL,
  25. LTQ_PINCONF_PARAM_OPEN_DRAIN,
  26. LTQ_PINCONF_PARAM_DRIVE_CURRENT,
  27. LTQ_PINCONF_PARAM_SLEW_RATE,
  28. LTQ_PINCONF_PARAM_OUTPUT,
  29. };
  30. struct ltq_cfg_param {
  31. const char *property;
  32. enum ltq_pinconf_param param;
  33. };
  34. struct ltq_mfp_pin {
  35. const char *name;
  36. const unsigned int pin;
  37. const unsigned short func[LTQ_MAX_MUX];
  38. };
  39. struct ltq_pin_group {
  40. const char *name;
  41. const unsigned mux;
  42. const unsigned *pins;
  43. const unsigned npins;
  44. };
  45. struct ltq_pmx_func {
  46. const char *name;
  47. const char * const *groups;
  48. const unsigned num_groups;
  49. };
  50. struct ltq_pinmux_info {
  51. struct device *dev;
  52. struct pinctrl_dev *pctrl;
  53. /* we need to manage up to 5 pad controllers */
  54. void __iomem *membase[5];
  55. /* the descriptor for the subsystem */
  56. struct pinctrl_desc *desc;
  57. /* we expose our pads to the subsystem */
  58. struct pinctrl_pin_desc *pads;
  59. /* the number of pads. this varies between socs */
  60. unsigned int num_pads;
  61. /* these are our multifunction pins */
  62. const struct ltq_mfp_pin *mfp;
  63. unsigned int num_mfp;
  64. /* a number of multifunction pins can be grouped together */
  65. const struct ltq_pin_group *grps;
  66. unsigned int num_grps;
  67. /* a mapping between function string and id */
  68. const struct ltq_pmx_func *funcs;
  69. unsigned int num_funcs;
  70. /* the pinconf options that we are able to read from the DT */
  71. const struct ltq_cfg_param *params;
  72. unsigned int num_params;
  73. /* the pad controller can have a irq mapping */
  74. const unsigned *exin;
  75. unsigned int num_exin;
  76. /* we need 5 clocks max */
  77. struct clk *clk[5];
  78. /* soc specific callback used to apply muxing */
  79. int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
  80. };
  81. enum ltq_pin {
  82. GPIO0 = 0,
  83. GPIO1,
  84. GPIO2,
  85. GPIO3,
  86. GPIO4,
  87. GPIO5,
  88. GPIO6,
  89. GPIO7,
  90. GPIO8,
  91. GPIO9,
  92. GPIO10, /* 10 */
  93. GPIO11,
  94. GPIO12,
  95. GPIO13,
  96. GPIO14,
  97. GPIO15,
  98. GPIO16,
  99. GPIO17,
  100. GPIO18,
  101. GPIO19,
  102. GPIO20, /* 20 */
  103. GPIO21,
  104. GPIO22,
  105. GPIO23,
  106. GPIO24,
  107. GPIO25,
  108. GPIO26,
  109. GPIO27,
  110. GPIO28,
  111. GPIO29,
  112. GPIO30, /* 30 */
  113. GPIO31,
  114. GPIO32,
  115. GPIO33,
  116. GPIO34,
  117. GPIO35,
  118. GPIO36,
  119. GPIO37,
  120. GPIO38,
  121. GPIO39,
  122. GPIO40, /* 40 */
  123. GPIO41,
  124. GPIO42,
  125. GPIO43,
  126. GPIO44,
  127. GPIO45,
  128. GPIO46,
  129. GPIO47,
  130. GPIO48,
  131. GPIO49,
  132. GPIO50, /* 50 */
  133. GPIO51,
  134. GPIO52,
  135. GPIO53,
  136. GPIO54,
  137. GPIO55,
  138. GPIO56,
  139. GPIO57,
  140. GPIO58,
  141. GPIO59,
  142. GPIO60, /* 60 */
  143. GPIO61,
  144. GPIO62,
  145. GPIO63,
  146. GPIO64,
  147. GPIO65,
  148. GPIO66,
  149. GPIO67,
  150. GPIO68,
  151. GPIO69,
  152. GPIO70,
  153. GPIO71,
  154. GPIO72,
  155. GPIO73,
  156. GPIO74,
  157. GPIO75,
  158. GPIO76,
  159. GPIO77,
  160. GPIO78,
  161. GPIO79,
  162. GPIO80,
  163. GPIO81,
  164. GPIO82,
  165. GPIO83,
  166. GPIO84,
  167. GPIO85,
  168. GPIO86,
  169. GPIO87,
  170. GPIO88,
  171. };
  172. extern int ltq_pinctrl_register(struct platform_device *pdev,
  173. struct ltq_pinmux_info *info);
  174. extern int ltq_pinctrl_unregister(struct platform_device *pdev);
  175. #endif /* __PINCTRL_LANTIQ_H */