pinctrl-ingenic.c 113 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ingenic SoCs pinctrl driver
  4. *
  5. * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
  6. * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
  7. * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
  8. */
  9. #include <linux/compiler.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/of_device.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/pinctrl/pinctrl.h>
  17. #include <linux/pinctrl/pinmux.h>
  18. #include <linux/pinctrl/pinconf.h>
  19. #include <linux/pinctrl/pinconf-generic.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/regmap.h>
  22. #include <linux/slab.h>
  23. #include "core.h"
  24. #include "pinconf.h"
  25. #include "pinmux.h"
  26. #define GPIO_PIN 0x00
  27. #define GPIO_MSK 0x20
  28. #define JZ4740_GPIO_DATA 0x10
  29. #define JZ4740_GPIO_PULL_DIS 0x30
  30. #define JZ4740_GPIO_FUNC 0x40
  31. #define JZ4740_GPIO_SELECT 0x50
  32. #define JZ4740_GPIO_DIR 0x60
  33. #define JZ4740_GPIO_TRIG 0x70
  34. #define JZ4740_GPIO_FLAG 0x80
  35. #define JZ4760_GPIO_INT 0x10
  36. #define JZ4760_GPIO_PAT1 0x30
  37. #define JZ4760_GPIO_PAT0 0x40
  38. #define JZ4760_GPIO_FLAG 0x50
  39. #define JZ4760_GPIO_PEN 0x70
  40. #define X1830_GPIO_PEL 0x110
  41. #define X1830_GPIO_PEH 0x120
  42. #define REG_SET(x) ((x) + 0x4)
  43. #define REG_CLEAR(x) ((x) + 0x8)
  44. #define REG_PZ_BASE(x) ((x) * 7)
  45. #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
  46. #define GPIO_PULL_DIS 0
  47. #define GPIO_PULL_UP 1
  48. #define GPIO_PULL_DOWN 2
  49. #define PINS_PER_GPIO_CHIP 32
  50. enum jz_version {
  51. ID_JZ4740,
  52. ID_JZ4725B,
  53. ID_JZ4760,
  54. ID_JZ4770,
  55. ID_JZ4780,
  56. ID_X1000,
  57. ID_X1500,
  58. ID_X1830,
  59. };
  60. struct ingenic_chip_info {
  61. unsigned int num_chips;
  62. unsigned int reg_offset;
  63. enum jz_version version;
  64. const struct group_desc *groups;
  65. unsigned int num_groups;
  66. const struct function_desc *functions;
  67. unsigned int num_functions;
  68. const u32 *pull_ups, *pull_downs;
  69. };
  70. struct ingenic_pinctrl {
  71. struct device *dev;
  72. struct regmap *map;
  73. struct pinctrl_dev *pctl;
  74. struct pinctrl_pin_desc *pdesc;
  75. const struct ingenic_chip_info *info;
  76. };
  77. struct ingenic_gpio_chip {
  78. struct ingenic_pinctrl *jzpc;
  79. struct gpio_chip gc;
  80. struct irq_chip irq_chip;
  81. unsigned int irq, reg_base;
  82. };
  83. static const u32 jz4740_pull_ups[4] = {
  84. 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
  85. };
  86. static const u32 jz4740_pull_downs[4] = {
  87. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  88. };
  89. static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
  90. static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
  91. static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
  92. static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
  93. static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
  94. static int jz4740_lcd_8bit_pins[] = {
  95. 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
  96. };
  97. static int jz4740_lcd_16bit_pins[] = {
  98. 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
  99. };
  100. static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
  101. static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
  102. static int jz4740_nand_cs1_pins[] = { 0x39, };
  103. static int jz4740_nand_cs2_pins[] = { 0x3a, };
  104. static int jz4740_nand_cs3_pins[] = { 0x3b, };
  105. static int jz4740_nand_cs4_pins[] = { 0x3c, };
  106. static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
  107. static int jz4740_pwm_pwm0_pins[] = { 0x77, };
  108. static int jz4740_pwm_pwm1_pins[] = { 0x78, };
  109. static int jz4740_pwm_pwm2_pins[] = { 0x79, };
  110. static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
  111. static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
  112. static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
  113. static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
  114. static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
  115. static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
  116. static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
  117. static int jz4740_uart0_data_funcs[] = { 1, 1, };
  118. static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
  119. static int jz4740_uart1_data_funcs[] = { 2, 2, };
  120. static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  121. static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  122. static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
  123. static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
  124. static int jz4740_nand_cs1_funcs[] = { 0, };
  125. static int jz4740_nand_cs2_funcs[] = { 0, };
  126. static int jz4740_nand_cs3_funcs[] = { 0, };
  127. static int jz4740_nand_cs4_funcs[] = { 0, };
  128. static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, };
  129. static int jz4740_pwm_pwm0_funcs[] = { 0, };
  130. static int jz4740_pwm_pwm1_funcs[] = { 0, };
  131. static int jz4740_pwm_pwm2_funcs[] = { 0, };
  132. static int jz4740_pwm_pwm3_funcs[] = { 0, };
  133. static int jz4740_pwm_pwm4_funcs[] = { 0, };
  134. static int jz4740_pwm_pwm5_funcs[] = { 0, };
  135. static int jz4740_pwm_pwm6_funcs[] = { 0, };
  136. static int jz4740_pwm_pwm7_funcs[] = { 0, };
  137. #define INGENIC_PIN_GROUP(name, id) \
  138. { \
  139. name, \
  140. id##_pins, \
  141. ARRAY_SIZE(id##_pins), \
  142. id##_funcs, \
  143. }
  144. static const struct group_desc jz4740_groups[] = {
  145. INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
  146. INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
  147. INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
  148. INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
  149. INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
  150. INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
  151. INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
  152. INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
  153. INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
  154. { "lcd-no-pins", },
  155. INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
  156. INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
  157. INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
  158. INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
  159. INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe),
  160. INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
  161. INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
  162. INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
  163. INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
  164. INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
  165. INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
  166. INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
  167. INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
  168. };
  169. static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
  170. static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
  171. static const char *jz4740_uart1_groups[] = { "uart1-data", };
  172. static const char *jz4740_lcd_groups[] = {
  173. "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
  174. };
  175. static const char *jz4740_nand_groups[] = {
  176. "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
  177. };
  178. static const char *jz4740_pwm0_groups[] = { "pwm0", };
  179. static const char *jz4740_pwm1_groups[] = { "pwm1", };
  180. static const char *jz4740_pwm2_groups[] = { "pwm2", };
  181. static const char *jz4740_pwm3_groups[] = { "pwm3", };
  182. static const char *jz4740_pwm4_groups[] = { "pwm4", };
  183. static const char *jz4740_pwm5_groups[] = { "pwm5", };
  184. static const char *jz4740_pwm6_groups[] = { "pwm6", };
  185. static const char *jz4740_pwm7_groups[] = { "pwm7", };
  186. static const struct function_desc jz4740_functions[] = {
  187. { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
  188. { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
  189. { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
  190. { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
  191. { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
  192. { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
  193. { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
  194. { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
  195. { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
  196. { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
  197. { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
  198. { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
  199. { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
  200. };
  201. static const struct ingenic_chip_info jz4740_chip_info = {
  202. .num_chips = 4,
  203. .reg_offset = 0x100,
  204. .version = ID_JZ4740,
  205. .groups = jz4740_groups,
  206. .num_groups = ARRAY_SIZE(jz4740_groups),
  207. .functions = jz4740_functions,
  208. .num_functions = ARRAY_SIZE(jz4740_functions),
  209. .pull_ups = jz4740_pull_ups,
  210. .pull_downs = jz4740_pull_downs,
  211. };
  212. static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
  213. static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
  214. static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
  215. static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
  216. static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
  217. static int jz4725b_nand_cs1_pins[] = { 0x55, };
  218. static int jz4725b_nand_cs2_pins[] = { 0x56, };
  219. static int jz4725b_nand_cs3_pins[] = { 0x57, };
  220. static int jz4725b_nand_cs4_pins[] = { 0x58, };
  221. static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
  222. static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
  223. static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
  224. static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
  225. static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
  226. static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
  227. static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
  228. static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
  229. static int jz4725b_lcd_8bit_pins[] = {
  230. 0x72, 0x73, 0x74,
  231. 0x60, 0x61, 0x62, 0x63,
  232. 0x64, 0x65, 0x66, 0x67,
  233. };
  234. static int jz4725b_lcd_16bit_pins[] = {
  235. 0x68, 0x69, 0x6a, 0x6b,
  236. 0x6c, 0x6d, 0x6e, 0x6f,
  237. };
  238. static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
  239. static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
  240. static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
  241. static int jz4725b_lcd_generic_pins[] = { 0x75, };
  242. static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
  243. static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
  244. static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, };
  245. static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, };
  246. static int jz4725b_uart_data_funcs[] = { 1, 1, };
  247. static int jz4725b_nand_cs1_funcs[] = { 0, };
  248. static int jz4725b_nand_cs2_funcs[] = { 0, };
  249. static int jz4725b_nand_cs3_funcs[] = { 0, };
  250. static int jz4725b_nand_cs4_funcs[] = { 0, };
  251. static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, };
  252. static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, };
  253. static int jz4725b_pwm_pwm0_funcs[] = { 0, };
  254. static int jz4725b_pwm_pwm1_funcs[] = { 0, };
  255. static int jz4725b_pwm_pwm2_funcs[] = { 0, };
  256. static int jz4725b_pwm_pwm3_funcs[] = { 0, };
  257. static int jz4725b_pwm_pwm4_funcs[] = { 0, };
  258. static int jz4725b_pwm_pwm5_funcs[] = { 0, };
  259. static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  260. static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  261. static int jz4725b_lcd_18bit_funcs[] = { 0, 0, };
  262. static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, };
  263. static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, };
  264. static int jz4725b_lcd_generic_funcs[] = { 0, };
  265. static const struct group_desc jz4725b_groups[] = {
  266. INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
  267. INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
  268. INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
  269. INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
  270. INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
  271. INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
  272. INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
  273. INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
  274. INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
  275. INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
  276. INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
  277. INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0),
  278. INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1),
  279. INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2),
  280. INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
  281. INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
  282. INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
  283. INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
  284. INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
  285. INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
  286. INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
  287. INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
  288. INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
  289. };
  290. static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
  291. static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
  292. static const char *jz4725b_uart_groups[] = { "uart-data", };
  293. static const char *jz4725b_nand_groups[] = {
  294. "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
  295. "nand-cle-ale", "nand-fre-fwe",
  296. };
  297. static const char *jz4725b_pwm0_groups[] = { "pwm0", };
  298. static const char *jz4725b_pwm1_groups[] = { "pwm1", };
  299. static const char *jz4725b_pwm2_groups[] = { "pwm2", };
  300. static const char *jz4725b_pwm3_groups[] = { "pwm3", };
  301. static const char *jz4725b_pwm4_groups[] = { "pwm4", };
  302. static const char *jz4725b_pwm5_groups[] = { "pwm5", };
  303. static const char *jz4725b_lcd_groups[] = {
  304. "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
  305. "lcd-special", "lcd-generic",
  306. };
  307. static const struct function_desc jz4725b_functions[] = {
  308. { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
  309. { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
  310. { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
  311. { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
  312. { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
  313. { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
  314. { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
  315. { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
  316. { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
  317. { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
  318. { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
  319. };
  320. static const struct ingenic_chip_info jz4725b_chip_info = {
  321. .num_chips = 4,
  322. .reg_offset = 0x100,
  323. .version = ID_JZ4725B,
  324. .groups = jz4725b_groups,
  325. .num_groups = ARRAY_SIZE(jz4725b_groups),
  326. .functions = jz4725b_functions,
  327. .num_functions = ARRAY_SIZE(jz4725b_functions),
  328. .pull_ups = jz4740_pull_ups,
  329. .pull_downs = jz4740_pull_downs,
  330. };
  331. static const u32 jz4760_pull_ups[6] = {
  332. 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
  333. };
  334. static const u32 jz4760_pull_downs[6] = {
  335. 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
  336. };
  337. static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
  338. static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
  339. static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
  340. static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
  341. static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
  342. static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
  343. static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
  344. static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
  345. static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
  346. static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
  347. static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
  348. static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
  349. static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
  350. static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
  351. static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
  352. static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
  353. static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
  354. static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
  355. static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
  356. static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
  357. static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
  358. static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
  359. static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
  360. static int jz4760_nemc_8bit_data_pins[] = {
  361. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  362. };
  363. static int jz4760_nemc_16bit_data_pins[] = {
  364. 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  365. };
  366. static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
  367. static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
  368. static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
  369. static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
  370. static int jz4760_nemc_wait_pins[] = { 0x1b, };
  371. static int jz4760_nemc_cs1_pins[] = { 0x15, };
  372. static int jz4760_nemc_cs2_pins[] = { 0x16, };
  373. static int jz4760_nemc_cs3_pins[] = { 0x17, };
  374. static int jz4760_nemc_cs4_pins[] = { 0x18, };
  375. static int jz4760_nemc_cs5_pins[] = { 0x19, };
  376. static int jz4760_nemc_cs6_pins[] = { 0x1a, };
  377. static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
  378. static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
  379. static int jz4760_cim_pins[] = {
  380. 0x26, 0x27, 0x28, 0x29,
  381. 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
  382. };
  383. static int jz4760_lcd_24bit_pins[] = {
  384. 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  385. 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  386. 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  387. 0x58, 0x59, 0x5a, 0x5b,
  388. };
  389. static int jz4760_pwm_pwm0_pins[] = { 0x80, };
  390. static int jz4760_pwm_pwm1_pins[] = { 0x81, };
  391. static int jz4760_pwm_pwm2_pins[] = { 0x82, };
  392. static int jz4760_pwm_pwm3_pins[] = { 0x83, };
  393. static int jz4760_pwm_pwm4_pins[] = { 0x84, };
  394. static int jz4760_pwm_pwm5_pins[] = { 0x85, };
  395. static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
  396. static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
  397. static int jz4760_uart0_data_funcs[] = { 0, 0, };
  398. static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
  399. static int jz4760_uart1_data_funcs[] = { 0, 0, };
  400. static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
  401. static int jz4760_uart2_data_funcs[] = { 0, 0, };
  402. static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
  403. static int jz4760_uart3_data_funcs[] = { 0, 1, };
  404. static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
  405. static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
  406. static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
  407. static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
  408. static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
  409. static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
  410. static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
  411. static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
  412. static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
  413. static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
  414. static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
  415. static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
  416. static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
  417. static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
  418. static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
  419. static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
  420. static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  421. static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  422. static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
  423. static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
  424. static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
  425. static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
  426. static int jz4760_nemc_wait_funcs[] = { 0, };
  427. static int jz4760_nemc_cs1_funcs[] = { 0, };
  428. static int jz4760_nemc_cs2_funcs[] = { 0, };
  429. static int jz4760_nemc_cs3_funcs[] = { 0, };
  430. static int jz4760_nemc_cs4_funcs[] = { 0, };
  431. static int jz4760_nemc_cs5_funcs[] = { 0, };
  432. static int jz4760_nemc_cs6_funcs[] = { 0, };
  433. static int jz4760_i2c0_funcs[] = { 0, 0, };
  434. static int jz4760_i2c1_funcs[] = { 0, 0, };
  435. static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  436. static int jz4760_lcd_24bit_funcs[] = {
  437. 0, 0, 0, 0, 0, 0, 0, 0,
  438. 0, 0, 0, 0, 0, 0, 0, 0,
  439. 0, 0, 0, 0, 0, 0, 0, 0,
  440. 0, 0, 0, 0,
  441. };
  442. static int jz4760_pwm_pwm0_funcs[] = { 0, };
  443. static int jz4760_pwm_pwm1_funcs[] = { 0, };
  444. static int jz4760_pwm_pwm2_funcs[] = { 0, };
  445. static int jz4760_pwm_pwm3_funcs[] = { 0, };
  446. static int jz4760_pwm_pwm4_funcs[] = { 0, };
  447. static int jz4760_pwm_pwm5_funcs[] = { 0, };
  448. static int jz4760_pwm_pwm6_funcs[] = { 0, };
  449. static int jz4760_pwm_pwm7_funcs[] = { 0, };
  450. static const struct group_desc jz4760_groups[] = {
  451. INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
  452. INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
  453. INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
  454. INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
  455. INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
  456. INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
  457. INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
  458. INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
  459. INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
  460. INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
  461. INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
  462. INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
  463. INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
  464. INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
  465. INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
  466. INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
  467. INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
  468. INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
  469. INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
  470. INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
  471. INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
  472. INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
  473. INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
  474. INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
  475. INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
  476. INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
  477. INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
  478. INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
  479. INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
  480. INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
  481. INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
  482. INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
  483. INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
  484. INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
  485. INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
  486. INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
  487. INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
  488. INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
  489. INGENIC_PIN_GROUP("cim-data", jz4760_cim),
  490. INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
  491. { "lcd-no-pins", },
  492. INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
  493. INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
  494. INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
  495. INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
  496. INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
  497. INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
  498. INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
  499. INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
  500. };
  501. static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
  502. static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
  503. static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
  504. static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
  505. static const char *jz4760_mmc0_groups[] = {
  506. "mmc0-1bit-a", "mmc0-4bit-a",
  507. "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
  508. };
  509. static const char *jz4760_mmc1_groups[] = {
  510. "mmc1-1bit-d", "mmc1-4bit-d",
  511. "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
  512. };
  513. static const char *jz4760_mmc2_groups[] = {
  514. "mmc2-1bit-b", "mmc2-4bit-b",
  515. "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
  516. };
  517. static const char *jz4760_nemc_groups[] = {
  518. "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
  519. "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
  520. };
  521. static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
  522. static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
  523. static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
  524. static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
  525. static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
  526. static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
  527. static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
  528. static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
  529. static const char *jz4760_cim_groups[] = { "cim-data", };
  530. static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
  531. static const char *jz4760_pwm0_groups[] = { "pwm0", };
  532. static const char *jz4760_pwm1_groups[] = { "pwm1", };
  533. static const char *jz4760_pwm2_groups[] = { "pwm2", };
  534. static const char *jz4760_pwm3_groups[] = { "pwm3", };
  535. static const char *jz4760_pwm4_groups[] = { "pwm4", };
  536. static const char *jz4760_pwm5_groups[] = { "pwm5", };
  537. static const char *jz4760_pwm6_groups[] = { "pwm6", };
  538. static const char *jz4760_pwm7_groups[] = { "pwm7", };
  539. static const struct function_desc jz4760_functions[] = {
  540. { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
  541. { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
  542. { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
  543. { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
  544. { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
  545. { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
  546. { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
  547. { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
  548. { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
  549. { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
  550. { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
  551. { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
  552. { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
  553. { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
  554. { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
  555. { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
  556. { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
  557. { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
  558. { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
  559. { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
  560. { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
  561. { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
  562. { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
  563. { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
  564. { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
  565. { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
  566. };
  567. static const struct ingenic_chip_info jz4760_chip_info = {
  568. .num_chips = 6,
  569. .reg_offset = 0x100,
  570. .version = ID_JZ4760,
  571. .groups = jz4760_groups,
  572. .num_groups = ARRAY_SIZE(jz4760_groups),
  573. .functions = jz4760_functions,
  574. .num_functions = ARRAY_SIZE(jz4760_functions),
  575. .pull_ups = jz4760_pull_ups,
  576. .pull_downs = jz4760_pull_downs,
  577. };
  578. static const u32 jz4770_pull_ups[6] = {
  579. 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
  580. };
  581. static const u32 jz4770_pull_downs[6] = {
  582. 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
  583. };
  584. static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
  585. static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
  586. static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
  587. static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
  588. static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
  589. static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
  590. static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
  591. static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
  592. static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
  593. static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
  594. static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
  595. static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
  596. static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
  597. static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
  598. static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
  599. static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
  600. static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
  601. static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
  602. static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
  603. static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
  604. static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
  605. static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
  606. static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
  607. static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
  608. static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
  609. static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
  610. static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
  611. static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
  612. static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
  613. static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
  614. static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
  615. static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
  616. static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
  617. static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
  618. static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
  619. static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
  620. static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
  621. static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
  622. static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
  623. static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
  624. static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
  625. static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
  626. static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
  627. static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
  628. static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
  629. static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
  630. static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
  631. static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
  632. static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
  633. static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
  634. static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
  635. static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
  636. static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
  637. static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
  638. static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
  639. static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
  640. static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
  641. static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
  642. static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
  643. static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
  644. static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
  645. static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
  646. static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
  647. static int jz4770_nemc_8bit_data_pins[] = {
  648. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  649. };
  650. static int jz4770_nemc_16bit_data_pins[] = {
  651. 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  652. };
  653. static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
  654. static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
  655. static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
  656. static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
  657. static int jz4770_nemc_wait_pins[] = { 0x1b, };
  658. static int jz4770_nemc_cs1_pins[] = { 0x15, };
  659. static int jz4770_nemc_cs2_pins[] = { 0x16, };
  660. static int jz4770_nemc_cs3_pins[] = { 0x17, };
  661. static int jz4770_nemc_cs4_pins[] = { 0x18, };
  662. static int jz4770_nemc_cs5_pins[] = { 0x19, };
  663. static int jz4770_nemc_cs6_pins[] = { 0x1a, };
  664. static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
  665. static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
  666. static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
  667. static int jz4770_cim_8bit_pins[] = {
  668. 0x26, 0x27, 0x28, 0x29,
  669. 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
  670. };
  671. static int jz4770_cim_12bit_pins[] = {
  672. 0x32, 0x33, 0xb0, 0xb1,
  673. };
  674. static int jz4770_lcd_24bit_pins[] = {
  675. 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  676. 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  677. 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  678. 0x58, 0x59, 0x5a, 0x5b,
  679. };
  680. static int jz4770_pwm_pwm0_pins[] = { 0x80, };
  681. static int jz4770_pwm_pwm1_pins[] = { 0x81, };
  682. static int jz4770_pwm_pwm2_pins[] = { 0x82, };
  683. static int jz4770_pwm_pwm3_pins[] = { 0x83, };
  684. static int jz4770_pwm_pwm4_pins[] = { 0x84, };
  685. static int jz4770_pwm_pwm5_pins[] = { 0x85, };
  686. static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
  687. static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
  688. static int jz4770_mac_rmii_pins[] = {
  689. 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
  690. };
  691. static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
  692. static int jz4770_otg_pins[] = { 0x8a, };
  693. static int jz4770_uart0_data_funcs[] = { 0, 0, };
  694. static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
  695. static int jz4770_uart1_data_funcs[] = { 0, 0, };
  696. static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
  697. static int jz4770_uart2_data_funcs[] = { 0, 0, };
  698. static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
  699. static int jz4770_uart3_data_funcs[] = { 0, 1, };
  700. static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
  701. static int jz4770_ssi0_dt_a_funcs[] = { 2, };
  702. static int jz4770_ssi0_dt_b_funcs[] = { 1, };
  703. static int jz4770_ssi0_dt_d_funcs[] = { 1, };
  704. static int jz4770_ssi0_dt_e_funcs[] = { 0, };
  705. static int jz4770_ssi0_dr_a_funcs[] = { 1, };
  706. static int jz4770_ssi0_dr_b_funcs[] = { 1, };
  707. static int jz4770_ssi0_dr_d_funcs[] = { 1, };
  708. static int jz4770_ssi0_dr_e_funcs[] = { 0, };
  709. static int jz4770_ssi0_clk_a_funcs[] = { 2, };
  710. static int jz4770_ssi0_clk_b_funcs[] = { 1, };
  711. static int jz4770_ssi0_clk_d_funcs[] = { 1, };
  712. static int jz4770_ssi0_clk_e_funcs[] = { 0, };
  713. static int jz4770_ssi0_gpc_b_funcs[] = { 1, };
  714. static int jz4770_ssi0_gpc_d_funcs[] = { 1, };
  715. static int jz4770_ssi0_gpc_e_funcs[] = { 0, };
  716. static int jz4770_ssi0_ce0_a_funcs[] = { 2, };
  717. static int jz4770_ssi0_ce0_b_funcs[] = { 1, };
  718. static int jz4770_ssi0_ce0_d_funcs[] = { 1, };
  719. static int jz4770_ssi0_ce0_e_funcs[] = { 0, };
  720. static int jz4770_ssi0_ce1_b_funcs[] = { 1, };
  721. static int jz4770_ssi0_ce1_d_funcs[] = { 1, };
  722. static int jz4770_ssi0_ce1_e_funcs[] = { 0, };
  723. static int jz4770_ssi1_dt_b_funcs[] = { 2, };
  724. static int jz4770_ssi1_dt_d_funcs[] = { 2, };
  725. static int jz4770_ssi1_dt_e_funcs[] = { 1, };
  726. static int jz4770_ssi1_dr_b_funcs[] = { 2, };
  727. static int jz4770_ssi1_dr_d_funcs[] = { 2, };
  728. static int jz4770_ssi1_dr_e_funcs[] = { 1, };
  729. static int jz4770_ssi1_clk_b_funcs[] = { 2, };
  730. static int jz4770_ssi1_clk_d_funcs[] = { 2, };
  731. static int jz4770_ssi1_clk_e_funcs[] = { 1, };
  732. static int jz4770_ssi1_gpc_b_funcs[] = { 2, };
  733. static int jz4770_ssi1_gpc_d_funcs[] = { 2, };
  734. static int jz4770_ssi1_gpc_e_funcs[] = { 1, };
  735. static int jz4770_ssi1_ce0_b_funcs[] = { 2, };
  736. static int jz4770_ssi1_ce0_d_funcs[] = { 2, };
  737. static int jz4770_ssi1_ce0_e_funcs[] = { 1, };
  738. static int jz4770_ssi1_ce1_b_funcs[] = { 2, };
  739. static int jz4770_ssi1_ce1_d_funcs[] = { 2, };
  740. static int jz4770_ssi1_ce1_e_funcs[] = { 1, };
  741. static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
  742. static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
  743. static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
  744. static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
  745. static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
  746. static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
  747. static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
  748. static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
  749. static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
  750. static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
  751. static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
  752. static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
  753. static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
  754. static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
  755. static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
  756. static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  757. static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  758. static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
  759. static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
  760. static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
  761. static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
  762. static int jz4770_nemc_wait_funcs[] = { 0, };
  763. static int jz4770_nemc_cs1_funcs[] = { 0, };
  764. static int jz4770_nemc_cs2_funcs[] = { 0, };
  765. static int jz4770_nemc_cs3_funcs[] = { 0, };
  766. static int jz4770_nemc_cs4_funcs[] = { 0, };
  767. static int jz4770_nemc_cs5_funcs[] = { 0, };
  768. static int jz4770_nemc_cs6_funcs[] = { 0, };
  769. static int jz4770_i2c0_funcs[] = { 0, 0, };
  770. static int jz4770_i2c1_funcs[] = { 0, 0, };
  771. static int jz4770_i2c2_funcs[] = { 2, 2, };
  772. static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  773. static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
  774. static int jz4770_lcd_24bit_funcs[] = {
  775. 0, 0, 0, 0, 0, 0, 0, 0,
  776. 0, 0, 0, 0, 0, 0, 0, 0,
  777. 0, 0, 0, 0, 0, 0, 0, 0,
  778. 0, 0, 0, 0,
  779. };
  780. static int jz4770_pwm_pwm0_funcs[] = { 0, };
  781. static int jz4770_pwm_pwm1_funcs[] = { 0, };
  782. static int jz4770_pwm_pwm2_funcs[] = { 0, };
  783. static int jz4770_pwm_pwm3_funcs[] = { 0, };
  784. static int jz4770_pwm_pwm4_funcs[] = { 0, };
  785. static int jz4770_pwm_pwm5_funcs[] = { 0, };
  786. static int jz4770_pwm_pwm6_funcs[] = { 0, };
  787. static int jz4770_pwm_pwm7_funcs[] = { 0, };
  788. static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  789. static int jz4770_mac_mii_funcs[] = { 0, 0, };
  790. static int jz4770_otg_funcs[] = { 0, };
  791. static const struct group_desc jz4770_groups[] = {
  792. INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
  793. INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
  794. INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
  795. INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
  796. INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
  797. INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
  798. INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
  799. INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
  800. INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a),
  801. INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b),
  802. INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d),
  803. INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
  804. INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a),
  805. INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b),
  806. INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d),
  807. INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
  808. INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a),
  809. INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b),
  810. INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d),
  811. INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
  812. INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b),
  813. INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d),
  814. INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
  815. INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a),
  816. INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b),
  817. INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d),
  818. INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
  819. INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b),
  820. INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d),
  821. INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
  822. INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b),
  823. INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d),
  824. INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
  825. INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b),
  826. INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d),
  827. INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
  828. INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b),
  829. INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d),
  830. INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
  831. INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b),
  832. INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d),
  833. INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
  834. INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b),
  835. INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d),
  836. INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
  837. INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b),
  838. INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d),
  839. INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
  840. INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
  841. INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
  842. INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
  843. INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
  844. INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
  845. INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
  846. INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
  847. INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
  848. INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
  849. INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
  850. INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
  851. INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
  852. INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
  853. INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
  854. INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
  855. INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
  856. INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
  857. INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
  858. INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
  859. INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
  860. INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
  861. INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
  862. INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
  863. INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
  864. INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
  865. INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
  866. INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
  867. INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
  868. INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
  869. INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
  870. INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
  871. INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
  872. INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
  873. INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
  874. { "lcd-no-pins", },
  875. INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
  876. INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
  877. INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
  878. INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
  879. INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
  880. INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
  881. INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
  882. INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
  883. INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
  884. INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
  885. INGENIC_PIN_GROUP("otg-vbus", jz4770_otg),
  886. };
  887. static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
  888. static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
  889. static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
  890. static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
  891. static const char *jz4770_ssi0_groups[] = {
  892. "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
  893. "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
  894. "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
  895. "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
  896. "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
  897. "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
  898. };
  899. static const char *jz4770_ssi1_groups[] = {
  900. "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
  901. "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
  902. "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
  903. "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
  904. "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
  905. "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
  906. };
  907. static const char *jz4770_mmc0_groups[] = {
  908. "mmc0-1bit-a", "mmc0-4bit-a",
  909. "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
  910. };
  911. static const char *jz4770_mmc1_groups[] = {
  912. "mmc1-1bit-d", "mmc1-4bit-d",
  913. "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
  914. };
  915. static const char *jz4770_mmc2_groups[] = {
  916. "mmc2-1bit-b", "mmc2-4bit-b",
  917. "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
  918. };
  919. static const char *jz4770_nemc_groups[] = {
  920. "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
  921. "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
  922. };
  923. static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
  924. static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
  925. static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
  926. static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
  927. static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
  928. static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
  929. static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
  930. static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
  931. static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
  932. static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
  933. static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
  934. static const char *jz4770_pwm0_groups[] = { "pwm0", };
  935. static const char *jz4770_pwm1_groups[] = { "pwm1", };
  936. static const char *jz4770_pwm2_groups[] = { "pwm2", };
  937. static const char *jz4770_pwm3_groups[] = { "pwm3", };
  938. static const char *jz4770_pwm4_groups[] = { "pwm4", };
  939. static const char *jz4770_pwm5_groups[] = { "pwm5", };
  940. static const char *jz4770_pwm6_groups[] = { "pwm6", };
  941. static const char *jz4770_pwm7_groups[] = { "pwm7", };
  942. static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
  943. static const char *jz4770_otg_groups[] = { "otg-vbus", };
  944. static const struct function_desc jz4770_functions[] = {
  945. { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
  946. { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
  947. { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
  948. { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
  949. { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
  950. { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
  951. { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
  952. { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
  953. { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
  954. { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
  955. { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
  956. { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
  957. { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
  958. { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
  959. { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
  960. { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
  961. { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
  962. { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
  963. { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
  964. { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
  965. { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
  966. { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
  967. { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
  968. { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
  969. { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
  970. { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
  971. { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
  972. { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
  973. { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
  974. { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
  975. { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
  976. };
  977. static const struct ingenic_chip_info jz4770_chip_info = {
  978. .num_chips = 6,
  979. .reg_offset = 0x100,
  980. .version = ID_JZ4770,
  981. .groups = jz4770_groups,
  982. .num_groups = ARRAY_SIZE(jz4770_groups),
  983. .functions = jz4770_functions,
  984. .num_functions = ARRAY_SIZE(jz4770_functions),
  985. .pull_ups = jz4770_pull_ups,
  986. .pull_downs = jz4770_pull_downs,
  987. };
  988. static const u32 jz4780_pull_ups[6] = {
  989. 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
  990. };
  991. static const u32 jz4780_pull_downs[6] = {
  992. 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
  993. };
  994. static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
  995. static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
  996. static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
  997. static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
  998. static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
  999. static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
  1000. static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
  1001. static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
  1002. static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
  1003. static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
  1004. static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
  1005. static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
  1006. static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
  1007. static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
  1008. static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
  1009. static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
  1010. static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
  1011. static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
  1012. static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
  1013. static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
  1014. static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
  1015. static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
  1016. static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
  1017. static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
  1018. static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
  1019. static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
  1020. static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
  1021. static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
  1022. static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
  1023. static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
  1024. static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
  1025. static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
  1026. static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
  1027. static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
  1028. static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
  1029. static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
  1030. static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
  1031. static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
  1032. static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
  1033. static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
  1034. static int jz4780_i2s_data_tx_pins[] = { 0x87, };
  1035. static int jz4780_i2s_data_rx_pins[] = { 0x86, };
  1036. static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
  1037. static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
  1038. static int jz4780_i2s_sysclk_pins[] = { 0x85, };
  1039. static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
  1040. static int jz4780_uart2_data_funcs[] = { 1, 1, };
  1041. static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
  1042. static int jz4780_uart4_data_funcs[] = { 2, 2, };
  1043. static int jz4780_ssi0_dt_a_19_funcs[] = { 2, };
  1044. static int jz4780_ssi0_dt_a_21_funcs[] = { 2, };
  1045. static int jz4780_ssi0_dt_a_28_funcs[] = { 2, };
  1046. static int jz4780_ssi0_dt_b_funcs[] = { 1, };
  1047. static int jz4780_ssi0_dt_d_funcs[] = { 1, };
  1048. static int jz4780_ssi0_dr_a_20_funcs[] = { 2, };
  1049. static int jz4780_ssi0_dr_a_27_funcs[] = { 2, };
  1050. static int jz4780_ssi0_dr_b_funcs[] = { 1, };
  1051. static int jz4780_ssi0_dr_d_funcs[] = { 1, };
  1052. static int jz4780_ssi0_clk_a_funcs[] = { 2, };
  1053. static int jz4780_ssi0_clk_b_5_funcs[] = { 1, };
  1054. static int jz4780_ssi0_clk_b_28_funcs[] = { 1, };
  1055. static int jz4780_ssi0_clk_d_funcs[] = { 1, };
  1056. static int jz4780_ssi0_gpc_b_funcs[] = { 1, };
  1057. static int jz4780_ssi0_gpc_d_funcs[] = { 1, };
  1058. static int jz4780_ssi0_ce0_a_23_funcs[] = { 2, };
  1059. static int jz4780_ssi0_ce0_a_25_funcs[] = { 2, };
  1060. static int jz4780_ssi0_ce0_b_funcs[] = { 1, };
  1061. static int jz4780_ssi0_ce0_d_funcs[] = { 1, };
  1062. static int jz4780_ssi0_ce1_b_funcs[] = { 1, };
  1063. static int jz4780_ssi0_ce1_d_funcs[] = { 1, };
  1064. static int jz4780_ssi1_dt_b_funcs[] = { 2, };
  1065. static int jz4780_ssi1_dt_d_funcs[] = { 2, };
  1066. static int jz4780_ssi1_dr_b_funcs[] = { 2, };
  1067. static int jz4780_ssi1_dr_d_funcs[] = { 2, };
  1068. static int jz4780_ssi1_clk_b_funcs[] = { 2, };
  1069. static int jz4780_ssi1_clk_d_funcs[] = { 2, };
  1070. static int jz4780_ssi1_gpc_b_funcs[] = { 2, };
  1071. static int jz4780_ssi1_gpc_d_funcs[] = { 2, };
  1072. static int jz4780_ssi1_ce0_b_funcs[] = { 2, };
  1073. static int jz4780_ssi1_ce0_d_funcs[] = { 2, };
  1074. static int jz4780_ssi1_ce1_b_funcs[] = { 2, };
  1075. static int jz4780_ssi1_ce1_d_funcs[] = { 2, };
  1076. static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
  1077. static int jz4780_i2c3_funcs[] = { 1, 1, };
  1078. static int jz4780_i2c4_e_funcs[] = { 1, 1, };
  1079. static int jz4780_i2c4_f_funcs[] = { 1, 1, };
  1080. static int jz4780_i2s_data_tx_funcs[] = { 0, };
  1081. static int jz4780_i2s_data_rx_funcs[] = { 0, };
  1082. static int jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
  1083. static int jz4780_i2s_clk_rx_funcs[] = { 1, 1, };
  1084. static int jz4780_i2s_sysclk_funcs[] = { 2, };
  1085. static int jz4780_hdmi_ddc_funcs[] = { 0, 0, };
  1086. static const struct group_desc jz4780_groups[] = {
  1087. INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
  1088. INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
  1089. INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
  1090. INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
  1091. INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
  1092. INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
  1093. INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
  1094. INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
  1095. INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
  1096. INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19),
  1097. INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21),
  1098. INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28),
  1099. INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b),
  1100. INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d),
  1101. INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
  1102. INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20),
  1103. INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27),
  1104. INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b),
  1105. INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d),
  1106. INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
  1107. INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a),
  1108. INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5),
  1109. INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28),
  1110. INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d),
  1111. INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
  1112. INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b),
  1113. INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d),
  1114. INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
  1115. INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23),
  1116. INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25),
  1117. INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b),
  1118. INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d),
  1119. INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
  1120. INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b),
  1121. INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d),
  1122. INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
  1123. INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b),
  1124. INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d),
  1125. INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
  1126. INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b),
  1127. INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d),
  1128. INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
  1129. INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b),
  1130. INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d),
  1131. INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
  1132. INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b),
  1133. INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d),
  1134. INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
  1135. INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b),
  1136. INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d),
  1137. INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
  1138. INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b),
  1139. INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d),
  1140. INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
  1141. INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
  1142. INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
  1143. INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
  1144. INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
  1145. INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
  1146. INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
  1147. INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
  1148. INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
  1149. INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
  1150. INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
  1151. INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
  1152. INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
  1153. INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
  1154. INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
  1155. INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
  1156. INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
  1157. INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
  1158. INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
  1159. INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
  1160. INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
  1161. INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
  1162. INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
  1163. INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
  1164. INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
  1165. INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
  1166. INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
  1167. INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
  1168. INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
  1169. INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
  1170. INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
  1171. INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
  1172. INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx),
  1173. INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx),
  1174. INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx),
  1175. INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx),
  1176. INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk),
  1177. INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc),
  1178. INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
  1179. INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
  1180. { "lcd-no-pins", },
  1181. INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
  1182. INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
  1183. INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
  1184. INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
  1185. INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
  1186. INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
  1187. INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
  1188. INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
  1189. };
  1190. static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
  1191. static const char *jz4780_uart4_groups[] = { "uart4-data", };
  1192. static const char *jz4780_ssi0_groups[] = {
  1193. "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
  1194. "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
  1195. "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
  1196. "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
  1197. "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
  1198. "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
  1199. };
  1200. static const char *jz4780_ssi1_groups[] = {
  1201. "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
  1202. "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
  1203. "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
  1204. "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
  1205. "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
  1206. "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
  1207. };
  1208. static const char *jz4780_mmc0_groups[] = {
  1209. "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
  1210. "mmc0-1bit-e", "mmc0-4bit-e",
  1211. };
  1212. static const char *jz4780_mmc1_groups[] = {
  1213. "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
  1214. };
  1215. static const char *jz4780_mmc2_groups[] = {
  1216. "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
  1217. };
  1218. static const char *jz4780_nemc_groups[] = {
  1219. "nemc-data", "nemc-cle-ale", "nemc-addr",
  1220. "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
  1221. };
  1222. static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
  1223. static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
  1224. static const char *jz4780_i2s_groups[] = {
  1225. "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
  1226. };
  1227. static const char *jz4780_cim_groups[] = { "cim-data", };
  1228. static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
  1229. static const struct function_desc jz4780_functions[] = {
  1230. { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
  1231. { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
  1232. { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
  1233. { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
  1234. { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
  1235. { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
  1236. { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
  1237. { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
  1238. { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
  1239. { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
  1240. { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
  1241. { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
  1242. { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
  1243. { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
  1244. { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
  1245. { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
  1246. { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
  1247. { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
  1248. { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
  1249. { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
  1250. { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
  1251. { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
  1252. { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
  1253. { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
  1254. { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
  1255. { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
  1256. { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
  1257. { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
  1258. { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
  1259. { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
  1260. { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
  1261. { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
  1262. { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
  1263. { "hdmi-ddc", jz4780_hdmi_ddc_groups,
  1264. ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
  1265. };
  1266. static const struct ingenic_chip_info jz4780_chip_info = {
  1267. .num_chips = 6,
  1268. .reg_offset = 0x100,
  1269. .version = ID_JZ4780,
  1270. .groups = jz4780_groups,
  1271. .num_groups = ARRAY_SIZE(jz4780_groups),
  1272. .functions = jz4780_functions,
  1273. .num_functions = ARRAY_SIZE(jz4780_functions),
  1274. .pull_ups = jz4780_pull_ups,
  1275. .pull_downs = jz4780_pull_downs,
  1276. };
  1277. static const u32 x1000_pull_ups[4] = {
  1278. 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
  1279. };
  1280. static const u32 x1000_pull_downs[4] = {
  1281. 0x00000000, 0x02000000, 0x02000000, 0x00000000,
  1282. };
  1283. static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
  1284. static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
  1285. static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
  1286. static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
  1287. static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
  1288. static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
  1289. static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
  1290. static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
  1291. static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
  1292. static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
  1293. static int x1000_ssi_dt_d_pins[] = { 0x62, };
  1294. static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
  1295. static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
  1296. static int x1000_ssi_dr_d_pins[] = { 0x63, };
  1297. static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
  1298. static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
  1299. static int x1000_ssi_clk_d_pins[] = { 0x60, };
  1300. static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
  1301. static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
  1302. static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
  1303. static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
  1304. static int x1000_ssi_ce0_d_pins[] = { 0x61, };
  1305. static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
  1306. static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
  1307. static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
  1308. static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
  1309. static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
  1310. static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
  1311. static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
  1312. static int x1000_emc_8bit_data_pins[] = {
  1313. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  1314. };
  1315. static int x1000_emc_16bit_data_pins[] = {
  1316. 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  1317. };
  1318. static int x1000_emc_addr_pins[] = {
  1319. 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
  1320. 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
  1321. };
  1322. static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
  1323. static int x1000_emc_wait_pins[] = { 0x34, };
  1324. static int x1000_emc_cs1_pins[] = { 0x32, };
  1325. static int x1000_emc_cs2_pins[] = { 0x33, };
  1326. static int x1000_i2c0_pins[] = { 0x38, 0x37, };
  1327. static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
  1328. static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
  1329. static int x1000_i2c2_pins[] = { 0x61, 0x60, };
  1330. static int x1000_i2s_data_tx_pins[] = { 0x24, };
  1331. static int x1000_i2s_data_rx_pins[] = { 0x23, };
  1332. static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
  1333. static int x1000_i2s_sysclk_pins[] = { 0x20, };
  1334. static int x1000_cim_pins[] = {
  1335. 0x08, 0x09, 0x0a, 0x0b,
  1336. 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
  1337. };
  1338. static int x1000_lcd_8bit_pins[] = {
  1339. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  1340. 0x30, 0x31, 0x32, 0x33, 0x34,
  1341. };
  1342. static int x1000_lcd_16bit_pins[] = {
  1343. 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  1344. };
  1345. static int x1000_pwm_pwm0_pins[] = { 0x59, };
  1346. static int x1000_pwm_pwm1_pins[] = { 0x5a, };
  1347. static int x1000_pwm_pwm2_pins[] = { 0x5b, };
  1348. static int x1000_pwm_pwm3_pins[] = { 0x26, };
  1349. static int x1000_pwm_pwm4_pins[] = { 0x58, };
  1350. static int x1000_mac_pins[] = {
  1351. 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
  1352. };
  1353. static int x1000_uart0_data_funcs[] = { 0, 0, };
  1354. static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
  1355. static int x1000_uart1_data_a_funcs[] = { 2, 2, };
  1356. static int x1000_uart1_data_d_funcs[] = { 1, 1, };
  1357. static int x1000_uart1_hwflow_funcs[] = { 1, 1, };
  1358. static int x1000_uart2_data_a_funcs[] = { 2, 2, };
  1359. static int x1000_uart2_data_d_funcs[] = { 0, 0, };
  1360. static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
  1361. static int x1000_ssi_dt_a_22_funcs[] = { 2, };
  1362. static int x1000_ssi_dt_a_29_funcs[] = { 2, };
  1363. static int x1000_ssi_dt_d_funcs[] = { 0, };
  1364. static int x1000_ssi_dr_a_23_funcs[] = { 2, };
  1365. static int x1000_ssi_dr_a_28_funcs[] = { 2, };
  1366. static int x1000_ssi_dr_d_funcs[] = { 0, };
  1367. static int x1000_ssi_clk_a_24_funcs[] = { 2, };
  1368. static int x1000_ssi_clk_a_26_funcs[] = { 2, };
  1369. static int x1000_ssi_clk_d_funcs[] = { 0, };
  1370. static int x1000_ssi_gpc_a_20_funcs[] = { 2, };
  1371. static int x1000_ssi_gpc_a_31_funcs[] = { 2, };
  1372. static int x1000_ssi_ce0_a_25_funcs[] = { 2, };
  1373. static int x1000_ssi_ce0_a_27_funcs[] = { 2, };
  1374. static int x1000_ssi_ce0_d_funcs[] = { 0, };
  1375. static int x1000_ssi_ce1_a_21_funcs[] = { 2, };
  1376. static int x1000_ssi_ce1_a_30_funcs[] = { 2, };
  1377. static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
  1378. static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
  1379. static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
  1380. static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
  1381. static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
  1382. static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  1383. static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  1384. static int x1000_emc_addr_funcs[] = {
  1385. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1386. };
  1387. static int x1000_emc_rd_we_funcs[] = { 0, 0, };
  1388. static int x1000_emc_wait_funcs[] = { 0, };
  1389. static int x1000_emc_cs1_funcs[] = { 0, };
  1390. static int x1000_emc_cs2_funcs[] = { 0, };
  1391. static int x1000_i2c0_funcs[] = { 0, 0, };
  1392. static int x1000_i2c1_a_funcs[] = { 2, 2, };
  1393. static int x1000_i2c1_c_funcs[] = { 0, 0, };
  1394. static int x1000_i2c2_funcs[] = { 1, 1, };
  1395. static int x1000_i2s_data_tx_funcs[] = { 1, };
  1396. static int x1000_i2s_data_rx_funcs[] = { 1, };
  1397. static int x1000_i2s_clk_txrx_funcs[] = { 1, 1, };
  1398. static int x1000_i2s_sysclk_funcs[] = { 1, };
  1399. static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
  1400. static int x1000_lcd_8bit_funcs[] = {
  1401. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  1402. };
  1403. static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
  1404. static int x1000_pwm_pwm0_funcs[] = { 0, };
  1405. static int x1000_pwm_pwm1_funcs[] = { 1, };
  1406. static int x1000_pwm_pwm2_funcs[] = { 1, };
  1407. static int x1000_pwm_pwm3_funcs[] = { 2, };
  1408. static int x1000_pwm_pwm4_funcs[] = { 0, };
  1409. static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
  1410. static const struct group_desc x1000_groups[] = {
  1411. INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
  1412. INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
  1413. INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
  1414. INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
  1415. INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow),
  1416. INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
  1417. INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
  1418. INGENIC_PIN_GROUP("sfc", x1000_sfc),
  1419. INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22),
  1420. INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29),
  1421. INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d),
  1422. INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23),
  1423. INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28),
  1424. INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d),
  1425. INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24),
  1426. INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26),
  1427. INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d),
  1428. INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20),
  1429. INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31),
  1430. INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25),
  1431. INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27),
  1432. INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d),
  1433. INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21),
  1434. INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30),
  1435. INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
  1436. INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
  1437. INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
  1438. INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
  1439. INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
  1440. INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data),
  1441. INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data),
  1442. INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr),
  1443. INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we),
  1444. INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait),
  1445. INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1),
  1446. INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2),
  1447. INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
  1448. INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
  1449. INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
  1450. INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
  1451. INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx),
  1452. INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx),
  1453. INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx),
  1454. INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk),
  1455. INGENIC_PIN_GROUP("cim-data", x1000_cim),
  1456. INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
  1457. INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
  1458. { "lcd-no-pins", },
  1459. INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
  1460. INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
  1461. INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
  1462. INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
  1463. INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
  1464. INGENIC_PIN_GROUP("mac", x1000_mac),
  1465. };
  1466. static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
  1467. static const char *x1000_uart1_groups[] = {
  1468. "uart1-data-a", "uart1-data-d", "uart1-hwflow",
  1469. };
  1470. static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
  1471. static const char *x1000_sfc_groups[] = { "sfc", };
  1472. static const char *x1000_ssi_groups[] = {
  1473. "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
  1474. "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
  1475. "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
  1476. "ssi-gpc-a-20", "ssi-gpc-a-31",
  1477. "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
  1478. "ssi-ce1-a-21", "ssi-ce1-a-30",
  1479. };
  1480. static const char *x1000_mmc0_groups[] = {
  1481. "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
  1482. };
  1483. static const char *x1000_mmc1_groups[] = {
  1484. "mmc1-1bit", "mmc1-4bit",
  1485. };
  1486. static const char *x1000_emc_groups[] = {
  1487. "emc-8bit-data", "emc-16bit-data",
  1488. "emc-addr", "emc-rd-we", "emc-wait",
  1489. };
  1490. static const char *x1000_cs1_groups[] = { "emc-cs1", };
  1491. static const char *x1000_cs2_groups[] = { "emc-cs2", };
  1492. static const char *x1000_i2c0_groups[] = { "i2c0-data", };
  1493. static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
  1494. static const char *x1000_i2c2_groups[] = { "i2c2-data", };
  1495. static const char *x1000_i2s_groups[] = {
  1496. "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
  1497. };
  1498. static const char *x1000_cim_groups[] = { "cim-data", };
  1499. static const char *x1000_lcd_groups[] = {
  1500. "lcd-8bit", "lcd-16bit", "lcd-no-pins",
  1501. };
  1502. static const char *x1000_pwm0_groups[] = { "pwm0", };
  1503. static const char *x1000_pwm1_groups[] = { "pwm1", };
  1504. static const char *x1000_pwm2_groups[] = { "pwm2", };
  1505. static const char *x1000_pwm3_groups[] = { "pwm3", };
  1506. static const char *x1000_pwm4_groups[] = { "pwm4", };
  1507. static const char *x1000_mac_groups[] = { "mac", };
  1508. static const struct function_desc x1000_functions[] = {
  1509. { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
  1510. { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
  1511. { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
  1512. { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
  1513. { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
  1514. { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
  1515. { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
  1516. { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
  1517. { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
  1518. { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
  1519. { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
  1520. { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
  1521. { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
  1522. { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
  1523. { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
  1524. { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
  1525. { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
  1526. { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
  1527. { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
  1528. { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
  1529. { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
  1530. { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
  1531. };
  1532. static const struct ingenic_chip_info x1000_chip_info = {
  1533. .num_chips = 4,
  1534. .reg_offset = 0x100,
  1535. .version = ID_X1000,
  1536. .groups = x1000_groups,
  1537. .num_groups = ARRAY_SIZE(x1000_groups),
  1538. .functions = x1000_functions,
  1539. .num_functions = ARRAY_SIZE(x1000_functions),
  1540. .pull_ups = x1000_pull_ups,
  1541. .pull_downs = x1000_pull_downs,
  1542. };
  1543. static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
  1544. static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
  1545. static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
  1546. static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
  1547. static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
  1548. static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
  1549. static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
  1550. static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
  1551. static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
  1552. static int x1500_i2c0_pins[] = { 0x38, 0x37, };
  1553. static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
  1554. static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
  1555. static int x1500_i2c2_pins[] = { 0x61, 0x60, };
  1556. static int x1500_i2s_data_tx_pins[] = { 0x24, };
  1557. static int x1500_i2s_data_rx_pins[] = { 0x23, };
  1558. static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
  1559. static int x1500_i2s_sysclk_pins[] = { 0x20, };
  1560. static int x1500_cim_pins[] = {
  1561. 0x08, 0x09, 0x0a, 0x0b,
  1562. 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
  1563. };
  1564. static int x1500_pwm_pwm0_pins[] = { 0x59, };
  1565. static int x1500_pwm_pwm1_pins[] = { 0x5a, };
  1566. static int x1500_pwm_pwm2_pins[] = { 0x5b, };
  1567. static int x1500_pwm_pwm3_pins[] = { 0x26, };
  1568. static int x1500_pwm_pwm4_pins[] = { 0x58, };
  1569. static int x1500_uart0_data_funcs[] = { 0, 0, };
  1570. static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
  1571. static int x1500_uart1_data_a_funcs[] = { 2, 2, };
  1572. static int x1500_uart1_data_d_funcs[] = { 1, 1, };
  1573. static int x1500_uart1_hwflow_funcs[] = { 1, 1, };
  1574. static int x1500_uart2_data_a_funcs[] = { 2, 2, };
  1575. static int x1500_uart2_data_d_funcs[] = { 0, 0, };
  1576. static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, };
  1577. static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, };
  1578. static int x1500_i2c0_funcs[] = { 0, 0, };
  1579. static int x1500_i2c1_a_funcs[] = { 2, 2, };
  1580. static int x1500_i2c1_c_funcs[] = { 0, 0, };
  1581. static int x1500_i2c2_funcs[] = { 1, 1, };
  1582. static int x1500_i2s_data_tx_funcs[] = { 1, };
  1583. static int x1500_i2s_data_rx_funcs[] = { 1, };
  1584. static int x1500_i2s_clk_txrx_funcs[] = { 1, 1, };
  1585. static int x1500_i2s_sysclk_funcs[] = { 1, };
  1586. static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
  1587. static int x1500_pwm_pwm0_funcs[] = { 0, };
  1588. static int x1500_pwm_pwm1_funcs[] = { 1, };
  1589. static int x1500_pwm_pwm2_funcs[] = { 1, };
  1590. static int x1500_pwm_pwm3_funcs[] = { 2, };
  1591. static int x1500_pwm_pwm4_funcs[] = { 0, };
  1592. static const struct group_desc x1500_groups[] = {
  1593. INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
  1594. INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
  1595. INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
  1596. INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
  1597. INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow),
  1598. INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
  1599. INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
  1600. INGENIC_PIN_GROUP("sfc", x1000_sfc),
  1601. INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit),
  1602. INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit),
  1603. INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
  1604. INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
  1605. INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
  1606. INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
  1607. INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx),
  1608. INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx),
  1609. INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx),
  1610. INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk),
  1611. INGENIC_PIN_GROUP("cim-data", x1500_cim),
  1612. { "lcd-no-pins", },
  1613. INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
  1614. INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
  1615. INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
  1616. INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
  1617. INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
  1618. };
  1619. static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
  1620. static const char *x1500_uart1_groups[] = {
  1621. "uart1-data-a", "uart1-data-d", "uart1-hwflow",
  1622. };
  1623. static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
  1624. static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
  1625. static const char *x1500_i2c0_groups[] = { "i2c0-data", };
  1626. static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
  1627. static const char *x1500_i2c2_groups[] = { "i2c2-data", };
  1628. static const char *x1500_i2s_groups[] = {
  1629. "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
  1630. };
  1631. static const char *x1500_cim_groups[] = { "cim-data", };
  1632. static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
  1633. static const char *x1500_pwm0_groups[] = { "pwm0", };
  1634. static const char *x1500_pwm1_groups[] = { "pwm1", };
  1635. static const char *x1500_pwm2_groups[] = { "pwm2", };
  1636. static const char *x1500_pwm3_groups[] = { "pwm3", };
  1637. static const char *x1500_pwm4_groups[] = { "pwm4", };
  1638. static const struct function_desc x1500_functions[] = {
  1639. { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
  1640. { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
  1641. { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
  1642. { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
  1643. { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
  1644. { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
  1645. { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
  1646. { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
  1647. { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
  1648. { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
  1649. { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
  1650. { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
  1651. { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
  1652. { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
  1653. { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
  1654. { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
  1655. };
  1656. static const struct ingenic_chip_info x1500_chip_info = {
  1657. .num_chips = 4,
  1658. .reg_offset = 0x100,
  1659. .version = ID_X1500,
  1660. .groups = x1500_groups,
  1661. .num_groups = ARRAY_SIZE(x1500_groups),
  1662. .functions = x1500_functions,
  1663. .num_functions = ARRAY_SIZE(x1500_functions),
  1664. .pull_ups = x1000_pull_ups,
  1665. .pull_downs = x1000_pull_downs,
  1666. };
  1667. static const u32 x1830_pull_ups[4] = {
  1668. 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
  1669. };
  1670. static const u32 x1830_pull_downs[4] = {
  1671. 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
  1672. };
  1673. static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
  1674. static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
  1675. static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
  1676. static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
  1677. static int x1830_ssi0_dt_pins[] = { 0x4c, };
  1678. static int x1830_ssi0_dr_pins[] = { 0x4b, };
  1679. static int x1830_ssi0_clk_pins[] = { 0x4f, };
  1680. static int x1830_ssi0_gpc_pins[] = { 0x4d, };
  1681. static int x1830_ssi0_ce0_pins[] = { 0x50, };
  1682. static int x1830_ssi0_ce1_pins[] = { 0x4e, };
  1683. static int x1830_ssi1_dt_c_pins[] = { 0x53, };
  1684. static int x1830_ssi1_dr_c_pins[] = { 0x54, };
  1685. static int x1830_ssi1_clk_c_pins[] = { 0x57, };
  1686. static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
  1687. static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
  1688. static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
  1689. static int x1830_ssi1_dt_d_pins[] = { 0x62, };
  1690. static int x1830_ssi1_dr_d_pins[] = { 0x63, };
  1691. static int x1830_ssi1_clk_d_pins[] = { 0x66, };
  1692. static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
  1693. static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
  1694. static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
  1695. static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
  1696. static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
  1697. static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
  1698. static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
  1699. static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
  1700. static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
  1701. static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
  1702. static int x1830_i2s_data_tx_pins[] = { 0x53, };
  1703. static int x1830_i2s_data_rx_pins[] = { 0x54, };
  1704. static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
  1705. static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
  1706. static int x1830_i2s_sysclk_pins[] = { 0x57, };
  1707. static int x1830_lcd_rgb_18bit_pins[] = {
  1708. 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
  1709. 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f,
  1710. 0x70, 0x71, 0x72, 0x73, 0x76, 0x77,
  1711. 0x78, 0x79, 0x7a, 0x7b,
  1712. };
  1713. static int x1830_lcd_slcd_8bit_pins[] = {
  1714. 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
  1715. 0x69, 0x72, 0x73, 0x7b, 0x7a,
  1716. };
  1717. static int x1830_lcd_slcd_16bit_pins[] = {
  1718. 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
  1719. };
  1720. static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
  1721. static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
  1722. static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
  1723. static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
  1724. static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
  1725. static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
  1726. static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
  1727. static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
  1728. static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
  1729. static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
  1730. static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
  1731. static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
  1732. static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
  1733. static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
  1734. static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
  1735. static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
  1736. static int x1830_mac_pins[] = {
  1737. 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
  1738. };
  1739. static int x1830_uart0_data_funcs[] = { 0, 0, };
  1740. static int x1830_uart0_hwflow_funcs[] = { 0, 0, };
  1741. static int x1830_uart1_data_funcs[] = { 0, 0, };
  1742. static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
  1743. static int x1830_ssi0_dt_funcs[] = { 0, };
  1744. static int x1830_ssi0_dr_funcs[] = { 0, };
  1745. static int x1830_ssi0_clk_funcs[] = { 0, };
  1746. static int x1830_ssi0_gpc_funcs[] = { 0, };
  1747. static int x1830_ssi0_ce0_funcs[] = { 0, };
  1748. static int x1830_ssi0_ce1_funcs[] = { 0, };
  1749. static int x1830_ssi1_dt_c_funcs[] = { 1, };
  1750. static int x1830_ssi1_dr_c_funcs[] = { 1, };
  1751. static int x1830_ssi1_clk_c_funcs[] = { 1, };
  1752. static int x1830_ssi1_gpc_c_funcs[] = { 1, };
  1753. static int x1830_ssi1_ce0_c_funcs[] = { 1, };
  1754. static int x1830_ssi1_ce1_c_funcs[] = { 1, };
  1755. static int x1830_ssi1_dt_d_funcs[] = { 2, };
  1756. static int x1830_ssi1_dr_d_funcs[] = { 2, };
  1757. static int x1830_ssi1_clk_d_funcs[] = { 2, };
  1758. static int x1830_ssi1_gpc_d_funcs[] = { 2, };
  1759. static int x1830_ssi1_ce0_d_funcs[] = { 2, };
  1760. static int x1830_ssi1_ce1_d_funcs[] = { 2, };
  1761. static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, };
  1762. static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, };
  1763. static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, };
  1764. static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, };
  1765. static int x1830_i2c0_funcs[] = { 1, 1, };
  1766. static int x1830_i2c1_funcs[] = { 0, 0, };
  1767. static int x1830_i2c2_funcs[] = { 1, 1, };
  1768. static int x1830_i2s_data_tx_funcs[] = { 0, };
  1769. static int x1830_i2s_data_rx_funcs[] = { 0, };
  1770. static int x1830_i2s_clk_txrx_funcs[] = { 0, 0, };
  1771. static int x1830_i2s_clk_rx_funcs[] = { 0, 0, };
  1772. static int x1830_i2s_sysclk_funcs[] = { 0, };
  1773. static int x1830_lcd_rgb_18bit_funcs[] = {
  1774. 0, 0, 0, 0, 0, 0,
  1775. 0, 0, 0, 0, 0, 0,
  1776. 0, 0, 0, 0, 0, 0,
  1777. 0, 0, 0, 0,
  1778. };
  1779. static int x1830_lcd_slcd_8bit_funcs[] = {
  1780. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  1781. };
  1782. static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
  1783. static int x1830_pwm_pwm0_b_funcs[] = { 0, };
  1784. static int x1830_pwm_pwm0_c_funcs[] = { 1, };
  1785. static int x1830_pwm_pwm1_b_funcs[] = { 0, };
  1786. static int x1830_pwm_pwm1_c_funcs[] = { 1, };
  1787. static int x1830_pwm_pwm2_c_8_funcs[] = { 0, };
  1788. static int x1830_pwm_pwm2_c_13_funcs[] = { 1, };
  1789. static int x1830_pwm_pwm3_c_9_funcs[] = { 0, };
  1790. static int x1830_pwm_pwm3_c_14_funcs[] = { 1, };
  1791. static int x1830_pwm_pwm4_c_15_funcs[] = { 1, };
  1792. static int x1830_pwm_pwm4_c_25_funcs[] = { 0, };
  1793. static int x1830_pwm_pwm5_c_16_funcs[] = { 1, };
  1794. static int x1830_pwm_pwm5_c_26_funcs[] = { 0, };
  1795. static int x1830_pwm_pwm6_c_17_funcs[] = { 1, };
  1796. static int x1830_pwm_pwm6_c_27_funcs[] = { 0, };
  1797. static int x1830_pwm_pwm7_c_18_funcs[] = { 1, };
  1798. static int x1830_pwm_pwm7_c_28_funcs[] = { 0, };
  1799. static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  1800. static const struct group_desc x1830_groups[] = {
  1801. INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data),
  1802. INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow),
  1803. INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data),
  1804. INGENIC_PIN_GROUP("sfc", x1830_sfc),
  1805. INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt),
  1806. INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr),
  1807. INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk),
  1808. INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc),
  1809. INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0),
  1810. INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1),
  1811. INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c),
  1812. INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c),
  1813. INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c),
  1814. INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c),
  1815. INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c),
  1816. INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c),
  1817. INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d),
  1818. INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d),
  1819. INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d),
  1820. INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d),
  1821. INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d),
  1822. INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d),
  1823. INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit),
  1824. INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit),
  1825. INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit),
  1826. INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit),
  1827. INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
  1828. INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
  1829. INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
  1830. INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx),
  1831. INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx),
  1832. INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx),
  1833. INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx),
  1834. INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk),
  1835. INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit),
  1836. INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit),
  1837. INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit),
  1838. { "lcd-no-pins", },
  1839. INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b),
  1840. INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c),
  1841. INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b),
  1842. INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c),
  1843. INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8),
  1844. INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13),
  1845. INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9),
  1846. INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14),
  1847. INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15),
  1848. INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25),
  1849. INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16),
  1850. INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26),
  1851. INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17),
  1852. INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27),
  1853. INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18),
  1854. INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28),
  1855. INGENIC_PIN_GROUP("mac", x1830_mac),
  1856. };
  1857. static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
  1858. static const char *x1830_uart1_groups[] = { "uart1-data", };
  1859. static const char *x1830_sfc_groups[] = { "sfc", };
  1860. static const char *x1830_ssi0_groups[] = {
  1861. "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
  1862. };
  1863. static const char *x1830_ssi1_groups[] = {
  1864. "ssi1-dt-c", "ssi1-dt-d",
  1865. "ssi1-dr-c", "ssi1-dr-d",
  1866. "ssi1-clk-c", "ssi1-clk-d",
  1867. "ssi1-gpc-c", "ssi1-gpc-d",
  1868. "ssi1-ce0-c", "ssi1-ce0-d",
  1869. "ssi1-ce1-c", "ssi1-ce1-d",
  1870. };
  1871. static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
  1872. static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
  1873. static const char *x1830_i2c0_groups[] = { "i2c0-data", };
  1874. static const char *x1830_i2c1_groups[] = { "i2c1-data", };
  1875. static const char *x1830_i2c2_groups[] = { "i2c2-data", };
  1876. static const char *x1830_i2s_groups[] = {
  1877. "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
  1878. };
  1879. static const char *x1830_lcd_groups[] = {
  1880. "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins",
  1881. };
  1882. static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
  1883. static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
  1884. static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
  1885. static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
  1886. static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
  1887. static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
  1888. static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
  1889. static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
  1890. static const char *x1830_mac_groups[] = { "mac", };
  1891. static const struct function_desc x1830_functions[] = {
  1892. { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
  1893. { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
  1894. { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
  1895. { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
  1896. { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
  1897. { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
  1898. { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
  1899. { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
  1900. { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
  1901. { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
  1902. { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
  1903. { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
  1904. { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
  1905. { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
  1906. { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
  1907. { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
  1908. { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
  1909. { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
  1910. { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
  1911. { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
  1912. { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
  1913. };
  1914. static const struct ingenic_chip_info x1830_chip_info = {
  1915. .num_chips = 4,
  1916. .reg_offset = 0x1000,
  1917. .version = ID_X1830,
  1918. .groups = x1830_groups,
  1919. .num_groups = ARRAY_SIZE(x1830_groups),
  1920. .functions = x1830_functions,
  1921. .num_functions = ARRAY_SIZE(x1830_functions),
  1922. .pull_ups = x1830_pull_ups,
  1923. .pull_downs = x1830_pull_downs,
  1924. };
  1925. static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
  1926. {
  1927. unsigned int val;
  1928. regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
  1929. return (u32) val;
  1930. }
  1931. static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
  1932. u8 reg, u8 offset, bool set)
  1933. {
  1934. if (set)
  1935. reg = REG_SET(reg);
  1936. else
  1937. reg = REG_CLEAR(reg);
  1938. regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
  1939. }
  1940. static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
  1941. u8 reg, u8 offset, bool set)
  1942. {
  1943. if (set)
  1944. reg = REG_SET(reg);
  1945. else
  1946. reg = REG_CLEAR(reg);
  1947. regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
  1948. jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
  1949. }
  1950. static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
  1951. {
  1952. regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
  1953. jzgc->jzpc->info->reg_offset),
  1954. jzgc->gc.base / PINS_PER_GPIO_CHIP);
  1955. }
  1956. static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
  1957. u8 offset)
  1958. {
  1959. unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
  1960. return !!(val & BIT(offset));
  1961. }
  1962. static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
  1963. u8 offset, int value)
  1964. {
  1965. if (jzgc->jzpc->info->version >= ID_JZ4770)
  1966. ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
  1967. else
  1968. ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
  1969. }
  1970. static void irq_set_type(struct ingenic_gpio_chip *jzgc,
  1971. u8 offset, unsigned int type)
  1972. {
  1973. u8 reg1, reg2;
  1974. bool val1, val2;
  1975. switch (type) {
  1976. case IRQ_TYPE_EDGE_RISING:
  1977. val1 = val2 = true;
  1978. break;
  1979. case IRQ_TYPE_EDGE_FALLING:
  1980. val1 = false;
  1981. val2 = true;
  1982. break;
  1983. case IRQ_TYPE_LEVEL_HIGH:
  1984. val1 = true;
  1985. val2 = false;
  1986. break;
  1987. case IRQ_TYPE_LEVEL_LOW:
  1988. default:
  1989. val1 = val2 = false;
  1990. break;
  1991. }
  1992. if (jzgc->jzpc->info->version >= ID_JZ4770) {
  1993. reg1 = JZ4760_GPIO_PAT1;
  1994. reg2 = JZ4760_GPIO_PAT0;
  1995. } else {
  1996. reg1 = JZ4740_GPIO_TRIG;
  1997. reg2 = JZ4740_GPIO_DIR;
  1998. }
  1999. if (jzgc->jzpc->info->version >= ID_X1000) {
  2000. ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
  2001. ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
  2002. ingenic_gpio_shadow_set_bit_load(jzgc);
  2003. } else {
  2004. ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
  2005. ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
  2006. }
  2007. }
  2008. static void ingenic_gpio_irq_mask(struct irq_data *irqd)
  2009. {
  2010. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  2011. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2012. ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
  2013. }
  2014. static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
  2015. {
  2016. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  2017. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2018. ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
  2019. }
  2020. static void ingenic_gpio_irq_enable(struct irq_data *irqd)
  2021. {
  2022. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  2023. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2024. int irq = irqd->hwirq;
  2025. if (jzgc->jzpc->info->version >= ID_JZ4770)
  2026. ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
  2027. else
  2028. ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
  2029. ingenic_gpio_irq_unmask(irqd);
  2030. }
  2031. static void ingenic_gpio_irq_disable(struct irq_data *irqd)
  2032. {
  2033. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  2034. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2035. int irq = irqd->hwirq;
  2036. ingenic_gpio_irq_mask(irqd);
  2037. if (jzgc->jzpc->info->version >= ID_JZ4770)
  2038. ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
  2039. else
  2040. ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
  2041. }
  2042. static void ingenic_gpio_irq_ack(struct irq_data *irqd)
  2043. {
  2044. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  2045. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2046. int irq = irqd->hwirq;
  2047. bool high;
  2048. if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
  2049. /*
  2050. * Switch to an interrupt for the opposite edge to the one that
  2051. * triggered the interrupt being ACKed.
  2052. */
  2053. high = ingenic_gpio_get_value(jzgc, irq);
  2054. if (high)
  2055. irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
  2056. else
  2057. irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
  2058. }
  2059. if (jzgc->jzpc->info->version >= ID_JZ4770)
  2060. ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
  2061. else
  2062. ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
  2063. }
  2064. static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
  2065. {
  2066. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  2067. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2068. switch (type) {
  2069. case IRQ_TYPE_EDGE_BOTH:
  2070. case IRQ_TYPE_EDGE_RISING:
  2071. case IRQ_TYPE_EDGE_FALLING:
  2072. irq_set_handler_locked(irqd, handle_edge_irq);
  2073. break;
  2074. case IRQ_TYPE_LEVEL_HIGH:
  2075. case IRQ_TYPE_LEVEL_LOW:
  2076. irq_set_handler_locked(irqd, handle_level_irq);
  2077. break;
  2078. default:
  2079. irq_set_handler_locked(irqd, handle_bad_irq);
  2080. }
  2081. if (type == IRQ_TYPE_EDGE_BOTH) {
  2082. /*
  2083. * The hardware does not support interrupts on both edges. The
  2084. * best we can do is to set up a single-edge interrupt and then
  2085. * switch to the opposing edge when ACKing the interrupt.
  2086. */
  2087. bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
  2088. type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
  2089. }
  2090. irq_set_type(jzgc, irqd->hwirq, type);
  2091. return 0;
  2092. }
  2093. static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
  2094. {
  2095. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  2096. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2097. return irq_set_irq_wake(jzgc->irq, on);
  2098. }
  2099. static void ingenic_gpio_irq_handler(struct irq_desc *desc)
  2100. {
  2101. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  2102. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2103. struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
  2104. unsigned long flag, i;
  2105. chained_irq_enter(irq_chip, desc);
  2106. if (jzgc->jzpc->info->version >= ID_JZ4770)
  2107. flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
  2108. else
  2109. flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
  2110. for_each_set_bit(i, &flag, 32)
  2111. generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
  2112. chained_irq_exit(irq_chip, desc);
  2113. }
  2114. static void ingenic_gpio_set(struct gpio_chip *gc,
  2115. unsigned int offset, int value)
  2116. {
  2117. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2118. ingenic_gpio_set_value(jzgc, offset, value);
  2119. }
  2120. static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
  2121. {
  2122. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2123. return (int) ingenic_gpio_get_value(jzgc, offset);
  2124. }
  2125. static int ingenic_gpio_direction_input(struct gpio_chip *gc,
  2126. unsigned int offset)
  2127. {
  2128. return pinctrl_gpio_direction_input(gc->base + offset);
  2129. }
  2130. static int ingenic_gpio_direction_output(struct gpio_chip *gc,
  2131. unsigned int offset, int value)
  2132. {
  2133. ingenic_gpio_set(gc, offset, value);
  2134. return pinctrl_gpio_direction_output(gc->base + offset);
  2135. }
  2136. static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
  2137. unsigned int pin, u8 reg, bool set)
  2138. {
  2139. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2140. unsigned int offt = pin / PINS_PER_GPIO_CHIP;
  2141. regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
  2142. (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
  2143. }
  2144. static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
  2145. unsigned int pin, u8 reg, bool set)
  2146. {
  2147. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2148. regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
  2149. (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
  2150. }
  2151. static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
  2152. unsigned int pin)
  2153. {
  2154. regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
  2155. pin / PINS_PER_GPIO_CHIP);
  2156. }
  2157. static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
  2158. unsigned int pin, u8 reg)
  2159. {
  2160. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2161. unsigned int offt = pin / PINS_PER_GPIO_CHIP;
  2162. unsigned int val;
  2163. regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
  2164. return val & BIT(idx);
  2165. }
  2166. static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
  2167. {
  2168. struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
  2169. struct ingenic_pinctrl *jzpc = jzgc->jzpc;
  2170. unsigned int pin = gc->base + offset;
  2171. if (jzpc->info->version >= ID_JZ4770) {
  2172. if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_INT) ||
  2173. ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1))
  2174. return GPIO_LINE_DIRECTION_IN;
  2175. return GPIO_LINE_DIRECTION_OUT;
  2176. }
  2177. if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
  2178. return GPIO_LINE_DIRECTION_IN;
  2179. if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
  2180. return GPIO_LINE_DIRECTION_OUT;
  2181. return GPIO_LINE_DIRECTION_IN;
  2182. }
  2183. static const struct pinctrl_ops ingenic_pctlops = {
  2184. .get_groups_count = pinctrl_generic_get_group_count,
  2185. .get_group_name = pinctrl_generic_get_group_name,
  2186. .get_group_pins = pinctrl_generic_get_group_pins,
  2187. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  2188. .dt_free_map = pinconf_generic_dt_free_map,
  2189. };
  2190. static int ingenic_gpio_irq_request(struct irq_data *data)
  2191. {
  2192. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  2193. int ret;
  2194. ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);
  2195. if (ret)
  2196. return ret;
  2197. return gpiochip_reqres_irq(gpio_chip, data->hwirq);
  2198. }
  2199. static void ingenic_gpio_irq_release(struct irq_data *data)
  2200. {
  2201. struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
  2202. return gpiochip_relres_irq(gpio_chip, data->hwirq);
  2203. }
  2204. static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
  2205. int pin, int func)
  2206. {
  2207. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2208. unsigned int offt = pin / PINS_PER_GPIO_CHIP;
  2209. dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
  2210. 'A' + offt, idx, func);
  2211. if (jzpc->info->version >= ID_X1000) {
  2212. ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
  2213. ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
  2214. ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
  2215. ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
  2216. ingenic_shadow_config_pin_load(jzpc, pin);
  2217. } else if (jzpc->info->version >= ID_JZ4770) {
  2218. ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
  2219. ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
  2220. ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
  2221. ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
  2222. } else {
  2223. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
  2224. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
  2225. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
  2226. }
  2227. return 0;
  2228. }
  2229. static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
  2230. unsigned int selector, unsigned int group)
  2231. {
  2232. struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
  2233. struct function_desc *func;
  2234. struct group_desc *grp;
  2235. unsigned int i;
  2236. func = pinmux_generic_get_function(pctldev, selector);
  2237. if (!func)
  2238. return -EINVAL;
  2239. grp = pinctrl_generic_get_group(pctldev, group);
  2240. if (!grp)
  2241. return -EINVAL;
  2242. dev_dbg(pctldev->dev, "enable function %s group %s\n",
  2243. func->name, grp->name);
  2244. for (i = 0; i < grp->num_pins; i++) {
  2245. int *pin_modes = grp->data;
  2246. ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
  2247. }
  2248. return 0;
  2249. }
  2250. static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
  2251. struct pinctrl_gpio_range *range,
  2252. unsigned int pin, bool input)
  2253. {
  2254. struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
  2255. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2256. unsigned int offt = pin / PINS_PER_GPIO_CHIP;
  2257. dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
  2258. 'A' + offt, idx, input ? "in" : "out");
  2259. if (jzpc->info->version >= ID_X1000) {
  2260. ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
  2261. ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
  2262. ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
  2263. ingenic_shadow_config_pin_load(jzpc, pin);
  2264. } else if (jzpc->info->version >= ID_JZ4770) {
  2265. ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
  2266. ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
  2267. ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
  2268. } else {
  2269. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
  2270. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
  2271. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
  2272. }
  2273. return 0;
  2274. }
  2275. static const struct pinmux_ops ingenic_pmxops = {
  2276. .get_functions_count = pinmux_generic_get_function_count,
  2277. .get_function_name = pinmux_generic_get_function_name,
  2278. .get_function_groups = pinmux_generic_get_function_groups,
  2279. .set_mux = ingenic_pinmux_set_mux,
  2280. .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
  2281. };
  2282. static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
  2283. unsigned int pin, unsigned long *config)
  2284. {
  2285. struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
  2286. enum pin_config_param param = pinconf_to_config_param(*config);
  2287. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2288. unsigned int offt = pin / PINS_PER_GPIO_CHIP;
  2289. bool pull;
  2290. if (jzpc->info->version >= ID_JZ4770)
  2291. pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
  2292. else
  2293. pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
  2294. switch (param) {
  2295. case PIN_CONFIG_BIAS_DISABLE:
  2296. if (pull)
  2297. return -EINVAL;
  2298. break;
  2299. case PIN_CONFIG_BIAS_PULL_UP:
  2300. if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
  2301. return -EINVAL;
  2302. break;
  2303. case PIN_CONFIG_BIAS_PULL_DOWN:
  2304. if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
  2305. return -EINVAL;
  2306. break;
  2307. default:
  2308. return -ENOTSUPP;
  2309. }
  2310. *config = pinconf_to_config_packed(param, 1);
  2311. return 0;
  2312. }
  2313. static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
  2314. unsigned int pin, unsigned int bias)
  2315. {
  2316. if (jzpc->info->version >= ID_X1830) {
  2317. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2318. unsigned int half = PINS_PER_GPIO_CHIP / 2;
  2319. unsigned int idxh = pin % half * 2;
  2320. unsigned int offt = pin / PINS_PER_GPIO_CHIP;
  2321. if (idx < half) {
  2322. regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
  2323. REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
  2324. regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
  2325. REG_SET(X1830_GPIO_PEL), bias << idxh);
  2326. } else {
  2327. regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
  2328. REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
  2329. regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
  2330. REG_SET(X1830_GPIO_PEH), bias << idxh);
  2331. }
  2332. } else if (jzpc->info->version >= ID_JZ4770) {
  2333. ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias);
  2334. } else {
  2335. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
  2336. }
  2337. }
  2338. static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
  2339. unsigned int pin, bool high)
  2340. {
  2341. if (jzpc->info->version >= ID_JZ4770)
  2342. ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);
  2343. else
  2344. ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
  2345. }
  2346. static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  2347. unsigned long *configs, unsigned int num_configs)
  2348. {
  2349. struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
  2350. unsigned int idx = pin % PINS_PER_GPIO_CHIP;
  2351. unsigned int offt = pin / PINS_PER_GPIO_CHIP;
  2352. unsigned int cfg, arg;
  2353. int ret;
  2354. for (cfg = 0; cfg < num_configs; cfg++) {
  2355. switch (pinconf_to_config_param(configs[cfg])) {
  2356. case PIN_CONFIG_BIAS_DISABLE:
  2357. case PIN_CONFIG_BIAS_PULL_UP:
  2358. case PIN_CONFIG_BIAS_PULL_DOWN:
  2359. case PIN_CONFIG_OUTPUT:
  2360. continue;
  2361. default:
  2362. return -ENOTSUPP;
  2363. }
  2364. }
  2365. for (cfg = 0; cfg < num_configs; cfg++) {
  2366. arg = pinconf_to_config_argument(configs[cfg]);
  2367. switch (pinconf_to_config_param(configs[cfg])) {
  2368. case PIN_CONFIG_BIAS_DISABLE:
  2369. dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
  2370. 'A' + offt, idx);
  2371. ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
  2372. break;
  2373. case PIN_CONFIG_BIAS_PULL_UP:
  2374. if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
  2375. return -EINVAL;
  2376. dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
  2377. 'A' + offt, idx);
  2378. ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
  2379. break;
  2380. case PIN_CONFIG_BIAS_PULL_DOWN:
  2381. if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
  2382. return -EINVAL;
  2383. dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
  2384. 'A' + offt, idx);
  2385. ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
  2386. break;
  2387. case PIN_CONFIG_OUTPUT:
  2388. ret = pinctrl_gpio_direction_output(pin);
  2389. if (ret)
  2390. return ret;
  2391. ingenic_set_output_level(jzpc, pin, arg);
  2392. break;
  2393. default:
  2394. /* unreachable */
  2395. break;
  2396. }
  2397. }
  2398. return 0;
  2399. }
  2400. static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
  2401. unsigned int group, unsigned long *config)
  2402. {
  2403. const unsigned int *pins;
  2404. unsigned int i, npins, old = 0;
  2405. int ret;
  2406. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  2407. if (ret)
  2408. return ret;
  2409. for (i = 0; i < npins; i++) {
  2410. if (ingenic_pinconf_get(pctldev, pins[i], config))
  2411. return -ENOTSUPP;
  2412. /* configs do not match between two pins */
  2413. if (i && (old != *config))
  2414. return -ENOTSUPP;
  2415. old = *config;
  2416. }
  2417. return 0;
  2418. }
  2419. static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
  2420. unsigned int group, unsigned long *configs,
  2421. unsigned int num_configs)
  2422. {
  2423. const unsigned int *pins;
  2424. unsigned int i, npins;
  2425. int ret;
  2426. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  2427. if (ret)
  2428. return ret;
  2429. for (i = 0; i < npins; i++) {
  2430. ret = ingenic_pinconf_set(pctldev,
  2431. pins[i], configs, num_configs);
  2432. if (ret)
  2433. return ret;
  2434. }
  2435. return 0;
  2436. }
  2437. static const struct pinconf_ops ingenic_confops = {
  2438. .is_generic = true,
  2439. .pin_config_get = ingenic_pinconf_get,
  2440. .pin_config_set = ingenic_pinconf_set,
  2441. .pin_config_group_get = ingenic_pinconf_group_get,
  2442. .pin_config_group_set = ingenic_pinconf_group_set,
  2443. };
  2444. static const struct regmap_config ingenic_pinctrl_regmap_config = {
  2445. .reg_bits = 32,
  2446. .val_bits = 32,
  2447. .reg_stride = 4,
  2448. };
  2449. static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
  2450. { .compatible = "ingenic,jz4740-gpio", },
  2451. { .compatible = "ingenic,jz4725b-gpio", },
  2452. { .compatible = "ingenic,jz4760-gpio", },
  2453. { .compatible = "ingenic,jz4770-gpio", },
  2454. { .compatible = "ingenic,jz4780-gpio", },
  2455. { .compatible = "ingenic,x1000-gpio", },
  2456. { .compatible = "ingenic,x1830-gpio", },
  2457. {},
  2458. };
  2459. static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
  2460. struct device_node *node)
  2461. {
  2462. struct ingenic_gpio_chip *jzgc;
  2463. struct device *dev = jzpc->dev;
  2464. struct gpio_irq_chip *girq;
  2465. unsigned int bank;
  2466. int err;
  2467. err = of_property_read_u32(node, "reg", &bank);
  2468. if (err) {
  2469. dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
  2470. return err;
  2471. }
  2472. jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
  2473. if (!jzgc)
  2474. return -ENOMEM;
  2475. jzgc->jzpc = jzpc;
  2476. jzgc->reg_base = bank * jzpc->info->reg_offset;
  2477. jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
  2478. if (!jzgc->gc.label)
  2479. return -ENOMEM;
  2480. /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
  2481. * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
  2482. * <linux/gpio/consumer.h> INSTEAD.
  2483. */
  2484. jzgc->gc.base = bank * 32;
  2485. jzgc->gc.ngpio = 32;
  2486. jzgc->gc.parent = dev;
  2487. jzgc->gc.of_node = node;
  2488. jzgc->gc.owner = THIS_MODULE;
  2489. jzgc->gc.set = ingenic_gpio_set;
  2490. jzgc->gc.get = ingenic_gpio_get;
  2491. jzgc->gc.direction_input = ingenic_gpio_direction_input;
  2492. jzgc->gc.direction_output = ingenic_gpio_direction_output;
  2493. jzgc->gc.get_direction = ingenic_gpio_get_direction;
  2494. jzgc->gc.request = gpiochip_generic_request;
  2495. jzgc->gc.free = gpiochip_generic_free;
  2496. jzgc->irq = irq_of_parse_and_map(node, 0);
  2497. if (!jzgc->irq)
  2498. return -EINVAL;
  2499. jzgc->irq_chip.name = jzgc->gc.label;
  2500. jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
  2501. jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
  2502. jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
  2503. jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
  2504. jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
  2505. jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
  2506. jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
  2507. jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
  2508. jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
  2509. jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
  2510. girq = &jzgc->gc.irq;
  2511. girq->chip = &jzgc->irq_chip;
  2512. girq->parent_handler = ingenic_gpio_irq_handler;
  2513. girq->num_parents = 1;
  2514. girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
  2515. GFP_KERNEL);
  2516. if (!girq->parents)
  2517. return -ENOMEM;
  2518. girq->parents[0] = jzgc->irq;
  2519. girq->default_type = IRQ_TYPE_NONE;
  2520. girq->handler = handle_level_irq;
  2521. err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
  2522. if (err)
  2523. return err;
  2524. return 0;
  2525. }
  2526. static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
  2527. {
  2528. struct device *dev = &pdev->dev;
  2529. struct ingenic_pinctrl *jzpc;
  2530. struct pinctrl_desc *pctl_desc;
  2531. void __iomem *base;
  2532. const struct ingenic_chip_info *chip_info;
  2533. struct device_node *node;
  2534. unsigned int i;
  2535. int err;
  2536. jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
  2537. if (!jzpc)
  2538. return -ENOMEM;
  2539. base = devm_platform_ioremap_resource(pdev, 0);
  2540. if (IS_ERR(base))
  2541. return PTR_ERR(base);
  2542. jzpc->map = devm_regmap_init_mmio(dev, base,
  2543. &ingenic_pinctrl_regmap_config);
  2544. if (IS_ERR(jzpc->map)) {
  2545. dev_err(dev, "Failed to create regmap\n");
  2546. return PTR_ERR(jzpc->map);
  2547. }
  2548. jzpc->dev = dev;
  2549. jzpc->info = chip_info = of_device_get_match_data(dev);
  2550. pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
  2551. if (!pctl_desc)
  2552. return -ENOMEM;
  2553. /* fill in pinctrl_desc structure */
  2554. pctl_desc->name = dev_name(dev);
  2555. pctl_desc->owner = THIS_MODULE;
  2556. pctl_desc->pctlops = &ingenic_pctlops;
  2557. pctl_desc->pmxops = &ingenic_pmxops;
  2558. pctl_desc->confops = &ingenic_confops;
  2559. pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
  2560. pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
  2561. pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
  2562. if (!jzpc->pdesc)
  2563. return -ENOMEM;
  2564. for (i = 0; i < pctl_desc->npins; i++) {
  2565. jzpc->pdesc[i].number = i;
  2566. jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
  2567. 'A' + (i / PINS_PER_GPIO_CHIP),
  2568. i % PINS_PER_GPIO_CHIP);
  2569. }
  2570. jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
  2571. if (IS_ERR(jzpc->pctl)) {
  2572. dev_err(dev, "Failed to register pinctrl\n");
  2573. return PTR_ERR(jzpc->pctl);
  2574. }
  2575. for (i = 0; i < chip_info->num_groups; i++) {
  2576. const struct group_desc *group = &chip_info->groups[i];
  2577. err = pinctrl_generic_add_group(jzpc->pctl, group->name,
  2578. group->pins, group->num_pins, group->data);
  2579. if (err < 0) {
  2580. dev_err(dev, "Failed to register group %s\n",
  2581. group->name);
  2582. return err;
  2583. }
  2584. }
  2585. for (i = 0; i < chip_info->num_functions; i++) {
  2586. const struct function_desc *func = &chip_info->functions[i];
  2587. err = pinmux_generic_add_function(jzpc->pctl, func->name,
  2588. func->group_names, func->num_group_names,
  2589. func->data);
  2590. if (err < 0) {
  2591. dev_err(dev, "Failed to register function %s\n",
  2592. func->name);
  2593. return err;
  2594. }
  2595. }
  2596. dev_set_drvdata(dev, jzpc->map);
  2597. for_each_child_of_node(dev->of_node, node) {
  2598. if (of_match_node(ingenic_gpio_of_match, node)) {
  2599. err = ingenic_gpio_probe(jzpc, node);
  2600. if (err)
  2601. return err;
  2602. }
  2603. }
  2604. return 0;
  2605. }
  2606. static const struct of_device_id ingenic_pinctrl_of_match[] = {
  2607. { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
  2608. { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
  2609. { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
  2610. { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
  2611. { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
  2612. { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
  2613. { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
  2614. { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
  2615. { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
  2616. { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
  2617. {},
  2618. };
  2619. static struct platform_driver ingenic_pinctrl_driver = {
  2620. .driver = {
  2621. .name = "pinctrl-ingenic",
  2622. .of_match_table = ingenic_pinctrl_of_match,
  2623. },
  2624. };
  2625. static int __init ingenic_pinctrl_drv_register(void)
  2626. {
  2627. return platform_driver_probe(&ingenic_pinctrl_driver,
  2628. ingenic_pinctrl_probe);
  2629. }
  2630. subsys_initcall(ingenic_pinctrl_drv_register);