pinctrl-bm1880.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Bitmain BM1880 SoC Pinctrl driver
  4. *
  5. * Copyright (c) 2019 Linaro Ltd.
  6. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7. */
  8. #include <linux/io.h>
  9. #include <linux/of.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include <linux/pinctrl/pinmux.h>
  13. #include <linux/pinctrl/pinconf-generic.h>
  14. #include <linux/slab.h>
  15. #include "core.h"
  16. #include "pinctrl-utils.h"
  17. #define BM1880_REG_MUX 0x20
  18. /**
  19. * struct bm1880_pinctrl - driver data
  20. * @base: Pinctrl base address
  21. * @pctrldev: Pinctrl device
  22. * @groups: Pingroups
  23. * @ngroups: Number of @groups
  24. * @funcs: Pinmux functions
  25. * @nfuncs: Number of @funcs
  26. * @pinconf: Pinconf data
  27. */
  28. struct bm1880_pinctrl {
  29. void __iomem *base;
  30. struct pinctrl_dev *pctrldev;
  31. const struct bm1880_pctrl_group *groups;
  32. unsigned int ngroups;
  33. const struct bm1880_pinmux_function *funcs;
  34. unsigned int nfuncs;
  35. const struct bm1880_pinconf_data *pinconf;
  36. };
  37. /**
  38. * struct bm1880_pctrl_group - pinctrl group
  39. * @name: Name of the group
  40. * @pins: Array of pins belonging to this group
  41. * @npins: Number of @pins
  42. */
  43. struct bm1880_pctrl_group {
  44. const char *name;
  45. const unsigned int *pins;
  46. const unsigned int npins;
  47. };
  48. /**
  49. * struct bm1880_pinmux_function - a pinmux function
  50. * @name: Name of the pinmux function.
  51. * @groups: List of pingroups for this function.
  52. * @ngroups: Number of entries in @groups.
  53. * @mux_val: Selector for this function
  54. * @mux: Offset of function specific mux
  55. * @mux_shift: Shift for function specific selector
  56. */
  57. struct bm1880_pinmux_function {
  58. const char *name;
  59. const char * const *groups;
  60. unsigned int ngroups;
  61. u32 mux_val;
  62. u32 mux;
  63. u8 mux_shift;
  64. };
  65. /**
  66. * struct bm1880_pinconf_data - pinconf data
  67. * @drv_bits: Drive strength bit width
  68. */
  69. struct bm1880_pinconf_data {
  70. u32 drv_bits;
  71. };
  72. static const struct pinctrl_pin_desc bm1880_pins[] = {
  73. PINCTRL_PIN(0, "MIO0"),
  74. PINCTRL_PIN(1, "MIO1"),
  75. PINCTRL_PIN(2, "MIO2"),
  76. PINCTRL_PIN(3, "MIO3"),
  77. PINCTRL_PIN(4, "MIO4"),
  78. PINCTRL_PIN(5, "MIO5"),
  79. PINCTRL_PIN(6, "MIO6"),
  80. PINCTRL_PIN(7, "MIO7"),
  81. PINCTRL_PIN(8, "MIO8"),
  82. PINCTRL_PIN(9, "MIO9"),
  83. PINCTRL_PIN(10, "MIO10"),
  84. PINCTRL_PIN(11, "MIO11"),
  85. PINCTRL_PIN(12, "MIO12"),
  86. PINCTRL_PIN(13, "MIO13"),
  87. PINCTRL_PIN(14, "MIO14"),
  88. PINCTRL_PIN(15, "MIO15"),
  89. PINCTRL_PIN(16, "MIO16"),
  90. PINCTRL_PIN(17, "MIO17"),
  91. PINCTRL_PIN(18, "MIO18"),
  92. PINCTRL_PIN(19, "MIO19"),
  93. PINCTRL_PIN(20, "MIO20"),
  94. PINCTRL_PIN(21, "MIO21"),
  95. PINCTRL_PIN(22, "MIO22"),
  96. PINCTRL_PIN(23, "MIO23"),
  97. PINCTRL_PIN(24, "MIO24"),
  98. PINCTRL_PIN(25, "MIO25"),
  99. PINCTRL_PIN(26, "MIO26"),
  100. PINCTRL_PIN(27, "MIO27"),
  101. PINCTRL_PIN(28, "MIO28"),
  102. PINCTRL_PIN(29, "MIO29"),
  103. PINCTRL_PIN(30, "MIO30"),
  104. PINCTRL_PIN(31, "MIO31"),
  105. PINCTRL_PIN(32, "MIO32"),
  106. PINCTRL_PIN(33, "MIO33"),
  107. PINCTRL_PIN(34, "MIO34"),
  108. PINCTRL_PIN(35, "MIO35"),
  109. PINCTRL_PIN(36, "MIO36"),
  110. PINCTRL_PIN(37, "MIO37"),
  111. PINCTRL_PIN(38, "MIO38"),
  112. PINCTRL_PIN(39, "MIO39"),
  113. PINCTRL_PIN(40, "MIO40"),
  114. PINCTRL_PIN(41, "MIO41"),
  115. PINCTRL_PIN(42, "MIO42"),
  116. PINCTRL_PIN(43, "MIO43"),
  117. PINCTRL_PIN(44, "MIO44"),
  118. PINCTRL_PIN(45, "MIO45"),
  119. PINCTRL_PIN(46, "MIO46"),
  120. PINCTRL_PIN(47, "MIO47"),
  121. PINCTRL_PIN(48, "MIO48"),
  122. PINCTRL_PIN(49, "MIO49"),
  123. PINCTRL_PIN(50, "MIO50"),
  124. PINCTRL_PIN(51, "MIO51"),
  125. PINCTRL_PIN(52, "MIO52"),
  126. PINCTRL_PIN(53, "MIO53"),
  127. PINCTRL_PIN(54, "MIO54"),
  128. PINCTRL_PIN(55, "MIO55"),
  129. PINCTRL_PIN(56, "MIO56"),
  130. PINCTRL_PIN(57, "MIO57"),
  131. PINCTRL_PIN(58, "MIO58"),
  132. PINCTRL_PIN(59, "MIO59"),
  133. PINCTRL_PIN(60, "MIO60"),
  134. PINCTRL_PIN(61, "MIO61"),
  135. PINCTRL_PIN(62, "MIO62"),
  136. PINCTRL_PIN(63, "MIO63"),
  137. PINCTRL_PIN(64, "MIO64"),
  138. PINCTRL_PIN(65, "MIO65"),
  139. PINCTRL_PIN(66, "MIO66"),
  140. PINCTRL_PIN(67, "MIO67"),
  141. PINCTRL_PIN(68, "MIO68"),
  142. PINCTRL_PIN(69, "MIO69"),
  143. PINCTRL_PIN(70, "MIO70"),
  144. PINCTRL_PIN(71, "MIO71"),
  145. PINCTRL_PIN(72, "MIO72"),
  146. PINCTRL_PIN(73, "MIO73"),
  147. PINCTRL_PIN(74, "MIO74"),
  148. PINCTRL_PIN(75, "MIO75"),
  149. PINCTRL_PIN(76, "MIO76"),
  150. PINCTRL_PIN(77, "MIO77"),
  151. PINCTRL_PIN(78, "MIO78"),
  152. PINCTRL_PIN(79, "MIO79"),
  153. PINCTRL_PIN(80, "MIO80"),
  154. PINCTRL_PIN(81, "MIO81"),
  155. PINCTRL_PIN(82, "MIO82"),
  156. PINCTRL_PIN(83, "MIO83"),
  157. PINCTRL_PIN(84, "MIO84"),
  158. PINCTRL_PIN(85, "MIO85"),
  159. PINCTRL_PIN(86, "MIO86"),
  160. PINCTRL_PIN(87, "MIO87"),
  161. PINCTRL_PIN(88, "MIO88"),
  162. PINCTRL_PIN(89, "MIO89"),
  163. PINCTRL_PIN(90, "MIO90"),
  164. PINCTRL_PIN(91, "MIO91"),
  165. PINCTRL_PIN(92, "MIO92"),
  166. PINCTRL_PIN(93, "MIO93"),
  167. PINCTRL_PIN(94, "MIO94"),
  168. PINCTRL_PIN(95, "MIO95"),
  169. PINCTRL_PIN(96, "MIO96"),
  170. PINCTRL_PIN(97, "MIO97"),
  171. PINCTRL_PIN(98, "MIO98"),
  172. PINCTRL_PIN(99, "MIO99"),
  173. PINCTRL_PIN(100, "MIO100"),
  174. PINCTRL_PIN(101, "MIO101"),
  175. PINCTRL_PIN(102, "MIO102"),
  176. PINCTRL_PIN(103, "MIO103"),
  177. PINCTRL_PIN(104, "MIO104"),
  178. PINCTRL_PIN(105, "MIO105"),
  179. PINCTRL_PIN(106, "MIO106"),
  180. PINCTRL_PIN(107, "MIO107"),
  181. PINCTRL_PIN(108, "MIO108"),
  182. PINCTRL_PIN(109, "MIO109"),
  183. PINCTRL_PIN(110, "MIO110"),
  184. PINCTRL_PIN(111, "MIO111"),
  185. };
  186. enum bm1880_pinmux_functions {
  187. F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2,
  188. F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10,
  189. F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17,
  190. F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24,
  191. F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31,
  192. F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1,
  193. F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4,
  194. F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11,
  195. F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2,
  196. F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10,
  197. F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17,
  198. F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24,
  199. F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31,
  200. F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38,
  201. F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45,
  202. F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52,
  203. F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59,
  204. F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66,
  205. F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0,
  206. F_max
  207. };
  208. static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
  209. 10, 11, 12, 13, 14, 15, 16 };
  210. static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 };
  211. static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 };
  212. static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24,
  213. 25, 26 };
  214. static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35,
  215. 36, 37, 38, 39, 40, 41, 42 };
  216. static const unsigned int pwm0_pins[] = { 29 };
  217. static const unsigned int pwm1_pins[] = { 30 };
  218. static const unsigned int pwm2_pins[] = { 34 };
  219. static const unsigned int pwm3_pins[] = { 35 };
  220. static const unsigned int pwm4_pins[] = { 43 };
  221. static const unsigned int pwm5_pins[] = { 44 };
  222. static const unsigned int pwm6_pins[] = { 45 };
  223. static const unsigned int pwm7_pins[] = { 46 };
  224. static const unsigned int pwm8_pins[] = { 47 };
  225. static const unsigned int pwm9_pins[] = { 48 };
  226. static const unsigned int pwm10_pins[] = { 49 };
  227. static const unsigned int pwm11_pins[] = { 50 };
  228. static const unsigned int pwm12_pins[] = { 51 };
  229. static const unsigned int pwm13_pins[] = { 52 };
  230. static const unsigned int pwm14_pins[] = { 53 };
  231. static const unsigned int pwm15_pins[] = { 54 };
  232. static const unsigned int pwm16_pins[] = { 55 };
  233. static const unsigned int pwm17_pins[] = { 56 };
  234. static const unsigned int pwm18_pins[] = { 57 };
  235. static const unsigned int pwm19_pins[] = { 58 };
  236. static const unsigned int pwm20_pins[] = { 59 };
  237. static const unsigned int pwm21_pins[] = { 60 };
  238. static const unsigned int pwm22_pins[] = { 61 };
  239. static const unsigned int pwm23_pins[] = { 62 };
  240. static const unsigned int pwm24_pins[] = { 97 };
  241. static const unsigned int pwm25_pins[] = { 98 };
  242. static const unsigned int pwm26_pins[] = { 99 };
  243. static const unsigned int pwm27_pins[] = { 100 };
  244. static const unsigned int pwm28_pins[] = { 101 };
  245. static const unsigned int pwm29_pins[] = { 102 };
  246. static const unsigned int pwm30_pins[] = { 103 };
  247. static const unsigned int pwm31_pins[] = { 104 };
  248. static const unsigned int pwm32_pins[] = { 105 };
  249. static const unsigned int pwm33_pins[] = { 106 };
  250. static const unsigned int pwm34_pins[] = { 107 };
  251. static const unsigned int pwm35_pins[] = { 108 };
  252. static const unsigned int pwm36_pins[] = { 109 };
  253. static const unsigned int pwm37_pins[] = { 110 };
  254. static const unsigned int i2c0_pins[] = { 63, 64 };
  255. static const unsigned int i2c1_pins[] = { 65, 66 };
  256. static const unsigned int i2c2_pins[] = { 67, 68 };
  257. static const unsigned int i2c3_pins[] = { 69, 70 };
  258. static const unsigned int i2c4_pins[] = { 71, 72 };
  259. static const unsigned int uart0_pins[] = { 73, 74 };
  260. static const unsigned int uart1_pins[] = { 75, 76 };
  261. static const unsigned int uart2_pins[] = { 77, 78 };
  262. static const unsigned int uart3_pins[] = { 79, 80 };
  263. static const unsigned int uart4_pins[] = { 81, 82 };
  264. static const unsigned int uart5_pins[] = { 83, 84 };
  265. static const unsigned int uart6_pins[] = { 85, 86 };
  266. static const unsigned int uart7_pins[] = { 87, 88 };
  267. static const unsigned int uart8_pins[] = { 89, 90 };
  268. static const unsigned int uart9_pins[] = { 91, 92 };
  269. static const unsigned int uart10_pins[] = { 93, 94 };
  270. static const unsigned int uart11_pins[] = { 95, 96 };
  271. static const unsigned int uart12_pins[] = { 73, 74, 75, 76 };
  272. static const unsigned int uart13_pins[] = { 77, 78, 83, 84 };
  273. static const unsigned int uart14_pins[] = { 79, 80, 85, 86 };
  274. static const unsigned int uart15_pins[] = { 81, 82, 87, 88 };
  275. static const unsigned int gpio0_pins[] = { 97 };
  276. static const unsigned int gpio1_pins[] = { 98 };
  277. static const unsigned int gpio2_pins[] = { 99 };
  278. static const unsigned int gpio3_pins[] = { 100 };
  279. static const unsigned int gpio4_pins[] = { 101 };
  280. static const unsigned int gpio5_pins[] = { 102 };
  281. static const unsigned int gpio6_pins[] = { 103 };
  282. static const unsigned int gpio7_pins[] = { 104 };
  283. static const unsigned int gpio8_pins[] = { 105 };
  284. static const unsigned int gpio9_pins[] = { 106 };
  285. static const unsigned int gpio10_pins[] = { 107 };
  286. static const unsigned int gpio11_pins[] = { 108 };
  287. static const unsigned int gpio12_pins[] = { 109 };
  288. static const unsigned int gpio13_pins[] = { 110 };
  289. static const unsigned int gpio14_pins[] = { 43 };
  290. static const unsigned int gpio15_pins[] = { 44 };
  291. static const unsigned int gpio16_pins[] = { 45 };
  292. static const unsigned int gpio17_pins[] = { 46 };
  293. static const unsigned int gpio18_pins[] = { 47 };
  294. static const unsigned int gpio19_pins[] = { 48 };
  295. static const unsigned int gpio20_pins[] = { 49 };
  296. static const unsigned int gpio21_pins[] = { 50 };
  297. static const unsigned int gpio22_pins[] = { 51 };
  298. static const unsigned int gpio23_pins[] = { 52 };
  299. static const unsigned int gpio24_pins[] = { 53 };
  300. static const unsigned int gpio25_pins[] = { 54 };
  301. static const unsigned int gpio26_pins[] = { 55 };
  302. static const unsigned int gpio27_pins[] = { 56 };
  303. static const unsigned int gpio28_pins[] = { 57 };
  304. static const unsigned int gpio29_pins[] = { 58 };
  305. static const unsigned int gpio30_pins[] = { 59 };
  306. static const unsigned int gpio31_pins[] = { 60 };
  307. static const unsigned int gpio32_pins[] = { 61 };
  308. static const unsigned int gpio33_pins[] = { 62 };
  309. static const unsigned int gpio34_pins[] = { 63 };
  310. static const unsigned int gpio35_pins[] = { 64 };
  311. static const unsigned int gpio36_pins[] = { 65 };
  312. static const unsigned int gpio37_pins[] = { 66 };
  313. static const unsigned int gpio38_pins[] = { 67 };
  314. static const unsigned int gpio39_pins[] = { 68 };
  315. static const unsigned int gpio40_pins[] = { 69 };
  316. static const unsigned int gpio41_pins[] = { 70 };
  317. static const unsigned int gpio42_pins[] = { 71 };
  318. static const unsigned int gpio43_pins[] = { 72 };
  319. static const unsigned int gpio44_pins[] = { 73 };
  320. static const unsigned int gpio45_pins[] = { 74 };
  321. static const unsigned int gpio46_pins[] = { 75 };
  322. static const unsigned int gpio47_pins[] = { 76 };
  323. static const unsigned int gpio48_pins[] = { 77 };
  324. static const unsigned int gpio49_pins[] = { 78 };
  325. static const unsigned int gpio50_pins[] = { 79 };
  326. static const unsigned int gpio51_pins[] = { 80 };
  327. static const unsigned int gpio52_pins[] = { 81 };
  328. static const unsigned int gpio53_pins[] = { 82 };
  329. static const unsigned int gpio54_pins[] = { 83 };
  330. static const unsigned int gpio55_pins[] = { 84 };
  331. static const unsigned int gpio56_pins[] = { 85 };
  332. static const unsigned int gpio57_pins[] = { 86 };
  333. static const unsigned int gpio58_pins[] = { 87 };
  334. static const unsigned int gpio59_pins[] = { 88 };
  335. static const unsigned int gpio60_pins[] = { 89 };
  336. static const unsigned int gpio61_pins[] = { 90 };
  337. static const unsigned int gpio62_pins[] = { 91 };
  338. static const unsigned int gpio63_pins[] = { 92 };
  339. static const unsigned int gpio64_pins[] = { 93 };
  340. static const unsigned int gpio65_pins[] = { 94 };
  341. static const unsigned int gpio66_pins[] = { 95 };
  342. static const unsigned int gpio67_pins[] = { 96 };
  343. static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51,
  344. 52, 53, 54, 55, 56, 57, 58 };
  345. static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 };
  346. static const unsigned int i2s0_mclkin_pins[] = { 97 };
  347. static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 };
  348. static const unsigned int i2s1_mclkin_pins[] = { 98 };
  349. static const unsigned int spi0_pins[] = { 59, 60, 61, 62 };
  350. #define BM1880_PINCTRL_GRP(nm) \
  351. { \
  352. .name = #nm "_grp", \
  353. .pins = nm ## _pins, \
  354. .npins = ARRAY_SIZE(nm ## _pins), \
  355. }
  356. static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = {
  357. BM1880_PINCTRL_GRP(nand),
  358. BM1880_PINCTRL_GRP(spi),
  359. BM1880_PINCTRL_GRP(emmc),
  360. BM1880_PINCTRL_GRP(sdio),
  361. BM1880_PINCTRL_GRP(eth0),
  362. BM1880_PINCTRL_GRP(pwm0),
  363. BM1880_PINCTRL_GRP(pwm1),
  364. BM1880_PINCTRL_GRP(pwm2),
  365. BM1880_PINCTRL_GRP(pwm3),
  366. BM1880_PINCTRL_GRP(pwm4),
  367. BM1880_PINCTRL_GRP(pwm5),
  368. BM1880_PINCTRL_GRP(pwm6),
  369. BM1880_PINCTRL_GRP(pwm7),
  370. BM1880_PINCTRL_GRP(pwm8),
  371. BM1880_PINCTRL_GRP(pwm9),
  372. BM1880_PINCTRL_GRP(pwm10),
  373. BM1880_PINCTRL_GRP(pwm11),
  374. BM1880_PINCTRL_GRP(pwm12),
  375. BM1880_PINCTRL_GRP(pwm13),
  376. BM1880_PINCTRL_GRP(pwm14),
  377. BM1880_PINCTRL_GRP(pwm15),
  378. BM1880_PINCTRL_GRP(pwm16),
  379. BM1880_PINCTRL_GRP(pwm17),
  380. BM1880_PINCTRL_GRP(pwm18),
  381. BM1880_PINCTRL_GRP(pwm19),
  382. BM1880_PINCTRL_GRP(pwm20),
  383. BM1880_PINCTRL_GRP(pwm21),
  384. BM1880_PINCTRL_GRP(pwm22),
  385. BM1880_PINCTRL_GRP(pwm23),
  386. BM1880_PINCTRL_GRP(pwm24),
  387. BM1880_PINCTRL_GRP(pwm25),
  388. BM1880_PINCTRL_GRP(pwm26),
  389. BM1880_PINCTRL_GRP(pwm27),
  390. BM1880_PINCTRL_GRP(pwm28),
  391. BM1880_PINCTRL_GRP(pwm29),
  392. BM1880_PINCTRL_GRP(pwm30),
  393. BM1880_PINCTRL_GRP(pwm31),
  394. BM1880_PINCTRL_GRP(pwm32),
  395. BM1880_PINCTRL_GRP(pwm33),
  396. BM1880_PINCTRL_GRP(pwm34),
  397. BM1880_PINCTRL_GRP(pwm35),
  398. BM1880_PINCTRL_GRP(pwm36),
  399. BM1880_PINCTRL_GRP(pwm37),
  400. BM1880_PINCTRL_GRP(i2c0),
  401. BM1880_PINCTRL_GRP(i2c1),
  402. BM1880_PINCTRL_GRP(i2c2),
  403. BM1880_PINCTRL_GRP(i2c3),
  404. BM1880_PINCTRL_GRP(i2c4),
  405. BM1880_PINCTRL_GRP(uart0),
  406. BM1880_PINCTRL_GRP(uart1),
  407. BM1880_PINCTRL_GRP(uart2),
  408. BM1880_PINCTRL_GRP(uart3),
  409. BM1880_PINCTRL_GRP(uart4),
  410. BM1880_PINCTRL_GRP(uart5),
  411. BM1880_PINCTRL_GRP(uart6),
  412. BM1880_PINCTRL_GRP(uart7),
  413. BM1880_PINCTRL_GRP(uart8),
  414. BM1880_PINCTRL_GRP(uart9),
  415. BM1880_PINCTRL_GRP(uart10),
  416. BM1880_PINCTRL_GRP(uart11),
  417. BM1880_PINCTRL_GRP(uart12),
  418. BM1880_PINCTRL_GRP(uart13),
  419. BM1880_PINCTRL_GRP(uart14),
  420. BM1880_PINCTRL_GRP(uart15),
  421. BM1880_PINCTRL_GRP(gpio0),
  422. BM1880_PINCTRL_GRP(gpio1),
  423. BM1880_PINCTRL_GRP(gpio2),
  424. BM1880_PINCTRL_GRP(gpio3),
  425. BM1880_PINCTRL_GRP(gpio4),
  426. BM1880_PINCTRL_GRP(gpio5),
  427. BM1880_PINCTRL_GRP(gpio6),
  428. BM1880_PINCTRL_GRP(gpio7),
  429. BM1880_PINCTRL_GRP(gpio8),
  430. BM1880_PINCTRL_GRP(gpio9),
  431. BM1880_PINCTRL_GRP(gpio10),
  432. BM1880_PINCTRL_GRP(gpio11),
  433. BM1880_PINCTRL_GRP(gpio12),
  434. BM1880_PINCTRL_GRP(gpio13),
  435. BM1880_PINCTRL_GRP(gpio14),
  436. BM1880_PINCTRL_GRP(gpio15),
  437. BM1880_PINCTRL_GRP(gpio16),
  438. BM1880_PINCTRL_GRP(gpio17),
  439. BM1880_PINCTRL_GRP(gpio18),
  440. BM1880_PINCTRL_GRP(gpio19),
  441. BM1880_PINCTRL_GRP(gpio20),
  442. BM1880_PINCTRL_GRP(gpio21),
  443. BM1880_PINCTRL_GRP(gpio22),
  444. BM1880_PINCTRL_GRP(gpio23),
  445. BM1880_PINCTRL_GRP(gpio24),
  446. BM1880_PINCTRL_GRP(gpio25),
  447. BM1880_PINCTRL_GRP(gpio26),
  448. BM1880_PINCTRL_GRP(gpio27),
  449. BM1880_PINCTRL_GRP(gpio28),
  450. BM1880_PINCTRL_GRP(gpio29),
  451. BM1880_PINCTRL_GRP(gpio30),
  452. BM1880_PINCTRL_GRP(gpio31),
  453. BM1880_PINCTRL_GRP(gpio32),
  454. BM1880_PINCTRL_GRP(gpio33),
  455. BM1880_PINCTRL_GRP(gpio34),
  456. BM1880_PINCTRL_GRP(gpio35),
  457. BM1880_PINCTRL_GRP(gpio36),
  458. BM1880_PINCTRL_GRP(gpio37),
  459. BM1880_PINCTRL_GRP(gpio38),
  460. BM1880_PINCTRL_GRP(gpio39),
  461. BM1880_PINCTRL_GRP(gpio40),
  462. BM1880_PINCTRL_GRP(gpio41),
  463. BM1880_PINCTRL_GRP(gpio42),
  464. BM1880_PINCTRL_GRP(gpio43),
  465. BM1880_PINCTRL_GRP(gpio44),
  466. BM1880_PINCTRL_GRP(gpio45),
  467. BM1880_PINCTRL_GRP(gpio46),
  468. BM1880_PINCTRL_GRP(gpio47),
  469. BM1880_PINCTRL_GRP(gpio48),
  470. BM1880_PINCTRL_GRP(gpio49),
  471. BM1880_PINCTRL_GRP(gpio50),
  472. BM1880_PINCTRL_GRP(gpio51),
  473. BM1880_PINCTRL_GRP(gpio52),
  474. BM1880_PINCTRL_GRP(gpio53),
  475. BM1880_PINCTRL_GRP(gpio54),
  476. BM1880_PINCTRL_GRP(gpio55),
  477. BM1880_PINCTRL_GRP(gpio56),
  478. BM1880_PINCTRL_GRP(gpio57),
  479. BM1880_PINCTRL_GRP(gpio58),
  480. BM1880_PINCTRL_GRP(gpio59),
  481. BM1880_PINCTRL_GRP(gpio60),
  482. BM1880_PINCTRL_GRP(gpio61),
  483. BM1880_PINCTRL_GRP(gpio62),
  484. BM1880_PINCTRL_GRP(gpio63),
  485. BM1880_PINCTRL_GRP(gpio64),
  486. BM1880_PINCTRL_GRP(gpio65),
  487. BM1880_PINCTRL_GRP(gpio66),
  488. BM1880_PINCTRL_GRP(gpio67),
  489. BM1880_PINCTRL_GRP(eth1),
  490. BM1880_PINCTRL_GRP(i2s0),
  491. BM1880_PINCTRL_GRP(i2s0_mclkin),
  492. BM1880_PINCTRL_GRP(i2s1),
  493. BM1880_PINCTRL_GRP(i2s1_mclkin),
  494. BM1880_PINCTRL_GRP(spi0),
  495. };
  496. static const char * const nand_group[] = { "nand_grp" };
  497. static const char * const spi_group[] = { "spi_grp" };
  498. static const char * const emmc_group[] = { "emmc_grp" };
  499. static const char * const sdio_group[] = { "sdio_grp" };
  500. static const char * const eth0_group[] = { "eth0_grp" };
  501. static const char * const pwm0_group[] = { "pwm0_grp" };
  502. static const char * const pwm1_group[] = { "pwm1_grp" };
  503. static const char * const pwm2_group[] = { "pwm2_grp" };
  504. static const char * const pwm3_group[] = { "pwm3_grp" };
  505. static const char * const pwm4_group[] = { "pwm4_grp" };
  506. static const char * const pwm5_group[] = { "pwm5_grp" };
  507. static const char * const pwm6_group[] = { "pwm6_grp" };
  508. static const char * const pwm7_group[] = { "pwm7_grp" };
  509. static const char * const pwm8_group[] = { "pwm8_grp" };
  510. static const char * const pwm9_group[] = { "pwm9_grp" };
  511. static const char * const pwm10_group[] = { "pwm10_grp" };
  512. static const char * const pwm11_group[] = { "pwm11_grp" };
  513. static const char * const pwm12_group[] = { "pwm12_grp" };
  514. static const char * const pwm13_group[] = { "pwm13_grp" };
  515. static const char * const pwm14_group[] = { "pwm14_grp" };
  516. static const char * const pwm15_group[] = { "pwm15_grp" };
  517. static const char * const pwm16_group[] = { "pwm16_grp" };
  518. static const char * const pwm17_group[] = { "pwm17_grp" };
  519. static const char * const pwm18_group[] = { "pwm18_grp" };
  520. static const char * const pwm19_group[] = { "pwm19_grp" };
  521. static const char * const pwm20_group[] = { "pwm20_grp" };
  522. static const char * const pwm21_group[] = { "pwm21_grp" };
  523. static const char * const pwm22_group[] = { "pwm22_grp" };
  524. static const char * const pwm23_group[] = { "pwm23_grp" };
  525. static const char * const pwm24_group[] = { "pwm24_grp" };
  526. static const char * const pwm25_group[] = { "pwm25_grp" };
  527. static const char * const pwm26_group[] = { "pwm26_grp" };
  528. static const char * const pwm27_group[] = { "pwm27_grp" };
  529. static const char * const pwm28_group[] = { "pwm28_grp" };
  530. static const char * const pwm29_group[] = { "pwm29_grp" };
  531. static const char * const pwm30_group[] = { "pwm30_grp" };
  532. static const char * const pwm31_group[] = { "pwm31_grp" };
  533. static const char * const pwm32_group[] = { "pwm32_grp" };
  534. static const char * const pwm33_group[] = { "pwm33_grp" };
  535. static const char * const pwm34_group[] = { "pwm34_grp" };
  536. static const char * const pwm35_group[] = { "pwm35_grp" };
  537. static const char * const pwm36_group[] = { "pwm36_grp" };
  538. static const char * const pwm37_group[] = { "pwm37_grp" };
  539. static const char * const i2c0_group[] = { "i2c0_grp" };
  540. static const char * const i2c1_group[] = { "i2c1_grp" };
  541. static const char * const i2c2_group[] = { "i2c2_grp" };
  542. static const char * const i2c3_group[] = { "i2c3_grp" };
  543. static const char * const i2c4_group[] = { "i2c4_grp" };
  544. static const char * const uart0_group[] = { "uart0_grp" };
  545. static const char * const uart1_group[] = { "uart1_grp" };
  546. static const char * const uart2_group[] = { "uart2_grp" };
  547. static const char * const uart3_group[] = { "uart3_grp" };
  548. static const char * const uart4_group[] = { "uart4_grp" };
  549. static const char * const uart5_group[] = { "uart5_grp" };
  550. static const char * const uart6_group[] = { "uart6_grp" };
  551. static const char * const uart7_group[] = { "uart7_grp" };
  552. static const char * const uart8_group[] = { "uart8_grp" };
  553. static const char * const uart9_group[] = { "uart9_grp" };
  554. static const char * const uart10_group[] = { "uart10_grp" };
  555. static const char * const uart11_group[] = { "uart11_grp" };
  556. static const char * const uart12_group[] = { "uart12_grp" };
  557. static const char * const uart13_group[] = { "uart13_grp" };
  558. static const char * const uart14_group[] = { "uart14_grp" };
  559. static const char * const uart15_group[] = { "uart15_grp" };
  560. static const char * const gpio0_group[] = { "gpio0_grp" };
  561. static const char * const gpio1_group[] = { "gpio1_grp" };
  562. static const char * const gpio2_group[] = { "gpio2_grp" };
  563. static const char * const gpio3_group[] = { "gpio3_grp" };
  564. static const char * const gpio4_group[] = { "gpio4_grp" };
  565. static const char * const gpio5_group[] = { "gpio5_grp" };
  566. static const char * const gpio6_group[] = { "gpio6_grp" };
  567. static const char * const gpio7_group[] = { "gpio7_grp" };
  568. static const char * const gpio8_group[] = { "gpio8_grp" };
  569. static const char * const gpio9_group[] = { "gpio9_grp" };
  570. static const char * const gpio10_group[] = { "gpio10_grp" };
  571. static const char * const gpio11_group[] = { "gpio11_grp" };
  572. static const char * const gpio12_group[] = { "gpio12_grp" };
  573. static const char * const gpio13_group[] = { "gpio13_grp" };
  574. static const char * const gpio14_group[] = { "gpio14_grp" };
  575. static const char * const gpio15_group[] = { "gpio15_grp" };
  576. static const char * const gpio16_group[] = { "gpio16_grp" };
  577. static const char * const gpio17_group[] = { "gpio17_grp" };
  578. static const char * const gpio18_group[] = { "gpio18_grp" };
  579. static const char * const gpio19_group[] = { "gpio19_grp" };
  580. static const char * const gpio20_group[] = { "gpio20_grp" };
  581. static const char * const gpio21_group[] = { "gpio21_grp" };
  582. static const char * const gpio22_group[] = { "gpio22_grp" };
  583. static const char * const gpio23_group[] = { "gpio23_grp" };
  584. static const char * const gpio24_group[] = { "gpio24_grp" };
  585. static const char * const gpio25_group[] = { "gpio25_grp" };
  586. static const char * const gpio26_group[] = { "gpio26_grp" };
  587. static const char * const gpio27_group[] = { "gpio27_grp" };
  588. static const char * const gpio28_group[] = { "gpio28_grp" };
  589. static const char * const gpio29_group[] = { "gpio29_grp" };
  590. static const char * const gpio30_group[] = { "gpio30_grp" };
  591. static const char * const gpio31_group[] = { "gpio31_grp" };
  592. static const char * const gpio32_group[] = { "gpio32_grp" };
  593. static const char * const gpio33_group[] = { "gpio33_grp" };
  594. static const char * const gpio34_group[] = { "gpio34_grp" };
  595. static const char * const gpio35_group[] = { "gpio35_grp" };
  596. static const char * const gpio36_group[] = { "gpio36_grp" };
  597. static const char * const gpio37_group[] = { "gpio37_grp" };
  598. static const char * const gpio38_group[] = { "gpio38_grp" };
  599. static const char * const gpio39_group[] = { "gpio39_grp" };
  600. static const char * const gpio40_group[] = { "gpio40_grp" };
  601. static const char * const gpio41_group[] = { "gpio41_grp" };
  602. static const char * const gpio42_group[] = { "gpio42_grp" };
  603. static const char * const gpio43_group[] = { "gpio43_grp" };
  604. static const char * const gpio44_group[] = { "gpio44_grp" };
  605. static const char * const gpio45_group[] = { "gpio45_grp" };
  606. static const char * const gpio46_group[] = { "gpio46_grp" };
  607. static const char * const gpio47_group[] = { "gpio47_grp" };
  608. static const char * const gpio48_group[] = { "gpio48_grp" };
  609. static const char * const gpio49_group[] = { "gpio49_grp" };
  610. static const char * const gpio50_group[] = { "gpio50_grp" };
  611. static const char * const gpio51_group[] = { "gpio51_grp" };
  612. static const char * const gpio52_group[] = { "gpio52_grp" };
  613. static const char * const gpio53_group[] = { "gpio53_grp" };
  614. static const char * const gpio54_group[] = { "gpio54_grp" };
  615. static const char * const gpio55_group[] = { "gpio55_grp" };
  616. static const char * const gpio56_group[] = { "gpio56_grp" };
  617. static const char * const gpio57_group[] = { "gpio57_grp" };
  618. static const char * const gpio58_group[] = { "gpio58_grp" };
  619. static const char * const gpio59_group[] = { "gpio59_grp" };
  620. static const char * const gpio60_group[] = { "gpio60_grp" };
  621. static const char * const gpio61_group[] = { "gpio61_grp" };
  622. static const char * const gpio62_group[] = { "gpio62_grp" };
  623. static const char * const gpio63_group[] = { "gpio63_grp" };
  624. static const char * const gpio64_group[] = { "gpio64_grp" };
  625. static const char * const gpio65_group[] = { "gpio65_grp" };
  626. static const char * const gpio66_group[] = { "gpio66_grp" };
  627. static const char * const gpio67_group[] = { "gpio67_grp" };
  628. static const char * const eth1_group[] = { "eth1_grp" };
  629. static const char * const i2s0_group[] = { "i2s0_grp" };
  630. static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" };
  631. static const char * const i2s1_group[] = { "i2s1_grp" };
  632. static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" };
  633. static const char * const spi0_group[] = { "spi0_grp" };
  634. #define BM1880_PINMUX_FUNCTION(fname, mval) \
  635. [F_##fname] = { \
  636. .name = #fname, \
  637. .groups = fname##_group, \
  638. .ngroups = ARRAY_SIZE(fname##_group), \
  639. .mux_val = mval, \
  640. }
  641. static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
  642. BM1880_PINMUX_FUNCTION(nand, 2),
  643. BM1880_PINMUX_FUNCTION(spi, 0),
  644. BM1880_PINMUX_FUNCTION(emmc, 1),
  645. BM1880_PINMUX_FUNCTION(sdio, 0),
  646. BM1880_PINMUX_FUNCTION(eth0, 0),
  647. BM1880_PINMUX_FUNCTION(pwm0, 2),
  648. BM1880_PINMUX_FUNCTION(pwm1, 2),
  649. BM1880_PINMUX_FUNCTION(pwm2, 2),
  650. BM1880_PINMUX_FUNCTION(pwm3, 2),
  651. BM1880_PINMUX_FUNCTION(pwm4, 2),
  652. BM1880_PINMUX_FUNCTION(pwm5, 2),
  653. BM1880_PINMUX_FUNCTION(pwm6, 2),
  654. BM1880_PINMUX_FUNCTION(pwm7, 2),
  655. BM1880_PINMUX_FUNCTION(pwm8, 2),
  656. BM1880_PINMUX_FUNCTION(pwm9, 2),
  657. BM1880_PINMUX_FUNCTION(pwm10, 2),
  658. BM1880_PINMUX_FUNCTION(pwm11, 2),
  659. BM1880_PINMUX_FUNCTION(pwm12, 2),
  660. BM1880_PINMUX_FUNCTION(pwm13, 2),
  661. BM1880_PINMUX_FUNCTION(pwm14, 2),
  662. BM1880_PINMUX_FUNCTION(pwm15, 2),
  663. BM1880_PINMUX_FUNCTION(pwm16, 2),
  664. BM1880_PINMUX_FUNCTION(pwm17, 2),
  665. BM1880_PINMUX_FUNCTION(pwm18, 2),
  666. BM1880_PINMUX_FUNCTION(pwm19, 2),
  667. BM1880_PINMUX_FUNCTION(pwm20, 2),
  668. BM1880_PINMUX_FUNCTION(pwm21, 2),
  669. BM1880_PINMUX_FUNCTION(pwm22, 2),
  670. BM1880_PINMUX_FUNCTION(pwm23, 2),
  671. BM1880_PINMUX_FUNCTION(pwm24, 2),
  672. BM1880_PINMUX_FUNCTION(pwm25, 2),
  673. BM1880_PINMUX_FUNCTION(pwm26, 2),
  674. BM1880_PINMUX_FUNCTION(pwm27, 2),
  675. BM1880_PINMUX_FUNCTION(pwm28, 2),
  676. BM1880_PINMUX_FUNCTION(pwm29, 2),
  677. BM1880_PINMUX_FUNCTION(pwm30, 2),
  678. BM1880_PINMUX_FUNCTION(pwm31, 2),
  679. BM1880_PINMUX_FUNCTION(pwm32, 2),
  680. BM1880_PINMUX_FUNCTION(pwm33, 2),
  681. BM1880_PINMUX_FUNCTION(pwm34, 2),
  682. BM1880_PINMUX_FUNCTION(pwm35, 2),
  683. BM1880_PINMUX_FUNCTION(pwm36, 2),
  684. BM1880_PINMUX_FUNCTION(pwm37, 2),
  685. BM1880_PINMUX_FUNCTION(i2c0, 1),
  686. BM1880_PINMUX_FUNCTION(i2c1, 1),
  687. BM1880_PINMUX_FUNCTION(i2c2, 1),
  688. BM1880_PINMUX_FUNCTION(i2c3, 1),
  689. BM1880_PINMUX_FUNCTION(i2c4, 1),
  690. BM1880_PINMUX_FUNCTION(uart0, 3),
  691. BM1880_PINMUX_FUNCTION(uart1, 3),
  692. BM1880_PINMUX_FUNCTION(uart2, 3),
  693. BM1880_PINMUX_FUNCTION(uart3, 3),
  694. BM1880_PINMUX_FUNCTION(uart4, 1),
  695. BM1880_PINMUX_FUNCTION(uart5, 1),
  696. BM1880_PINMUX_FUNCTION(uart6, 1),
  697. BM1880_PINMUX_FUNCTION(uart7, 1),
  698. BM1880_PINMUX_FUNCTION(uart8, 1),
  699. BM1880_PINMUX_FUNCTION(uart9, 1),
  700. BM1880_PINMUX_FUNCTION(uart10, 1),
  701. BM1880_PINMUX_FUNCTION(uart11, 1),
  702. BM1880_PINMUX_FUNCTION(uart12, 3),
  703. BM1880_PINMUX_FUNCTION(uart13, 3),
  704. BM1880_PINMUX_FUNCTION(uart14, 3),
  705. BM1880_PINMUX_FUNCTION(uart15, 3),
  706. BM1880_PINMUX_FUNCTION(gpio0, 0),
  707. BM1880_PINMUX_FUNCTION(gpio1, 0),
  708. BM1880_PINMUX_FUNCTION(gpio2, 0),
  709. BM1880_PINMUX_FUNCTION(gpio3, 0),
  710. BM1880_PINMUX_FUNCTION(gpio4, 0),
  711. BM1880_PINMUX_FUNCTION(gpio5, 0),
  712. BM1880_PINMUX_FUNCTION(gpio6, 0),
  713. BM1880_PINMUX_FUNCTION(gpio7, 0),
  714. BM1880_PINMUX_FUNCTION(gpio8, 0),
  715. BM1880_PINMUX_FUNCTION(gpio9, 0),
  716. BM1880_PINMUX_FUNCTION(gpio10, 0),
  717. BM1880_PINMUX_FUNCTION(gpio11, 0),
  718. BM1880_PINMUX_FUNCTION(gpio12, 1),
  719. BM1880_PINMUX_FUNCTION(gpio13, 1),
  720. BM1880_PINMUX_FUNCTION(gpio14, 0),
  721. BM1880_PINMUX_FUNCTION(gpio15, 0),
  722. BM1880_PINMUX_FUNCTION(gpio16, 0),
  723. BM1880_PINMUX_FUNCTION(gpio17, 0),
  724. BM1880_PINMUX_FUNCTION(gpio18, 0),
  725. BM1880_PINMUX_FUNCTION(gpio19, 0),
  726. BM1880_PINMUX_FUNCTION(gpio20, 0),
  727. BM1880_PINMUX_FUNCTION(gpio21, 0),
  728. BM1880_PINMUX_FUNCTION(gpio22, 0),
  729. BM1880_PINMUX_FUNCTION(gpio23, 0),
  730. BM1880_PINMUX_FUNCTION(gpio24, 0),
  731. BM1880_PINMUX_FUNCTION(gpio25, 0),
  732. BM1880_PINMUX_FUNCTION(gpio26, 0),
  733. BM1880_PINMUX_FUNCTION(gpio27, 0),
  734. BM1880_PINMUX_FUNCTION(gpio28, 0),
  735. BM1880_PINMUX_FUNCTION(gpio29, 0),
  736. BM1880_PINMUX_FUNCTION(gpio30, 0),
  737. BM1880_PINMUX_FUNCTION(gpio31, 0),
  738. BM1880_PINMUX_FUNCTION(gpio32, 0),
  739. BM1880_PINMUX_FUNCTION(gpio33, 0),
  740. BM1880_PINMUX_FUNCTION(gpio34, 0),
  741. BM1880_PINMUX_FUNCTION(gpio35, 0),
  742. BM1880_PINMUX_FUNCTION(gpio36, 0),
  743. BM1880_PINMUX_FUNCTION(gpio37, 0),
  744. BM1880_PINMUX_FUNCTION(gpio38, 0),
  745. BM1880_PINMUX_FUNCTION(gpio39, 0),
  746. BM1880_PINMUX_FUNCTION(gpio40, 0),
  747. BM1880_PINMUX_FUNCTION(gpio41, 0),
  748. BM1880_PINMUX_FUNCTION(gpio42, 0),
  749. BM1880_PINMUX_FUNCTION(gpio43, 0),
  750. BM1880_PINMUX_FUNCTION(gpio44, 0),
  751. BM1880_PINMUX_FUNCTION(gpio45, 0),
  752. BM1880_PINMUX_FUNCTION(gpio46, 0),
  753. BM1880_PINMUX_FUNCTION(gpio47, 0),
  754. BM1880_PINMUX_FUNCTION(gpio48, 0),
  755. BM1880_PINMUX_FUNCTION(gpio49, 0),
  756. BM1880_PINMUX_FUNCTION(gpio50, 0),
  757. BM1880_PINMUX_FUNCTION(gpio51, 0),
  758. BM1880_PINMUX_FUNCTION(gpio52, 0),
  759. BM1880_PINMUX_FUNCTION(gpio53, 0),
  760. BM1880_PINMUX_FUNCTION(gpio54, 0),
  761. BM1880_PINMUX_FUNCTION(gpio55, 0),
  762. BM1880_PINMUX_FUNCTION(gpio56, 0),
  763. BM1880_PINMUX_FUNCTION(gpio57, 0),
  764. BM1880_PINMUX_FUNCTION(gpio58, 0),
  765. BM1880_PINMUX_FUNCTION(gpio59, 0),
  766. BM1880_PINMUX_FUNCTION(gpio60, 0),
  767. BM1880_PINMUX_FUNCTION(gpio61, 0),
  768. BM1880_PINMUX_FUNCTION(gpio62, 0),
  769. BM1880_PINMUX_FUNCTION(gpio63, 0),
  770. BM1880_PINMUX_FUNCTION(gpio64, 0),
  771. BM1880_PINMUX_FUNCTION(gpio65, 0),
  772. BM1880_PINMUX_FUNCTION(gpio66, 0),
  773. BM1880_PINMUX_FUNCTION(gpio67, 0),
  774. BM1880_PINMUX_FUNCTION(eth1, 1),
  775. BM1880_PINMUX_FUNCTION(i2s0, 2),
  776. BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1),
  777. BM1880_PINMUX_FUNCTION(i2s1, 2),
  778. BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1),
  779. BM1880_PINMUX_FUNCTION(spi0, 1),
  780. };
  781. #define BM1880_PINCONF_DAT(_width) \
  782. { \
  783. .drv_bits = _width, \
  784. }
  785. static const struct bm1880_pinconf_data bm1880_pinconf[] = {
  786. BM1880_PINCONF_DAT(0x03),
  787. BM1880_PINCONF_DAT(0x03),
  788. BM1880_PINCONF_DAT(0x03),
  789. BM1880_PINCONF_DAT(0x03),
  790. BM1880_PINCONF_DAT(0x03),
  791. BM1880_PINCONF_DAT(0x03),
  792. BM1880_PINCONF_DAT(0x03),
  793. BM1880_PINCONF_DAT(0x03),
  794. BM1880_PINCONF_DAT(0x03),
  795. BM1880_PINCONF_DAT(0x03),
  796. BM1880_PINCONF_DAT(0x03),
  797. BM1880_PINCONF_DAT(0x03),
  798. BM1880_PINCONF_DAT(0x03),
  799. BM1880_PINCONF_DAT(0x03),
  800. BM1880_PINCONF_DAT(0x03),
  801. BM1880_PINCONF_DAT(0x03),
  802. BM1880_PINCONF_DAT(0x03),
  803. BM1880_PINCONF_DAT(0x03),
  804. BM1880_PINCONF_DAT(0x03),
  805. BM1880_PINCONF_DAT(0x03),
  806. BM1880_PINCONF_DAT(0x03),
  807. BM1880_PINCONF_DAT(0x03),
  808. BM1880_PINCONF_DAT(0x03),
  809. BM1880_PINCONF_DAT(0x03),
  810. BM1880_PINCONF_DAT(0x03),
  811. BM1880_PINCONF_DAT(0x03),
  812. BM1880_PINCONF_DAT(0x03),
  813. BM1880_PINCONF_DAT(0x03),
  814. BM1880_PINCONF_DAT(0x03),
  815. BM1880_PINCONF_DAT(0x03),
  816. BM1880_PINCONF_DAT(0x03),
  817. BM1880_PINCONF_DAT(0x03),
  818. BM1880_PINCONF_DAT(0x03),
  819. BM1880_PINCONF_DAT(0x03),
  820. BM1880_PINCONF_DAT(0x03),
  821. BM1880_PINCONF_DAT(0x03),
  822. BM1880_PINCONF_DAT(0x03),
  823. BM1880_PINCONF_DAT(0x03),
  824. BM1880_PINCONF_DAT(0x03),
  825. BM1880_PINCONF_DAT(0x03),
  826. BM1880_PINCONF_DAT(0x03),
  827. BM1880_PINCONF_DAT(0x03),
  828. BM1880_PINCONF_DAT(0x03),
  829. BM1880_PINCONF_DAT(0x03),
  830. BM1880_PINCONF_DAT(0x03),
  831. BM1880_PINCONF_DAT(0x03),
  832. BM1880_PINCONF_DAT(0x03),
  833. BM1880_PINCONF_DAT(0x03),
  834. BM1880_PINCONF_DAT(0x03),
  835. BM1880_PINCONF_DAT(0x03),
  836. BM1880_PINCONF_DAT(0x03),
  837. BM1880_PINCONF_DAT(0x03),
  838. BM1880_PINCONF_DAT(0x03),
  839. BM1880_PINCONF_DAT(0x03),
  840. BM1880_PINCONF_DAT(0x03),
  841. BM1880_PINCONF_DAT(0x03),
  842. BM1880_PINCONF_DAT(0x03),
  843. BM1880_PINCONF_DAT(0x03),
  844. BM1880_PINCONF_DAT(0x03),
  845. BM1880_PINCONF_DAT(0x03),
  846. BM1880_PINCONF_DAT(0x02),
  847. BM1880_PINCONF_DAT(0x02),
  848. BM1880_PINCONF_DAT(0x02),
  849. BM1880_PINCONF_DAT(0x02),
  850. BM1880_PINCONF_DAT(0x02),
  851. BM1880_PINCONF_DAT(0x02),
  852. BM1880_PINCONF_DAT(0x02),
  853. BM1880_PINCONF_DAT(0x02),
  854. BM1880_PINCONF_DAT(0x02),
  855. BM1880_PINCONF_DAT(0x02),
  856. BM1880_PINCONF_DAT(0x02),
  857. BM1880_PINCONF_DAT(0x02),
  858. BM1880_PINCONF_DAT(0x02),
  859. BM1880_PINCONF_DAT(0x02),
  860. BM1880_PINCONF_DAT(0x02),
  861. BM1880_PINCONF_DAT(0x02),
  862. BM1880_PINCONF_DAT(0x02),
  863. BM1880_PINCONF_DAT(0x02),
  864. BM1880_PINCONF_DAT(0x02),
  865. BM1880_PINCONF_DAT(0x02),
  866. BM1880_PINCONF_DAT(0x02),
  867. BM1880_PINCONF_DAT(0x02),
  868. BM1880_PINCONF_DAT(0x02),
  869. BM1880_PINCONF_DAT(0x02),
  870. BM1880_PINCONF_DAT(0x02),
  871. BM1880_PINCONF_DAT(0x02),
  872. BM1880_PINCONF_DAT(0x02),
  873. BM1880_PINCONF_DAT(0x02),
  874. BM1880_PINCONF_DAT(0x02),
  875. BM1880_PINCONF_DAT(0x02),
  876. BM1880_PINCONF_DAT(0x02),
  877. BM1880_PINCONF_DAT(0x02),
  878. BM1880_PINCONF_DAT(0x02),
  879. BM1880_PINCONF_DAT(0x02),
  880. BM1880_PINCONF_DAT(0x02),
  881. BM1880_PINCONF_DAT(0x02),
  882. BM1880_PINCONF_DAT(0x02),
  883. BM1880_PINCONF_DAT(0x02),
  884. BM1880_PINCONF_DAT(0x02),
  885. BM1880_PINCONF_DAT(0x02),
  886. BM1880_PINCONF_DAT(0x02),
  887. BM1880_PINCONF_DAT(0x02),
  888. BM1880_PINCONF_DAT(0x02),
  889. BM1880_PINCONF_DAT(0x02),
  890. BM1880_PINCONF_DAT(0x02),
  891. BM1880_PINCONF_DAT(0x02),
  892. BM1880_PINCONF_DAT(0x02),
  893. BM1880_PINCONF_DAT(0x02),
  894. BM1880_PINCONF_DAT(0x02),
  895. BM1880_PINCONF_DAT(0x02),
  896. BM1880_PINCONF_DAT(0x02),
  897. BM1880_PINCONF_DAT(0x02),
  898. };
  899. static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
  900. {
  901. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  902. return pctrl->ngroups;
  903. }
  904. static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev,
  905. unsigned int selector)
  906. {
  907. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  908. return pctrl->groups[selector].name;
  909. }
  910. static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
  911. unsigned int selector,
  912. const unsigned int **pins,
  913. unsigned int *num_pins)
  914. {
  915. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  916. *pins = pctrl->groups[selector].pins;
  917. *num_pins = pctrl->groups[selector].npins;
  918. return 0;
  919. }
  920. static const struct pinctrl_ops bm1880_pctrl_ops = {
  921. .get_groups_count = bm1880_pctrl_get_groups_count,
  922. .get_group_name = bm1880_pctrl_get_group_name,
  923. .get_group_pins = bm1880_pctrl_get_group_pins,
  924. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  925. .dt_free_map = pinctrl_utils_free_map,
  926. };
  927. /* pinmux */
  928. static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev)
  929. {
  930. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  931. return pctrl->nfuncs;
  932. }
  933. static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev,
  934. unsigned int selector)
  935. {
  936. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  937. return pctrl->funcs[selector].name;
  938. }
  939. static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev,
  940. unsigned int selector,
  941. const char * const **groups,
  942. unsigned * const num_groups)
  943. {
  944. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  945. *groups = pctrl->funcs[selector].groups;
  946. *num_groups = pctrl->funcs[selector].ngroups;
  947. return 0;
  948. }
  949. static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev,
  950. unsigned int function,
  951. unsigned int group)
  952. {
  953. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  954. const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group];
  955. const struct bm1880_pinmux_function *func = &pctrl->funcs[function];
  956. int i;
  957. for (i = 0; i < pgrp->npins; i++) {
  958. unsigned int pin = pgrp->pins[i];
  959. u32 offset = (pin >> 1) << 2;
  960. u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
  961. u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +
  962. offset);
  963. regval &= ~(0x03 << mux_offset);
  964. regval |= func->mux_val << mux_offset;
  965. writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
  966. }
  967. return 0;
  968. }
  969. #define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx)
  970. #define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0)
  971. #define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1)
  972. #define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2)
  973. #define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6)
  974. #define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9)
  975. #define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10)
  976. static int bm1880_pinconf_drv_set(unsigned int mA, u32 width,
  977. u32 *regval, u32 bit_offset)
  978. {
  979. u32 _regval;
  980. _regval = *regval;
  981. /*
  982. * There are two sets of drive strength bit width exposed by the
  983. * SoC at 4mA step, hence we need to handle them separately.
  984. */
  985. if (width == 0x03) {
  986. switch (mA) {
  987. case 4:
  988. _regval &= ~(width << bit_offset);
  989. _regval |= (0 << bit_offset);
  990. break;
  991. case 8:
  992. _regval &= ~(width << bit_offset);
  993. _regval |= (1 << bit_offset);
  994. break;
  995. case 12:
  996. _regval &= ~(width << bit_offset);
  997. _regval |= (2 << bit_offset);
  998. break;
  999. case 16:
  1000. _regval &= ~(width << bit_offset);
  1001. _regval |= (3 << bit_offset);
  1002. break;
  1003. case 20:
  1004. _regval &= ~(width << bit_offset);
  1005. _regval |= (4 << bit_offset);
  1006. break;
  1007. case 24:
  1008. _regval &= ~(width << bit_offset);
  1009. _regval |= (5 << bit_offset);
  1010. break;
  1011. case 28:
  1012. _regval &= ~(width << bit_offset);
  1013. _regval |= (6 << bit_offset);
  1014. break;
  1015. case 32:
  1016. _regval &= ~(width << bit_offset);
  1017. _regval |= (7 << bit_offset);
  1018. break;
  1019. default:
  1020. return -EINVAL;
  1021. }
  1022. } else {
  1023. switch (mA) {
  1024. case 4:
  1025. _regval &= ~(width << bit_offset);
  1026. _regval |= (0 << bit_offset);
  1027. break;
  1028. case 8:
  1029. _regval &= ~(width << bit_offset);
  1030. _regval |= (1 << bit_offset);
  1031. break;
  1032. case 12:
  1033. _regval &= ~(width << bit_offset);
  1034. _regval |= (2 << bit_offset);
  1035. break;
  1036. case 16:
  1037. _regval &= ~(width << bit_offset);
  1038. _regval |= (3 << bit_offset);
  1039. break;
  1040. default:
  1041. return -EINVAL;
  1042. }
  1043. }
  1044. *regval = _regval;
  1045. return 0;
  1046. }
  1047. static int bm1880_pinconf_drv_get(u32 width, u32 drv)
  1048. {
  1049. int ret = -ENOTSUPP;
  1050. /*
  1051. * There are two sets of drive strength bit width exposed by the
  1052. * SoC at 4mA step, hence we need to handle them separately.
  1053. */
  1054. if (width == 0x03) {
  1055. switch (drv) {
  1056. case 0:
  1057. ret = 4;
  1058. break;
  1059. case 1:
  1060. ret = 8;
  1061. break;
  1062. case 2:
  1063. ret = 12;
  1064. break;
  1065. case 3:
  1066. ret = 16;
  1067. break;
  1068. case 4:
  1069. ret = 20;
  1070. break;
  1071. case 5:
  1072. ret = 24;
  1073. break;
  1074. case 6:
  1075. ret = 28;
  1076. break;
  1077. case 7:
  1078. ret = 32;
  1079. break;
  1080. default:
  1081. break;
  1082. }
  1083. } else {
  1084. switch (drv) {
  1085. case 0:
  1086. ret = 4;
  1087. break;
  1088. case 1:
  1089. ret = 8;
  1090. break;
  1091. case 2:
  1092. ret = 12;
  1093. break;
  1094. case 3:
  1095. ret = 16;
  1096. break;
  1097. default:
  1098. break;
  1099. }
  1100. }
  1101. return ret;
  1102. }
  1103. static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
  1104. unsigned int pin,
  1105. unsigned long *config)
  1106. {
  1107. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  1108. unsigned int param = pinconf_to_config_param(*config);
  1109. unsigned int arg = 0;
  1110. u32 regval, offset, bit_offset;
  1111. int ret;
  1112. offset = (pin >> 1) << 2;
  1113. regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
  1114. switch (param) {
  1115. case PIN_CONFIG_BIAS_PULL_UP:
  1116. bit_offset = BM1880_PINCONF_PULLUP(pin);
  1117. arg = !!(regval & BIT(bit_offset));
  1118. break;
  1119. case PIN_CONFIG_BIAS_PULL_DOWN:
  1120. bit_offset = BM1880_PINCONF_PULLDOWN(pin);
  1121. arg = !!(regval & BIT(bit_offset));
  1122. break;
  1123. case PIN_CONFIG_BIAS_DISABLE:
  1124. bit_offset = BM1880_PINCONF_PULLCTRL(pin);
  1125. arg = !!(regval & BIT(bit_offset));
  1126. break;
  1127. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  1128. bit_offset = BM1880_PINCONF_SCHMITT(pin);
  1129. arg = !!(regval & BIT(bit_offset));
  1130. break;
  1131. case PIN_CONFIG_SLEW_RATE:
  1132. bit_offset = BM1880_PINCONF_SLEW(pin);
  1133. arg = !!(regval & BIT(bit_offset));
  1134. break;
  1135. case PIN_CONFIG_DRIVE_STRENGTH:
  1136. bit_offset = BM1880_PINCONF_DRV(pin);
  1137. ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits,
  1138. !!(regval & BIT(bit_offset)));
  1139. if (ret < 0)
  1140. return ret;
  1141. arg = ret;
  1142. break;
  1143. default:
  1144. return -ENOTSUPP;
  1145. }
  1146. *config = pinconf_to_config_packed(param, arg);
  1147. return 0;
  1148. }
  1149. static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev,
  1150. unsigned int pin,
  1151. unsigned long *configs,
  1152. unsigned int num_configs)
  1153. {
  1154. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  1155. u32 regval, offset, bit_offset;
  1156. int i, ret;
  1157. offset = (pin >> 1) << 2;
  1158. regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
  1159. for (i = 0; i < num_configs; i++) {
  1160. unsigned int param = pinconf_to_config_param(configs[i]);
  1161. unsigned int arg = pinconf_to_config_argument(configs[i]);
  1162. switch (param) {
  1163. case PIN_CONFIG_BIAS_PULL_UP:
  1164. bit_offset = BM1880_PINCONF_PULLUP(pin);
  1165. regval |= BIT(bit_offset);
  1166. break;
  1167. case PIN_CONFIG_BIAS_PULL_DOWN:
  1168. bit_offset = BM1880_PINCONF_PULLDOWN(pin);
  1169. regval |= BIT(bit_offset);
  1170. break;
  1171. case PIN_CONFIG_BIAS_DISABLE:
  1172. bit_offset = BM1880_PINCONF_PULLCTRL(pin);
  1173. regval |= BIT(bit_offset);
  1174. break;
  1175. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  1176. bit_offset = BM1880_PINCONF_SCHMITT(pin);
  1177. if (arg)
  1178. regval |= BIT(bit_offset);
  1179. else
  1180. regval &= ~BIT(bit_offset);
  1181. break;
  1182. case PIN_CONFIG_SLEW_RATE:
  1183. bit_offset = BM1880_PINCONF_SLEW(pin);
  1184. if (arg)
  1185. regval |= BIT(bit_offset);
  1186. else
  1187. regval &= ~BIT(bit_offset);
  1188. break;
  1189. case PIN_CONFIG_DRIVE_STRENGTH:
  1190. bit_offset = BM1880_PINCONF_DRV(pin);
  1191. ret = bm1880_pinconf_drv_set(arg,
  1192. pctrl->pinconf[pin].drv_bits,
  1193. &regval, bit_offset);
  1194. if (ret < 0)
  1195. return ret;
  1196. break;
  1197. default:
  1198. dev_warn(pctldev->dev,
  1199. "unsupported configuration parameter '%u'\n",
  1200. param);
  1201. continue;
  1202. }
  1203. writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
  1204. }
  1205. return 0;
  1206. }
  1207. static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev,
  1208. unsigned int selector,
  1209. unsigned long *configs,
  1210. unsigned int num_configs)
  1211. {
  1212. int i, ret;
  1213. struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  1214. const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector];
  1215. for (i = 0; i < pgrp->npins; i++) {
  1216. ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
  1217. num_configs);
  1218. if (ret)
  1219. return ret;
  1220. }
  1221. return 0;
  1222. }
  1223. static const struct pinconf_ops bm1880_pinconf_ops = {
  1224. .is_generic = true,
  1225. .pin_config_get = bm1880_pinconf_cfg_get,
  1226. .pin_config_set = bm1880_pinconf_cfg_set,
  1227. .pin_config_group_set = bm1880_pinconf_group_set,
  1228. };
  1229. static const struct pinmux_ops bm1880_pinmux_ops = {
  1230. .get_functions_count = bm1880_pmux_get_functions_count,
  1231. .get_function_name = bm1880_pmux_get_function_name,
  1232. .get_function_groups = bm1880_pmux_get_function_groups,
  1233. .set_mux = bm1880_pinmux_set_mux,
  1234. };
  1235. static struct pinctrl_desc bm1880_desc = {
  1236. .name = "bm1880_pinctrl",
  1237. .pins = bm1880_pins,
  1238. .npins = ARRAY_SIZE(bm1880_pins),
  1239. .pctlops = &bm1880_pctrl_ops,
  1240. .pmxops = &bm1880_pinmux_ops,
  1241. .confops = &bm1880_pinconf_ops,
  1242. .owner = THIS_MODULE,
  1243. };
  1244. static int bm1880_pinctrl_probe(struct platform_device *pdev)
  1245. {
  1246. struct bm1880_pinctrl *pctrl;
  1247. pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
  1248. if (!pctrl)
  1249. return -ENOMEM;
  1250. pctrl->base = devm_platform_ioremap_resource(pdev, 0);
  1251. if (IS_ERR(pctrl->base))
  1252. return PTR_ERR(pctrl->base);
  1253. pctrl->groups = bm1880_pctrl_groups;
  1254. pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
  1255. pctrl->funcs = bm1880_pmux_functions;
  1256. pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
  1257. pctrl->pinconf = bm1880_pinconf;
  1258. pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
  1259. pctrl);
  1260. if (IS_ERR(pctrl->pctrldev))
  1261. return PTR_ERR(pctrl->pctrldev);
  1262. platform_set_drvdata(pdev, pctrl);
  1263. dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n");
  1264. return 0;
  1265. }
  1266. static const struct of_device_id bm1880_pinctrl_of_match[] = {
  1267. { .compatible = "bitmain,bm1880-pinctrl" },
  1268. { }
  1269. };
  1270. static struct platform_driver bm1880_pinctrl_driver = {
  1271. .driver = {
  1272. .name = "pinctrl-bm1880",
  1273. .of_match_table = of_match_ptr(bm1880_pinctrl_of_match),
  1274. },
  1275. .probe = bm1880_pinctrl_probe,
  1276. };
  1277. static int __init bm1880_pinctrl_init(void)
  1278. {
  1279. return platform_driver_register(&bm1880_pinctrl_driver);
  1280. }
  1281. arch_initcall(bm1880_pinctrl_init);