pinctrl-axp209.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * AXP20x pinctrl and GPIO driver
  4. *
  5. * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
  6. * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/device.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/mfd/axp20x.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/pinctrl/pinconf-generic.h>
  19. #include <linux/pinctrl/pinctrl.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regmap.h>
  23. #include <linux/slab.h>
  24. #define AXP20X_GPIO_FUNCTIONS 0x7
  25. #define AXP20X_GPIO_FUNCTION_OUT_LOW 0
  26. #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
  27. #define AXP20X_GPIO_FUNCTION_INPUT 2
  28. #define AXP20X_FUNC_GPIO_OUT 0
  29. #define AXP20X_FUNC_GPIO_IN 1
  30. #define AXP20X_FUNC_LDO 2
  31. #define AXP20X_FUNC_ADC 3
  32. #define AXP20X_FUNCS_NB 4
  33. #define AXP20X_MUX_GPIO_OUT 0
  34. #define AXP20X_MUX_GPIO_IN BIT(1)
  35. #define AXP20X_MUX_ADC BIT(2)
  36. #define AXP813_MUX_ADC (BIT(2) | BIT(0))
  37. struct axp20x_pctrl_desc {
  38. const struct pinctrl_pin_desc *pins;
  39. unsigned int npins;
  40. /* Stores the pins supporting LDO function. Bit offset is pin number. */
  41. u8 ldo_mask;
  42. /* Stores the pins supporting ADC function. Bit offset is pin number. */
  43. u8 adc_mask;
  44. u8 gpio_status_offset;
  45. u8 adc_mux;
  46. };
  47. struct axp20x_pinctrl_function {
  48. const char *name;
  49. unsigned int muxval;
  50. const char **groups;
  51. unsigned int ngroups;
  52. };
  53. struct axp20x_pctl {
  54. struct gpio_chip chip;
  55. struct regmap *regmap;
  56. struct pinctrl_dev *pctl_dev;
  57. struct device *dev;
  58. const struct axp20x_pctrl_desc *desc;
  59. struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
  60. };
  61. static const struct pinctrl_pin_desc axp209_pins[] = {
  62. PINCTRL_PIN(0, "GPIO0"),
  63. PINCTRL_PIN(1, "GPIO1"),
  64. PINCTRL_PIN(2, "GPIO2"),
  65. };
  66. static const struct pinctrl_pin_desc axp813_pins[] = {
  67. PINCTRL_PIN(0, "GPIO0"),
  68. PINCTRL_PIN(1, "GPIO1"),
  69. };
  70. static const struct axp20x_pctrl_desc axp20x_data = {
  71. .pins = axp209_pins,
  72. .npins = ARRAY_SIZE(axp209_pins),
  73. .ldo_mask = BIT(0) | BIT(1),
  74. .adc_mask = BIT(0) | BIT(1),
  75. .gpio_status_offset = 4,
  76. .adc_mux = AXP20X_MUX_ADC,
  77. };
  78. static const struct axp20x_pctrl_desc axp813_data = {
  79. .pins = axp813_pins,
  80. .npins = ARRAY_SIZE(axp813_pins),
  81. .ldo_mask = BIT(0) | BIT(1),
  82. .adc_mask = BIT(0),
  83. .gpio_status_offset = 0,
  84. .adc_mux = AXP813_MUX_ADC,
  85. };
  86. static int axp20x_gpio_get_reg(unsigned int offset)
  87. {
  88. switch (offset) {
  89. case 0:
  90. return AXP20X_GPIO0_CTRL;
  91. case 1:
  92. return AXP20X_GPIO1_CTRL;
  93. case 2:
  94. return AXP20X_GPIO2_CTRL;
  95. }
  96. return -EINVAL;
  97. }
  98. static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
  99. {
  100. return pinctrl_gpio_direction_input(chip->base + offset);
  101. }
  102. static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
  103. {
  104. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  105. unsigned int val;
  106. int ret;
  107. ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
  108. if (ret)
  109. return ret;
  110. return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
  111. }
  112. static int axp20x_gpio_get_direction(struct gpio_chip *chip,
  113. unsigned int offset)
  114. {
  115. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  116. unsigned int val;
  117. int reg, ret;
  118. reg = axp20x_gpio_get_reg(offset);
  119. if (reg < 0)
  120. return reg;
  121. ret = regmap_read(pctl->regmap, reg, &val);
  122. if (ret)
  123. return ret;
  124. /*
  125. * This shouldn't really happen if the pin is in use already,
  126. * or if it's not in use yet, it doesn't matter since we're
  127. * going to change the value soon anyway. Default to output.
  128. */
  129. if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
  130. return GPIO_LINE_DIRECTION_OUT;
  131. /*
  132. * The GPIO directions are the three lowest values.
  133. * 2 is input, 0 and 1 are output
  134. */
  135. if (val & 2)
  136. return GPIO_LINE_DIRECTION_IN;
  137. return GPIO_LINE_DIRECTION_OUT;
  138. }
  139. static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
  140. int value)
  141. {
  142. chip->set(chip, offset, value);
  143. return 0;
  144. }
  145. static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
  146. int value)
  147. {
  148. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  149. int reg;
  150. reg = axp20x_gpio_get_reg(offset);
  151. if (reg < 0)
  152. return;
  153. regmap_update_bits(pctl->regmap, reg,
  154. AXP20X_GPIO_FUNCTIONS,
  155. value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
  156. AXP20X_GPIO_FUNCTION_OUT_LOW);
  157. }
  158. static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
  159. u8 config)
  160. {
  161. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  162. int reg;
  163. reg = axp20x_gpio_get_reg(offset);
  164. if (reg < 0)
  165. return reg;
  166. return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
  167. config);
  168. }
  169. static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
  170. {
  171. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  172. return ARRAY_SIZE(pctl->funcs);
  173. }
  174. static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
  175. unsigned int selector)
  176. {
  177. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  178. return pctl->funcs[selector].name;
  179. }
  180. static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
  181. unsigned int selector,
  182. const char * const **groups,
  183. unsigned int *num_groups)
  184. {
  185. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  186. *groups = pctl->funcs[selector].groups;
  187. *num_groups = pctl->funcs[selector].ngroups;
  188. return 0;
  189. }
  190. static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
  191. unsigned int function, unsigned int group)
  192. {
  193. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  194. unsigned int mask;
  195. /* Every pin supports GPIO_OUT and GPIO_IN functions */
  196. if (function <= AXP20X_FUNC_GPIO_IN)
  197. return axp20x_pmx_set(pctldev, group,
  198. pctl->funcs[function].muxval);
  199. if (function == AXP20X_FUNC_LDO)
  200. mask = pctl->desc->ldo_mask;
  201. else
  202. mask = pctl->desc->adc_mask;
  203. if (!(BIT(group) & mask))
  204. return -EINVAL;
  205. /*
  206. * We let the regulator framework handle the LDO muxing as muxing bits
  207. * are basically also regulators on/off bits. It's better not to enforce
  208. * any state of the regulator when selecting LDO mux so that we don't
  209. * interfere with the regulator driver.
  210. */
  211. if (function == AXP20X_FUNC_LDO)
  212. return 0;
  213. return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
  214. }
  215. static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  216. struct pinctrl_gpio_range *range,
  217. unsigned int offset, bool input)
  218. {
  219. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  220. if (input)
  221. return axp20x_pmx_set(pctldev, offset,
  222. pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
  223. return axp20x_pmx_set(pctldev, offset,
  224. pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
  225. }
  226. static const struct pinmux_ops axp20x_pmx_ops = {
  227. .get_functions_count = axp20x_pmx_func_cnt,
  228. .get_function_name = axp20x_pmx_func_name,
  229. .get_function_groups = axp20x_pmx_func_groups,
  230. .set_mux = axp20x_pmx_set_mux,
  231. .gpio_set_direction = axp20x_pmx_gpio_set_direction,
  232. .strict = true,
  233. };
  234. static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
  235. {
  236. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  237. return pctl->desc->npins;
  238. }
  239. static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
  240. const unsigned int **pins, unsigned int *num_pins)
  241. {
  242. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  243. *pins = (unsigned int *)&pctl->desc->pins[selector];
  244. *num_pins = 1;
  245. return 0;
  246. }
  247. static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
  248. unsigned int selector)
  249. {
  250. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  251. return pctl->desc->pins[selector].name;
  252. }
  253. static const struct pinctrl_ops axp20x_pctrl_ops = {
  254. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  255. .dt_free_map = pinconf_generic_dt_free_map,
  256. .get_groups_count = axp20x_groups_cnt,
  257. .get_group_name = axp20x_group_name,
  258. .get_group_pins = axp20x_group_pins,
  259. };
  260. static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
  261. unsigned int mask_len,
  262. struct axp20x_pinctrl_function *func,
  263. const struct pinctrl_pin_desc *pins)
  264. {
  265. unsigned long int mask_cpy = mask;
  266. const char **group;
  267. unsigned int ngroups = hweight8(mask);
  268. int bit;
  269. func->ngroups = ngroups;
  270. if (func->ngroups > 0) {
  271. func->groups = devm_kcalloc(dev,
  272. ngroups, sizeof(const char *),
  273. GFP_KERNEL);
  274. if (!func->groups)
  275. return -ENOMEM;
  276. group = func->groups;
  277. for_each_set_bit(bit, &mask_cpy, mask_len) {
  278. *group = pins[bit].name;
  279. group++;
  280. }
  281. }
  282. return 0;
  283. }
  284. static int axp20x_build_funcs_groups(struct platform_device *pdev)
  285. {
  286. struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
  287. int i, ret, pin, npins = pctl->desc->npins;
  288. pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
  289. pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
  290. pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
  291. pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
  292. pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
  293. /*
  294. * Muxval for LDO is useless as we won't use it.
  295. * See comment in axp20x_pmx_set_mux.
  296. */
  297. pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
  298. pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
  299. /* Every pin supports GPIO_OUT and GPIO_IN functions */
  300. for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
  301. pctl->funcs[i].ngroups = npins;
  302. pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
  303. npins, sizeof(char *),
  304. GFP_KERNEL);
  305. if (!pctl->funcs[i].groups)
  306. return -ENOMEM;
  307. for (pin = 0; pin < npins; pin++)
  308. pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
  309. }
  310. ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
  311. npins, &pctl->funcs[AXP20X_FUNC_LDO],
  312. pctl->desc->pins);
  313. if (ret)
  314. return ret;
  315. ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
  316. npins, &pctl->funcs[AXP20X_FUNC_ADC],
  317. pctl->desc->pins);
  318. if (ret)
  319. return ret;
  320. return 0;
  321. }
  322. static const struct of_device_id axp20x_pctl_match[] = {
  323. { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
  324. { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
  325. { }
  326. };
  327. MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
  328. static int axp20x_pctl_probe(struct platform_device *pdev)
  329. {
  330. struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
  331. struct axp20x_pctl *pctl;
  332. struct device *dev = &pdev->dev;
  333. struct pinctrl_desc *pctrl_desc;
  334. int ret;
  335. if (!of_device_is_available(pdev->dev.of_node))
  336. return -ENODEV;
  337. if (!axp20x) {
  338. dev_err(&pdev->dev, "Parent drvdata not set\n");
  339. return -EINVAL;
  340. }
  341. pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
  342. if (!pctl)
  343. return -ENOMEM;
  344. pctl->chip.base = -1;
  345. pctl->chip.can_sleep = true;
  346. pctl->chip.request = gpiochip_generic_request;
  347. pctl->chip.free = gpiochip_generic_free;
  348. pctl->chip.parent = &pdev->dev;
  349. pctl->chip.label = dev_name(&pdev->dev);
  350. pctl->chip.owner = THIS_MODULE;
  351. pctl->chip.get = axp20x_gpio_get;
  352. pctl->chip.get_direction = axp20x_gpio_get_direction;
  353. pctl->chip.set = axp20x_gpio_set;
  354. pctl->chip.direction_input = axp20x_gpio_input;
  355. pctl->chip.direction_output = axp20x_gpio_output;
  356. pctl->desc = of_device_get_match_data(dev);
  357. pctl->chip.ngpio = pctl->desc->npins;
  358. pctl->regmap = axp20x->regmap;
  359. pctl->dev = &pdev->dev;
  360. platform_set_drvdata(pdev, pctl);
  361. ret = axp20x_build_funcs_groups(pdev);
  362. if (ret) {
  363. dev_err(&pdev->dev, "failed to build groups\n");
  364. return ret;
  365. }
  366. pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
  367. if (!pctrl_desc)
  368. return -ENOMEM;
  369. pctrl_desc->name = dev_name(&pdev->dev);
  370. pctrl_desc->owner = THIS_MODULE;
  371. pctrl_desc->pins = pctl->desc->pins;
  372. pctrl_desc->npins = pctl->desc->npins;
  373. pctrl_desc->pctlops = &axp20x_pctrl_ops;
  374. pctrl_desc->pmxops = &axp20x_pmx_ops;
  375. pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
  376. if (IS_ERR(pctl->pctl_dev)) {
  377. dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
  378. return PTR_ERR(pctl->pctl_dev);
  379. }
  380. ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
  381. if (ret) {
  382. dev_err(&pdev->dev, "Failed to register GPIO chip\n");
  383. return ret;
  384. }
  385. ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
  386. pctl->desc->pins->number,
  387. pctl->desc->pins->number,
  388. pctl->desc->npins);
  389. if (ret) {
  390. dev_err(&pdev->dev, "failed to add pin range\n");
  391. return ret;
  392. }
  393. dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
  394. return 0;
  395. }
  396. static struct platform_driver axp20x_pctl_driver = {
  397. .probe = axp20x_pctl_probe,
  398. .driver = {
  399. .name = "axp20x-gpio",
  400. .of_match_table = axp20x_pctl_match,
  401. },
  402. };
  403. module_platform_driver(axp20x_pctl_driver);
  404. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  405. MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
  406. MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
  407. MODULE_LICENSE("GPL");