pinctrl-at91-pio4.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the Atmel PIO4 controller
  4. *
  5. * Copyright (C) 2015 Atmel,
  6. * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
  7. */
  8. #include <dt-bindings/pinctrl/at91.h>
  9. #include <linux/clk.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/init.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pinctrl/pinconf.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include <linux/pinctrl/pinctrl.h>
  19. #include <linux/pinctrl/pinmux.h>
  20. #include <linux/slab.h>
  21. #include "core.h"
  22. #include "pinconf.h"
  23. #include "pinctrl-utils.h"
  24. /*
  25. * Warning:
  26. * In order to not introduce confusion between Atmel PIO groups and pinctrl
  27. * framework groups, Atmel PIO groups will be called banks, line is kept to
  28. * designed the pin id into this bank.
  29. */
  30. #define ATMEL_PIO_MSKR 0x0000
  31. #define ATMEL_PIO_CFGR 0x0004
  32. #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
  33. #define ATMEL_PIO_DIR_MASK BIT(8)
  34. #define ATMEL_PIO_PUEN_MASK BIT(9)
  35. #define ATMEL_PIO_PDEN_MASK BIT(10)
  36. #define ATMEL_PIO_IFEN_MASK BIT(12)
  37. #define ATMEL_PIO_IFSCEN_MASK BIT(13)
  38. #define ATMEL_PIO_OPD_MASK BIT(14)
  39. #define ATMEL_PIO_SCHMITT_MASK BIT(15)
  40. #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
  41. #define ATMEL_PIO_DRVSTR_OFFSET 16
  42. #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
  43. #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
  44. #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
  45. #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
  46. #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
  47. #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
  48. #define ATMEL_PIO_PDSR 0x0008
  49. #define ATMEL_PIO_LOCKSR 0x000C
  50. #define ATMEL_PIO_SODR 0x0010
  51. #define ATMEL_PIO_CODR 0x0014
  52. #define ATMEL_PIO_ODSR 0x0018
  53. #define ATMEL_PIO_IER 0x0020
  54. #define ATMEL_PIO_IDR 0x0024
  55. #define ATMEL_PIO_IMR 0x0028
  56. #define ATMEL_PIO_ISR 0x002C
  57. #define ATMEL_PIO_IOFR 0x003C
  58. #define ATMEL_PIO_NPINS_PER_BANK 32
  59. #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
  60. #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
  61. #define ATMEL_PIO_BANK_OFFSET 0x40
  62. #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
  63. #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
  64. #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
  65. /* Custom pinconf parameters */
  66. #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
  67. struct atmel_pioctrl_data {
  68. unsigned nbanks;
  69. };
  70. struct atmel_group {
  71. const char *name;
  72. u32 pin;
  73. };
  74. struct atmel_pin {
  75. unsigned pin_id;
  76. unsigned mux;
  77. unsigned ioset;
  78. unsigned bank;
  79. unsigned line;
  80. const char *device;
  81. };
  82. /**
  83. * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
  84. * @reg_base: base address of the controller.
  85. * @clk: clock of the controller.
  86. * @nbanks: number of PIO groups, it can vary depending on the SoC.
  87. * @pinctrl_dev: pinctrl device registered.
  88. * @groups: groups table to provide group name and pin in the group to pinctrl.
  89. * @group_names: group names table to provide all the group/pin names to
  90. * pinctrl or gpio.
  91. * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
  92. * fields are set at probe time. Other ones are set when parsing dt
  93. * pinctrl.
  94. * @npins: number of pins.
  95. * @gpio_chip: gpio chip registered.
  96. * @irq_domain: irq domain for the gpio controller.
  97. * @irqs: table containing the hw irq number of the bank. The index of the
  98. * table is the bank id.
  99. * @pm_wakeup_sources: bitmap of wakeup sources (lines)
  100. * @pm_suspend_backup: backup/restore register values on suspend/resume
  101. * @dev: device entry for the Atmel PIO controller.
  102. * @node: node of the Atmel PIO controller.
  103. */
  104. struct atmel_pioctrl {
  105. void __iomem *reg_base;
  106. struct clk *clk;
  107. unsigned nbanks;
  108. struct pinctrl_dev *pinctrl_dev;
  109. struct atmel_group *groups;
  110. const char * const *group_names;
  111. struct atmel_pin **pins;
  112. unsigned npins;
  113. struct gpio_chip *gpio_chip;
  114. struct irq_domain *irq_domain;
  115. int *irqs;
  116. unsigned *pm_wakeup_sources;
  117. struct {
  118. u32 imr;
  119. u32 odsr;
  120. u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
  121. } *pm_suspend_backup;
  122. struct device *dev;
  123. struct device_node *node;
  124. };
  125. static const char * const atmel_functions[] = {
  126. "GPIO", "A", "B", "C", "D", "E", "F", "G"
  127. };
  128. static const struct pinconf_generic_params atmel_custom_bindings[] = {
  129. {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
  130. };
  131. /* --- GPIO --- */
  132. static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
  133. unsigned int bank, unsigned int reg)
  134. {
  135. return readl_relaxed(atmel_pioctrl->reg_base
  136. + ATMEL_PIO_BANK_OFFSET * bank + reg);
  137. }
  138. static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
  139. unsigned int bank, unsigned int reg,
  140. unsigned int val)
  141. {
  142. writel_relaxed(val, atmel_pioctrl->reg_base
  143. + ATMEL_PIO_BANK_OFFSET * bank + reg);
  144. }
  145. static void atmel_gpio_irq_ack(struct irq_data *d)
  146. {
  147. /*
  148. * Nothing to do, interrupt is cleared when reading the status
  149. * register.
  150. */
  151. }
  152. static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
  153. {
  154. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  155. struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
  156. unsigned reg;
  157. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
  158. BIT(pin->line));
  159. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
  160. reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
  161. switch (type) {
  162. case IRQ_TYPE_EDGE_RISING:
  163. irq_set_handler_locked(d, handle_edge_irq);
  164. reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
  165. break;
  166. case IRQ_TYPE_EDGE_FALLING:
  167. irq_set_handler_locked(d, handle_edge_irq);
  168. reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
  169. break;
  170. case IRQ_TYPE_EDGE_BOTH:
  171. irq_set_handler_locked(d, handle_edge_irq);
  172. reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
  173. break;
  174. case IRQ_TYPE_LEVEL_LOW:
  175. irq_set_handler_locked(d, handle_level_irq);
  176. reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
  177. break;
  178. case IRQ_TYPE_LEVEL_HIGH:
  179. irq_set_handler_locked(d, handle_level_irq);
  180. reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
  181. break;
  182. case IRQ_TYPE_NONE:
  183. default:
  184. return -EINVAL;
  185. }
  186. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
  187. return 0;
  188. }
  189. static void atmel_gpio_irq_mask(struct irq_data *d)
  190. {
  191. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  192. struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
  193. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
  194. BIT(pin->line));
  195. }
  196. static void atmel_gpio_irq_unmask(struct irq_data *d)
  197. {
  198. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  199. struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
  200. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
  201. BIT(pin->line));
  202. }
  203. #ifdef CONFIG_PM_SLEEP
  204. static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
  205. {
  206. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  207. int bank = ATMEL_PIO_BANK(d->hwirq);
  208. int line = ATMEL_PIO_LINE(d->hwirq);
  209. /* The gpio controller has one interrupt line per bank. */
  210. irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
  211. if (on)
  212. atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
  213. else
  214. atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
  215. return 0;
  216. }
  217. #else
  218. #define atmel_gpio_irq_set_wake NULL
  219. #endif /* CONFIG_PM_SLEEP */
  220. static struct irq_chip atmel_gpio_irq_chip = {
  221. .name = "GPIO",
  222. .irq_ack = atmel_gpio_irq_ack,
  223. .irq_mask = atmel_gpio_irq_mask,
  224. .irq_unmask = atmel_gpio_irq_unmask,
  225. .irq_set_type = atmel_gpio_irq_set_type,
  226. .irq_set_wake = atmel_gpio_irq_set_wake,
  227. };
  228. static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  229. {
  230. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  231. return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
  232. }
  233. static void atmel_gpio_irq_handler(struct irq_desc *desc)
  234. {
  235. unsigned int irq = irq_desc_get_irq(desc);
  236. struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
  237. struct irq_chip *chip = irq_desc_get_chip(desc);
  238. unsigned long isr;
  239. int n, bank = -1;
  240. /* Find from which bank is the irq received. */
  241. for (n = 0; n < atmel_pioctrl->nbanks; n++) {
  242. if (atmel_pioctrl->irqs[n] == irq) {
  243. bank = n;
  244. break;
  245. }
  246. }
  247. if (bank < 0) {
  248. dev_err(atmel_pioctrl->dev,
  249. "no bank associated to irq %u\n", irq);
  250. return;
  251. }
  252. chained_irq_enter(chip, desc);
  253. for (;;) {
  254. isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
  255. ATMEL_PIO_ISR);
  256. isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
  257. ATMEL_PIO_IMR);
  258. if (!isr)
  259. break;
  260. for_each_set_bit(n, &isr, BITS_PER_LONG)
  261. generic_handle_irq(atmel_gpio_to_irq(
  262. atmel_pioctrl->gpio_chip,
  263. bank * ATMEL_PIO_NPINS_PER_BANK + n));
  264. }
  265. chained_irq_exit(chip, desc);
  266. }
  267. static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  268. {
  269. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  270. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  271. unsigned reg;
  272. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
  273. BIT(pin->line));
  274. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
  275. reg &= ~ATMEL_PIO_DIR_MASK;
  276. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
  277. return 0;
  278. }
  279. static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
  280. {
  281. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  282. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  283. unsigned reg;
  284. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
  285. return !!(reg & BIT(pin->line));
  286. }
  287. static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
  288. unsigned long *bits)
  289. {
  290. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  291. unsigned int bank;
  292. bitmap_zero(bits, atmel_pioctrl->npins);
  293. for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
  294. unsigned int word = bank;
  295. unsigned int offset = 0;
  296. unsigned int reg;
  297. #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
  298. word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
  299. offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
  300. #endif
  301. if (!mask[word])
  302. continue;
  303. reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
  304. bits[word] |= mask[word] & (reg << offset);
  305. }
  306. return 0;
  307. }
  308. static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  309. int value)
  310. {
  311. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  312. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  313. unsigned reg;
  314. atmel_gpio_write(atmel_pioctrl, pin->bank,
  315. value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
  316. BIT(pin->line));
  317. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
  318. BIT(pin->line));
  319. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
  320. reg |= ATMEL_PIO_DIR_MASK;
  321. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
  322. return 0;
  323. }
  324. static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  325. {
  326. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  327. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  328. atmel_gpio_write(atmel_pioctrl, pin->bank,
  329. val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
  330. BIT(pin->line));
  331. }
  332. static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
  333. unsigned long *bits)
  334. {
  335. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  336. unsigned int bank;
  337. for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
  338. unsigned int bitmask;
  339. unsigned int word = bank;
  340. /*
  341. * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
  342. * two 32bit words to handle the whole bitmask
  343. */
  344. #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
  345. word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
  346. #endif
  347. if (!mask[word])
  348. continue;
  349. bitmask = mask[word] & bits[word];
  350. atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
  351. bitmask = mask[word] & ~bits[word];
  352. atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
  353. #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
  354. mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
  355. bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
  356. #endif
  357. }
  358. }
  359. static struct gpio_chip atmel_gpio_chip = {
  360. .direction_input = atmel_gpio_direction_input,
  361. .get = atmel_gpio_get,
  362. .get_multiple = atmel_gpio_get_multiple,
  363. .direction_output = atmel_gpio_direction_output,
  364. .set = atmel_gpio_set,
  365. .set_multiple = atmel_gpio_set_multiple,
  366. .to_irq = atmel_gpio_to_irq,
  367. .base = 0,
  368. };
  369. /* --- PINCTRL --- */
  370. static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
  371. unsigned pin_id)
  372. {
  373. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  374. unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
  375. unsigned line = atmel_pioctrl->pins[pin_id]->line;
  376. void __iomem *addr = atmel_pioctrl->reg_base
  377. + bank * ATMEL_PIO_BANK_OFFSET;
  378. writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
  379. /* Have to set MSKR first, to access the right pin CFGR. */
  380. wmb();
  381. return readl_relaxed(addr + ATMEL_PIO_CFGR);
  382. }
  383. static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
  384. unsigned pin_id, u32 conf)
  385. {
  386. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  387. unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
  388. unsigned line = atmel_pioctrl->pins[pin_id]->line;
  389. void __iomem *addr = atmel_pioctrl->reg_base
  390. + bank * ATMEL_PIO_BANK_OFFSET;
  391. writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
  392. /* Have to set MSKR first, to access the right pin CFGR. */
  393. wmb();
  394. writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
  395. }
  396. static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  397. {
  398. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  399. return atmel_pioctrl->npins;
  400. }
  401. static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
  402. unsigned selector)
  403. {
  404. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  405. return atmel_pioctrl->groups[selector].name;
  406. }
  407. static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  408. unsigned selector, const unsigned **pins,
  409. unsigned *num_pins)
  410. {
  411. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  412. *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
  413. *num_pins = 1;
  414. return 0;
  415. }
  416. static struct atmel_group *
  417. atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
  418. {
  419. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  420. int i;
  421. for (i = 0; i < atmel_pioctrl->npins; i++) {
  422. struct atmel_group *grp = atmel_pioctrl->groups + i;
  423. if (grp->pin == pin)
  424. return grp;
  425. }
  426. return NULL;
  427. }
  428. static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
  429. struct device_node *np,
  430. u32 pinfunc, const char **grp_name,
  431. const char **func_name)
  432. {
  433. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  434. unsigned pin_id, func_id;
  435. struct atmel_group *grp;
  436. pin_id = ATMEL_GET_PIN_NO(pinfunc);
  437. func_id = ATMEL_GET_PIN_FUNC(pinfunc);
  438. if (func_id >= ARRAY_SIZE(atmel_functions))
  439. return -EINVAL;
  440. *func_name = atmel_functions[func_id];
  441. grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
  442. if (!grp)
  443. return -EINVAL;
  444. *grp_name = grp->name;
  445. atmel_pioctrl->pins[pin_id]->mux = func_id;
  446. atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
  447. /* Want the device name not the group one. */
  448. if (np->parent == atmel_pioctrl->node)
  449. atmel_pioctrl->pins[pin_id]->device = np->name;
  450. else
  451. atmel_pioctrl->pins[pin_id]->device = np->parent->name;
  452. return 0;
  453. }
  454. static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
  455. struct device_node *np,
  456. struct pinctrl_map **map,
  457. unsigned *reserved_maps,
  458. unsigned *num_maps)
  459. {
  460. unsigned num_pins, num_configs, reserve;
  461. unsigned long *configs;
  462. struct property *pins;
  463. u32 pinfunc;
  464. int ret, i;
  465. pins = of_find_property(np, "pinmux", NULL);
  466. if (!pins)
  467. return -EINVAL;
  468. ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
  469. &num_configs);
  470. if (ret < 0) {
  471. dev_err(pctldev->dev, "%pOF: could not parse node property\n",
  472. np);
  473. return ret;
  474. }
  475. num_pins = pins->length / sizeof(u32);
  476. if (!num_pins) {
  477. dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
  478. ret = -EINVAL;
  479. goto exit;
  480. }
  481. /*
  482. * Reserve maps, at least there is a mux map and an optional conf
  483. * map for each pin.
  484. */
  485. reserve = 1;
  486. if (num_configs)
  487. reserve++;
  488. reserve *= num_pins;
  489. ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
  490. reserve);
  491. if (ret < 0)
  492. goto exit;
  493. for (i = 0; i < num_pins; i++) {
  494. const char *group, *func;
  495. ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
  496. if (ret)
  497. goto exit;
  498. ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
  499. &func);
  500. if (ret)
  501. goto exit;
  502. pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
  503. group, func);
  504. if (num_configs) {
  505. ret = pinctrl_utils_add_map_configs(pctldev, map,
  506. reserved_maps, num_maps, group,
  507. configs, num_configs,
  508. PIN_MAP_TYPE_CONFIGS_GROUP);
  509. if (ret < 0)
  510. goto exit;
  511. }
  512. }
  513. exit:
  514. kfree(configs);
  515. return ret;
  516. }
  517. static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
  518. struct device_node *np_config,
  519. struct pinctrl_map **map,
  520. unsigned *num_maps)
  521. {
  522. struct device_node *np;
  523. unsigned reserved_maps;
  524. int ret;
  525. *map = NULL;
  526. *num_maps = 0;
  527. reserved_maps = 0;
  528. /*
  529. * If all the pins of a device have the same configuration (or no one),
  530. * it is useless to add a subnode, so directly parse node referenced by
  531. * phandle.
  532. */
  533. ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
  534. &reserved_maps, num_maps);
  535. if (ret) {
  536. for_each_child_of_node(np_config, np) {
  537. ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
  538. &reserved_maps, num_maps);
  539. if (ret < 0) {
  540. of_node_put(np);
  541. break;
  542. }
  543. }
  544. }
  545. if (ret < 0) {
  546. pinctrl_utils_free_map(pctldev, *map, *num_maps);
  547. dev_err(pctldev->dev, "can't create maps for node %pOF\n",
  548. np_config);
  549. }
  550. return ret;
  551. }
  552. static const struct pinctrl_ops atmel_pctlops = {
  553. .get_groups_count = atmel_pctl_get_groups_count,
  554. .get_group_name = atmel_pctl_get_group_name,
  555. .get_group_pins = atmel_pctl_get_group_pins,
  556. .dt_node_to_map = atmel_pctl_dt_node_to_map,
  557. .dt_free_map = pinctrl_utils_free_map,
  558. };
  559. static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
  560. {
  561. return ARRAY_SIZE(atmel_functions);
  562. }
  563. static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
  564. unsigned selector)
  565. {
  566. return atmel_functions[selector];
  567. }
  568. static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
  569. unsigned selector,
  570. const char * const **groups,
  571. unsigned * const num_groups)
  572. {
  573. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  574. *groups = atmel_pioctrl->group_names;
  575. *num_groups = atmel_pioctrl->npins;
  576. return 0;
  577. }
  578. static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
  579. unsigned function,
  580. unsigned group)
  581. {
  582. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  583. unsigned pin;
  584. u32 conf;
  585. dev_dbg(pctldev->dev, "enable function %s group %s\n",
  586. atmel_functions[function], atmel_pioctrl->groups[group].name);
  587. pin = atmel_pioctrl->groups[group].pin;
  588. conf = atmel_pin_config_read(pctldev, pin);
  589. conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
  590. conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
  591. dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
  592. atmel_pin_config_write(pctldev, pin, conf);
  593. return 0;
  594. }
  595. static const struct pinmux_ops atmel_pmxops = {
  596. .get_functions_count = atmel_pmx_get_functions_count,
  597. .get_function_name = atmel_pmx_get_function_name,
  598. .get_function_groups = atmel_pmx_get_function_groups,
  599. .set_mux = atmel_pmx_set_mux,
  600. };
  601. static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
  602. unsigned group,
  603. unsigned long *config)
  604. {
  605. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  606. unsigned param = pinconf_to_config_param(*config), arg = 0;
  607. struct atmel_group *grp = atmel_pioctrl->groups + group;
  608. unsigned pin_id = grp->pin;
  609. u32 res;
  610. res = atmel_pin_config_read(pctldev, pin_id);
  611. switch (param) {
  612. case PIN_CONFIG_BIAS_PULL_UP:
  613. if (!(res & ATMEL_PIO_PUEN_MASK))
  614. return -EINVAL;
  615. arg = 1;
  616. break;
  617. case PIN_CONFIG_BIAS_PULL_DOWN:
  618. if ((res & ATMEL_PIO_PUEN_MASK) ||
  619. (!(res & ATMEL_PIO_PDEN_MASK)))
  620. return -EINVAL;
  621. arg = 1;
  622. break;
  623. case PIN_CONFIG_BIAS_DISABLE:
  624. if ((res & ATMEL_PIO_PUEN_MASK) ||
  625. ((res & ATMEL_PIO_PDEN_MASK)))
  626. return -EINVAL;
  627. arg = 1;
  628. break;
  629. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  630. if (!(res & ATMEL_PIO_OPD_MASK))
  631. return -EINVAL;
  632. arg = 1;
  633. break;
  634. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  635. if (!(res & ATMEL_PIO_SCHMITT_MASK))
  636. return -EINVAL;
  637. arg = 1;
  638. break;
  639. case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
  640. if (!(res & ATMEL_PIO_DRVSTR_MASK))
  641. return -EINVAL;
  642. arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
  643. break;
  644. default:
  645. return -ENOTSUPP;
  646. }
  647. *config = pinconf_to_config_packed(param, arg);
  648. return 0;
  649. }
  650. static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
  651. unsigned group,
  652. unsigned long *configs,
  653. unsigned num_configs)
  654. {
  655. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  656. struct atmel_group *grp = atmel_pioctrl->groups + group;
  657. unsigned bank, pin, pin_id = grp->pin;
  658. u32 mask, conf = 0;
  659. int i;
  660. conf = atmel_pin_config_read(pctldev, pin_id);
  661. for (i = 0; i < num_configs; i++) {
  662. unsigned param = pinconf_to_config_param(configs[i]);
  663. unsigned arg = pinconf_to_config_argument(configs[i]);
  664. dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
  665. __func__, pin_id, configs[i]);
  666. switch (param) {
  667. case PIN_CONFIG_BIAS_DISABLE:
  668. conf &= (~ATMEL_PIO_PUEN_MASK);
  669. conf &= (~ATMEL_PIO_PDEN_MASK);
  670. break;
  671. case PIN_CONFIG_BIAS_PULL_UP:
  672. conf |= ATMEL_PIO_PUEN_MASK;
  673. conf &= (~ATMEL_PIO_PDEN_MASK);
  674. break;
  675. case PIN_CONFIG_BIAS_PULL_DOWN:
  676. conf |= ATMEL_PIO_PDEN_MASK;
  677. conf &= (~ATMEL_PIO_PUEN_MASK);
  678. break;
  679. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  680. if (arg == 0)
  681. conf &= (~ATMEL_PIO_OPD_MASK);
  682. else
  683. conf |= ATMEL_PIO_OPD_MASK;
  684. break;
  685. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  686. if (arg == 0)
  687. conf |= ATMEL_PIO_SCHMITT_MASK;
  688. else
  689. conf &= (~ATMEL_PIO_SCHMITT_MASK);
  690. break;
  691. case PIN_CONFIG_INPUT_DEBOUNCE:
  692. if (arg == 0) {
  693. conf &= (~ATMEL_PIO_IFEN_MASK);
  694. conf &= (~ATMEL_PIO_IFSCEN_MASK);
  695. } else {
  696. /*
  697. * We don't care about the debounce value for several reasons:
  698. * - can't have different debounce periods inside a same group,
  699. * - the register to configure this period is a secure register.
  700. * The debouncing filter can filter a pulse with a duration of less
  701. * than 1/2 slow clock period.
  702. */
  703. conf |= ATMEL_PIO_IFEN_MASK;
  704. conf |= ATMEL_PIO_IFSCEN_MASK;
  705. }
  706. break;
  707. case PIN_CONFIG_OUTPUT:
  708. conf |= ATMEL_PIO_DIR_MASK;
  709. bank = ATMEL_PIO_BANK(pin_id);
  710. pin = ATMEL_PIO_LINE(pin_id);
  711. mask = 1 << pin;
  712. if (arg == 0) {
  713. writel_relaxed(mask, atmel_pioctrl->reg_base +
  714. bank * ATMEL_PIO_BANK_OFFSET +
  715. ATMEL_PIO_CODR);
  716. } else {
  717. writel_relaxed(mask, atmel_pioctrl->reg_base +
  718. bank * ATMEL_PIO_BANK_OFFSET +
  719. ATMEL_PIO_SODR);
  720. }
  721. break;
  722. case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
  723. switch (arg) {
  724. case ATMEL_PIO_DRVSTR_LO:
  725. case ATMEL_PIO_DRVSTR_ME:
  726. case ATMEL_PIO_DRVSTR_HI:
  727. conf &= (~ATMEL_PIO_DRVSTR_MASK);
  728. conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
  729. break;
  730. default:
  731. dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
  732. }
  733. break;
  734. default:
  735. dev_warn(pctldev->dev,
  736. "unsupported configuration parameter: %u\n",
  737. param);
  738. continue;
  739. }
  740. }
  741. dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
  742. atmel_pin_config_write(pctldev, pin_id, conf);
  743. return 0;
  744. }
  745. static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
  746. struct seq_file *s, unsigned pin_id)
  747. {
  748. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  749. u32 conf;
  750. if (!atmel_pioctrl->pins[pin_id]->device)
  751. return;
  752. if (atmel_pioctrl->pins[pin_id])
  753. seq_printf(s, " (%s, ioset %u) ",
  754. atmel_pioctrl->pins[pin_id]->device,
  755. atmel_pioctrl->pins[pin_id]->ioset);
  756. conf = atmel_pin_config_read(pctldev, pin_id);
  757. if (conf & ATMEL_PIO_PUEN_MASK)
  758. seq_printf(s, "%s ", "pull-up");
  759. if (conf & ATMEL_PIO_PDEN_MASK)
  760. seq_printf(s, "%s ", "pull-down");
  761. if (conf & ATMEL_PIO_IFEN_MASK)
  762. seq_printf(s, "%s ", "debounce");
  763. if (conf & ATMEL_PIO_OPD_MASK)
  764. seq_printf(s, "%s ", "open-drain");
  765. if (conf & ATMEL_PIO_SCHMITT_MASK)
  766. seq_printf(s, "%s ", "schmitt");
  767. if (conf & ATMEL_PIO_DRVSTR_MASK) {
  768. switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
  769. case ATMEL_PIO_DRVSTR_ME:
  770. seq_printf(s, "%s ", "medium-drive");
  771. break;
  772. case ATMEL_PIO_DRVSTR_HI:
  773. seq_printf(s, "%s ", "high-drive");
  774. break;
  775. /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
  776. default:
  777. seq_printf(s, "%s ", "low-drive");
  778. }
  779. }
  780. }
  781. static const struct pinconf_ops atmel_confops = {
  782. .pin_config_group_get = atmel_conf_pin_config_group_get,
  783. .pin_config_group_set = atmel_conf_pin_config_group_set,
  784. .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
  785. };
  786. static struct pinctrl_desc atmel_pinctrl_desc = {
  787. .name = "atmel_pinctrl",
  788. .confops = &atmel_confops,
  789. .pctlops = &atmel_pctlops,
  790. .pmxops = &atmel_pmxops,
  791. };
  792. static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
  793. {
  794. struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
  795. int i, j;
  796. /*
  797. * For each bank, save IMR to restore it later and disable all GPIO
  798. * interrupts excepting the ones marked as wakeup sources.
  799. */
  800. for (i = 0; i < atmel_pioctrl->nbanks; i++) {
  801. atmel_pioctrl->pm_suspend_backup[i].imr =
  802. atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
  803. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
  804. ~atmel_pioctrl->pm_wakeup_sources[i]);
  805. atmel_pioctrl->pm_suspend_backup[i].odsr =
  806. atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
  807. for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
  808. atmel_gpio_write(atmel_pioctrl, i,
  809. ATMEL_PIO_MSKR, BIT(j));
  810. atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
  811. atmel_gpio_read(atmel_pioctrl, i,
  812. ATMEL_PIO_CFGR);
  813. }
  814. }
  815. return 0;
  816. }
  817. static int __maybe_unused atmel_pctrl_resume(struct device *dev)
  818. {
  819. struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
  820. int i, j;
  821. for (i = 0; i < atmel_pioctrl->nbanks; i++) {
  822. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
  823. atmel_pioctrl->pm_suspend_backup[i].imr);
  824. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
  825. atmel_pioctrl->pm_suspend_backup[i].odsr);
  826. for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
  827. atmel_gpio_write(atmel_pioctrl, i,
  828. ATMEL_PIO_MSKR, BIT(j));
  829. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
  830. atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
  831. }
  832. }
  833. return 0;
  834. }
  835. static const struct dev_pm_ops atmel_pctrl_pm_ops = {
  836. SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
  837. };
  838. /*
  839. * The number of banks can be different from a SoC to another one.
  840. * We can have up to 16 banks.
  841. */
  842. static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
  843. .nbanks = 4,
  844. };
  845. static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
  846. .nbanks = 5,
  847. };
  848. static const struct of_device_id atmel_pctrl_of_match[] = {
  849. {
  850. .compatible = "atmel,sama5d2-pinctrl",
  851. .data = &atmel_sama5d2_pioctrl_data,
  852. }, {
  853. .compatible = "microchip,sama7g5-pinctrl",
  854. .data = &microchip_sama7g5_pioctrl_data,
  855. }, {
  856. /* sentinel */
  857. }
  858. };
  859. static int atmel_pinctrl_probe(struct platform_device *pdev)
  860. {
  861. struct device *dev = &pdev->dev;
  862. struct pinctrl_pin_desc *pin_desc;
  863. const char **group_names;
  864. const struct of_device_id *match;
  865. int i, ret;
  866. struct resource *res;
  867. struct atmel_pioctrl *atmel_pioctrl;
  868. const struct atmel_pioctrl_data *atmel_pioctrl_data;
  869. atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
  870. if (!atmel_pioctrl)
  871. return -ENOMEM;
  872. atmel_pioctrl->dev = dev;
  873. atmel_pioctrl->node = dev->of_node;
  874. platform_set_drvdata(pdev, atmel_pioctrl);
  875. match = of_match_node(atmel_pctrl_of_match, dev->of_node);
  876. if (!match) {
  877. dev_err(dev, "unknown compatible string\n");
  878. return -ENODEV;
  879. }
  880. atmel_pioctrl_data = match->data;
  881. atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
  882. atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
  883. atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
  884. if (IS_ERR(atmel_pioctrl->reg_base))
  885. return PTR_ERR(atmel_pioctrl->reg_base);
  886. atmel_pioctrl->clk = devm_clk_get(dev, NULL);
  887. if (IS_ERR(atmel_pioctrl->clk)) {
  888. dev_err(dev, "failed to get clock\n");
  889. return PTR_ERR(atmel_pioctrl->clk);
  890. }
  891. atmel_pioctrl->pins = devm_kcalloc(dev,
  892. atmel_pioctrl->npins,
  893. sizeof(*atmel_pioctrl->pins),
  894. GFP_KERNEL);
  895. if (!atmel_pioctrl->pins)
  896. return -ENOMEM;
  897. pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
  898. GFP_KERNEL);
  899. if (!pin_desc)
  900. return -ENOMEM;
  901. atmel_pinctrl_desc.pins = pin_desc;
  902. atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
  903. atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
  904. atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
  905. /* One pin is one group since a pin can achieve all functions. */
  906. group_names = devm_kcalloc(dev,
  907. atmel_pioctrl->npins, sizeof(*group_names),
  908. GFP_KERNEL);
  909. if (!group_names)
  910. return -ENOMEM;
  911. atmel_pioctrl->group_names = group_names;
  912. atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
  913. atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
  914. GFP_KERNEL);
  915. if (!atmel_pioctrl->groups)
  916. return -ENOMEM;
  917. for (i = 0 ; i < atmel_pioctrl->npins; i++) {
  918. struct atmel_group *group = atmel_pioctrl->groups + i;
  919. unsigned bank = ATMEL_PIO_BANK(i);
  920. unsigned line = ATMEL_PIO_LINE(i);
  921. atmel_pioctrl->pins[i] = devm_kzalloc(dev,
  922. sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
  923. if (!atmel_pioctrl->pins[i])
  924. return -ENOMEM;
  925. atmel_pioctrl->pins[i]->pin_id = i;
  926. atmel_pioctrl->pins[i]->bank = bank;
  927. atmel_pioctrl->pins[i]->line = line;
  928. pin_desc[i].number = i;
  929. /* Pin naming convention: P(bank_name)(bank_pin_number). */
  930. pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
  931. bank + 'A', line);
  932. group->name = group_names[i] = pin_desc[i].name;
  933. group->pin = pin_desc[i].number;
  934. dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
  935. }
  936. atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
  937. atmel_pioctrl->gpio_chip->of_node = dev->of_node;
  938. atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
  939. atmel_pioctrl->gpio_chip->label = dev_name(dev);
  940. atmel_pioctrl->gpio_chip->parent = dev;
  941. atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
  942. atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
  943. atmel_pioctrl->nbanks,
  944. sizeof(*atmel_pioctrl->pm_wakeup_sources),
  945. GFP_KERNEL);
  946. if (!atmel_pioctrl->pm_wakeup_sources)
  947. return -ENOMEM;
  948. atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
  949. atmel_pioctrl->nbanks,
  950. sizeof(*atmel_pioctrl->pm_suspend_backup),
  951. GFP_KERNEL);
  952. if (!atmel_pioctrl->pm_suspend_backup)
  953. return -ENOMEM;
  954. atmel_pioctrl->irqs = devm_kcalloc(dev,
  955. atmel_pioctrl->nbanks,
  956. sizeof(*atmel_pioctrl->irqs),
  957. GFP_KERNEL);
  958. if (!atmel_pioctrl->irqs)
  959. return -ENOMEM;
  960. /* There is one controller but each bank has its own irq line. */
  961. for (i = 0; i < atmel_pioctrl->nbanks; i++) {
  962. res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
  963. if (!res) {
  964. dev_err(dev, "missing irq resource for group %c\n",
  965. 'A' + i);
  966. return -EINVAL;
  967. }
  968. atmel_pioctrl->irqs[i] = res->start;
  969. irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
  970. irq_set_handler_data(res->start, atmel_pioctrl);
  971. dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
  972. }
  973. atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
  974. atmel_pioctrl->gpio_chip->ngpio,
  975. &irq_domain_simple_ops, NULL);
  976. if (!atmel_pioctrl->irq_domain) {
  977. dev_err(dev, "can't add the irq domain\n");
  978. return -ENODEV;
  979. }
  980. atmel_pioctrl->irq_domain->name = "atmel gpio";
  981. for (i = 0; i < atmel_pioctrl->npins; i++) {
  982. int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
  983. irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
  984. handle_simple_irq);
  985. irq_set_chip_data(irq, atmel_pioctrl);
  986. dev_dbg(dev,
  987. "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
  988. i, irq);
  989. }
  990. ret = clk_prepare_enable(atmel_pioctrl->clk);
  991. if (ret) {
  992. dev_err(dev, "failed to prepare and enable clock\n");
  993. goto clk_prepare_enable_error;
  994. }
  995. atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
  996. &atmel_pinctrl_desc,
  997. atmel_pioctrl);
  998. if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
  999. ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
  1000. dev_err(dev, "pinctrl registration failed\n");
  1001. goto clk_unprep;
  1002. }
  1003. ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
  1004. if (ret) {
  1005. dev_err(dev, "failed to add gpiochip\n");
  1006. goto clk_unprep;
  1007. }
  1008. ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
  1009. 0, 0, atmel_pioctrl->gpio_chip->ngpio);
  1010. if (ret) {
  1011. dev_err(dev, "failed to add gpio pin range\n");
  1012. goto gpiochip_add_pin_range_error;
  1013. }
  1014. dev_info(&pdev->dev, "atmel pinctrl initialized\n");
  1015. return 0;
  1016. gpiochip_add_pin_range_error:
  1017. gpiochip_remove(atmel_pioctrl->gpio_chip);
  1018. clk_unprep:
  1019. clk_disable_unprepare(atmel_pioctrl->clk);
  1020. clk_prepare_enable_error:
  1021. irq_domain_remove(atmel_pioctrl->irq_domain);
  1022. return ret;
  1023. }
  1024. static struct platform_driver atmel_pinctrl_driver = {
  1025. .driver = {
  1026. .name = "pinctrl-at91-pio4",
  1027. .of_match_table = atmel_pctrl_of_match,
  1028. .pm = &atmel_pctrl_pm_ops,
  1029. .suppress_bind_attrs = true,
  1030. },
  1031. .probe = atmel_pinctrl_probe,
  1032. };
  1033. builtin_platform_driver(atmel_pinctrl_driver);