pinctrl-as3722.c 17 KB

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  1. /*
  2. * ams AS3722 pin control and GPIO driver.
  3. *
  4. * Copyright (c) 2013, NVIDIA Corporation.
  5. *
  6. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  13. * whether express or implied; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20. * 02111-1307, USA
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/gpio/driver.h>
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/mfd/as3722.h>
  27. #include <linux/of.h>
  28. #include <linux/of_device.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/pinctrl/consumer.h>
  31. #include <linux/pinctrl/machine.h>
  32. #include <linux/pinctrl/pinctrl.h>
  33. #include <linux/pinctrl/pinconf-generic.h>
  34. #include <linux/pinctrl/pinconf.h>
  35. #include <linux/pinctrl/pinmux.h>
  36. #include <linux/pm.h>
  37. #include <linux/slab.h>
  38. #include "core.h"
  39. #include "pinconf.h"
  40. #include "pinctrl-utils.h"
  41. #define AS3722_PIN_GPIO0 0
  42. #define AS3722_PIN_GPIO1 1
  43. #define AS3722_PIN_GPIO2 2
  44. #define AS3722_PIN_GPIO3 3
  45. #define AS3722_PIN_GPIO4 4
  46. #define AS3722_PIN_GPIO5 5
  47. #define AS3722_PIN_GPIO6 6
  48. #define AS3722_PIN_GPIO7 7
  49. #define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
  50. #define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
  51. #define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
  52. #define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
  53. #define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
  54. struct as3722_pin_function {
  55. const char *name;
  56. const char * const *groups;
  57. unsigned ngroups;
  58. int mux_option;
  59. };
  60. struct as3722_gpio_pin_control {
  61. unsigned mode_prop;
  62. int io_function;
  63. };
  64. struct as3722_pingroup {
  65. const char *name;
  66. const unsigned pins[1];
  67. unsigned npins;
  68. };
  69. struct as3722_pctrl_info {
  70. struct device *dev;
  71. struct pinctrl_dev *pctl;
  72. struct as3722 *as3722;
  73. struct gpio_chip gpio_chip;
  74. int pins_current_opt[AS3722_PIN_NUM];
  75. const struct as3722_pin_function *functions;
  76. unsigned num_functions;
  77. const struct as3722_pingroup *pin_groups;
  78. int num_pin_groups;
  79. const struct pinctrl_pin_desc *pins;
  80. unsigned num_pins;
  81. struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
  82. };
  83. static const struct pinctrl_pin_desc as3722_pins_desc[] = {
  84. PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
  85. PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
  86. PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
  87. PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
  88. PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
  89. PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
  90. PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
  91. PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
  92. };
  93. static const char * const gpio_groups[] = {
  94. "gpio0",
  95. "gpio1",
  96. "gpio2",
  97. "gpio3",
  98. "gpio4",
  99. "gpio5",
  100. "gpio6",
  101. "gpio7",
  102. };
  103. enum as3722_pinmux_option {
  104. AS3722_PINMUX_GPIO = 0,
  105. AS3722_PINMUX_INTERRUPT_OUT = 1,
  106. AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,
  107. AS3722_PINMUX_GPIO_INTERRUPT = 3,
  108. AS3722_PINMUX_PWM_INPUT = 4,
  109. AS3722_PINMUX_VOLTAGE_IN_STBY = 5,
  110. AS3722_PINMUX_OC_PG_SD0 = 6,
  111. AS3722_PINMUX_PG_OUT = 7,
  112. AS3722_PINMUX_CLK32K_OUT = 8,
  113. AS3722_PINMUX_WATCHDOG_INPUT = 9,
  114. AS3722_PINMUX_SOFT_RESET_IN = 11,
  115. AS3722_PINMUX_PWM_OUTPUT = 12,
  116. AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
  117. AS3722_PINMUX_OC_PG_SD6 = 14,
  118. };
  119. #define FUNCTION_GROUP(fname, mux) \
  120. { \
  121. .name = #fname, \
  122. .groups = gpio_groups, \
  123. .ngroups = ARRAY_SIZE(gpio_groups), \
  124. .mux_option = AS3722_PINMUX_##mux, \
  125. }
  126. static const struct as3722_pin_function as3722_pin_function[] = {
  127. FUNCTION_GROUP(gpio, GPIO),
  128. FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
  129. FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
  130. FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
  131. FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
  132. FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
  133. FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
  134. FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
  135. FUNCTION_GROUP(powergood-out, PG_OUT),
  136. FUNCTION_GROUP(pwm-in, PWM_INPUT),
  137. FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
  138. FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
  139. FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
  140. FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
  141. };
  142. #define AS3722_PINGROUP(pg_name, pin_id) \
  143. { \
  144. .name = #pg_name, \
  145. .pins = {AS3722_PIN_##pin_id}, \
  146. .npins = 1, \
  147. }
  148. static const struct as3722_pingroup as3722_pingroups[] = {
  149. AS3722_PINGROUP(gpio0, GPIO0),
  150. AS3722_PINGROUP(gpio1, GPIO1),
  151. AS3722_PINGROUP(gpio2, GPIO2),
  152. AS3722_PINGROUP(gpio3, GPIO3),
  153. AS3722_PINGROUP(gpio4, GPIO4),
  154. AS3722_PINGROUP(gpio5, GPIO5),
  155. AS3722_PINGROUP(gpio6, GPIO6),
  156. AS3722_PINGROUP(gpio7, GPIO7),
  157. };
  158. static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  159. {
  160. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  161. return as_pci->num_pin_groups;
  162. }
  163. static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  164. unsigned group)
  165. {
  166. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  167. return as_pci->pin_groups[group].name;
  168. }
  169. static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  170. unsigned group, const unsigned **pins, unsigned *num_pins)
  171. {
  172. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  173. *pins = as_pci->pin_groups[group].pins;
  174. *num_pins = as_pci->pin_groups[group].npins;
  175. return 0;
  176. }
  177. static const struct pinctrl_ops as3722_pinctrl_ops = {
  178. .get_groups_count = as3722_pinctrl_get_groups_count,
  179. .get_group_name = as3722_pinctrl_get_group_name,
  180. .get_group_pins = as3722_pinctrl_get_group_pins,
  181. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  182. .dt_free_map = pinctrl_utils_free_map,
  183. };
  184. static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
  185. {
  186. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  187. return as_pci->num_functions;
  188. }
  189. static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
  190. unsigned function)
  191. {
  192. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  193. return as_pci->functions[function].name;
  194. }
  195. static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
  196. unsigned function, const char * const **groups,
  197. unsigned * const num_groups)
  198. {
  199. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  200. *groups = as_pci->functions[function].groups;
  201. *num_groups = as_pci->functions[function].ngroups;
  202. return 0;
  203. }
  204. static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
  205. unsigned group)
  206. {
  207. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  208. int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
  209. u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
  210. int ret;
  211. dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
  212. __func__, group, function, val);
  213. ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
  214. AS3722_GPIO_IOSF_MASK, val);
  215. if (ret < 0) {
  216. dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
  217. group, ret);
  218. return ret;
  219. }
  220. as_pci->gpio_control[group].io_function = function;
  221. switch (val) {
  222. case AS3722_GPIO_IOSF_SD0_OUT:
  223. case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
  224. case AS3722_GPIO_IOSF_Q32K_OUT:
  225. case AS3722_GPIO_IOSF_PWM_OUT:
  226. case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
  227. ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
  228. AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH);
  229. if (ret < 0) {
  230. dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n",
  231. group, ret);
  232. return ret;
  233. }
  234. as_pci->gpio_control[group].mode_prop =
  235. AS3722_GPIO_MODE_OUTPUT_VDDH;
  236. break;
  237. default:
  238. break;
  239. }
  240. return ret;
  241. }
  242. static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
  243. {
  244. if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
  245. return -EINVAL;
  246. if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
  247. if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
  248. return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
  249. return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
  250. }
  251. if (input) {
  252. if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
  253. return AS3722_GPIO_MODE_INPUT_PULL_UP;
  254. else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
  255. return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
  256. return AS3722_GPIO_MODE_INPUT;
  257. }
  258. if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
  259. return AS3722_GPIO_MODE_OUTPUT_VDDL;
  260. return AS3722_GPIO_MODE_OUTPUT_VDDH;
  261. }
  262. static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
  263. struct pinctrl_gpio_range *range, unsigned offset)
  264. {
  265. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  266. if (as_pci->gpio_control[offset].io_function)
  267. return -EBUSY;
  268. return 0;
  269. }
  270. static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
  271. struct pinctrl_gpio_range *range, unsigned offset, bool input)
  272. {
  273. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  274. struct as3722 *as3722 = as_pci->as3722;
  275. int mode;
  276. mode = as3722_pinctrl_gpio_get_mode(
  277. as_pci->gpio_control[offset].mode_prop, input);
  278. if (mode < 0) {
  279. dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
  280. (input) ? "Input" : "Output", offset);
  281. return mode;
  282. }
  283. return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset),
  284. AS3722_GPIO_MODE_MASK, mode);
  285. }
  286. static const struct pinmux_ops as3722_pinmux_ops = {
  287. .get_functions_count = as3722_pinctrl_get_funcs_count,
  288. .get_function_name = as3722_pinctrl_get_func_name,
  289. .get_function_groups = as3722_pinctrl_get_func_groups,
  290. .set_mux = as3722_pinctrl_set,
  291. .gpio_request_enable = as3722_pinctrl_gpio_request_enable,
  292. .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
  293. };
  294. static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
  295. unsigned pin, unsigned long *config)
  296. {
  297. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  298. enum pin_config_param param = pinconf_to_config_param(*config);
  299. int arg = 0;
  300. u16 prop;
  301. switch (param) {
  302. case PIN_CONFIG_BIAS_DISABLE:
  303. prop = AS3722_GPIO_MODE_PULL_UP |
  304. AS3722_GPIO_MODE_PULL_DOWN;
  305. if (!(as_pci->gpio_control[pin].mode_prop & prop))
  306. arg = 1;
  307. prop = 0;
  308. break;
  309. case PIN_CONFIG_BIAS_PULL_UP:
  310. prop = AS3722_GPIO_MODE_PULL_UP;
  311. break;
  312. case PIN_CONFIG_BIAS_PULL_DOWN:
  313. prop = AS3722_GPIO_MODE_PULL_DOWN;
  314. break;
  315. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  316. prop = AS3722_GPIO_MODE_OPEN_DRAIN;
  317. break;
  318. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  319. prop = AS3722_GPIO_MODE_HIGH_IMPED;
  320. break;
  321. default:
  322. dev_err(as_pci->dev, "Properties not supported\n");
  323. return -ENOTSUPP;
  324. }
  325. if (as_pci->gpio_control[pin].mode_prop & prop)
  326. arg = 1;
  327. *config = pinconf_to_config_packed(param, (u16)arg);
  328. return 0;
  329. }
  330. static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
  331. unsigned pin, unsigned long *configs,
  332. unsigned num_configs)
  333. {
  334. struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
  335. enum pin_config_param param;
  336. int mode_prop;
  337. int i;
  338. for (i = 0; i < num_configs; i++) {
  339. param = pinconf_to_config_param(configs[i]);
  340. mode_prop = as_pci->gpio_control[pin].mode_prop;
  341. switch (param) {
  342. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  343. break;
  344. case PIN_CONFIG_BIAS_DISABLE:
  345. mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
  346. AS3722_GPIO_MODE_PULL_DOWN);
  347. break;
  348. case PIN_CONFIG_BIAS_PULL_UP:
  349. mode_prop |= AS3722_GPIO_MODE_PULL_UP;
  350. break;
  351. case PIN_CONFIG_BIAS_PULL_DOWN:
  352. mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
  353. break;
  354. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  355. mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
  356. break;
  357. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  358. mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
  359. break;
  360. default:
  361. dev_err(as_pci->dev, "Properties not supported\n");
  362. return -ENOTSUPP;
  363. }
  364. as_pci->gpio_control[pin].mode_prop = mode_prop;
  365. }
  366. return 0;
  367. }
  368. static const struct pinconf_ops as3722_pinconf_ops = {
  369. .pin_config_get = as3722_pinconf_get,
  370. .pin_config_set = as3722_pinconf_set,
  371. };
  372. static struct pinctrl_desc as3722_pinctrl_desc = {
  373. .pctlops = &as3722_pinctrl_ops,
  374. .pmxops = &as3722_pinmux_ops,
  375. .confops = &as3722_pinconf_ops,
  376. .owner = THIS_MODULE,
  377. };
  378. static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
  379. {
  380. struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
  381. struct as3722 *as3722 = as_pci->as3722;
  382. int ret;
  383. u32 reg;
  384. u32 control;
  385. u32 val;
  386. int mode;
  387. int invert_enable;
  388. ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
  389. if (ret < 0) {
  390. dev_err(as_pci->dev,
  391. "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
  392. return ret;
  393. }
  394. invert_enable = !!(control & AS3722_GPIO_INV);
  395. mode = control & AS3722_GPIO_MODE_MASK;
  396. switch (mode) {
  397. case AS3722_GPIO_MODE_INPUT:
  398. case AS3722_GPIO_MODE_INPUT_PULL_UP:
  399. case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
  400. case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
  401. case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
  402. reg = AS3722_GPIO_SIGNAL_IN_REG;
  403. break;
  404. case AS3722_GPIO_MODE_OUTPUT_VDDH:
  405. case AS3722_GPIO_MODE_OUTPUT_VDDL:
  406. reg = AS3722_GPIO_SIGNAL_OUT_REG;
  407. break;
  408. default:
  409. return -EINVAL;
  410. }
  411. ret = as3722_read(as3722, reg, &val);
  412. if (ret < 0) {
  413. dev_err(as_pci->dev,
  414. "GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
  415. return ret;
  416. }
  417. val = !!(val & AS3722_GPIOn_SIGNAL(offset));
  418. return (invert_enable) ? !val : val;
  419. }
  420. static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
  421. int value)
  422. {
  423. struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
  424. struct as3722 *as3722 = as_pci->as3722;
  425. int en_invert;
  426. u32 val;
  427. int ret;
  428. ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val);
  429. if (ret < 0) {
  430. dev_err(as_pci->dev,
  431. "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
  432. return;
  433. }
  434. en_invert = !!(val & AS3722_GPIO_INV);
  435. if (value)
  436. val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
  437. else
  438. val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
  439. ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
  440. AS3722_GPIOn_SIGNAL(offset), val);
  441. if (ret < 0)
  442. dev_err(as_pci->dev,
  443. "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
  444. }
  445. static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  446. {
  447. return pinctrl_gpio_direction_input(chip->base + offset);
  448. }
  449. static int as3722_gpio_direction_output(struct gpio_chip *chip,
  450. unsigned offset, int value)
  451. {
  452. as3722_gpio_set(chip, offset, value);
  453. return pinctrl_gpio_direction_output(chip->base + offset);
  454. }
  455. static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  456. {
  457. struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
  458. return as3722_irq_get_virq(as_pci->as3722, offset);
  459. }
  460. static const struct gpio_chip as3722_gpio_chip = {
  461. .label = "as3722-gpio",
  462. .owner = THIS_MODULE,
  463. .request = gpiochip_generic_request,
  464. .free = gpiochip_generic_free,
  465. .get = as3722_gpio_get,
  466. .set = as3722_gpio_set,
  467. .direction_input = as3722_gpio_direction_input,
  468. .direction_output = as3722_gpio_direction_output,
  469. .to_irq = as3722_gpio_to_irq,
  470. .can_sleep = true,
  471. .ngpio = AS3722_PIN_NUM,
  472. .base = -1,
  473. };
  474. static int as3722_pinctrl_probe(struct platform_device *pdev)
  475. {
  476. struct as3722_pctrl_info *as_pci;
  477. int ret;
  478. as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
  479. if (!as_pci)
  480. return -ENOMEM;
  481. as_pci->dev = &pdev->dev;
  482. as_pci->dev->of_node = pdev->dev.parent->of_node;
  483. as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
  484. platform_set_drvdata(pdev, as_pci);
  485. as_pci->pins = as3722_pins_desc;
  486. as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
  487. as_pci->functions = as3722_pin_function;
  488. as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
  489. as_pci->pin_groups = as3722_pingroups;
  490. as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
  491. as3722_pinctrl_desc.name = dev_name(&pdev->dev);
  492. as3722_pinctrl_desc.pins = as3722_pins_desc;
  493. as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
  494. as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc,
  495. as_pci);
  496. if (IS_ERR(as_pci->pctl)) {
  497. dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
  498. return PTR_ERR(as_pci->pctl);
  499. }
  500. as_pci->gpio_chip = as3722_gpio_chip;
  501. as_pci->gpio_chip.parent = &pdev->dev;
  502. as_pci->gpio_chip.of_node = pdev->dev.parent->of_node;
  503. ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci);
  504. if (ret < 0) {
  505. dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
  506. return ret;
  507. }
  508. ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
  509. 0, 0, AS3722_PIN_NUM);
  510. if (ret < 0) {
  511. dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
  512. goto fail_range_add;
  513. }
  514. return 0;
  515. fail_range_add:
  516. gpiochip_remove(&as_pci->gpio_chip);
  517. return ret;
  518. }
  519. static int as3722_pinctrl_remove(struct platform_device *pdev)
  520. {
  521. struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
  522. gpiochip_remove(&as_pci->gpio_chip);
  523. return 0;
  524. }
  525. static const struct of_device_id as3722_pinctrl_of_match[] = {
  526. { .compatible = "ams,as3722-pinctrl", },
  527. { },
  528. };
  529. MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
  530. static struct platform_driver as3722_pinctrl_driver = {
  531. .driver = {
  532. .name = "as3722-pinctrl",
  533. .of_match_table = as3722_pinctrl_of_match,
  534. },
  535. .probe = as3722_pinctrl_probe,
  536. .remove = as3722_pinctrl_remove,
  537. };
  538. module_platform_driver(as3722_pinctrl_driver);
  539. MODULE_ALIAS("platform:as3722-pinctrl");
  540. MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
  541. MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
  542. MODULE_LICENSE("GPL v2");