pinctrl-amd.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPIO driver for AMD
  4. *
  5. * Copyright (c) 2014,2015 AMD Corporation.
  6. * Authors: Ken Xue <Ken.Xue@amd.com>
  7. * Wu, Jeff <Jeff.Wu@amd.com>
  8. *
  9. * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
  10. * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
  11. */
  12. #include <linux/err.h>
  13. #include <linux/bug.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/compiler.h>
  18. #include <linux/types.h>
  19. #include <linux/errno.h>
  20. #include <linux/log2.h>
  21. #include <linux/io.h>
  22. #include <linux/gpio/driver.h>
  23. #include <linux/slab.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/mutex.h>
  26. #include <linux/acpi.h>
  27. #include <linux/seq_file.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/list.h>
  30. #include <linux/bitops.h>
  31. #include <linux/pinctrl/pinconf.h>
  32. #include <linux/pinctrl/pinconf-generic.h>
  33. #include "core.h"
  34. #include "pinctrl-utils.h"
  35. #include "pinctrl-amd.h"
  36. static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
  37. {
  38. unsigned long flags;
  39. u32 pin_reg;
  40. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  41. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  42. pin_reg = readl(gpio_dev->base + offset * 4);
  43. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  44. if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
  45. return GPIO_LINE_DIRECTION_OUT;
  46. return GPIO_LINE_DIRECTION_IN;
  47. }
  48. static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  49. {
  50. unsigned long flags;
  51. u32 pin_reg;
  52. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  53. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  54. pin_reg = readl(gpio_dev->base + offset * 4);
  55. pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
  56. writel(pin_reg, gpio_dev->base + offset * 4);
  57. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  58. return 0;
  59. }
  60. static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
  61. int value)
  62. {
  63. u32 pin_reg;
  64. unsigned long flags;
  65. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  66. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  67. pin_reg = readl(gpio_dev->base + offset * 4);
  68. pin_reg |= BIT(OUTPUT_ENABLE_OFF);
  69. if (value)
  70. pin_reg |= BIT(OUTPUT_VALUE_OFF);
  71. else
  72. pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
  73. writel(pin_reg, gpio_dev->base + offset * 4);
  74. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  75. return 0;
  76. }
  77. static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
  78. {
  79. u32 pin_reg;
  80. unsigned long flags;
  81. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  82. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  83. pin_reg = readl(gpio_dev->base + offset * 4);
  84. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  85. return !!(pin_reg & BIT(PIN_STS_OFF));
  86. }
  87. static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
  88. {
  89. u32 pin_reg;
  90. unsigned long flags;
  91. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  92. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  93. pin_reg = readl(gpio_dev->base + offset * 4);
  94. if (value)
  95. pin_reg |= BIT(OUTPUT_VALUE_OFF);
  96. else
  97. pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
  98. writel(pin_reg, gpio_dev->base + offset * 4);
  99. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  100. }
  101. static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
  102. unsigned debounce)
  103. {
  104. u32 time;
  105. u32 pin_reg;
  106. int ret = 0;
  107. unsigned long flags;
  108. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  109. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  110. pin_reg = readl(gpio_dev->base + offset * 4);
  111. if (debounce) {
  112. pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
  113. pin_reg &= ~DB_TMR_OUT_MASK;
  114. /*
  115. Debounce Debounce Timer Max
  116. TmrLarge TmrOutUnit Unit Debounce
  117. Time
  118. 0 0 61 usec (2 RtcClk) 976 usec
  119. 0 1 244 usec (8 RtcClk) 3.9 msec
  120. 1 0 15.6 msec (512 RtcClk) 250 msec
  121. 1 1 62.5 msec (2048 RtcClk) 1 sec
  122. */
  123. if (debounce < 61) {
  124. pin_reg |= 1;
  125. pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
  126. pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
  127. } else if (debounce < 976) {
  128. time = debounce / 61;
  129. pin_reg |= time & DB_TMR_OUT_MASK;
  130. pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
  131. pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
  132. } else if (debounce < 3900) {
  133. time = debounce / 244;
  134. pin_reg |= time & DB_TMR_OUT_MASK;
  135. pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
  136. pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
  137. } else if (debounce < 250000) {
  138. time = debounce / 15625;
  139. pin_reg |= time & DB_TMR_OUT_MASK;
  140. pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
  141. pin_reg |= BIT(DB_TMR_LARGE_OFF);
  142. } else if (debounce < 1000000) {
  143. time = debounce / 62500;
  144. pin_reg |= time & DB_TMR_OUT_MASK;
  145. pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
  146. pin_reg |= BIT(DB_TMR_LARGE_OFF);
  147. } else {
  148. pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
  149. ret = -EINVAL;
  150. }
  151. } else {
  152. pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
  153. pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
  154. pin_reg &= ~DB_TMR_OUT_MASK;
  155. pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
  156. }
  157. writel(pin_reg, gpio_dev->base + offset * 4);
  158. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  159. return ret;
  160. }
  161. static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
  162. unsigned long config)
  163. {
  164. u32 debounce;
  165. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  166. return -ENOTSUPP;
  167. debounce = pinconf_to_config_argument(config);
  168. return amd_gpio_set_debounce(gc, offset, debounce);
  169. }
  170. #ifdef CONFIG_DEBUG_FS
  171. static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
  172. {
  173. u32 pin_reg;
  174. unsigned long flags;
  175. unsigned int bank, i, pin_num;
  176. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  177. char *level_trig;
  178. char *active_level;
  179. char *interrupt_enable;
  180. char *interrupt_mask;
  181. char *wake_cntrl0;
  182. char *wake_cntrl1;
  183. char *wake_cntrl2;
  184. char *pin_sts;
  185. char *pull_up_sel;
  186. char *pull_up_enable;
  187. char *pull_down_enable;
  188. char *output_value;
  189. char *output_enable;
  190. for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
  191. seq_printf(s, "GPIO bank%d\t", bank);
  192. switch (bank) {
  193. case 0:
  194. i = 0;
  195. pin_num = AMD_GPIO_PINS_BANK0;
  196. break;
  197. case 1:
  198. i = 64;
  199. pin_num = AMD_GPIO_PINS_BANK1 + i;
  200. break;
  201. case 2:
  202. i = 128;
  203. pin_num = AMD_GPIO_PINS_BANK2 + i;
  204. break;
  205. case 3:
  206. i = 192;
  207. pin_num = AMD_GPIO_PINS_BANK3 + i;
  208. break;
  209. default:
  210. /* Illegal bank number, ignore */
  211. continue;
  212. }
  213. for (; i < pin_num; i++) {
  214. seq_printf(s, "pin%d\t", i);
  215. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  216. pin_reg = readl(gpio_dev->base + i * 4);
  217. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  218. if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
  219. u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
  220. ACTIVE_LEVEL_MASK;
  221. interrupt_enable = "interrupt is enabled|";
  222. if (level == ACTIVE_LEVEL_HIGH)
  223. active_level = "Active high|";
  224. else if (level == ACTIVE_LEVEL_LOW)
  225. active_level = "Active low|";
  226. else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
  227. level == ACTIVE_LEVEL_BOTH)
  228. active_level = "Active on both|";
  229. else
  230. active_level = "Unknown Active level|";
  231. if (pin_reg & BIT(LEVEL_TRIG_OFF))
  232. level_trig = "Level trigger|";
  233. else
  234. level_trig = "Edge trigger|";
  235. } else {
  236. interrupt_enable =
  237. "interrupt is disabled|";
  238. active_level = " ";
  239. level_trig = " ";
  240. }
  241. if (pin_reg & BIT(INTERRUPT_MASK_OFF))
  242. interrupt_mask =
  243. "interrupt is unmasked|";
  244. else
  245. interrupt_mask =
  246. "interrupt is masked|";
  247. if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
  248. wake_cntrl0 = "enable wakeup in S0i3 state|";
  249. else
  250. wake_cntrl0 = "disable wakeup in S0i3 state|";
  251. if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
  252. wake_cntrl1 = "enable wakeup in S3 state|";
  253. else
  254. wake_cntrl1 = "disable wakeup in S3 state|";
  255. if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
  256. wake_cntrl2 = "enable wakeup in S4/S5 state|";
  257. else
  258. wake_cntrl2 = "disable wakeup in S4/S5 state|";
  259. if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
  260. pull_up_enable = "pull-up is enabled|";
  261. if (pin_reg & BIT(PULL_UP_SEL_OFF))
  262. pull_up_sel = "8k pull-up|";
  263. else
  264. pull_up_sel = "4k pull-up|";
  265. } else {
  266. pull_up_enable = "pull-up is disabled|";
  267. pull_up_sel = " ";
  268. }
  269. if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
  270. pull_down_enable = "pull-down is enabled|";
  271. else
  272. pull_down_enable = "Pull-down is disabled|";
  273. if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
  274. pin_sts = " ";
  275. output_enable = "output is enabled|";
  276. if (pin_reg & BIT(OUTPUT_VALUE_OFF))
  277. output_value = "output is high|";
  278. else
  279. output_value = "output is low|";
  280. } else {
  281. output_enable = "output is disabled|";
  282. output_value = " ";
  283. if (pin_reg & BIT(PIN_STS_OFF))
  284. pin_sts = "input is high|";
  285. else
  286. pin_sts = "input is low|";
  287. }
  288. seq_printf(s, "%s %s %s %s %s %s\n"
  289. " %s %s %s %s %s %s %s 0x%x\n",
  290. level_trig, active_level, interrupt_enable,
  291. interrupt_mask, wake_cntrl0, wake_cntrl1,
  292. wake_cntrl2, pin_sts, pull_up_sel,
  293. pull_up_enable, pull_down_enable,
  294. output_value, output_enable, pin_reg);
  295. }
  296. }
  297. }
  298. #else
  299. #define amd_gpio_dbg_show NULL
  300. #endif
  301. static void amd_gpio_irq_enable(struct irq_data *d)
  302. {
  303. u32 pin_reg;
  304. unsigned long flags;
  305. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  306. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  307. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  308. pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
  309. pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
  310. pin_reg |= BIT(INTERRUPT_MASK_OFF);
  311. writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
  312. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  313. }
  314. static void amd_gpio_irq_disable(struct irq_data *d)
  315. {
  316. u32 pin_reg;
  317. unsigned long flags;
  318. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  319. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  320. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  321. pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
  322. pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
  323. pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
  324. writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
  325. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  326. }
  327. static void amd_gpio_irq_mask(struct irq_data *d)
  328. {
  329. u32 pin_reg;
  330. unsigned long flags;
  331. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  332. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  333. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  334. pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
  335. pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
  336. writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
  337. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  338. }
  339. static void amd_gpio_irq_unmask(struct irq_data *d)
  340. {
  341. u32 pin_reg;
  342. unsigned long flags;
  343. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  344. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  345. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  346. pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
  347. pin_reg |= BIT(INTERRUPT_MASK_OFF);
  348. writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
  349. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  350. }
  351. static void amd_gpio_irq_eoi(struct irq_data *d)
  352. {
  353. u32 reg;
  354. unsigned long flags;
  355. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  356. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  357. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  358. reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
  359. reg |= EOI_MASK;
  360. writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
  361. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  362. }
  363. static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  364. {
  365. int ret = 0;
  366. u32 pin_reg, pin_reg_irq_en, mask;
  367. unsigned long flags;
  368. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  369. struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
  370. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  371. pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
  372. switch (type & IRQ_TYPE_SENSE_MASK) {
  373. case IRQ_TYPE_EDGE_RISING:
  374. pin_reg &= ~BIT(LEVEL_TRIG_OFF);
  375. pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
  376. pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
  377. irq_set_handler_locked(d, handle_edge_irq);
  378. break;
  379. case IRQ_TYPE_EDGE_FALLING:
  380. pin_reg &= ~BIT(LEVEL_TRIG_OFF);
  381. pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
  382. pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
  383. irq_set_handler_locked(d, handle_edge_irq);
  384. break;
  385. case IRQ_TYPE_EDGE_BOTH:
  386. pin_reg &= ~BIT(LEVEL_TRIG_OFF);
  387. pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
  388. pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
  389. irq_set_handler_locked(d, handle_edge_irq);
  390. break;
  391. case IRQ_TYPE_LEVEL_HIGH:
  392. pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
  393. pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
  394. pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
  395. irq_set_handler_locked(d, handle_level_irq);
  396. break;
  397. case IRQ_TYPE_LEVEL_LOW:
  398. pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
  399. pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
  400. pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
  401. irq_set_handler_locked(d, handle_level_irq);
  402. break;
  403. case IRQ_TYPE_NONE:
  404. break;
  405. default:
  406. dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
  407. ret = -EINVAL;
  408. }
  409. pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
  410. /*
  411. * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
  412. * debounce registers of any GPIO will block wake/interrupt status
  413. * generation for *all* GPIOs for a length of time that depends on
  414. * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
  415. * INTERRUPT_ENABLE bit will read as 0.
  416. *
  417. * We temporarily enable irq for the GPIO whose configuration is
  418. * changing, and then wait for it to read back as 1 to know when
  419. * debounce has settled and then disable the irq again.
  420. * We do this polling with the spinlock held to ensure other GPIO
  421. * access routines do not read an incorrect value for the irq enable
  422. * bit of other GPIOs. We keep the GPIO masked while polling to avoid
  423. * spurious irqs, and disable the irq again after polling.
  424. */
  425. mask = BIT(INTERRUPT_ENABLE_OFF);
  426. pin_reg_irq_en = pin_reg;
  427. pin_reg_irq_en |= mask;
  428. pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
  429. writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
  430. while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
  431. continue;
  432. writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
  433. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  434. return ret;
  435. }
  436. static void amd_irq_ack(struct irq_data *d)
  437. {
  438. /*
  439. * based on HW design,there is no need to ack HW
  440. * before handle current irq. But this routine is
  441. * necessary for handle_edge_irq
  442. */
  443. }
  444. static struct irq_chip amd_gpio_irqchip = {
  445. .name = "amd_gpio",
  446. .irq_ack = amd_irq_ack,
  447. .irq_enable = amd_gpio_irq_enable,
  448. .irq_disable = amd_gpio_irq_disable,
  449. .irq_mask = amd_gpio_irq_mask,
  450. .irq_unmask = amd_gpio_irq_unmask,
  451. .irq_eoi = amd_gpio_irq_eoi,
  452. .irq_set_type = amd_gpio_irq_set_type,
  453. .flags = IRQCHIP_SKIP_SET_WAKE,
  454. };
  455. #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
  456. static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
  457. {
  458. struct amd_gpio *gpio_dev = dev_id;
  459. struct gpio_chip *gc = &gpio_dev->gc;
  460. irqreturn_t ret = IRQ_NONE;
  461. unsigned int i, irqnr;
  462. unsigned long flags;
  463. u32 __iomem *regs;
  464. u32 regval;
  465. u64 status, mask;
  466. /* Read the wake status */
  467. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  468. status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
  469. status <<= 32;
  470. status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
  471. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  472. /* Bit 0-45 contain the relevant status bits */
  473. status &= (1ULL << 46) - 1;
  474. regs = gpio_dev->base;
  475. for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
  476. if (!(status & mask))
  477. continue;
  478. status &= ~mask;
  479. /* Each status bit covers four pins */
  480. for (i = 0; i < 4; i++) {
  481. regval = readl(regs + i);
  482. if (!(regval & PIN_IRQ_PENDING) ||
  483. !(regval & BIT(INTERRUPT_MASK_OFF)))
  484. continue;
  485. irq = irq_find_mapping(gc->irq.domain, irqnr + i);
  486. if (irq != 0)
  487. generic_handle_irq(irq);
  488. /* Clear interrupt.
  489. * We must read the pin register again, in case the
  490. * value was changed while executing
  491. * generic_handle_irq() above.
  492. * If we didn't find a mapping for the interrupt,
  493. * disable it in order to avoid a system hang caused
  494. * by an interrupt storm.
  495. */
  496. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  497. regval = readl(regs + i);
  498. if (irq == 0) {
  499. regval &= ~BIT(INTERRUPT_ENABLE_OFF);
  500. dev_dbg(&gpio_dev->pdev->dev,
  501. "Disabling spurious GPIO IRQ %d\n",
  502. irqnr + i);
  503. }
  504. writel(regval, regs + i);
  505. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  506. ret = IRQ_HANDLED;
  507. }
  508. }
  509. /* Signal EOI to the GPIO unit */
  510. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  511. regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
  512. regval |= EOI_MASK;
  513. writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
  514. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  515. return ret;
  516. }
  517. static int amd_get_groups_count(struct pinctrl_dev *pctldev)
  518. {
  519. struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
  520. return gpio_dev->ngroups;
  521. }
  522. static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
  523. unsigned group)
  524. {
  525. struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
  526. return gpio_dev->groups[group].name;
  527. }
  528. static int amd_get_group_pins(struct pinctrl_dev *pctldev,
  529. unsigned group,
  530. const unsigned **pins,
  531. unsigned *num_pins)
  532. {
  533. struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
  534. *pins = gpio_dev->groups[group].pins;
  535. *num_pins = gpio_dev->groups[group].npins;
  536. return 0;
  537. }
  538. static const struct pinctrl_ops amd_pinctrl_ops = {
  539. .get_groups_count = amd_get_groups_count,
  540. .get_group_name = amd_get_group_name,
  541. .get_group_pins = amd_get_group_pins,
  542. #ifdef CONFIG_OF
  543. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  544. .dt_free_map = pinctrl_utils_free_map,
  545. #endif
  546. };
  547. static int amd_pinconf_get(struct pinctrl_dev *pctldev,
  548. unsigned int pin,
  549. unsigned long *config)
  550. {
  551. u32 pin_reg;
  552. unsigned arg;
  553. unsigned long flags;
  554. struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
  555. enum pin_config_param param = pinconf_to_config_param(*config);
  556. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  557. pin_reg = readl(gpio_dev->base + pin*4);
  558. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  559. switch (param) {
  560. case PIN_CONFIG_INPUT_DEBOUNCE:
  561. arg = pin_reg & DB_TMR_OUT_MASK;
  562. break;
  563. case PIN_CONFIG_BIAS_PULL_DOWN:
  564. arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
  565. break;
  566. case PIN_CONFIG_BIAS_PULL_UP:
  567. arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
  568. break;
  569. case PIN_CONFIG_DRIVE_STRENGTH:
  570. arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
  571. break;
  572. default:
  573. dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
  574. param);
  575. return -ENOTSUPP;
  576. }
  577. *config = pinconf_to_config_packed(param, arg);
  578. return 0;
  579. }
  580. static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  581. unsigned long *configs, unsigned num_configs)
  582. {
  583. int i;
  584. u32 arg;
  585. int ret = 0;
  586. u32 pin_reg;
  587. unsigned long flags;
  588. enum pin_config_param param;
  589. struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
  590. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  591. for (i = 0; i < num_configs; i++) {
  592. param = pinconf_to_config_param(configs[i]);
  593. arg = pinconf_to_config_argument(configs[i]);
  594. pin_reg = readl(gpio_dev->base + pin*4);
  595. switch (param) {
  596. case PIN_CONFIG_INPUT_DEBOUNCE:
  597. pin_reg &= ~DB_TMR_OUT_MASK;
  598. pin_reg |= arg & DB_TMR_OUT_MASK;
  599. break;
  600. case PIN_CONFIG_BIAS_PULL_DOWN:
  601. pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
  602. pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
  603. break;
  604. case PIN_CONFIG_BIAS_PULL_UP:
  605. pin_reg &= ~BIT(PULL_UP_SEL_OFF);
  606. pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
  607. pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
  608. pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
  609. break;
  610. case PIN_CONFIG_DRIVE_STRENGTH:
  611. pin_reg &= ~(DRV_STRENGTH_SEL_MASK
  612. << DRV_STRENGTH_SEL_OFF);
  613. pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
  614. << DRV_STRENGTH_SEL_OFF;
  615. break;
  616. default:
  617. dev_err(&gpio_dev->pdev->dev,
  618. "Invalid config param %04x\n", param);
  619. ret = -ENOTSUPP;
  620. }
  621. writel(pin_reg, gpio_dev->base + pin*4);
  622. }
  623. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  624. return ret;
  625. }
  626. static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
  627. unsigned int group,
  628. unsigned long *config)
  629. {
  630. const unsigned *pins;
  631. unsigned npins;
  632. int ret;
  633. ret = amd_get_group_pins(pctldev, group, &pins, &npins);
  634. if (ret)
  635. return ret;
  636. if (amd_pinconf_get(pctldev, pins[0], config))
  637. return -ENOTSUPP;
  638. return 0;
  639. }
  640. static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
  641. unsigned group, unsigned long *configs,
  642. unsigned num_configs)
  643. {
  644. const unsigned *pins;
  645. unsigned npins;
  646. int i, ret;
  647. ret = amd_get_group_pins(pctldev, group, &pins, &npins);
  648. if (ret)
  649. return ret;
  650. for (i = 0; i < npins; i++) {
  651. if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
  652. return -ENOTSUPP;
  653. }
  654. return 0;
  655. }
  656. static const struct pinconf_ops amd_pinconf_ops = {
  657. .pin_config_get = amd_pinconf_get,
  658. .pin_config_set = amd_pinconf_set,
  659. .pin_config_group_get = amd_pinconf_group_get,
  660. .pin_config_group_set = amd_pinconf_group_set,
  661. };
  662. static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
  663. {
  664. struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
  665. unsigned long flags;
  666. u32 pin_reg, mask;
  667. int i;
  668. mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
  669. BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
  670. BIT(WAKE_CNTRL_OFF_S4);
  671. for (i = 0; i < desc->npins; i++) {
  672. int pin = desc->pins[i].number;
  673. const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
  674. if (!pd)
  675. continue;
  676. raw_spin_lock_irqsave(&gpio_dev->lock, flags);
  677. pin_reg = readl(gpio_dev->base + i * 4);
  678. pin_reg &= ~mask;
  679. writel(pin_reg, gpio_dev->base + i * 4);
  680. raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
  681. }
  682. }
  683. #ifdef CONFIG_PM_SLEEP
  684. static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
  685. {
  686. const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
  687. if (!pd)
  688. return false;
  689. /*
  690. * Only restore the pin if it is actually in use by the kernel (or
  691. * by userspace).
  692. */
  693. if (pd->mux_owner || pd->gpio_owner ||
  694. gpiochip_line_is_irq(&gpio_dev->gc, pin))
  695. return true;
  696. return false;
  697. }
  698. static int amd_gpio_suspend(struct device *dev)
  699. {
  700. struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
  701. struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
  702. int i;
  703. for (i = 0; i < desc->npins; i++) {
  704. int pin = desc->pins[i].number;
  705. if (!amd_gpio_should_save(gpio_dev, pin))
  706. continue;
  707. gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
  708. }
  709. return 0;
  710. }
  711. static int amd_gpio_resume(struct device *dev)
  712. {
  713. struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
  714. struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
  715. int i;
  716. for (i = 0; i < desc->npins; i++) {
  717. int pin = desc->pins[i].number;
  718. if (!amd_gpio_should_save(gpio_dev, pin))
  719. continue;
  720. writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
  721. }
  722. return 0;
  723. }
  724. static const struct dev_pm_ops amd_gpio_pm_ops = {
  725. SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
  726. amd_gpio_resume)
  727. };
  728. #endif
  729. static struct pinctrl_desc amd_pinctrl_desc = {
  730. .pins = kerncz_pins,
  731. .npins = ARRAY_SIZE(kerncz_pins),
  732. .pctlops = &amd_pinctrl_ops,
  733. .confops = &amd_pinconf_ops,
  734. .owner = THIS_MODULE,
  735. };
  736. static int amd_gpio_probe(struct platform_device *pdev)
  737. {
  738. int ret = 0;
  739. int irq_base;
  740. struct resource *res;
  741. struct amd_gpio *gpio_dev;
  742. struct gpio_irq_chip *girq;
  743. gpio_dev = devm_kzalloc(&pdev->dev,
  744. sizeof(struct amd_gpio), GFP_KERNEL);
  745. if (!gpio_dev)
  746. return -ENOMEM;
  747. raw_spin_lock_init(&gpio_dev->lock);
  748. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  749. if (!res) {
  750. dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
  751. return -EINVAL;
  752. }
  753. gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
  754. resource_size(res));
  755. if (!gpio_dev->base)
  756. return -ENOMEM;
  757. irq_base = platform_get_irq(pdev, 0);
  758. if (irq_base < 0)
  759. return irq_base;
  760. #ifdef CONFIG_PM_SLEEP
  761. gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
  762. sizeof(*gpio_dev->saved_regs),
  763. GFP_KERNEL);
  764. if (!gpio_dev->saved_regs)
  765. return -ENOMEM;
  766. #endif
  767. gpio_dev->pdev = pdev;
  768. gpio_dev->gc.get_direction = amd_gpio_get_direction;
  769. gpio_dev->gc.direction_input = amd_gpio_direction_input;
  770. gpio_dev->gc.direction_output = amd_gpio_direction_output;
  771. gpio_dev->gc.get = amd_gpio_get_value;
  772. gpio_dev->gc.set = amd_gpio_set_value;
  773. gpio_dev->gc.set_config = amd_gpio_set_config;
  774. gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
  775. gpio_dev->gc.base = -1;
  776. gpio_dev->gc.label = pdev->name;
  777. gpio_dev->gc.owner = THIS_MODULE;
  778. gpio_dev->gc.parent = &pdev->dev;
  779. gpio_dev->gc.ngpio = resource_size(res) / 4;
  780. #if defined(CONFIG_OF_GPIO)
  781. gpio_dev->gc.of_node = pdev->dev.of_node;
  782. #endif
  783. gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
  784. gpio_dev->groups = kerncz_groups;
  785. gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
  786. amd_pinctrl_desc.name = dev_name(&pdev->dev);
  787. gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
  788. gpio_dev);
  789. if (IS_ERR(gpio_dev->pctrl)) {
  790. dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
  791. return PTR_ERR(gpio_dev->pctrl);
  792. }
  793. /* Disable and mask interrupts */
  794. amd_gpio_irq_init(gpio_dev);
  795. girq = &gpio_dev->gc.irq;
  796. girq->chip = &amd_gpio_irqchip;
  797. /* This will let us handle the parent IRQ in the driver */
  798. girq->parent_handler = NULL;
  799. girq->num_parents = 0;
  800. girq->parents = NULL;
  801. girq->default_type = IRQ_TYPE_NONE;
  802. girq->handler = handle_simple_irq;
  803. ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
  804. if (ret)
  805. return ret;
  806. ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
  807. 0, 0, gpio_dev->gc.ngpio);
  808. if (ret) {
  809. dev_err(&pdev->dev, "Failed to add pin range\n");
  810. goto out2;
  811. }
  812. ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
  813. IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
  814. if (ret)
  815. goto out2;
  816. platform_set_drvdata(pdev, gpio_dev);
  817. dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
  818. return ret;
  819. out2:
  820. gpiochip_remove(&gpio_dev->gc);
  821. return ret;
  822. }
  823. static int amd_gpio_remove(struct platform_device *pdev)
  824. {
  825. struct amd_gpio *gpio_dev;
  826. gpio_dev = platform_get_drvdata(pdev);
  827. gpiochip_remove(&gpio_dev->gc);
  828. return 0;
  829. }
  830. #ifdef CONFIG_ACPI
  831. static const struct acpi_device_id amd_gpio_acpi_match[] = {
  832. { "AMD0030", 0 },
  833. { "AMDI0030", 0},
  834. { "AMDI0031", 0},
  835. { },
  836. };
  837. MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
  838. #endif
  839. static struct platform_driver amd_gpio_driver = {
  840. .driver = {
  841. .name = "amd_gpio",
  842. .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
  843. #ifdef CONFIG_PM_SLEEP
  844. .pm = &amd_gpio_pm_ops,
  845. #endif
  846. },
  847. .probe = amd_gpio_probe,
  848. .remove = amd_gpio_remove,
  849. };
  850. module_platform_driver(amd_gpio_driver);
  851. MODULE_LICENSE("GPL v2");
  852. MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
  853. MODULE_DESCRIPTION("AMD GPIO pinctrl driver");