pinctrl-npcm7xx.c 73 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2016-2018 Nuvoton Technology corporation.
  3. // Copyright (c) 2016, Dell Inc
  4. #include <linux/device.h>
  5. #include <linux/gpio/driver.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/irq.h>
  8. #include <linux/mfd/syscon.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/pinctrl/machine.h>
  14. #include <linux/pinctrl/pinconf.h>
  15. #include <linux/pinctrl/pinconf-generic.h>
  16. #include <linux/pinctrl/pinctrl.h>
  17. #include <linux/pinctrl/pinmux.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. /* GCR registers */
  21. #define NPCM7XX_GCR_PDID 0x00
  22. #define NPCM7XX_GCR_MFSEL1 0x0C
  23. #define NPCM7XX_GCR_MFSEL2 0x10
  24. #define NPCM7XX_GCR_MFSEL3 0x64
  25. #define NPCM7XX_GCR_MFSEL4 0xb0
  26. #define NPCM7XX_GCR_CPCTL 0xD0
  27. #define NPCM7XX_GCR_CP2BST 0xD4
  28. #define NPCM7XX_GCR_B2CPNT 0xD8
  29. #define NPCM7XX_GCR_I2CSEGSEL 0xE0
  30. #define NPCM7XX_GCR_I2CSEGCTL 0xE4
  31. #define NPCM7XX_GCR_SRCNT 0x68
  32. #define NPCM7XX_GCR_FLOCKR1 0x74
  33. #define NPCM7XX_GCR_DSCNT 0x78
  34. #define SRCNT_ESPI BIT(3)
  35. /* GPIO registers */
  36. #define NPCM7XX_GP_N_TLOCK1 0x00
  37. #define NPCM7XX_GP_N_DIN 0x04 /* Data IN */
  38. #define NPCM7XX_GP_N_POL 0x08 /* Polarity */
  39. #define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */
  40. #define NPCM7XX_GP_N_OE 0x10 /* Output Enable */
  41. #define NPCM7XX_GP_N_OTYP 0x14
  42. #define NPCM7XX_GP_N_MP 0x18
  43. #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
  44. #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
  45. #define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */
  46. #define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */
  47. #define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */
  48. #define NPCM7XX_GP_N_OBL0 0x30
  49. #define NPCM7XX_GP_N_OBL1 0x34
  50. #define NPCM7XX_GP_N_OBL2 0x38
  51. #define NPCM7XX_GP_N_OBL3 0x3c
  52. #define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */
  53. #define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */
  54. #define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */
  55. #define NPCM7XX_GP_N_EVST 0x4c /* Event Status */
  56. #define NPCM7XX_GP_N_SPLCK 0x50
  57. #define NPCM7XX_GP_N_MPLCK 0x54
  58. #define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */
  59. #define NPCM7XX_GP_N_OSRC 0x5c
  60. #define NPCM7XX_GP_N_ODSC 0x60
  61. #define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */
  62. #define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */
  63. #define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */
  64. #define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */
  65. #define NPCM7XX_GP_N_TLOCK2 0x7c
  66. #define NPCM7XX_GPIO_PER_BANK 32
  67. #define NPCM7XX_GPIO_BANK_NUM 8
  68. #define NPCM7XX_GCR_NONE 0
  69. /* Structure for register banks */
  70. struct npcm7xx_gpio {
  71. void __iomem *base;
  72. struct gpio_chip gc;
  73. int irqbase;
  74. int irq;
  75. struct irq_chip irq_chip;
  76. u32 pinctrl_id;
  77. int (*direction_input)(struct gpio_chip *chip, unsigned offset);
  78. int (*direction_output)(struct gpio_chip *chip, unsigned offset,
  79. int value);
  80. int (*request)(struct gpio_chip *chip, unsigned offset);
  81. void (*free)(struct gpio_chip *chip, unsigned offset);
  82. };
  83. struct npcm7xx_pinctrl {
  84. struct pinctrl_dev *pctldev;
  85. struct device *dev;
  86. struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];
  87. struct irq_domain *domain;
  88. struct regmap *gcr_regmap;
  89. void __iomem *regs;
  90. u32 bank_num;
  91. };
  92. /* GPIO handling in the pinctrl driver */
  93. static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
  94. unsigned int pinmask)
  95. {
  96. unsigned long flags;
  97. unsigned long val;
  98. spin_lock_irqsave(&gc->bgpio_lock, flags);
  99. val = ioread32(reg) | pinmask;
  100. iowrite32(val, reg);
  101. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  102. }
  103. static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
  104. unsigned int pinmask)
  105. {
  106. unsigned long flags;
  107. unsigned long val;
  108. spin_lock_irqsave(&gc->bgpio_lock, flags);
  109. val = ioread32(reg) & ~pinmask;
  110. iowrite32(val, reg);
  111. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  112. }
  113. static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  114. {
  115. struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
  116. seq_printf(s, "-- module %d [gpio%d - %d]\n",
  117. bank->gc.base / bank->gc.ngpio,
  118. bank->gc.base,
  119. bank->gc.base + bank->gc.ngpio);
  120. seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n",
  121. ioread32(bank->base + NPCM7XX_GP_N_DIN),
  122. ioread32(bank->base + NPCM7XX_GP_N_DOUT),
  123. ioread32(bank->base + NPCM7XX_GP_N_IEM),
  124. ioread32(bank->base + NPCM7XX_GP_N_OE));
  125. seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n",
  126. ioread32(bank->base + NPCM7XX_GP_N_PU),
  127. ioread32(bank->base + NPCM7XX_GP_N_PD),
  128. ioread32(bank->base + NPCM7XX_GP_N_DBNC),
  129. ioread32(bank->base + NPCM7XX_GP_N_POL));
  130. seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
  131. ioread32(bank->base + NPCM7XX_GP_N_EVTYP),
  132. ioread32(bank->base + NPCM7XX_GP_N_EVBE),
  133. ioread32(bank->base + NPCM7XX_GP_N_EVEN),
  134. ioread32(bank->base + NPCM7XX_GP_N_EVST));
  135. seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
  136. ioread32(bank->base + NPCM7XX_GP_N_OTYP),
  137. ioread32(bank->base + NPCM7XX_GP_N_OSRC),
  138. ioread32(bank->base + NPCM7XX_GP_N_ODSC));
  139. seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
  140. ioread32(bank->base + NPCM7XX_GP_N_OBL0),
  141. ioread32(bank->base + NPCM7XX_GP_N_OBL1),
  142. ioread32(bank->base + NPCM7XX_GP_N_OBL2),
  143. ioread32(bank->base + NPCM7XX_GP_N_OBL3));
  144. seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
  145. ioread32(bank->base + NPCM7XX_GP_N_SPLCK),
  146. ioread32(bank->base + NPCM7XX_GP_N_MPLCK));
  147. }
  148. static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
  149. {
  150. struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
  151. int ret;
  152. ret = pinctrl_gpio_direction_input(offset + chip->base);
  153. if (ret)
  154. return ret;
  155. return bank->direction_input(chip, offset);
  156. }
  157. /* Set GPIO to Output with initial value */
  158. static int npcmgpio_direction_output(struct gpio_chip *chip,
  159. unsigned int offset, int value)
  160. {
  161. struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
  162. int ret;
  163. dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,
  164. value);
  165. ret = pinctrl_gpio_direction_output(offset + chip->base);
  166. if (ret)
  167. return ret;
  168. return bank->direction_output(chip, offset, value);
  169. }
  170. static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
  171. {
  172. struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
  173. int ret;
  174. dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);
  175. ret = pinctrl_gpio_request(offset + chip->base);
  176. if (ret)
  177. return ret;
  178. return bank->request(chip, offset);
  179. }
  180. static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
  181. {
  182. dev_dbg(chip->parent, "gpio_free: offset%d\n", offset);
  183. pinctrl_gpio_free(offset + chip->base);
  184. }
  185. static void npcmgpio_irq_handler(struct irq_desc *desc)
  186. {
  187. struct gpio_chip *gc;
  188. struct irq_chip *chip;
  189. struct npcm7xx_gpio *bank;
  190. u32 sts, en, bit;
  191. gc = irq_desc_get_handler_data(desc);
  192. bank = gpiochip_get_data(gc);
  193. chip = irq_desc_get_chip(desc);
  194. chained_irq_enter(chip, desc);
  195. sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
  196. en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
  197. dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts,
  198. en);
  199. sts &= en;
  200. for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
  201. generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
  202. chained_irq_exit(chip, desc);
  203. }
  204. static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
  205. {
  206. struct npcm7xx_gpio *bank =
  207. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  208. unsigned int gpio = BIT(d->hwirq);
  209. dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,
  210. d->irq, type);
  211. switch (type) {
  212. case IRQ_TYPE_EDGE_RISING:
  213. dev_dbg(bank->gc.parent, "edge.rising\n");
  214. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
  215. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
  216. break;
  217. case IRQ_TYPE_EDGE_FALLING:
  218. dev_dbg(bank->gc.parent, "edge.falling\n");
  219. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
  220. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
  221. break;
  222. case IRQ_TYPE_EDGE_BOTH:
  223. dev_dbg(bank->gc.parent, "edge.both\n");
  224. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
  225. break;
  226. case IRQ_TYPE_LEVEL_LOW:
  227. dev_dbg(bank->gc.parent, "level.low\n");
  228. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
  229. break;
  230. case IRQ_TYPE_LEVEL_HIGH:
  231. dev_dbg(bank->gc.parent, "level.high\n");
  232. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
  233. break;
  234. default:
  235. dev_dbg(bank->gc.parent, "invalid irq type\n");
  236. return -EINVAL;
  237. }
  238. if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  239. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
  240. irq_set_handler_locked(d, handle_level_irq);
  241. } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING
  242. | IRQ_TYPE_EDGE_FALLING)) {
  243. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
  244. irq_set_handler_locked(d, handle_edge_irq);
  245. }
  246. return 0;
  247. }
  248. static void npcmgpio_irq_ack(struct irq_data *d)
  249. {
  250. struct npcm7xx_gpio *bank =
  251. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  252. unsigned int gpio = d->hwirq;
  253. dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);
  254. iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);
  255. }
  256. /* Disable GPIO interrupt */
  257. static void npcmgpio_irq_mask(struct irq_data *d)
  258. {
  259. struct npcm7xx_gpio *bank =
  260. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  261. unsigned int gpio = d->hwirq;
  262. /* Clear events */
  263. dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);
  264. iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);
  265. }
  266. /* Enable GPIO interrupt */
  267. static void npcmgpio_irq_unmask(struct irq_data *d)
  268. {
  269. struct npcm7xx_gpio *bank =
  270. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  271. unsigned int gpio = d->hwirq;
  272. /* Enable events */
  273. dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);
  274. iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);
  275. }
  276. static unsigned int npcmgpio_irq_startup(struct irq_data *d)
  277. {
  278. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  279. unsigned int gpio = d->hwirq;
  280. /* active-high, input, clear interrupt, enable interrupt */
  281. dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);
  282. npcmgpio_direction_input(gc, gpio);
  283. npcmgpio_irq_ack(d);
  284. npcmgpio_irq_unmask(d);
  285. return 0;
  286. }
  287. static const struct irq_chip npcmgpio_irqchip = {
  288. .name = "NPCM7XX-GPIO-IRQ",
  289. .irq_ack = npcmgpio_irq_ack,
  290. .irq_unmask = npcmgpio_irq_unmask,
  291. .irq_mask = npcmgpio_irq_mask,
  292. .irq_set_type = npcmgpio_set_irq_type,
  293. .irq_startup = npcmgpio_irq_startup,
  294. };
  295. /* pinmux handing in the pinctrl driver*/
  296. static const int smb0_pins[] = { 115, 114 };
  297. static const int smb0b_pins[] = { 195, 194 };
  298. static const int smb0c_pins[] = { 202, 196 };
  299. static const int smb0d_pins[] = { 198, 199 };
  300. static const int smb0den_pins[] = { 197 };
  301. static const int smb1_pins[] = { 117, 116 };
  302. static const int smb1b_pins[] = { 126, 127 };
  303. static const int smb1c_pins[] = { 124, 125 };
  304. static const int smb1d_pins[] = { 4, 5 };
  305. static const int smb2_pins[] = { 119, 118 };
  306. static const int smb2b_pins[] = { 122, 123 };
  307. static const int smb2c_pins[] = { 120, 121 };
  308. static const int smb2d_pins[] = { 6, 7 };
  309. static const int smb3_pins[] = { 30, 31 };
  310. static const int smb3b_pins[] = { 39, 40 };
  311. static const int smb3c_pins[] = { 37, 38 };
  312. static const int smb3d_pins[] = { 59, 60 };
  313. static const int smb4_pins[] = { 28, 29 };
  314. static const int smb4b_pins[] = { 18, 19 };
  315. static const int smb4c_pins[] = { 20, 21 };
  316. static const int smb4d_pins[] = { 22, 23 };
  317. static const int smb4den_pins[] = { 17 };
  318. static const int smb5_pins[] = { 26, 27 };
  319. static const int smb5b_pins[] = { 13, 12 };
  320. static const int smb5c_pins[] = { 15, 14 };
  321. static const int smb5d_pins[] = { 94, 93 };
  322. static const int ga20kbc_pins[] = { 94, 93 };
  323. static const int smb6_pins[] = { 172, 171 };
  324. static const int smb7_pins[] = { 174, 173 };
  325. static const int smb8_pins[] = { 129, 128 };
  326. static const int smb9_pins[] = { 131, 130 };
  327. static const int smb10_pins[] = { 133, 132 };
  328. static const int smb11_pins[] = { 135, 134 };
  329. static const int smb12_pins[] = { 221, 220 };
  330. static const int smb13_pins[] = { 223, 222 };
  331. static const int smb14_pins[] = { 22, 23 };
  332. static const int smb15_pins[] = { 20, 21 };
  333. static const int fanin0_pins[] = { 64 };
  334. static const int fanin1_pins[] = { 65 };
  335. static const int fanin2_pins[] = { 66 };
  336. static const int fanin3_pins[] = { 67 };
  337. static const int fanin4_pins[] = { 68 };
  338. static const int fanin5_pins[] = { 69 };
  339. static const int fanin6_pins[] = { 70 };
  340. static const int fanin7_pins[] = { 71 };
  341. static const int fanin8_pins[] = { 72 };
  342. static const int fanin9_pins[] = { 73 };
  343. static const int fanin10_pins[] = { 74 };
  344. static const int fanin11_pins[] = { 75 };
  345. static const int fanin12_pins[] = { 76 };
  346. static const int fanin13_pins[] = { 77 };
  347. static const int fanin14_pins[] = { 78 };
  348. static const int fanin15_pins[] = { 79 };
  349. static const int faninx_pins[] = { 175, 176, 177, 203 };
  350. static const int pwm0_pins[] = { 80 };
  351. static const int pwm1_pins[] = { 81 };
  352. static const int pwm2_pins[] = { 82 };
  353. static const int pwm3_pins[] = { 83 };
  354. static const int pwm4_pins[] = { 144 };
  355. static const int pwm5_pins[] = { 145 };
  356. static const int pwm6_pins[] = { 146 };
  357. static const int pwm7_pins[] = { 147 };
  358. static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
  359. static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
  360. /* RGMII 1 pin group */
  361. static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
  362. 106, 107 };
  363. /* RGMII 1 MD interface pin group */
  364. static const int rg1mdio_pins[] = { 108, 109 };
  365. /* RGMII 2 pin group */
  366. static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
  367. 213, 214, 215 };
  368. /* RGMII 2 MD interface pin group */
  369. static const int rg2mdio_pins[] = { 216, 217 };
  370. static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
  371. 213, 214, 215, 216, 217 };
  372. /* Serial I/O Expander 1 */
  373. static const int iox1_pins[] = { 0, 1, 2, 3 };
  374. /* Serial I/O Expander 2 */
  375. static const int iox2_pins[] = { 4, 5, 6, 7 };
  376. /* Host Serial I/O Expander 2 */
  377. static const int ioxh_pins[] = { 10, 11, 24, 25 };
  378. static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
  379. static const int mmcwp_pins[] = { 153 };
  380. static const int mmccd_pins[] = { 155 };
  381. static const int mmcrst_pins[] = { 155 };
  382. static const int mmc8_pins[] = { 148, 149, 150, 151 };
  383. /* RMII 1 pin groups */
  384. static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
  385. static const int r1err_pins[] = { 56 };
  386. static const int r1md_pins[] = { 57, 58 };
  387. /* RMII 2 pin groups */
  388. static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
  389. static const int r2err_pins[] = { 90 };
  390. static const int r2md_pins[] = { 91, 92 };
  391. static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
  392. static const int sd1pwr_pins[] = { 143 };
  393. static const int wdog1_pins[] = { 218 };
  394. static const int wdog2_pins[] = { 219 };
  395. /* BMC serial port 0 */
  396. static const int bmcuart0a_pins[] = { 41, 42 };
  397. static const int bmcuart0b_pins[] = { 48, 49 };
  398. static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
  399. /* System Control Interrupt and Power Management Event pin group */
  400. static const int scipme_pins[] = { 169 };
  401. /* System Management Interrupt pin group */
  402. static const int sci_pins[] = { 170 };
  403. /* Serial Interrupt Line pin group */
  404. static const int serirq_pins[] = { 162 };
  405. static const int clkout_pins[] = { 160 };
  406. static const int clkreq_pins[] = { 231 };
  407. static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
  408. /* Graphics SPI Clock pin group */
  409. static const int gspi_pins[] = { 12, 13, 14, 15 };
  410. static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
  411. static const int spixcs1_pins[] = { 228 };
  412. static const int pspi1_pins[] = { 175, 176, 177 };
  413. static const int pspi2_pins[] = { 17, 18, 19 };
  414. static const int spi0cs1_pins[] = { 32 };
  415. static const int spi3_pins[] = { 183, 184, 185, 186 };
  416. static const int spi3cs1_pins[] = { 187 };
  417. static const int spi3quad_pins[] = { 188, 189 };
  418. static const int spi3cs2_pins[] = { 188 };
  419. static const int spi3cs3_pins[] = { 189 };
  420. static const int ddc_pins[] = { 204, 205, 206, 207 };
  421. static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
  422. static const int lpcclk_pins[] = { 168 };
  423. static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
  424. static const int lkgpo0_pins[] = { 16 };
  425. static const int lkgpo1_pins[] = { 8 };
  426. static const int lkgpo2_pins[] = { 9 };
  427. static const int nprd_smi_pins[] = { 190 };
  428. /*
  429. * pin: name, number
  430. * group: name, npins, pins
  431. * function: name, ngroups, groups
  432. */
  433. struct npcm7xx_group {
  434. const char *name;
  435. const unsigned int *pins;
  436. int npins;
  437. };
  438. #define NPCM7XX_GRPS \
  439. NPCM7XX_GRP(smb0), \
  440. NPCM7XX_GRP(smb0b), \
  441. NPCM7XX_GRP(smb0c), \
  442. NPCM7XX_GRP(smb0d), \
  443. NPCM7XX_GRP(smb0den), \
  444. NPCM7XX_GRP(smb1), \
  445. NPCM7XX_GRP(smb1b), \
  446. NPCM7XX_GRP(smb1c), \
  447. NPCM7XX_GRP(smb1d), \
  448. NPCM7XX_GRP(smb2), \
  449. NPCM7XX_GRP(smb2b), \
  450. NPCM7XX_GRP(smb2c), \
  451. NPCM7XX_GRP(smb2d), \
  452. NPCM7XX_GRP(smb3), \
  453. NPCM7XX_GRP(smb3b), \
  454. NPCM7XX_GRP(smb3c), \
  455. NPCM7XX_GRP(smb3d), \
  456. NPCM7XX_GRP(smb4), \
  457. NPCM7XX_GRP(smb4b), \
  458. NPCM7XX_GRP(smb4c), \
  459. NPCM7XX_GRP(smb4d), \
  460. NPCM7XX_GRP(smb4den), \
  461. NPCM7XX_GRP(smb5), \
  462. NPCM7XX_GRP(smb5b), \
  463. NPCM7XX_GRP(smb5c), \
  464. NPCM7XX_GRP(smb5d), \
  465. NPCM7XX_GRP(ga20kbc), \
  466. NPCM7XX_GRP(smb6), \
  467. NPCM7XX_GRP(smb7), \
  468. NPCM7XX_GRP(smb8), \
  469. NPCM7XX_GRP(smb9), \
  470. NPCM7XX_GRP(smb10), \
  471. NPCM7XX_GRP(smb11), \
  472. NPCM7XX_GRP(smb12), \
  473. NPCM7XX_GRP(smb13), \
  474. NPCM7XX_GRP(smb14), \
  475. NPCM7XX_GRP(smb15), \
  476. NPCM7XX_GRP(fanin0), \
  477. NPCM7XX_GRP(fanin1), \
  478. NPCM7XX_GRP(fanin2), \
  479. NPCM7XX_GRP(fanin3), \
  480. NPCM7XX_GRP(fanin4), \
  481. NPCM7XX_GRP(fanin5), \
  482. NPCM7XX_GRP(fanin6), \
  483. NPCM7XX_GRP(fanin7), \
  484. NPCM7XX_GRP(fanin8), \
  485. NPCM7XX_GRP(fanin9), \
  486. NPCM7XX_GRP(fanin10), \
  487. NPCM7XX_GRP(fanin11), \
  488. NPCM7XX_GRP(fanin12), \
  489. NPCM7XX_GRP(fanin13), \
  490. NPCM7XX_GRP(fanin14), \
  491. NPCM7XX_GRP(fanin15), \
  492. NPCM7XX_GRP(faninx), \
  493. NPCM7XX_GRP(pwm0), \
  494. NPCM7XX_GRP(pwm1), \
  495. NPCM7XX_GRP(pwm2), \
  496. NPCM7XX_GRP(pwm3), \
  497. NPCM7XX_GRP(pwm4), \
  498. NPCM7XX_GRP(pwm5), \
  499. NPCM7XX_GRP(pwm6), \
  500. NPCM7XX_GRP(pwm7), \
  501. NPCM7XX_GRP(rg1), \
  502. NPCM7XX_GRP(rg1mdio), \
  503. NPCM7XX_GRP(rg2), \
  504. NPCM7XX_GRP(rg2mdio), \
  505. NPCM7XX_GRP(ddr), \
  506. NPCM7XX_GRP(uart1), \
  507. NPCM7XX_GRP(uart2), \
  508. NPCM7XX_GRP(bmcuart0a), \
  509. NPCM7XX_GRP(bmcuart0b), \
  510. NPCM7XX_GRP(bmcuart1), \
  511. NPCM7XX_GRP(iox1), \
  512. NPCM7XX_GRP(iox2), \
  513. NPCM7XX_GRP(ioxh), \
  514. NPCM7XX_GRP(gspi), \
  515. NPCM7XX_GRP(mmc), \
  516. NPCM7XX_GRP(mmcwp), \
  517. NPCM7XX_GRP(mmccd), \
  518. NPCM7XX_GRP(mmcrst), \
  519. NPCM7XX_GRP(mmc8), \
  520. NPCM7XX_GRP(r1), \
  521. NPCM7XX_GRP(r1err), \
  522. NPCM7XX_GRP(r1md), \
  523. NPCM7XX_GRP(r2), \
  524. NPCM7XX_GRP(r2err), \
  525. NPCM7XX_GRP(r2md), \
  526. NPCM7XX_GRP(sd1), \
  527. NPCM7XX_GRP(sd1pwr), \
  528. NPCM7XX_GRP(wdog1), \
  529. NPCM7XX_GRP(wdog2), \
  530. NPCM7XX_GRP(scipme), \
  531. NPCM7XX_GRP(sci), \
  532. NPCM7XX_GRP(serirq), \
  533. NPCM7XX_GRP(jtag2), \
  534. NPCM7XX_GRP(spix), \
  535. NPCM7XX_GRP(spixcs1), \
  536. NPCM7XX_GRP(pspi1), \
  537. NPCM7XX_GRP(pspi2), \
  538. NPCM7XX_GRP(ddc), \
  539. NPCM7XX_GRP(clkreq), \
  540. NPCM7XX_GRP(clkout), \
  541. NPCM7XX_GRP(spi3), \
  542. NPCM7XX_GRP(spi3cs1), \
  543. NPCM7XX_GRP(spi3quad), \
  544. NPCM7XX_GRP(spi3cs2), \
  545. NPCM7XX_GRP(spi3cs3), \
  546. NPCM7XX_GRP(spi0cs1), \
  547. NPCM7XX_GRP(lpc), \
  548. NPCM7XX_GRP(lpcclk), \
  549. NPCM7XX_GRP(espi), \
  550. NPCM7XX_GRP(lkgpo0), \
  551. NPCM7XX_GRP(lkgpo1), \
  552. NPCM7XX_GRP(lkgpo2), \
  553. NPCM7XX_GRP(nprd_smi), \
  554. \
  555. enum {
  556. #define NPCM7XX_GRP(x) fn_ ## x
  557. NPCM7XX_GRPS
  558. /* add placeholder for none/gpio */
  559. NPCM7XX_GRP(none),
  560. NPCM7XX_GRP(gpio),
  561. #undef NPCM7XX_GRP
  562. };
  563. static struct npcm7xx_group npcm7xx_groups[] = {
  564. #define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
  565. .npins = ARRAY_SIZE(x ## _pins) }
  566. NPCM7XX_GRPS
  567. #undef NPCM7XX_GRP
  568. };
  569. #define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
  570. #define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
  571. #define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
  572. .groups = nm ## _grp }
  573. struct npcm7xx_func {
  574. const char *name;
  575. const unsigned int ngroups;
  576. const char *const *groups;
  577. };
  578. NPCM7XX_SFUNC(smb0);
  579. NPCM7XX_SFUNC(smb0b);
  580. NPCM7XX_SFUNC(smb0c);
  581. NPCM7XX_SFUNC(smb0d);
  582. NPCM7XX_SFUNC(smb0den);
  583. NPCM7XX_SFUNC(smb1);
  584. NPCM7XX_SFUNC(smb1b);
  585. NPCM7XX_SFUNC(smb1c);
  586. NPCM7XX_SFUNC(smb1d);
  587. NPCM7XX_SFUNC(smb2);
  588. NPCM7XX_SFUNC(smb2b);
  589. NPCM7XX_SFUNC(smb2c);
  590. NPCM7XX_SFUNC(smb2d);
  591. NPCM7XX_SFUNC(smb3);
  592. NPCM7XX_SFUNC(smb3b);
  593. NPCM7XX_SFUNC(smb3c);
  594. NPCM7XX_SFUNC(smb3d);
  595. NPCM7XX_SFUNC(smb4);
  596. NPCM7XX_SFUNC(smb4b);
  597. NPCM7XX_SFUNC(smb4c);
  598. NPCM7XX_SFUNC(smb4d);
  599. NPCM7XX_SFUNC(smb4den);
  600. NPCM7XX_SFUNC(smb5);
  601. NPCM7XX_SFUNC(smb5b);
  602. NPCM7XX_SFUNC(smb5c);
  603. NPCM7XX_SFUNC(smb5d);
  604. NPCM7XX_SFUNC(ga20kbc);
  605. NPCM7XX_SFUNC(smb6);
  606. NPCM7XX_SFUNC(smb7);
  607. NPCM7XX_SFUNC(smb8);
  608. NPCM7XX_SFUNC(smb9);
  609. NPCM7XX_SFUNC(smb10);
  610. NPCM7XX_SFUNC(smb11);
  611. NPCM7XX_SFUNC(smb12);
  612. NPCM7XX_SFUNC(smb13);
  613. NPCM7XX_SFUNC(smb14);
  614. NPCM7XX_SFUNC(smb15);
  615. NPCM7XX_SFUNC(fanin0);
  616. NPCM7XX_SFUNC(fanin1);
  617. NPCM7XX_SFUNC(fanin2);
  618. NPCM7XX_SFUNC(fanin3);
  619. NPCM7XX_SFUNC(fanin4);
  620. NPCM7XX_SFUNC(fanin5);
  621. NPCM7XX_SFUNC(fanin6);
  622. NPCM7XX_SFUNC(fanin7);
  623. NPCM7XX_SFUNC(fanin8);
  624. NPCM7XX_SFUNC(fanin9);
  625. NPCM7XX_SFUNC(fanin10);
  626. NPCM7XX_SFUNC(fanin11);
  627. NPCM7XX_SFUNC(fanin12);
  628. NPCM7XX_SFUNC(fanin13);
  629. NPCM7XX_SFUNC(fanin14);
  630. NPCM7XX_SFUNC(fanin15);
  631. NPCM7XX_SFUNC(faninx);
  632. NPCM7XX_SFUNC(pwm0);
  633. NPCM7XX_SFUNC(pwm1);
  634. NPCM7XX_SFUNC(pwm2);
  635. NPCM7XX_SFUNC(pwm3);
  636. NPCM7XX_SFUNC(pwm4);
  637. NPCM7XX_SFUNC(pwm5);
  638. NPCM7XX_SFUNC(pwm6);
  639. NPCM7XX_SFUNC(pwm7);
  640. NPCM7XX_SFUNC(rg1);
  641. NPCM7XX_SFUNC(rg1mdio);
  642. NPCM7XX_SFUNC(rg2);
  643. NPCM7XX_SFUNC(rg2mdio);
  644. NPCM7XX_SFUNC(ddr);
  645. NPCM7XX_SFUNC(uart1);
  646. NPCM7XX_SFUNC(uart2);
  647. NPCM7XX_SFUNC(bmcuart0a);
  648. NPCM7XX_SFUNC(bmcuart0b);
  649. NPCM7XX_SFUNC(bmcuart1);
  650. NPCM7XX_SFUNC(iox1);
  651. NPCM7XX_SFUNC(iox2);
  652. NPCM7XX_SFUNC(ioxh);
  653. NPCM7XX_SFUNC(gspi);
  654. NPCM7XX_SFUNC(mmc);
  655. NPCM7XX_SFUNC(mmcwp);
  656. NPCM7XX_SFUNC(mmccd);
  657. NPCM7XX_SFUNC(mmcrst);
  658. NPCM7XX_SFUNC(mmc8);
  659. NPCM7XX_SFUNC(r1);
  660. NPCM7XX_SFUNC(r1err);
  661. NPCM7XX_SFUNC(r1md);
  662. NPCM7XX_SFUNC(r2);
  663. NPCM7XX_SFUNC(r2err);
  664. NPCM7XX_SFUNC(r2md);
  665. NPCM7XX_SFUNC(sd1);
  666. NPCM7XX_SFUNC(sd1pwr);
  667. NPCM7XX_SFUNC(wdog1);
  668. NPCM7XX_SFUNC(wdog2);
  669. NPCM7XX_SFUNC(scipme);
  670. NPCM7XX_SFUNC(sci);
  671. NPCM7XX_SFUNC(serirq);
  672. NPCM7XX_SFUNC(jtag2);
  673. NPCM7XX_SFUNC(spix);
  674. NPCM7XX_SFUNC(spixcs1);
  675. NPCM7XX_SFUNC(pspi1);
  676. NPCM7XX_SFUNC(pspi2);
  677. NPCM7XX_SFUNC(ddc);
  678. NPCM7XX_SFUNC(clkreq);
  679. NPCM7XX_SFUNC(clkout);
  680. NPCM7XX_SFUNC(spi3);
  681. NPCM7XX_SFUNC(spi3cs1);
  682. NPCM7XX_SFUNC(spi3quad);
  683. NPCM7XX_SFUNC(spi3cs2);
  684. NPCM7XX_SFUNC(spi3cs3);
  685. NPCM7XX_SFUNC(spi0cs1);
  686. NPCM7XX_SFUNC(lpc);
  687. NPCM7XX_SFUNC(lpcclk);
  688. NPCM7XX_SFUNC(espi);
  689. NPCM7XX_SFUNC(lkgpo0);
  690. NPCM7XX_SFUNC(lkgpo1);
  691. NPCM7XX_SFUNC(lkgpo2);
  692. NPCM7XX_SFUNC(nprd_smi);
  693. /* Function names */
  694. static struct npcm7xx_func npcm7xx_funcs[] = {
  695. NPCM7XX_MKFUNC(smb0),
  696. NPCM7XX_MKFUNC(smb0b),
  697. NPCM7XX_MKFUNC(smb0c),
  698. NPCM7XX_MKFUNC(smb0d),
  699. NPCM7XX_MKFUNC(smb0den),
  700. NPCM7XX_MKFUNC(smb1),
  701. NPCM7XX_MKFUNC(smb1b),
  702. NPCM7XX_MKFUNC(smb1c),
  703. NPCM7XX_MKFUNC(smb1d),
  704. NPCM7XX_MKFUNC(smb2),
  705. NPCM7XX_MKFUNC(smb2b),
  706. NPCM7XX_MKFUNC(smb2c),
  707. NPCM7XX_MKFUNC(smb2d),
  708. NPCM7XX_MKFUNC(smb3),
  709. NPCM7XX_MKFUNC(smb3b),
  710. NPCM7XX_MKFUNC(smb3c),
  711. NPCM7XX_MKFUNC(smb3d),
  712. NPCM7XX_MKFUNC(smb4),
  713. NPCM7XX_MKFUNC(smb4b),
  714. NPCM7XX_MKFUNC(smb4c),
  715. NPCM7XX_MKFUNC(smb4d),
  716. NPCM7XX_MKFUNC(smb4den),
  717. NPCM7XX_MKFUNC(smb5),
  718. NPCM7XX_MKFUNC(smb5b),
  719. NPCM7XX_MKFUNC(smb5c),
  720. NPCM7XX_MKFUNC(smb5d),
  721. NPCM7XX_MKFUNC(ga20kbc),
  722. NPCM7XX_MKFUNC(smb6),
  723. NPCM7XX_MKFUNC(smb7),
  724. NPCM7XX_MKFUNC(smb8),
  725. NPCM7XX_MKFUNC(smb9),
  726. NPCM7XX_MKFUNC(smb10),
  727. NPCM7XX_MKFUNC(smb11),
  728. NPCM7XX_MKFUNC(smb12),
  729. NPCM7XX_MKFUNC(smb13),
  730. NPCM7XX_MKFUNC(smb14),
  731. NPCM7XX_MKFUNC(smb15),
  732. NPCM7XX_MKFUNC(fanin0),
  733. NPCM7XX_MKFUNC(fanin1),
  734. NPCM7XX_MKFUNC(fanin2),
  735. NPCM7XX_MKFUNC(fanin3),
  736. NPCM7XX_MKFUNC(fanin4),
  737. NPCM7XX_MKFUNC(fanin5),
  738. NPCM7XX_MKFUNC(fanin6),
  739. NPCM7XX_MKFUNC(fanin7),
  740. NPCM7XX_MKFUNC(fanin8),
  741. NPCM7XX_MKFUNC(fanin9),
  742. NPCM7XX_MKFUNC(fanin10),
  743. NPCM7XX_MKFUNC(fanin11),
  744. NPCM7XX_MKFUNC(fanin12),
  745. NPCM7XX_MKFUNC(fanin13),
  746. NPCM7XX_MKFUNC(fanin14),
  747. NPCM7XX_MKFUNC(fanin15),
  748. NPCM7XX_MKFUNC(faninx),
  749. NPCM7XX_MKFUNC(pwm0),
  750. NPCM7XX_MKFUNC(pwm1),
  751. NPCM7XX_MKFUNC(pwm2),
  752. NPCM7XX_MKFUNC(pwm3),
  753. NPCM7XX_MKFUNC(pwm4),
  754. NPCM7XX_MKFUNC(pwm5),
  755. NPCM7XX_MKFUNC(pwm6),
  756. NPCM7XX_MKFUNC(pwm7),
  757. NPCM7XX_MKFUNC(rg1),
  758. NPCM7XX_MKFUNC(rg1mdio),
  759. NPCM7XX_MKFUNC(rg2),
  760. NPCM7XX_MKFUNC(rg2mdio),
  761. NPCM7XX_MKFUNC(ddr),
  762. NPCM7XX_MKFUNC(uart1),
  763. NPCM7XX_MKFUNC(uart2),
  764. NPCM7XX_MKFUNC(bmcuart0a),
  765. NPCM7XX_MKFUNC(bmcuart0b),
  766. NPCM7XX_MKFUNC(bmcuart1),
  767. NPCM7XX_MKFUNC(iox1),
  768. NPCM7XX_MKFUNC(iox2),
  769. NPCM7XX_MKFUNC(ioxh),
  770. NPCM7XX_MKFUNC(gspi),
  771. NPCM7XX_MKFUNC(mmc),
  772. NPCM7XX_MKFUNC(mmcwp),
  773. NPCM7XX_MKFUNC(mmccd),
  774. NPCM7XX_MKFUNC(mmcrst),
  775. NPCM7XX_MKFUNC(mmc8),
  776. NPCM7XX_MKFUNC(r1),
  777. NPCM7XX_MKFUNC(r1err),
  778. NPCM7XX_MKFUNC(r1md),
  779. NPCM7XX_MKFUNC(r2),
  780. NPCM7XX_MKFUNC(r2err),
  781. NPCM7XX_MKFUNC(r2md),
  782. NPCM7XX_MKFUNC(sd1),
  783. NPCM7XX_MKFUNC(sd1pwr),
  784. NPCM7XX_MKFUNC(wdog1),
  785. NPCM7XX_MKFUNC(wdog2),
  786. NPCM7XX_MKFUNC(scipme),
  787. NPCM7XX_MKFUNC(sci),
  788. NPCM7XX_MKFUNC(serirq),
  789. NPCM7XX_MKFUNC(jtag2),
  790. NPCM7XX_MKFUNC(spix),
  791. NPCM7XX_MKFUNC(spixcs1),
  792. NPCM7XX_MKFUNC(pspi1),
  793. NPCM7XX_MKFUNC(pspi2),
  794. NPCM7XX_MKFUNC(ddc),
  795. NPCM7XX_MKFUNC(clkreq),
  796. NPCM7XX_MKFUNC(clkout),
  797. NPCM7XX_MKFUNC(spi3),
  798. NPCM7XX_MKFUNC(spi3cs1),
  799. NPCM7XX_MKFUNC(spi3quad),
  800. NPCM7XX_MKFUNC(spi3cs2),
  801. NPCM7XX_MKFUNC(spi3cs3),
  802. NPCM7XX_MKFUNC(spi0cs1),
  803. NPCM7XX_MKFUNC(lpc),
  804. NPCM7XX_MKFUNC(lpcclk),
  805. NPCM7XX_MKFUNC(espi),
  806. NPCM7XX_MKFUNC(lkgpo0),
  807. NPCM7XX_MKFUNC(lkgpo1),
  808. NPCM7XX_MKFUNC(lkgpo2),
  809. NPCM7XX_MKFUNC(nprd_smi),
  810. };
  811. #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
  812. [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
  813. .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
  814. .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
  815. .flag = k }
  816. /* Drive strength controlled by NPCM7XX_GP_N_ODSC */
  817. #define DRIVE_STRENGTH_LO_SHIFT 8
  818. #define DRIVE_STRENGTH_HI_SHIFT 12
  819. #define DRIVE_STRENGTH_MASK 0x0000FF00
  820. #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
  821. ((hi) << DRIVE_STRENGTH_HI_SHIFT))
  822. #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
  823. #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
  824. #define GPI 0x1 /* Not GPO */
  825. #define GPO 0x2 /* Not GPI */
  826. #define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
  827. #define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */
  828. struct npcm7xx_pincfg {
  829. int flag;
  830. int fn0, reg0, bit0;
  831. int fn1, reg1, bit1;
  832. int fn2, reg2, bit2;
  833. };
  834. static const struct npcm7xx_pincfg pincfg[] = {
  835. /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
  836. NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
  837. NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  838. NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  839. NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
  840. NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
  841. NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
  842. NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
  843. NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
  844. NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  845. NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  846. NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  847. NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  848. NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
  849. NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
  850. NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
  851. NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
  852. NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  853. NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)),
  854. NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
  855. NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
  856. NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
  857. NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
  858. NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
  859. NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
  860. NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  861. NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  862. NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
  863. NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
  864. NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
  865. NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
  866. NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
  867. NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
  868. NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0),
  869. NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
  870. NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
  871. NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
  872. NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
  873. NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
  874. NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
  875. NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
  876. NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
  877. NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
  878. NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
  879. NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
  880. NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
  881. NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
  882. NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
  883. NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
  884. NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
  885. NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
  886. NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
  887. NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
  888. NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
  889. NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
  890. NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
  891. NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
  892. NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
  893. NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
  894. NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
  895. NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
  896. NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
  897. NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
  898. NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0),
  899. NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0),
  900. NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0),
  901. NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0),
  902. NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0),
  903. NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0),
  904. NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0),
  905. NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0),
  906. NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0),
  907. NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0),
  908. NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0),
  909. NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0),
  910. NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0),
  911. NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
  912. NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
  913. NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
  914. NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  915. NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  916. NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  917. NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  918. NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  919. NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  920. NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  921. NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
  922. NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
  923. NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
  924. NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
  925. NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
  926. NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
  927. NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
  928. NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
  929. NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
  930. NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  931. NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  932. NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  933. NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  934. NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  935. NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  936. NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  937. NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  938. NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  939. NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  940. NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  941. NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
  942. NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
  943. NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
  944. NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  945. NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  946. NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  947. NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  948. NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
  949. NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
  950. NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
  951. NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
  952. NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
  953. NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
  954. NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
  955. NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
  956. NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
  957. NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
  958. NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
  959. NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
  960. NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
  961. NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
  962. NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
  963. NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
  964. NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
  965. NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
  966. NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
  967. NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
  968. NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
  969. NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
  970. NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  971. NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  972. NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  973. NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  974. NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  975. NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
  976. NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  977. NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
  978. NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  979. NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  980. NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  981. NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  982. NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  983. NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  984. NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  985. NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  986. NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  987. NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
  988. NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  989. NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
  990. NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  991. NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  992. NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  993. NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  994. NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  995. NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),
  996. NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),
  997. NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
  998. NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
  999. NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
  1000. NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
  1001. NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
  1002. NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),
  1003. NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0),
  1004. NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0),
  1005. NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
  1006. NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
  1007. NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
  1008. NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
  1009. NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
  1010. NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
  1011. NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
  1012. NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1013. NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1014. NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1015. NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
  1016. NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
  1017. NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1018. NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
  1019. NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
  1020. NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  1021. NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  1022. NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW),
  1023. NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW),
  1024. NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),
  1025. NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
  1026. NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
  1027. NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
  1028. NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
  1029. NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
  1030. NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
  1031. NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW),
  1032. NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
  1033. NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
  1034. NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
  1035. NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
  1036. NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
  1037. NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  1038. NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
  1039. NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
  1040. NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
  1041. NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
  1042. NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1043. NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1044. NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1045. NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1046. NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1047. NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1048. NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1049. NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1050. NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1051. NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
  1052. NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
  1053. NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
  1054. NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
  1055. NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
  1056. NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
  1057. NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
  1058. NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
  1059. NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
  1060. NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
  1061. NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1062. NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1063. NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1064. NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
  1065. NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
  1066. NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
  1067. NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
  1068. NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
  1069. };
  1070. /* number, name, drv_data */
  1071. static const struct pinctrl_pin_desc npcm7xx_pins[] = {
  1072. PINCTRL_PIN(0, "GPIO0/IOX1DI"),
  1073. PINCTRL_PIN(1, "GPIO1/IOX1LD"),
  1074. PINCTRL_PIN(2, "GPIO2/IOX1CK"),
  1075. PINCTRL_PIN(3, "GPIO3/IOX1D0"),
  1076. PINCTRL_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"),
  1077. PINCTRL_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"),
  1078. PINCTRL_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"),
  1079. PINCTRL_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"),
  1080. PINCTRL_PIN(8, "GPIO8/LKGPO1"),
  1081. PINCTRL_PIN(9, "GPIO9/LKGPO2"),
  1082. PINCTRL_PIN(10, "GPIO10/IOXHLD"),
  1083. PINCTRL_PIN(11, "GPIO11/IOXHCK"),
  1084. PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
  1085. PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
  1086. PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
  1087. PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
  1088. PINCTRL_PIN(16, "GPIO16/LKGPO0"),
  1089. PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
  1090. PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
  1091. PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
  1092. PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
  1093. PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
  1094. PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
  1095. PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
  1096. PINCTRL_PIN(24, "GPIO24/IOXHDO"),
  1097. PINCTRL_PIN(25, "GPIO25/IOXHDI"),
  1098. PINCTRL_PIN(26, "GPIO26/SMB5SDA"),
  1099. PINCTRL_PIN(27, "GPIO27/SMB5SCL"),
  1100. PINCTRL_PIN(28, "GPIO28/SMB4SDA"),
  1101. PINCTRL_PIN(29, "GPIO29/SMB4SCL"),
  1102. PINCTRL_PIN(30, "GPIO30/SMB3SDA"),
  1103. PINCTRL_PIN(31, "GPIO31/SMB3SCL"),
  1104. PINCTRL_PIN(32, "GPIO32/nSPI0CS1"),
  1105. PINCTRL_PIN(33, "SPI0D2"),
  1106. PINCTRL_PIN(34, "SPI0D3"),
  1107. PINCTRL_PIN(37, "GPIO37/SMB3CSDA"),
  1108. PINCTRL_PIN(38, "GPIO38/SMB3CSCL"),
  1109. PINCTRL_PIN(39, "GPIO39/SMB3BSDA"),
  1110. PINCTRL_PIN(40, "GPIO40/SMB3BSCL"),
  1111. PINCTRL_PIN(41, "GPIO41/BSPRXD"),
  1112. PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"),
  1113. PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
  1114. PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
  1115. PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"),
  1116. PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"),
  1117. PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
  1118. PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"),
  1119. PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"),
  1120. PINCTRL_PIN(50, "GPIO50/nCTS2"),
  1121. PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"),
  1122. PINCTRL_PIN(52, "GPIO52/nDCD2"),
  1123. PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
  1124. PINCTRL_PIN(54, "GPIO54/nDSR2"),
  1125. PINCTRL_PIN(55, "GPIO55/nRI2"),
  1126. PINCTRL_PIN(56, "GPIO56/R1RXERR"),
  1127. PINCTRL_PIN(57, "GPIO57/R1MDC"),
  1128. PINCTRL_PIN(58, "GPIO58/R1MDIO"),
  1129. PINCTRL_PIN(59, "GPIO59/SMB3DSDA"),
  1130. PINCTRL_PIN(60, "GPIO60/SMB3DSCL"),
  1131. PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
  1132. PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"),
  1133. PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"),
  1134. PINCTRL_PIN(64, "GPIO64/FANIN0"),
  1135. PINCTRL_PIN(65, "GPIO65/FANIN1"),
  1136. PINCTRL_PIN(66, "GPIO66/FANIN2"),
  1137. PINCTRL_PIN(67, "GPIO67/FANIN3"),
  1138. PINCTRL_PIN(68, "GPIO68/FANIN4"),
  1139. PINCTRL_PIN(69, "GPIO69/FANIN5"),
  1140. PINCTRL_PIN(70, "GPIO70/FANIN6"),
  1141. PINCTRL_PIN(71, "GPIO71/FANIN7"),
  1142. PINCTRL_PIN(72, "GPIO72/FANIN8"),
  1143. PINCTRL_PIN(73, "GPIO73/FANIN9"),
  1144. PINCTRL_PIN(74, "GPIO74/FANIN10"),
  1145. PINCTRL_PIN(75, "GPIO75/FANIN11"),
  1146. PINCTRL_PIN(76, "GPIO76/FANIN12"),
  1147. PINCTRL_PIN(77, "GPIO77/FANIN13"),
  1148. PINCTRL_PIN(78, "GPIO78/FANIN14"),
  1149. PINCTRL_PIN(79, "GPIO79/FANIN15"),
  1150. PINCTRL_PIN(80, "GPIO80/PWM0"),
  1151. PINCTRL_PIN(81, "GPIO81/PWM1"),
  1152. PINCTRL_PIN(82, "GPIO82/PWM2"),
  1153. PINCTRL_PIN(83, "GPIO83/PWM3"),
  1154. PINCTRL_PIN(84, "GPIO84/R2TXD0"),
  1155. PINCTRL_PIN(85, "GPIO85/R2TXD1"),
  1156. PINCTRL_PIN(86, "GPIO86/R2TXEN"),
  1157. PINCTRL_PIN(87, "GPIO87/R2RXD0"),
  1158. PINCTRL_PIN(88, "GPIO88/R2RXD1"),
  1159. PINCTRL_PIN(89, "GPIO89/R2CRSDV"),
  1160. PINCTRL_PIN(90, "GPIO90/R2RXERR"),
  1161. PINCTRL_PIN(91, "GPIO91/R2MDC"),
  1162. PINCTRL_PIN(92, "GPIO92/R2MDIO"),
  1163. PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"),
  1164. PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
  1165. PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"),
  1166. PINCTRL_PIN(96, "GPIO96/RG1TXD0"),
  1167. PINCTRL_PIN(97, "GPIO97/RG1TXD1"),
  1168. PINCTRL_PIN(98, "GPIO98/RG1TXD2"),
  1169. PINCTRL_PIN(99, "GPIO99/RG1TXD3"),
  1170. PINCTRL_PIN(100, "GPIO100/RG1TXC"),
  1171. PINCTRL_PIN(101, "GPIO101/RG1TXCTL"),
  1172. PINCTRL_PIN(102, "GPIO102/RG1RXD0"),
  1173. PINCTRL_PIN(103, "GPIO103/RG1RXD1"),
  1174. PINCTRL_PIN(104, "GPIO104/RG1RXD2"),
  1175. PINCTRL_PIN(105, "GPIO105/RG1RXD3"),
  1176. PINCTRL_PIN(106, "GPIO106/RG1RXC"),
  1177. PINCTRL_PIN(107, "GPIO107/RG1RXCTL"),
  1178. PINCTRL_PIN(108, "GPIO108/RG1MDC"),
  1179. PINCTRL_PIN(109, "GPIO109/RG1MDIO"),
  1180. PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
  1181. PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
  1182. PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
  1183. PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
  1184. PINCTRL_PIN(114, "GPIO114/SMB0SCL"),
  1185. PINCTRL_PIN(115, "GPIO115/SMB0SDA"),
  1186. PINCTRL_PIN(116, "GPIO116/SMB1SCL"),
  1187. PINCTRL_PIN(117, "GPIO117/SMB1SDA"),
  1188. PINCTRL_PIN(118, "GPIO118/SMB2SCL"),
  1189. PINCTRL_PIN(119, "GPIO119/SMB2SDA"),
  1190. PINCTRL_PIN(120, "GPIO120/SMB2CSDA"),
  1191. PINCTRL_PIN(121, "GPIO121/SMB2CSCL"),
  1192. PINCTRL_PIN(122, "GPIO122/SMB2BSDA"),
  1193. PINCTRL_PIN(123, "GPIO123/SMB2BSCL"),
  1194. PINCTRL_PIN(124, "GPIO124/SMB1CSDA"),
  1195. PINCTRL_PIN(125, "GPIO125/SMB1CSCL"),
  1196. PINCTRL_PIN(126, "GPIO126/SMB1BSDA"),
  1197. PINCTRL_PIN(127, "GPIO127/SMB1BSCL"),
  1198. PINCTRL_PIN(128, "GPIO128/SMB8SCL"),
  1199. PINCTRL_PIN(129, "GPIO129/SMB8SDA"),
  1200. PINCTRL_PIN(130, "GPIO130/SMB9SCL"),
  1201. PINCTRL_PIN(131, "GPIO131/SMB9SDA"),
  1202. PINCTRL_PIN(132, "GPIO132/SMB10SCL"),
  1203. PINCTRL_PIN(133, "GPIO133/SMB10SDA"),
  1204. PINCTRL_PIN(134, "GPIO134/SMB11SCL"),
  1205. PINCTRL_PIN(135, "GPIO135/SMB11SDA"),
  1206. PINCTRL_PIN(136, "GPIO136/SD1DT0"),
  1207. PINCTRL_PIN(137, "GPIO137/SD1DT1"),
  1208. PINCTRL_PIN(138, "GPIO138/SD1DT2"),
  1209. PINCTRL_PIN(139, "GPIO139/SD1DT3"),
  1210. PINCTRL_PIN(140, "GPIO140/SD1CLK"),
  1211. PINCTRL_PIN(141, "GPIO141/SD1WP"),
  1212. PINCTRL_PIN(142, "GPIO142/SD1CMD"),
  1213. PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"),
  1214. PINCTRL_PIN(144, "GPIO144/PWM4"),
  1215. PINCTRL_PIN(145, "GPIO145/PWM5"),
  1216. PINCTRL_PIN(146, "GPIO146/PWM6"),
  1217. PINCTRL_PIN(147, "GPIO147/PWM7"),
  1218. PINCTRL_PIN(148, "GPIO148/MMCDT4"),
  1219. PINCTRL_PIN(149, "GPIO149/MMCDT5"),
  1220. PINCTRL_PIN(150, "GPIO150/MMCDT6"),
  1221. PINCTRL_PIN(151, "GPIO151/MMCDT7"),
  1222. PINCTRL_PIN(152, "GPIO152/MMCCLK"),
  1223. PINCTRL_PIN(153, "GPIO153/MMCWP"),
  1224. PINCTRL_PIN(154, "GPIO154/MMCCMD"),
  1225. PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
  1226. PINCTRL_PIN(156, "GPIO156/MMCDT0"),
  1227. PINCTRL_PIN(157, "GPIO157/MMCDT1"),
  1228. PINCTRL_PIN(158, "GPIO158/MMCDT2"),
  1229. PINCTRL_PIN(159, "GPIO159/MMCDT3"),
  1230. PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
  1231. PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"),
  1232. PINCTRL_PIN(162, "GPIO162/SERIRQ"),
  1233. PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"),
  1234. PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
  1235. PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
  1236. PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
  1237. PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
  1238. PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
  1239. PINCTRL_PIN(169, "GPIO169/nSCIPME"),
  1240. PINCTRL_PIN(170, "GPIO170/nSMI"),
  1241. PINCTRL_PIN(171, "GPIO171/SMB6SCL"),
  1242. PINCTRL_PIN(172, "GPIO172/SMB6SDA"),
  1243. PINCTRL_PIN(173, "GPIO173/SMB7SCL"),
  1244. PINCTRL_PIN(174, "GPIO174/SMB7SDA"),
  1245. PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
  1246. PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
  1247. PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
  1248. PINCTRL_PIN(178, "GPIO178/R1TXD0"),
  1249. PINCTRL_PIN(179, "GPIO179/R1TXD1"),
  1250. PINCTRL_PIN(180, "GPIO180/R1TXEN"),
  1251. PINCTRL_PIN(181, "GPIO181/R1RXD0"),
  1252. PINCTRL_PIN(182, "GPIO182/R1RXD1"),
  1253. PINCTRL_PIN(183, "GPIO183/SPI3CK"),
  1254. PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"),
  1255. PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"),
  1256. PINCTRL_PIN(186, "GPIO186/nSPI3CS0"),
  1257. PINCTRL_PIN(187, "GPIO187/nSPI3CS1"),
  1258. PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
  1259. PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
  1260. PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
  1261. PINCTRL_PIN(191, "GPIO191"),
  1262. PINCTRL_PIN(192, "GPIO192"),
  1263. PINCTRL_PIN(193, "GPIO193/R1CRSDV"),
  1264. PINCTRL_PIN(194, "GPIO194/SMB0BSCL"),
  1265. PINCTRL_PIN(195, "GPIO195/SMB0BSDA"),
  1266. PINCTRL_PIN(196, "GPIO196/SMB0CSCL"),
  1267. PINCTRL_PIN(197, "GPIO197/SMB0DEN"),
  1268. PINCTRL_PIN(198, "GPIO198/SMB0DSDA"),
  1269. PINCTRL_PIN(199, "GPIO199/SMB0DSCL"),
  1270. PINCTRL_PIN(200, "GPIO200/R2CK"),
  1271. PINCTRL_PIN(201, "GPIO201/R1CK"),
  1272. PINCTRL_PIN(202, "GPIO202/SMB0CSDA"),
  1273. PINCTRL_PIN(203, "GPIO203/FANIN16"),
  1274. PINCTRL_PIN(204, "GPIO204/DDC2SCL"),
  1275. PINCTRL_PIN(205, "GPIO205/DDC2SDA"),
  1276. PINCTRL_PIN(206, "GPIO206/HSYNC2"),
  1277. PINCTRL_PIN(207, "GPIO207/VSYNC2"),
  1278. PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"),
  1279. PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
  1280. PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
  1281. PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
  1282. PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
  1283. PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
  1284. PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"),
  1285. PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
  1286. PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"),
  1287. PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
  1288. PINCTRL_PIN(218, "GPIO218/nWDO1"),
  1289. PINCTRL_PIN(219, "GPIO219/nWDO2"),
  1290. PINCTRL_PIN(220, "GPIO220/SMB12SCL"),
  1291. PINCTRL_PIN(221, "GPIO221/SMB12SDA"),
  1292. PINCTRL_PIN(222, "GPIO222/SMB13SCL"),
  1293. PINCTRL_PIN(223, "GPIO223/SMB13SDA"),
  1294. PINCTRL_PIN(224, "GPIO224/SPIXCK"),
  1295. PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"),
  1296. PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"),
  1297. PINCTRL_PIN(227, "GPIO227/nSPIXCS0"),
  1298. PINCTRL_PIN(228, "GPIO228/nSPIXCS1"),
  1299. PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"),
  1300. PINCTRL_PIN(230, "GPIO230/SPIXD3"),
  1301. PINCTRL_PIN(231, "GPIO231/nCLKREQ"),
  1302. PINCTRL_PIN(255, "GPI255/DACOSEL"),
  1303. };
  1304. /* Enable mode in pin group */
  1305. static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
  1306. int pin_number, int mode)
  1307. {
  1308. const struct npcm7xx_pincfg *cfg;
  1309. int i;
  1310. for (i = 0 ; i < pin_number ; i++) {
  1311. cfg = &pincfg[pin[i]];
  1312. if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
  1313. if (cfg->reg0)
  1314. regmap_update_bits(gcr_regmap, cfg->reg0,
  1315. BIT(cfg->bit0),
  1316. !!(cfg->fn0 == mode) ?
  1317. BIT(cfg->bit0) : 0);
  1318. if (cfg->reg1)
  1319. regmap_update_bits(gcr_regmap, cfg->reg1,
  1320. BIT(cfg->bit1),
  1321. !!(cfg->fn1 == mode) ?
  1322. BIT(cfg->bit1) : 0);
  1323. if (cfg->reg2)
  1324. regmap_update_bits(gcr_regmap, cfg->reg2,
  1325. BIT(cfg->bit2),
  1326. !!(cfg->fn2 == mode) ?
  1327. BIT(cfg->bit2) : 0);
  1328. }
  1329. }
  1330. }
  1331. /* Get slew rate of pin (high/low) */
  1332. static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,
  1333. struct regmap *gcr_regmap, unsigned int pin)
  1334. {
  1335. u32 val;
  1336. int gpio = (pin % bank->gc.ngpio);
  1337. unsigned long pinmask = BIT(gpio);
  1338. if (pincfg[pin].flag & SLEW)
  1339. return ioread32(bank->base + NPCM7XX_GP_N_OSRC)
  1340. & pinmask;
  1341. /* LPC Slew rate in SRCNT register */
  1342. if (pincfg[pin].flag & SLEWLPC) {
  1343. regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val);
  1344. return !!(val & SRCNT_ESPI);
  1345. }
  1346. return -EINVAL;
  1347. }
  1348. /* Set slew rate of pin (high/low) */
  1349. static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,
  1350. struct regmap *gcr_regmap, unsigned int pin,
  1351. int arg)
  1352. {
  1353. int gpio = BIT(pin % bank->gc.ngpio);
  1354. if (pincfg[pin].flag & SLEW) {
  1355. switch (arg) {
  1356. case 0:
  1357. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
  1358. gpio);
  1359. return 0;
  1360. case 1:
  1361. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
  1362. gpio);
  1363. return 0;
  1364. default:
  1365. return -EINVAL;
  1366. }
  1367. }
  1368. /* LPC Slew rate in SRCNT register */
  1369. if (pincfg[pin].flag & SLEWLPC) {
  1370. switch (arg) {
  1371. case 0:
  1372. regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
  1373. SRCNT_ESPI, 0);
  1374. return 0;
  1375. case 1:
  1376. regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
  1377. SRCNT_ESPI, SRCNT_ESPI);
  1378. return 0;
  1379. default:
  1380. return -EINVAL;
  1381. }
  1382. }
  1383. return -EINVAL;
  1384. }
  1385. /* Get drive strength for a pin, if supported */
  1386. static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev,
  1387. unsigned int pin)
  1388. {
  1389. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1390. struct npcm7xx_gpio *bank =
  1391. &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
  1392. int gpio = (pin % bank->gc.ngpio);
  1393. unsigned long pinmask = BIT(gpio);
  1394. u32 ds = 0;
  1395. int flg, val;
  1396. flg = pincfg[pin].flag;
  1397. if (flg & DRIVE_STRENGTH_MASK) {
  1398. /* Get standard reading */
  1399. val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)
  1400. & pinmask;
  1401. ds = val ? DSHI(flg) : DSLO(flg);
  1402. dev_dbg(bank->gc.parent,
  1403. "pin %d strength %d = %d\n", pin, val, ds);
  1404. return ds;
  1405. }
  1406. return -EINVAL;
  1407. }
  1408. /* Set drive strength for a pin, if supported */
  1409. static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm,
  1410. unsigned int pin, int nval)
  1411. {
  1412. int v;
  1413. struct npcm7xx_gpio *bank =
  1414. &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
  1415. int gpio = BIT(pin % bank->gc.ngpio);
  1416. v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK);
  1417. if (!nval || !v)
  1418. return -ENOTSUPP;
  1419. if (DSLO(v) == nval) {
  1420. dev_dbg(bank->gc.parent,
  1421. "setting pin %d to low strength [%d]\n", pin, nval);
  1422. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
  1423. return 0;
  1424. } else if (DSHI(v) == nval) {
  1425. dev_dbg(bank->gc.parent,
  1426. "setting pin %d to high strength [%d]\n", pin, nval);
  1427. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
  1428. return 0;
  1429. }
  1430. return -ENOTSUPP;
  1431. }
  1432. /* pinctrl_ops */
  1433. static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev,
  1434. struct seq_file *s, unsigned int offset)
  1435. {
  1436. seq_printf(s, "pinctrl_ops.dbg: %d", offset);
  1437. }
  1438. static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)
  1439. {
  1440. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1441. dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));
  1442. return ARRAY_SIZE(npcm7xx_groups);
  1443. }
  1444. static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev,
  1445. unsigned int selector)
  1446. {
  1447. return npcm7xx_groups[selector].name;
  1448. }
  1449. static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,
  1450. unsigned int selector,
  1451. const unsigned int **pins,
  1452. unsigned int *npins)
  1453. {
  1454. *npins = npcm7xx_groups[selector].npins;
  1455. *pins = npcm7xx_groups[selector].pins;
  1456. return 0;
  1457. }
  1458. static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev,
  1459. struct device_node *np_config,
  1460. struct pinctrl_map **map,
  1461. u32 *num_maps)
  1462. {
  1463. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1464. dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name);
  1465. return pinconf_generic_dt_node_to_map(pctldev, np_config,
  1466. map, num_maps,
  1467. PIN_MAP_TYPE_INVALID);
  1468. }
  1469. static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,
  1470. struct pinctrl_map *map, u32 num_maps)
  1471. {
  1472. kfree(map);
  1473. }
  1474. static const struct pinctrl_ops npcm7xx_pinctrl_ops = {
  1475. .get_groups_count = npcm7xx_get_groups_count,
  1476. .get_group_name = npcm7xx_get_group_name,
  1477. .get_group_pins = npcm7xx_get_group_pins,
  1478. .pin_dbg_show = npcm7xx_pin_dbg_show,
  1479. .dt_node_to_map = npcm7xx_dt_node_to_map,
  1480. .dt_free_map = npcm7xx_dt_free_map,
  1481. };
  1482. /* pinmux_ops */
  1483. static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev)
  1484. {
  1485. return ARRAY_SIZE(npcm7xx_funcs);
  1486. }
  1487. static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev,
  1488. unsigned int function)
  1489. {
  1490. return npcm7xx_funcs[function].name;
  1491. }
  1492. static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev,
  1493. unsigned int function,
  1494. const char * const **groups,
  1495. unsigned int * const ngroups)
  1496. {
  1497. *ngroups = npcm7xx_funcs[function].ngroups;
  1498. *groups = npcm7xx_funcs[function].groups;
  1499. return 0;
  1500. }
  1501. static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
  1502. unsigned int function,
  1503. unsigned int group)
  1504. {
  1505. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1506. dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group,
  1507. npcm7xx_groups[group].name);
  1508. npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins,
  1509. npcm7xx_groups[group].npins, group);
  1510. return 0;
  1511. }
  1512. static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev,
  1513. struct pinctrl_gpio_range *range,
  1514. unsigned int offset)
  1515. {
  1516. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1517. if (!range) {
  1518. dev_err(npcm->dev, "invalid range\n");
  1519. return -EINVAL;
  1520. }
  1521. if (!range->gc) {
  1522. dev_err(npcm->dev, "invalid gpiochip\n");
  1523. return -EINVAL;
  1524. }
  1525. npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio);
  1526. return 0;
  1527. }
  1528. /* Release GPIO back to pinctrl mode */
  1529. static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev,
  1530. struct pinctrl_gpio_range *range,
  1531. unsigned int offset)
  1532. {
  1533. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1534. int virq;
  1535. virq = irq_find_mapping(npcm->domain, offset);
  1536. if (virq)
  1537. irq_dispose_mapping(virq);
  1538. }
  1539. /* Set GPIO direction */
  1540. static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
  1541. struct pinctrl_gpio_range *range,
  1542. unsigned int offset, bool input)
  1543. {
  1544. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1545. struct npcm7xx_gpio *bank =
  1546. &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];
  1547. int gpio = BIT(offset % bank->gc.ngpio);
  1548. dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset,
  1549. input);
  1550. if (input)
  1551. iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
  1552. else
  1553. iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
  1554. return 0;
  1555. }
  1556. static const struct pinmux_ops npcm7xx_pinmux_ops = {
  1557. .get_functions_count = npcm7xx_get_functions_count,
  1558. .get_function_name = npcm7xx_get_function_name,
  1559. .get_function_groups = npcm7xx_get_function_groups,
  1560. .set_mux = npcm7xx_pinmux_set_mux,
  1561. .gpio_request_enable = npcm7xx_gpio_request_enable,
  1562. .gpio_disable_free = npcm7xx_gpio_request_free,
  1563. .gpio_set_direction = npcm_gpio_set_direction,
  1564. };
  1565. /* pinconf_ops */
  1566. static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
  1567. unsigned long *config)
  1568. {
  1569. enum pin_config_param param = pinconf_to_config_param(*config);
  1570. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1571. struct npcm7xx_gpio *bank =
  1572. &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
  1573. int gpio = (pin % bank->gc.ngpio);
  1574. unsigned long pinmask = BIT(gpio);
  1575. u32 ie, oe, pu, pd;
  1576. int rc = 0;
  1577. switch (param) {
  1578. case PIN_CONFIG_BIAS_DISABLE:
  1579. case PIN_CONFIG_BIAS_PULL_UP:
  1580. case PIN_CONFIG_BIAS_PULL_DOWN:
  1581. pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;
  1582. pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;
  1583. if (param == PIN_CONFIG_BIAS_DISABLE)
  1584. rc = (!pu && !pd);
  1585. else if (param == PIN_CONFIG_BIAS_PULL_UP)
  1586. rc = (pu && !pd);
  1587. else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
  1588. rc = (!pu && pd);
  1589. break;
  1590. case PIN_CONFIG_OUTPUT:
  1591. case PIN_CONFIG_INPUT_ENABLE:
  1592. ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
  1593. oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
  1594. if (param == PIN_CONFIG_INPUT_ENABLE)
  1595. rc = (ie && !oe);
  1596. else if (param == PIN_CONFIG_OUTPUT)
  1597. rc = (!ie && oe);
  1598. break;
  1599. case PIN_CONFIG_DRIVE_PUSH_PULL:
  1600. rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);
  1601. break;
  1602. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  1603. rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;
  1604. break;
  1605. case PIN_CONFIG_INPUT_DEBOUNCE:
  1606. rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;
  1607. break;
  1608. case PIN_CONFIG_DRIVE_STRENGTH:
  1609. rc = npcm7xx_get_drive_strength(pctldev, pin);
  1610. if (rc)
  1611. *config = pinconf_to_config_packed(param, rc);
  1612. break;
  1613. case PIN_CONFIG_SLEW_RATE:
  1614. rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
  1615. if (rc >= 0)
  1616. *config = pinconf_to_config_packed(param, rc);
  1617. break;
  1618. default:
  1619. return -ENOTSUPP;
  1620. }
  1621. if (!rc)
  1622. return -EINVAL;
  1623. return 0;
  1624. }
  1625. static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
  1626. unsigned int pin, unsigned long config)
  1627. {
  1628. enum pin_config_param param = pinconf_to_config_param(config);
  1629. u16 arg = pinconf_to_config_argument(config);
  1630. struct npcm7xx_gpio *bank =
  1631. &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
  1632. int gpio = BIT(pin % bank->gc.ngpio);
  1633. dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin);
  1634. switch (param) {
  1635. case PIN_CONFIG_BIAS_DISABLE:
  1636. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
  1637. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
  1638. break;
  1639. case PIN_CONFIG_BIAS_PULL_DOWN:
  1640. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
  1641. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
  1642. break;
  1643. case PIN_CONFIG_BIAS_PULL_UP:
  1644. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
  1645. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
  1646. break;
  1647. case PIN_CONFIG_INPUT_ENABLE:
  1648. iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
  1649. bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
  1650. break;
  1651. case PIN_CONFIG_OUTPUT:
  1652. iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
  1653. bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
  1654. break;
  1655. case PIN_CONFIG_DRIVE_PUSH_PULL:
  1656. npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
  1657. break;
  1658. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  1659. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
  1660. break;
  1661. case PIN_CONFIG_INPUT_DEBOUNCE:
  1662. npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);
  1663. break;
  1664. case PIN_CONFIG_SLEW_RATE:
  1665. return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
  1666. case PIN_CONFIG_DRIVE_STRENGTH:
  1667. return npcm7xx_set_drive_strength(npcm, pin, arg);
  1668. default:
  1669. return -ENOTSUPP;
  1670. }
  1671. return 0;
  1672. }
  1673. /* Set multiple configuration settings for a pin */
  1674. static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
  1675. unsigned long *configs, unsigned int num_configs)
  1676. {
  1677. struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
  1678. int rc;
  1679. while (num_configs--) {
  1680. rc = npcm7xx_config_set_one(npcm, pin, *configs++);
  1681. if (rc)
  1682. return rc;
  1683. }
  1684. return 0;
  1685. }
  1686. static const struct pinconf_ops npcm7xx_pinconf_ops = {
  1687. .is_generic = true,
  1688. .pin_config_get = npcm7xx_config_get,
  1689. .pin_config_set = npcm7xx_config_set,
  1690. };
  1691. /* pinctrl_desc */
  1692. static struct pinctrl_desc npcm7xx_pinctrl_desc = {
  1693. .name = "npcm7xx-pinctrl",
  1694. .pins = npcm7xx_pins,
  1695. .npins = ARRAY_SIZE(npcm7xx_pins),
  1696. .pctlops = &npcm7xx_pinctrl_ops,
  1697. .pmxops = &npcm7xx_pinmux_ops,
  1698. .confops = &npcm7xx_pinconf_ops,
  1699. .owner = THIS_MODULE,
  1700. };
  1701. static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
  1702. {
  1703. int ret = -ENXIO;
  1704. struct resource res;
  1705. int id = 0, irq;
  1706. struct device_node *np;
  1707. struct of_phandle_args pinspec;
  1708. for_each_available_child_of_node(pctrl->dev->of_node, np)
  1709. if (of_find_property(np, "gpio-controller", NULL)) {
  1710. ret = of_address_to_resource(np, 0, &res);
  1711. if (ret < 0) {
  1712. dev_err(pctrl->dev,
  1713. "Resource fail for GPIO bank %u\n", id);
  1714. return ret;
  1715. }
  1716. pctrl->gpio_bank[id].base =
  1717. ioremap(res.start, resource_size(&res));
  1718. irq = irq_of_parse_and_map(np, 0);
  1719. if (irq < 0) {
  1720. dev_err(pctrl->dev,
  1721. "No IRQ for GPIO bank %u\n", id);
  1722. ret = irq;
  1723. return ret;
  1724. }
  1725. ret = bgpio_init(&pctrl->gpio_bank[id].gc,
  1726. pctrl->dev, 4,
  1727. pctrl->gpio_bank[id].base +
  1728. NPCM7XX_GP_N_DIN,
  1729. pctrl->gpio_bank[id].base +
  1730. NPCM7XX_GP_N_DOUT,
  1731. NULL,
  1732. NULL,
  1733. pctrl->gpio_bank[id].base +
  1734. NPCM7XX_GP_N_IEM,
  1735. BGPIOF_READ_OUTPUT_REG_SET);
  1736. if (ret) {
  1737. dev_err(pctrl->dev, "bgpio_init() failed\n");
  1738. return ret;
  1739. }
  1740. ret = of_parse_phandle_with_fixed_args(np,
  1741. "gpio-ranges", 3,
  1742. 0, &pinspec);
  1743. if (ret < 0) {
  1744. dev_err(pctrl->dev,
  1745. "gpio-ranges fail for GPIO bank %u\n",
  1746. id);
  1747. return ret;
  1748. }
  1749. pctrl->gpio_bank[id].irq = irq;
  1750. pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
  1751. pctrl->gpio_bank[id].gc.parent = pctrl->dev;
  1752. pctrl->gpio_bank[id].irqbase =
  1753. id * NPCM7XX_GPIO_PER_BANK;
  1754. pctrl->gpio_bank[id].pinctrl_id = pinspec.args[0];
  1755. pctrl->gpio_bank[id].gc.base = pinspec.args[1];
  1756. pctrl->gpio_bank[id].gc.ngpio = pinspec.args[2];
  1757. pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
  1758. pctrl->gpio_bank[id].gc.label =
  1759. devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOF",
  1760. np);
  1761. if (pctrl->gpio_bank[id].gc.label == NULL)
  1762. return -ENOMEM;
  1763. pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
  1764. pctrl->gpio_bank[id].direction_input =
  1765. pctrl->gpio_bank[id].gc.direction_input;
  1766. pctrl->gpio_bank[id].gc.direction_input =
  1767. npcmgpio_direction_input;
  1768. pctrl->gpio_bank[id].direction_output =
  1769. pctrl->gpio_bank[id].gc.direction_output;
  1770. pctrl->gpio_bank[id].gc.direction_output =
  1771. npcmgpio_direction_output;
  1772. pctrl->gpio_bank[id].request =
  1773. pctrl->gpio_bank[id].gc.request;
  1774. pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
  1775. pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
  1776. pctrl->gpio_bank[id].gc.of_node = np;
  1777. id++;
  1778. }
  1779. pctrl->bank_num = id;
  1780. return ret;
  1781. }
  1782. static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl)
  1783. {
  1784. int ret, id;
  1785. for (id = 0 ; id < pctrl->bank_num ; id++) {
  1786. struct gpio_irq_chip *girq;
  1787. girq = &pctrl->gpio_bank[id].gc.irq;
  1788. girq->chip = &pctrl->gpio_bank[id].irq_chip;
  1789. girq->parent_handler = npcmgpio_irq_handler;
  1790. girq->num_parents = 1;
  1791. girq->parents = devm_kcalloc(pctrl->dev, 1,
  1792. sizeof(*girq->parents),
  1793. GFP_KERNEL);
  1794. if (!girq->parents) {
  1795. ret = -ENOMEM;
  1796. goto err_register;
  1797. }
  1798. girq->parents[0] = pctrl->gpio_bank[id].irq;
  1799. girq->default_type = IRQ_TYPE_NONE;
  1800. girq->handler = handle_level_irq;
  1801. ret = devm_gpiochip_add_data(pctrl->dev,
  1802. &pctrl->gpio_bank[id].gc,
  1803. &pctrl->gpio_bank[id]);
  1804. if (ret) {
  1805. dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id);
  1806. goto err_register;
  1807. }
  1808. ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc,
  1809. dev_name(pctrl->dev),
  1810. pctrl->gpio_bank[id].pinctrl_id,
  1811. pctrl->gpio_bank[id].gc.base,
  1812. pctrl->gpio_bank[id].gc.ngpio);
  1813. if (ret < 0) {
  1814. dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id);
  1815. gpiochip_remove(&pctrl->gpio_bank[id].gc);
  1816. goto err_register;
  1817. }
  1818. }
  1819. return 0;
  1820. err_register:
  1821. for (; id > 0; id--)
  1822. gpiochip_remove(&pctrl->gpio_bank[id - 1].gc);
  1823. return ret;
  1824. }
  1825. static int npcm7xx_pinctrl_probe(struct platform_device *pdev)
  1826. {
  1827. struct npcm7xx_pinctrl *pctrl;
  1828. int ret;
  1829. pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
  1830. if (!pctrl)
  1831. return -ENOMEM;
  1832. pctrl->dev = &pdev->dev;
  1833. dev_set_drvdata(&pdev->dev, pctrl);
  1834. pctrl->gcr_regmap =
  1835. syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
  1836. if (IS_ERR(pctrl->gcr_regmap)) {
  1837. dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n");
  1838. return PTR_ERR(pctrl->gcr_regmap);
  1839. }
  1840. ret = npcm7xx_gpio_of(pctrl);
  1841. if (ret < 0) {
  1842. dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);
  1843. return ret;
  1844. }
  1845. pctrl->pctldev = devm_pinctrl_register(&pdev->dev,
  1846. &npcm7xx_pinctrl_desc, pctrl);
  1847. if (IS_ERR(pctrl->pctldev)) {
  1848. dev_err(&pdev->dev, "Failed to register pinctrl device\n");
  1849. return PTR_ERR(pctrl->pctldev);
  1850. }
  1851. ret = npcm7xx_gpio_register(pctrl);
  1852. if (ret < 0) {
  1853. dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);
  1854. return ret;
  1855. }
  1856. pr_info("NPCM7xx Pinctrl driver probed\n");
  1857. return 0;
  1858. }
  1859. static const struct of_device_id npcm7xx_pinctrl_match[] = {
  1860. { .compatible = "nuvoton,npcm750-pinctrl" },
  1861. { },
  1862. };
  1863. MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match);
  1864. static struct platform_driver npcm7xx_pinctrl_driver = {
  1865. .probe = npcm7xx_pinctrl_probe,
  1866. .driver = {
  1867. .name = "npcm7xx-pinctrl",
  1868. .of_match_table = npcm7xx_pinctrl_match,
  1869. .suppress_bind_attrs = true,
  1870. },
  1871. };
  1872. static int __init npcm7xx_pinctrl_register(void)
  1873. {
  1874. return platform_driver_register(&npcm7xx_pinctrl_driver);
  1875. }
  1876. arch_initcall(npcm7xx_pinctrl_register);
  1877. MODULE_LICENSE("GPL v2");
  1878. MODULE_AUTHOR("jordan_hargrave@dell.com");
  1879. MODULE_AUTHOR("tomer.maimon@nuvoton.com");
  1880. MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver");