pinctrl-meson.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Pin controller and GPIO driver for Amlogic Meson SoCs
  4. *
  5. * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
  6. */
  7. /*
  8. * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
  9. * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
  10. * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
  11. * variable number of pins.
  12. *
  13. * The AO bank is special because it belongs to the Always-On power
  14. * domain which can't be powered off; the bank also uses a set of
  15. * registers different from the other banks.
  16. *
  17. * For each pin controller there are 4 different register ranges that
  18. * control the following properties of the pins:
  19. * 1) pin muxing
  20. * 2) pull enable/disable
  21. * 3) pull up/down
  22. * 4) GPIO direction, output value, input value
  23. *
  24. * In some cases the register ranges for pull enable and pull
  25. * direction are the same and thus there are only 3 register ranges.
  26. *
  27. * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
  28. * and pull direction are the same, so there are only 2 register ranges.
  29. *
  30. * For the pull and GPIO configuration every bank uses a contiguous
  31. * set of bits in the register sets described above; the same register
  32. * can be shared by more banks with different offsets.
  33. *
  34. * In addition to this there are some registers shared between all
  35. * banks that control the IRQ functionality. This feature is not
  36. * supported at the moment by the driver.
  37. */
  38. #include <linux/device.h>
  39. #include <linux/gpio/driver.h>
  40. #include <linux/init.h>
  41. #include <linux/io.h>
  42. #include <linux/of.h>
  43. #include <linux/of_address.h>
  44. #include <linux/of_device.h>
  45. #include <linux/pinctrl/pinconf-generic.h>
  46. #include <linux/pinctrl/pinconf.h>
  47. #include <linux/pinctrl/pinctrl.h>
  48. #include <linux/pinctrl/pinmux.h>
  49. #include <linux/platform_device.h>
  50. #include <linux/regmap.h>
  51. #include <linux/seq_file.h>
  52. #include "../core.h"
  53. #include "../pinctrl-utils.h"
  54. #include "pinctrl-meson.h"
  55. static const unsigned int meson_bit_strides[] = {
  56. 1, 1, 1, 1, 1, 2, 1
  57. };
  58. /**
  59. * meson_get_bank() - find the bank containing a given pin
  60. *
  61. * @pc: the pinctrl instance
  62. * @pin: the pin number
  63. * @bank: the found bank
  64. *
  65. * Return: 0 on success, a negative value on error
  66. */
  67. static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
  68. struct meson_bank **bank)
  69. {
  70. int i;
  71. for (i = 0; i < pc->data->num_banks; i++) {
  72. if (pin >= pc->data->banks[i].first &&
  73. pin <= pc->data->banks[i].last) {
  74. *bank = &pc->data->banks[i];
  75. return 0;
  76. }
  77. }
  78. return -EINVAL;
  79. }
  80. /**
  81. * meson_calc_reg_and_bit() - calculate register and bit for a pin
  82. *
  83. * @bank: the bank containing the pin
  84. * @pin: the pin number
  85. * @reg_type: the type of register needed (pull-enable, pull, etc...)
  86. * @reg: the computed register offset
  87. * @bit: the computed bit
  88. */
  89. static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
  90. enum meson_reg_type reg_type,
  91. unsigned int *reg, unsigned int *bit)
  92. {
  93. struct meson_reg_desc *desc = &bank->regs[reg_type];
  94. *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];
  95. *reg = (desc->reg + (*bit / 32)) * 4;
  96. *bit &= 0x1f;
  97. }
  98. static int meson_get_groups_count(struct pinctrl_dev *pcdev)
  99. {
  100. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  101. return pc->data->num_groups;
  102. }
  103. static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
  104. unsigned selector)
  105. {
  106. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  107. return pc->data->groups[selector].name;
  108. }
  109. static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
  110. const unsigned **pins, unsigned *num_pins)
  111. {
  112. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  113. *pins = pc->data->groups[selector].pins;
  114. *num_pins = pc->data->groups[selector].num_pins;
  115. return 0;
  116. }
  117. static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
  118. unsigned offset)
  119. {
  120. seq_printf(s, " %s", dev_name(pcdev->dev));
  121. }
  122. static const struct pinctrl_ops meson_pctrl_ops = {
  123. .get_groups_count = meson_get_groups_count,
  124. .get_group_name = meson_get_group_name,
  125. .get_group_pins = meson_get_group_pins,
  126. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  127. .dt_free_map = pinctrl_utils_free_map,
  128. .pin_dbg_show = meson_pin_dbg_show,
  129. };
  130. int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
  131. {
  132. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  133. return pc->data->num_funcs;
  134. }
  135. EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count);
  136. const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
  137. unsigned selector)
  138. {
  139. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  140. return pc->data->funcs[selector].name;
  141. }
  142. EXPORT_SYMBOL_GPL(meson_pmx_get_func_name);
  143. int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
  144. const char * const **groups,
  145. unsigned * const num_groups)
  146. {
  147. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  148. *groups = pc->data->funcs[selector].groups;
  149. *num_groups = pc->data->funcs[selector].num_groups;
  150. return 0;
  151. }
  152. EXPORT_SYMBOL_GPL(meson_pmx_get_groups);
  153. static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
  154. unsigned int pin,
  155. unsigned int reg_type,
  156. bool arg)
  157. {
  158. struct meson_bank *bank;
  159. unsigned int reg, bit;
  160. int ret;
  161. ret = meson_get_bank(pc, pin, &bank);
  162. if (ret)
  163. return ret;
  164. meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
  165. return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
  166. arg ? BIT(bit) : 0);
  167. }
  168. static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc,
  169. unsigned int pin,
  170. unsigned int reg_type)
  171. {
  172. struct meson_bank *bank;
  173. unsigned int reg, bit, val;
  174. int ret;
  175. ret = meson_get_bank(pc, pin, &bank);
  176. if (ret)
  177. return ret;
  178. meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
  179. ret = regmap_read(pc->reg_gpio, reg, &val);
  180. if (ret)
  181. return ret;
  182. return BIT(bit) & val ? 1 : 0;
  183. }
  184. static int meson_pinconf_set_output(struct meson_pinctrl *pc,
  185. unsigned int pin,
  186. bool out)
  187. {
  188. return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out);
  189. }
  190. static int meson_pinconf_get_output(struct meson_pinctrl *pc,
  191. unsigned int pin)
  192. {
  193. int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR);
  194. if (ret < 0)
  195. return ret;
  196. return !ret;
  197. }
  198. static int meson_pinconf_set_drive(struct meson_pinctrl *pc,
  199. unsigned int pin,
  200. bool high)
  201. {
  202. return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high);
  203. }
  204. static int meson_pinconf_get_drive(struct meson_pinctrl *pc,
  205. unsigned int pin)
  206. {
  207. return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT);
  208. }
  209. static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc,
  210. unsigned int pin,
  211. bool high)
  212. {
  213. int ret;
  214. ret = meson_pinconf_set_output(pc, pin, true);
  215. if (ret)
  216. return ret;
  217. return meson_pinconf_set_drive(pc, pin, high);
  218. }
  219. static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
  220. unsigned int pin)
  221. {
  222. struct meson_bank *bank;
  223. unsigned int reg, bit = 0;
  224. int ret;
  225. ret = meson_get_bank(pc, pin, &bank);
  226. if (ret)
  227. return ret;
  228. meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
  229. ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0);
  230. if (ret)
  231. return ret;
  232. return 0;
  233. }
  234. static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
  235. bool pull_up)
  236. {
  237. struct meson_bank *bank;
  238. unsigned int reg, bit, val = 0;
  239. int ret;
  240. ret = meson_get_bank(pc, pin, &bank);
  241. if (ret)
  242. return ret;
  243. meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
  244. if (pull_up)
  245. val = BIT(bit);
  246. ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val);
  247. if (ret)
  248. return ret;
  249. meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
  250. ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit));
  251. if (ret)
  252. return ret;
  253. return 0;
  254. }
  255. static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc,
  256. unsigned int pin,
  257. u16 drive_strength_ua)
  258. {
  259. struct meson_bank *bank;
  260. unsigned int reg, bit, ds_val;
  261. int ret;
  262. if (!pc->reg_ds) {
  263. dev_err(pc->dev, "drive-strength not supported\n");
  264. return -ENOTSUPP;
  265. }
  266. ret = meson_get_bank(pc, pin, &bank);
  267. if (ret)
  268. return ret;
  269. meson_calc_reg_and_bit(bank, pin, REG_DS, &reg, &bit);
  270. if (drive_strength_ua <= 500) {
  271. ds_val = MESON_PINCONF_DRV_500UA;
  272. } else if (drive_strength_ua <= 2500) {
  273. ds_val = MESON_PINCONF_DRV_2500UA;
  274. } else if (drive_strength_ua <= 3000) {
  275. ds_val = MESON_PINCONF_DRV_3000UA;
  276. } else if (drive_strength_ua <= 4000) {
  277. ds_val = MESON_PINCONF_DRV_4000UA;
  278. } else {
  279. dev_warn_once(pc->dev,
  280. "pin %u: invalid drive-strength : %d , default to 4mA\n",
  281. pin, drive_strength_ua);
  282. ds_val = MESON_PINCONF_DRV_4000UA;
  283. }
  284. ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit);
  285. if (ret)
  286. return ret;
  287. return 0;
  288. }
  289. static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
  290. unsigned long *configs, unsigned num_configs)
  291. {
  292. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  293. enum pin_config_param param;
  294. unsigned int arg = 0;
  295. int i, ret;
  296. for (i = 0; i < num_configs; i++) {
  297. param = pinconf_to_config_param(configs[i]);
  298. switch (param) {
  299. case PIN_CONFIG_DRIVE_STRENGTH_UA:
  300. case PIN_CONFIG_OUTPUT_ENABLE:
  301. case PIN_CONFIG_OUTPUT:
  302. arg = pinconf_to_config_argument(configs[i]);
  303. break;
  304. default:
  305. break;
  306. }
  307. switch (param) {
  308. case PIN_CONFIG_BIAS_DISABLE:
  309. ret = meson_pinconf_disable_bias(pc, pin);
  310. break;
  311. case PIN_CONFIG_BIAS_PULL_UP:
  312. ret = meson_pinconf_enable_bias(pc, pin, true);
  313. break;
  314. case PIN_CONFIG_BIAS_PULL_DOWN:
  315. ret = meson_pinconf_enable_bias(pc, pin, false);
  316. break;
  317. case PIN_CONFIG_DRIVE_STRENGTH_UA:
  318. ret = meson_pinconf_set_drive_strength(pc, pin, arg);
  319. break;
  320. case PIN_CONFIG_OUTPUT_ENABLE:
  321. ret = meson_pinconf_set_output(pc, pin, arg);
  322. break;
  323. case PIN_CONFIG_OUTPUT:
  324. ret = meson_pinconf_set_output_drive(pc, pin, arg);
  325. break;
  326. default:
  327. ret = -ENOTSUPP;
  328. }
  329. if (ret)
  330. return ret;
  331. }
  332. return 0;
  333. }
  334. static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
  335. {
  336. struct meson_bank *bank;
  337. unsigned int reg, bit, val;
  338. int ret, conf;
  339. ret = meson_get_bank(pc, pin, &bank);
  340. if (ret)
  341. return ret;
  342. meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
  343. ret = regmap_read(pc->reg_pullen, reg, &val);
  344. if (ret)
  345. return ret;
  346. if (!(val & BIT(bit))) {
  347. conf = PIN_CONFIG_BIAS_DISABLE;
  348. } else {
  349. meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
  350. ret = regmap_read(pc->reg_pull, reg, &val);
  351. if (ret)
  352. return ret;
  353. if (val & BIT(bit))
  354. conf = PIN_CONFIG_BIAS_PULL_UP;
  355. else
  356. conf = PIN_CONFIG_BIAS_PULL_DOWN;
  357. }
  358. return conf;
  359. }
  360. static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc,
  361. unsigned int pin,
  362. u16 *drive_strength_ua)
  363. {
  364. struct meson_bank *bank;
  365. unsigned int reg, bit;
  366. unsigned int val;
  367. int ret;
  368. if (!pc->reg_ds)
  369. return -ENOTSUPP;
  370. ret = meson_get_bank(pc, pin, &bank);
  371. if (ret)
  372. return ret;
  373. meson_calc_reg_and_bit(bank, pin, REG_DS, &reg, &bit);
  374. ret = regmap_read(pc->reg_ds, reg, &val);
  375. if (ret)
  376. return ret;
  377. switch ((val >> bit) & 0x3) {
  378. case MESON_PINCONF_DRV_500UA:
  379. *drive_strength_ua = 500;
  380. break;
  381. case MESON_PINCONF_DRV_2500UA:
  382. *drive_strength_ua = 2500;
  383. break;
  384. case MESON_PINCONF_DRV_3000UA:
  385. *drive_strength_ua = 3000;
  386. break;
  387. case MESON_PINCONF_DRV_4000UA:
  388. *drive_strength_ua = 4000;
  389. break;
  390. default:
  391. return -EINVAL;
  392. }
  393. return 0;
  394. }
  395. static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
  396. unsigned long *config)
  397. {
  398. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  399. enum pin_config_param param = pinconf_to_config_param(*config);
  400. u16 arg;
  401. int ret;
  402. switch (param) {
  403. case PIN_CONFIG_BIAS_DISABLE:
  404. case PIN_CONFIG_BIAS_PULL_DOWN:
  405. case PIN_CONFIG_BIAS_PULL_UP:
  406. if (meson_pinconf_get_pull(pc, pin) == param)
  407. arg = 1;
  408. else
  409. return -EINVAL;
  410. break;
  411. case PIN_CONFIG_DRIVE_STRENGTH_UA:
  412. ret = meson_pinconf_get_drive_strength(pc, pin, &arg);
  413. if (ret)
  414. return ret;
  415. break;
  416. case PIN_CONFIG_OUTPUT_ENABLE:
  417. ret = meson_pinconf_get_output(pc, pin);
  418. if (ret <= 0)
  419. return -EINVAL;
  420. arg = 1;
  421. break;
  422. case PIN_CONFIG_OUTPUT:
  423. ret = meson_pinconf_get_output(pc, pin);
  424. if (ret <= 0)
  425. return -EINVAL;
  426. ret = meson_pinconf_get_drive(pc, pin);
  427. if (ret < 0)
  428. return -EINVAL;
  429. arg = ret;
  430. break;
  431. default:
  432. return -ENOTSUPP;
  433. }
  434. *config = pinconf_to_config_packed(param, arg);
  435. dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
  436. return 0;
  437. }
  438. static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
  439. unsigned int num_group,
  440. unsigned long *configs, unsigned num_configs)
  441. {
  442. struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
  443. struct meson_pmx_group *group = &pc->data->groups[num_group];
  444. int i;
  445. dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
  446. for (i = 0; i < group->num_pins; i++) {
  447. meson_pinconf_set(pcdev, group->pins[i], configs,
  448. num_configs);
  449. }
  450. return 0;
  451. }
  452. static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
  453. unsigned int group, unsigned long *config)
  454. {
  455. return -ENOTSUPP;
  456. }
  457. static const struct pinconf_ops meson_pinconf_ops = {
  458. .pin_config_get = meson_pinconf_get,
  459. .pin_config_set = meson_pinconf_set,
  460. .pin_config_group_get = meson_pinconf_group_get,
  461. .pin_config_group_set = meson_pinconf_group_set,
  462. .is_generic = true,
  463. };
  464. static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
  465. {
  466. struct meson_pinctrl *pc = gpiochip_get_data(chip);
  467. int ret;
  468. ret = meson_pinconf_get_output(pc, gpio);
  469. if (ret < 0)
  470. return ret;
  471. return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
  472. }
  473. static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  474. {
  475. return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false);
  476. }
  477. static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
  478. int value)
  479. {
  480. return meson_pinconf_set_output_drive(gpiochip_get_data(chip),
  481. gpio, value);
  482. }
  483. static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
  484. {
  485. meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
  486. }
  487. static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
  488. {
  489. struct meson_pinctrl *pc = gpiochip_get_data(chip);
  490. unsigned int reg, bit, val;
  491. struct meson_bank *bank;
  492. int ret;
  493. ret = meson_get_bank(pc, gpio, &bank);
  494. if (ret)
  495. return ret;
  496. meson_calc_reg_and_bit(bank, gpio, REG_IN, &reg, &bit);
  497. regmap_read(pc->reg_gpio, reg, &val);
  498. return !!(val & BIT(bit));
  499. }
  500. static int meson_gpiolib_register(struct meson_pinctrl *pc)
  501. {
  502. int ret;
  503. pc->chip.label = pc->data->name;
  504. pc->chip.parent = pc->dev;
  505. pc->chip.request = gpiochip_generic_request;
  506. pc->chip.free = gpiochip_generic_free;
  507. pc->chip.set_config = gpiochip_generic_config;
  508. pc->chip.get_direction = meson_gpio_get_direction;
  509. pc->chip.direction_input = meson_gpio_direction_input;
  510. pc->chip.direction_output = meson_gpio_direction_output;
  511. pc->chip.get = meson_gpio_get;
  512. pc->chip.set = meson_gpio_set;
  513. pc->chip.base = -1;
  514. pc->chip.ngpio = pc->data->num_pins;
  515. pc->chip.can_sleep = false;
  516. pc->chip.of_node = pc->of_node;
  517. pc->chip.of_gpio_n_cells = 2;
  518. ret = gpiochip_add_data(&pc->chip, pc);
  519. if (ret) {
  520. dev_err(pc->dev, "can't add gpio chip %s\n",
  521. pc->data->name);
  522. return ret;
  523. }
  524. return 0;
  525. }
  526. static struct regmap_config meson_regmap_config = {
  527. .reg_bits = 32,
  528. .val_bits = 32,
  529. .reg_stride = 4,
  530. };
  531. static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
  532. struct device_node *node, char *name)
  533. {
  534. struct resource res;
  535. void __iomem *base;
  536. int i;
  537. i = of_property_match_string(node, "reg-names", name);
  538. if (of_address_to_resource(node, i, &res))
  539. return NULL;
  540. base = devm_ioremap_resource(pc->dev, &res);
  541. if (IS_ERR(base))
  542. return ERR_CAST(base);
  543. meson_regmap_config.max_register = resource_size(&res) - 4;
  544. meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
  545. "%pOFn-%s", node,
  546. name);
  547. if (!meson_regmap_config.name)
  548. return ERR_PTR(-ENOMEM);
  549. return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
  550. }
  551. static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
  552. struct device_node *node)
  553. {
  554. struct device_node *np, *gpio_np = NULL;
  555. for_each_child_of_node(node, np) {
  556. if (!of_find_property(np, "gpio-controller", NULL))
  557. continue;
  558. if (gpio_np) {
  559. dev_err(pc->dev, "multiple gpio nodes\n");
  560. of_node_put(np);
  561. return -EINVAL;
  562. }
  563. gpio_np = np;
  564. }
  565. if (!gpio_np) {
  566. dev_err(pc->dev, "no gpio node found\n");
  567. return -EINVAL;
  568. }
  569. pc->of_node = gpio_np;
  570. pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
  571. if (IS_ERR_OR_NULL(pc->reg_mux)) {
  572. dev_err(pc->dev, "mux registers not found\n");
  573. return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT;
  574. }
  575. pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
  576. if (IS_ERR_OR_NULL(pc->reg_gpio)) {
  577. dev_err(pc->dev, "gpio registers not found\n");
  578. return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT;
  579. }
  580. pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
  581. if (IS_ERR(pc->reg_pull))
  582. pc->reg_pull = NULL;
  583. pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
  584. if (IS_ERR(pc->reg_pullen))
  585. pc->reg_pullen = NULL;
  586. pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
  587. if (IS_ERR(pc->reg_ds)) {
  588. dev_dbg(pc->dev, "ds registers not found - skipping\n");
  589. pc->reg_ds = NULL;
  590. }
  591. if (pc->data->parse_dt)
  592. return pc->data->parse_dt(pc);
  593. return 0;
  594. }
  595. int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc)
  596. {
  597. if (!pc->reg_pull)
  598. return -EINVAL;
  599. pc->reg_pullen = pc->reg_pull;
  600. return 0;
  601. }
  602. EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra);
  603. int meson_a1_parse_dt_extra(struct meson_pinctrl *pc)
  604. {
  605. pc->reg_pull = pc->reg_gpio;
  606. pc->reg_pullen = pc->reg_gpio;
  607. pc->reg_ds = pc->reg_gpio;
  608. return 0;
  609. }
  610. EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra);
  611. int meson_pinctrl_probe(struct platform_device *pdev)
  612. {
  613. struct device *dev = &pdev->dev;
  614. struct meson_pinctrl *pc;
  615. int ret;
  616. pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
  617. if (!pc)
  618. return -ENOMEM;
  619. pc->dev = dev;
  620. pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev);
  621. ret = meson_pinctrl_parse_dt(pc, dev->of_node);
  622. if (ret)
  623. return ret;
  624. pc->desc.name = "pinctrl-meson";
  625. pc->desc.owner = THIS_MODULE;
  626. pc->desc.pctlops = &meson_pctrl_ops;
  627. pc->desc.pmxops = pc->data->pmx_ops;
  628. pc->desc.confops = &meson_pinconf_ops;
  629. pc->desc.pins = pc->data->pins;
  630. pc->desc.npins = pc->data->num_pins;
  631. pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
  632. if (IS_ERR(pc->pcdev)) {
  633. dev_err(pc->dev, "can't register pinctrl device");
  634. return PTR_ERR(pc->pcdev);
  635. }
  636. return meson_gpiolib_register(pc);
  637. }
  638. EXPORT_SYMBOL_GPL(meson_pinctrl_probe);
  639. MODULE_LICENSE("GPL v2");