xusb-tegra186.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/io.h>
  7. #include <linux/module.h>
  8. #include <linux/of.h>
  9. #include <linux/phy/phy.h>
  10. #include <linux/regulator/consumer.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/clk.h>
  13. #include <linux/slab.h>
  14. #include <soc/tegra/fuse.h>
  15. #include "xusb.h"
  16. /* FUSE USB_CALIB registers */
  17. #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
  18. #define HS_CURR_LEVEL_PAD_MASK 0x3f
  19. #define HS_TERM_RANGE_ADJ_SHIFT 7
  20. #define HS_TERM_RANGE_ADJ_MASK 0xf
  21. #define HS_SQUELCH_SHIFT 29
  22. #define HS_SQUELCH_MASK 0x7
  23. #define RPD_CTRL_SHIFT 0
  24. #define RPD_CTRL_MASK 0x1f
  25. /* XUSB PADCTL registers */
  26. #define XUSB_PADCTL_USB2_PAD_MUX 0x4
  27. #define USB2_PORT_SHIFT(x) ((x) * 2)
  28. #define USB2_PORT_MASK 0x3
  29. #define PORT_XUSB 1
  30. #define HSIC_PORT_SHIFT(x) ((x) + 20)
  31. #define HSIC_PORT_MASK 0x1
  32. #define PORT_HSIC 0
  33. #define XUSB_PADCTL_USB2_PORT_CAP 0x8
  34. #define XUSB_PADCTL_SS_PORT_CAP 0xc
  35. #define PORTX_CAP_SHIFT(x) ((x) * 4)
  36. #define PORT_CAP_MASK 0x3
  37. #define PORT_CAP_DISABLED 0x0
  38. #define PORT_CAP_HOST 0x1
  39. #define PORT_CAP_DEVICE 0x2
  40. #define PORT_CAP_OTG 0x3
  41. #define XUSB_PADCTL_ELPG_PROGRAM 0x20
  42. #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
  43. #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
  44. #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
  45. #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
  46. #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
  47. #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
  48. #define ALL_WAKE_EVENTS \
  49. (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
  50. USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
  51. SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
  52. USB2_HSIC_PORT_WAKEUP_EVENT(0))
  53. #define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
  54. #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
  55. #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
  56. #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
  57. #define XUSB_PADCTL_SS_PORT_CFG 0x2c
  58. #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
  59. #define PORTX_SPEED_SUPPORT_MASK (0x3)
  60. #define PORT_SPEED_SUPPORT_GEN1 (0x0)
  61. #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
  62. #define HS_CURR_LEVEL(x) ((x) & 0x3f)
  63. #define TERM_SEL BIT(25)
  64. #define USB2_OTG_PD BIT(26)
  65. #define USB2_OTG_PD2 BIT(27)
  66. #define USB2_OTG_PD2_OVRD_EN BIT(28)
  67. #define USB2_OTG_PD_ZI BIT(29)
  68. #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
  69. #define USB2_OTG_PD_DR BIT(2)
  70. #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
  71. #define RPD_CTRL(x) (((x) & 0x1f) << 26)
  72. #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
  73. #define BIAS_PAD_PD BIT(11)
  74. #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
  75. #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
  76. #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
  77. #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
  78. #define USB2_PD_TRK BIT(26)
  79. #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
  80. #define HSIC_PD_TX_DATA0 BIT(1)
  81. #define HSIC_PD_TX_STROBE BIT(3)
  82. #define HSIC_PD_RX_DATA0 BIT(4)
  83. #define HSIC_PD_RX_STROBE BIT(6)
  84. #define HSIC_PD_ZI_DATA0 BIT(7)
  85. #define HSIC_PD_ZI_STROBE BIT(9)
  86. #define HSIC_RPD_DATA0 BIT(13)
  87. #define HSIC_RPD_STROBE BIT(15)
  88. #define HSIC_RPU_DATA0 BIT(16)
  89. #define HSIC_RPU_STROBE BIT(18)
  90. #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
  91. #define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
  92. #define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
  93. #define HSIC_PD_TRK BIT(19)
  94. #define USB2_VBUS_ID 0x360
  95. #define VBUS_OVERRIDE BIT(14)
  96. #define ID_OVERRIDE(x) (((x) & 0xf) << 18)
  97. #define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
  98. #define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
  99. #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
  100. { \
  101. .name = _name, \
  102. .offset = _offset, \
  103. .shift = _shift, \
  104. .mask = _mask, \
  105. .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
  106. .funcs = tegra186_##_type##_functions, \
  107. }
  108. struct tegra_xusb_fuse_calibration {
  109. u32 *hs_curr_level;
  110. u32 hs_squelch;
  111. u32 hs_term_range_adj;
  112. u32 rpd_ctrl;
  113. };
  114. struct tegra186_xusb_padctl {
  115. struct tegra_xusb_padctl base;
  116. struct tegra_xusb_fuse_calibration calib;
  117. /* UTMI bias and tracking */
  118. struct clk *usb2_trk_clk;
  119. unsigned int bias_pad_enable;
  120. };
  121. static inline struct tegra186_xusb_padctl *
  122. to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
  123. {
  124. return container_of(padctl, struct tegra186_xusb_padctl, base);
  125. }
  126. /* USB 2.0 UTMI PHY support */
  127. static struct tegra_xusb_lane *
  128. tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
  129. unsigned int index)
  130. {
  131. struct tegra_xusb_usb2_lane *usb2;
  132. int err;
  133. usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
  134. if (!usb2)
  135. return ERR_PTR(-ENOMEM);
  136. INIT_LIST_HEAD(&usb2->base.list);
  137. usb2->base.soc = &pad->soc->lanes[index];
  138. usb2->base.index = index;
  139. usb2->base.pad = pad;
  140. usb2->base.np = np;
  141. err = tegra_xusb_lane_parse_dt(&usb2->base, np);
  142. if (err < 0) {
  143. kfree(usb2);
  144. return ERR_PTR(err);
  145. }
  146. return &usb2->base;
  147. }
  148. static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
  149. {
  150. struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
  151. kfree(usb2);
  152. }
  153. static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
  154. .probe = tegra186_usb2_lane_probe,
  155. .remove = tegra186_usb2_lane_remove,
  156. };
  157. static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
  158. {
  159. struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
  160. struct device *dev = padctl->dev;
  161. u32 value;
  162. int err;
  163. mutex_lock(&padctl->lock);
  164. if (priv->bias_pad_enable++ > 0) {
  165. mutex_unlock(&padctl->lock);
  166. return;
  167. }
  168. err = clk_prepare_enable(priv->usb2_trk_clk);
  169. if (err < 0)
  170. dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
  171. value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
  172. value &= ~USB2_TRK_START_TIMER(~0);
  173. value |= USB2_TRK_START_TIMER(0x1e);
  174. value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
  175. value |= USB2_TRK_DONE_RESET_TIMER(0xa);
  176. padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
  177. value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
  178. value &= ~BIAS_PAD_PD;
  179. value &= ~HS_SQUELCH_LEVEL(~0);
  180. value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
  181. padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
  182. udelay(1);
  183. value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
  184. value &= ~USB2_PD_TRK;
  185. padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
  186. mutex_unlock(&padctl->lock);
  187. }
  188. static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
  189. {
  190. struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
  191. u32 value;
  192. mutex_lock(&padctl->lock);
  193. if (WARN_ON(priv->bias_pad_enable == 0)) {
  194. mutex_unlock(&padctl->lock);
  195. return;
  196. }
  197. if (--priv->bias_pad_enable > 0) {
  198. mutex_unlock(&padctl->lock);
  199. return;
  200. }
  201. value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
  202. value |= USB2_PD_TRK;
  203. padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
  204. clk_disable_unprepare(priv->usb2_trk_clk);
  205. mutex_unlock(&padctl->lock);
  206. }
  207. static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
  208. {
  209. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  210. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  211. struct tegra_xusb_usb2_port *port;
  212. struct device *dev = padctl->dev;
  213. unsigned int index = lane->index;
  214. u32 value;
  215. if (!phy)
  216. return;
  217. port = tegra_xusb_find_usb2_port(padctl, index);
  218. if (!port) {
  219. dev_err(dev, "no port found for USB2 lane %u\n", index);
  220. return;
  221. }
  222. tegra186_utmi_bias_pad_power_on(padctl);
  223. udelay(2);
  224. value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
  225. value &= ~USB2_OTG_PD;
  226. padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
  227. value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
  228. value &= ~USB2_OTG_PD_DR;
  229. padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
  230. }
  231. static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
  232. {
  233. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  234. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  235. unsigned int index = lane->index;
  236. u32 value;
  237. if (!phy)
  238. return;
  239. value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
  240. value |= USB2_OTG_PD;
  241. padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
  242. value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
  243. value |= USB2_OTG_PD_DR;
  244. padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
  245. udelay(2);
  246. tegra186_utmi_bias_pad_power_off(padctl);
  247. }
  248. static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
  249. bool status)
  250. {
  251. u32 value;
  252. dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
  253. value = padctl_readl(padctl, USB2_VBUS_ID);
  254. if (status) {
  255. value |= VBUS_OVERRIDE;
  256. value &= ~ID_OVERRIDE(~0);
  257. value |= ID_OVERRIDE_FLOATING;
  258. } else {
  259. value &= ~VBUS_OVERRIDE;
  260. }
  261. padctl_writel(padctl, value, USB2_VBUS_ID);
  262. return 0;
  263. }
  264. static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
  265. bool status)
  266. {
  267. u32 value;
  268. dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
  269. value = padctl_readl(padctl, USB2_VBUS_ID);
  270. if (status) {
  271. if (value & VBUS_OVERRIDE) {
  272. value &= ~VBUS_OVERRIDE;
  273. padctl_writel(padctl, value, USB2_VBUS_ID);
  274. usleep_range(1000, 2000);
  275. value = padctl_readl(padctl, USB2_VBUS_ID);
  276. }
  277. value &= ~ID_OVERRIDE(~0);
  278. value |= ID_OVERRIDE_GROUNDED;
  279. } else {
  280. value &= ~ID_OVERRIDE(~0);
  281. value |= ID_OVERRIDE_FLOATING;
  282. }
  283. padctl_writel(padctl, value, USB2_VBUS_ID);
  284. return 0;
  285. }
  286. static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
  287. int submode)
  288. {
  289. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  290. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  291. struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
  292. lane->index);
  293. int err = 0;
  294. mutex_lock(&padctl->lock);
  295. dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
  296. if (mode == PHY_MODE_USB_OTG) {
  297. if (submode == USB_ROLE_HOST) {
  298. tegra186_xusb_padctl_id_override(padctl, true);
  299. err = regulator_enable(port->supply);
  300. } else if (submode == USB_ROLE_DEVICE) {
  301. tegra186_xusb_padctl_vbus_override(padctl, true);
  302. } else if (submode == USB_ROLE_NONE) {
  303. /*
  304. * When port is peripheral only or role transitions to
  305. * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
  306. * enabled.
  307. */
  308. if (regulator_is_enabled(port->supply))
  309. regulator_disable(port->supply);
  310. tegra186_xusb_padctl_id_override(padctl, false);
  311. tegra186_xusb_padctl_vbus_override(padctl, false);
  312. }
  313. }
  314. mutex_unlock(&padctl->lock);
  315. return err;
  316. }
  317. static int tegra186_utmi_phy_power_on(struct phy *phy)
  318. {
  319. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  320. struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
  321. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  322. struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
  323. struct tegra_xusb_usb2_port *port;
  324. unsigned int index = lane->index;
  325. struct device *dev = padctl->dev;
  326. u32 value;
  327. port = tegra_xusb_find_usb2_port(padctl, index);
  328. if (!port) {
  329. dev_err(dev, "no port found for USB2 lane %u\n", index);
  330. return -ENODEV;
  331. }
  332. value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
  333. value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
  334. value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
  335. padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
  336. value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
  337. value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
  338. if (port->mode == USB_DR_MODE_UNKNOWN)
  339. value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
  340. else if (port->mode == USB_DR_MODE_PERIPHERAL)
  341. value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
  342. else if (port->mode == USB_DR_MODE_HOST)
  343. value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
  344. else if (port->mode == USB_DR_MODE_OTG)
  345. value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
  346. padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
  347. value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
  348. value &= ~USB2_OTG_PD_ZI;
  349. value |= TERM_SEL;
  350. value &= ~HS_CURR_LEVEL(~0);
  351. if (usb2->hs_curr_level_offset) {
  352. int hs_current_level;
  353. hs_current_level = (int)priv->calib.hs_curr_level[index] +
  354. usb2->hs_curr_level_offset;
  355. if (hs_current_level < 0)
  356. hs_current_level = 0;
  357. if (hs_current_level > 0x3f)
  358. hs_current_level = 0x3f;
  359. value |= HS_CURR_LEVEL(hs_current_level);
  360. } else {
  361. value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
  362. }
  363. padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
  364. value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
  365. value &= ~TERM_RANGE_ADJ(~0);
  366. value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
  367. value &= ~RPD_CTRL(~0);
  368. value |= RPD_CTRL(priv->calib.rpd_ctrl);
  369. padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
  370. /* TODO: pad power saving */
  371. tegra_phy_xusb_utmi_pad_power_on(phy);
  372. return 0;
  373. }
  374. static int tegra186_utmi_phy_power_off(struct phy *phy)
  375. {
  376. /* TODO: pad power saving */
  377. tegra_phy_xusb_utmi_pad_power_down(phy);
  378. return 0;
  379. }
  380. static int tegra186_utmi_phy_init(struct phy *phy)
  381. {
  382. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  383. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  384. struct tegra_xusb_usb2_port *port;
  385. unsigned int index = lane->index;
  386. struct device *dev = padctl->dev;
  387. int err;
  388. port = tegra_xusb_find_usb2_port(padctl, index);
  389. if (!port) {
  390. dev_err(dev, "no port found for USB2 lane %u\n", index);
  391. return -ENODEV;
  392. }
  393. if (port->supply && port->mode == USB_DR_MODE_HOST) {
  394. err = regulator_enable(port->supply);
  395. if (err) {
  396. dev_err(dev, "failed to enable port %u VBUS: %d\n",
  397. index, err);
  398. return err;
  399. }
  400. }
  401. return 0;
  402. }
  403. static int tegra186_utmi_phy_exit(struct phy *phy)
  404. {
  405. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  406. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  407. struct tegra_xusb_usb2_port *port;
  408. unsigned int index = lane->index;
  409. struct device *dev = padctl->dev;
  410. int err;
  411. port = tegra_xusb_find_usb2_port(padctl, index);
  412. if (!port) {
  413. dev_err(dev, "no port found for USB2 lane %u\n", index);
  414. return -ENODEV;
  415. }
  416. if (port->supply && port->mode == USB_DR_MODE_HOST) {
  417. err = regulator_disable(port->supply);
  418. if (err) {
  419. dev_err(dev, "failed to disable port %u VBUS: %d\n",
  420. index, err);
  421. return err;
  422. }
  423. }
  424. return 0;
  425. }
  426. static const struct phy_ops utmi_phy_ops = {
  427. .init = tegra186_utmi_phy_init,
  428. .exit = tegra186_utmi_phy_exit,
  429. .power_on = tegra186_utmi_phy_power_on,
  430. .power_off = tegra186_utmi_phy_power_off,
  431. .set_mode = tegra186_utmi_phy_set_mode,
  432. .owner = THIS_MODULE,
  433. };
  434. static struct tegra_xusb_pad *
  435. tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
  436. const struct tegra_xusb_pad_soc *soc,
  437. struct device_node *np)
  438. {
  439. struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
  440. struct tegra_xusb_usb2_pad *usb2;
  441. struct tegra_xusb_pad *pad;
  442. int err;
  443. usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
  444. if (!usb2)
  445. return ERR_PTR(-ENOMEM);
  446. pad = &usb2->base;
  447. pad->ops = &tegra186_usb2_lane_ops;
  448. pad->soc = soc;
  449. err = tegra_xusb_pad_init(pad, padctl, np);
  450. if (err < 0) {
  451. kfree(usb2);
  452. goto out;
  453. }
  454. priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
  455. if (IS_ERR(priv->usb2_trk_clk)) {
  456. err = PTR_ERR(priv->usb2_trk_clk);
  457. dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
  458. goto unregister;
  459. }
  460. err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
  461. if (err < 0)
  462. goto unregister;
  463. dev_set_drvdata(&pad->dev, pad);
  464. return pad;
  465. unregister:
  466. device_unregister(&pad->dev);
  467. out:
  468. return ERR_PTR(err);
  469. }
  470. static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
  471. {
  472. struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
  473. kfree(usb2);
  474. }
  475. static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
  476. .probe = tegra186_usb2_pad_probe,
  477. .remove = tegra186_usb2_pad_remove,
  478. };
  479. static const char * const tegra186_usb2_functions[] = {
  480. "xusb",
  481. };
  482. static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
  483. {
  484. return 0;
  485. }
  486. static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
  487. {
  488. }
  489. static struct tegra_xusb_lane *
  490. tegra186_usb2_port_map(struct tegra_xusb_port *port)
  491. {
  492. return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
  493. }
  494. static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
  495. .release = tegra_xusb_usb2_port_release,
  496. .remove = tegra_xusb_usb2_port_remove,
  497. .enable = tegra186_usb2_port_enable,
  498. .disable = tegra186_usb2_port_disable,
  499. .map = tegra186_usb2_port_map,
  500. };
  501. /* SuperSpeed PHY support */
  502. static struct tegra_xusb_lane *
  503. tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
  504. unsigned int index)
  505. {
  506. struct tegra_xusb_usb3_lane *usb3;
  507. int err;
  508. usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
  509. if (!usb3)
  510. return ERR_PTR(-ENOMEM);
  511. INIT_LIST_HEAD(&usb3->base.list);
  512. usb3->base.soc = &pad->soc->lanes[index];
  513. usb3->base.index = index;
  514. usb3->base.pad = pad;
  515. usb3->base.np = np;
  516. err = tegra_xusb_lane_parse_dt(&usb3->base, np);
  517. if (err < 0) {
  518. kfree(usb3);
  519. return ERR_PTR(err);
  520. }
  521. return &usb3->base;
  522. }
  523. static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
  524. {
  525. struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
  526. kfree(usb3);
  527. }
  528. static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
  529. .probe = tegra186_usb3_lane_probe,
  530. .remove = tegra186_usb3_lane_remove,
  531. };
  532. static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
  533. {
  534. return 0;
  535. }
  536. static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
  537. {
  538. }
  539. static struct tegra_xusb_lane *
  540. tegra186_usb3_port_map(struct tegra_xusb_port *port)
  541. {
  542. return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
  543. }
  544. static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
  545. .release = tegra_xusb_usb3_port_release,
  546. .remove = tegra_xusb_usb3_port_remove,
  547. .enable = tegra186_usb3_port_enable,
  548. .disable = tegra186_usb3_port_disable,
  549. .map = tegra186_usb3_port_map,
  550. };
  551. static int tegra186_usb3_phy_power_on(struct phy *phy)
  552. {
  553. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  554. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  555. struct tegra_xusb_usb3_port *port;
  556. struct tegra_xusb_usb2_port *usb2;
  557. unsigned int index = lane->index;
  558. struct device *dev = padctl->dev;
  559. u32 value;
  560. port = tegra_xusb_find_usb3_port(padctl, index);
  561. if (!port) {
  562. dev_err(dev, "no port found for USB3 lane %u\n", index);
  563. return -ENODEV;
  564. }
  565. usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
  566. if (!usb2) {
  567. dev_err(dev, "no companion port found for USB3 lane %u\n",
  568. index);
  569. return -ENODEV;
  570. }
  571. mutex_lock(&padctl->lock);
  572. value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
  573. value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
  574. if (usb2->mode == USB_DR_MODE_UNKNOWN)
  575. value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
  576. else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
  577. value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
  578. else if (usb2->mode == USB_DR_MODE_HOST)
  579. value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
  580. else if (usb2->mode == USB_DR_MODE_OTG)
  581. value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
  582. padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
  583. if (padctl->soc->supports_gen2 && port->disable_gen2) {
  584. value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
  585. value &= ~(PORTX_SPEED_SUPPORT_MASK <<
  586. PORTX_SPEED_SUPPORT_SHIFT(index));
  587. value |= (PORT_SPEED_SUPPORT_GEN1 <<
  588. PORTX_SPEED_SUPPORT_SHIFT(index));
  589. padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
  590. }
  591. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
  592. value &= ~SSPX_ELPG_VCORE_DOWN(index);
  593. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
  594. usleep_range(100, 200);
  595. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
  596. value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
  597. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
  598. usleep_range(100, 200);
  599. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
  600. value &= ~SSPX_ELPG_CLAMP_EN(index);
  601. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
  602. mutex_unlock(&padctl->lock);
  603. return 0;
  604. }
  605. static int tegra186_usb3_phy_power_off(struct phy *phy)
  606. {
  607. struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
  608. struct tegra_xusb_padctl *padctl = lane->pad->padctl;
  609. struct tegra_xusb_usb3_port *port;
  610. unsigned int index = lane->index;
  611. struct device *dev = padctl->dev;
  612. u32 value;
  613. port = tegra_xusb_find_usb3_port(padctl, index);
  614. if (!port) {
  615. dev_err(dev, "no port found for USB3 lane %u\n", index);
  616. return -ENODEV;
  617. }
  618. mutex_lock(&padctl->lock);
  619. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
  620. value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
  621. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
  622. usleep_range(100, 200);
  623. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
  624. value |= SSPX_ELPG_CLAMP_EN(index);
  625. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
  626. usleep_range(250, 350);
  627. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
  628. value |= SSPX_ELPG_VCORE_DOWN(index);
  629. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
  630. mutex_unlock(&padctl->lock);
  631. return 0;
  632. }
  633. static int tegra186_usb3_phy_init(struct phy *phy)
  634. {
  635. return 0;
  636. }
  637. static int tegra186_usb3_phy_exit(struct phy *phy)
  638. {
  639. return 0;
  640. }
  641. static const struct phy_ops usb3_phy_ops = {
  642. .init = tegra186_usb3_phy_init,
  643. .exit = tegra186_usb3_phy_exit,
  644. .power_on = tegra186_usb3_phy_power_on,
  645. .power_off = tegra186_usb3_phy_power_off,
  646. .owner = THIS_MODULE,
  647. };
  648. static struct tegra_xusb_pad *
  649. tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
  650. const struct tegra_xusb_pad_soc *soc,
  651. struct device_node *np)
  652. {
  653. struct tegra_xusb_usb3_pad *usb3;
  654. struct tegra_xusb_pad *pad;
  655. int err;
  656. usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
  657. if (!usb3)
  658. return ERR_PTR(-ENOMEM);
  659. pad = &usb3->base;
  660. pad->ops = &tegra186_usb3_lane_ops;
  661. pad->soc = soc;
  662. err = tegra_xusb_pad_init(pad, padctl, np);
  663. if (err < 0) {
  664. kfree(usb3);
  665. goto out;
  666. }
  667. err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
  668. if (err < 0)
  669. goto unregister;
  670. dev_set_drvdata(&pad->dev, pad);
  671. return pad;
  672. unregister:
  673. device_unregister(&pad->dev);
  674. out:
  675. return ERR_PTR(err);
  676. }
  677. static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
  678. {
  679. struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
  680. kfree(usb2);
  681. }
  682. static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
  683. .probe = tegra186_usb3_pad_probe,
  684. .remove = tegra186_usb3_pad_remove,
  685. };
  686. static const char * const tegra186_usb3_functions[] = {
  687. "xusb",
  688. };
  689. static int
  690. tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
  691. {
  692. struct device *dev = padctl->base.dev;
  693. unsigned int i, count;
  694. u32 value, *level;
  695. int err;
  696. count = padctl->base.soc->ports.usb2.count;
  697. level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
  698. if (!level)
  699. return -ENOMEM;
  700. err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
  701. if (err) {
  702. if (err != -EPROBE_DEFER)
  703. dev_err(dev, "failed to read calibration fuse: %d\n",
  704. err);
  705. return err;
  706. }
  707. dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
  708. for (i = 0; i < count; i++)
  709. level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
  710. HS_CURR_LEVEL_PAD_MASK;
  711. padctl->calib.hs_curr_level = level;
  712. padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
  713. HS_SQUELCH_MASK;
  714. padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
  715. HS_TERM_RANGE_ADJ_MASK;
  716. err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
  717. if (err) {
  718. dev_err(dev, "failed to read calibration fuse: %d\n", err);
  719. return err;
  720. }
  721. dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
  722. padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
  723. return 0;
  724. }
  725. static struct tegra_xusb_padctl *
  726. tegra186_xusb_padctl_probe(struct device *dev,
  727. const struct tegra_xusb_padctl_soc *soc)
  728. {
  729. struct tegra186_xusb_padctl *priv;
  730. int err;
  731. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  732. if (!priv)
  733. return ERR_PTR(-ENOMEM);
  734. priv->base.dev = dev;
  735. priv->base.soc = soc;
  736. err = tegra186_xusb_read_fuse_calibration(priv);
  737. if (err < 0)
  738. return ERR_PTR(err);
  739. return &priv->base;
  740. }
  741. static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
  742. {
  743. }
  744. static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
  745. .probe = tegra186_xusb_padctl_probe,
  746. .remove = tegra186_xusb_padctl_remove,
  747. .vbus_override = tegra186_xusb_padctl_vbus_override,
  748. };
  749. #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
  750. static const char * const tegra186_xusb_padctl_supply_names[] = {
  751. "avdd-pll-erefeut",
  752. "avdd-usb",
  753. "vclamp-usb",
  754. "vddio-hsic",
  755. };
  756. static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
  757. TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
  758. TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
  759. TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
  760. };
  761. static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
  762. .name = "usb2",
  763. .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
  764. .lanes = tegra186_usb2_lanes,
  765. .ops = &tegra186_usb2_pad_ops,
  766. };
  767. static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
  768. TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
  769. TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
  770. TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
  771. };
  772. static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
  773. .name = "usb3",
  774. .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
  775. .lanes = tegra186_usb3_lanes,
  776. .ops = &tegra186_usb3_pad_ops,
  777. };
  778. static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
  779. &tegra186_usb2_pad,
  780. &tegra186_usb3_pad,
  781. #if 0 /* TODO implement */
  782. &tegra186_hsic_pad,
  783. #endif
  784. };
  785. const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
  786. .num_pads = ARRAY_SIZE(tegra186_pads),
  787. .pads = tegra186_pads,
  788. .ports = {
  789. .usb2 = {
  790. .ops = &tegra186_usb2_port_ops,
  791. .count = 3,
  792. },
  793. #if 0 /* TODO implement */
  794. .hsic = {
  795. .ops = &tegra186_hsic_port_ops,
  796. .count = 1,
  797. },
  798. #endif
  799. .usb3 = {
  800. .ops = &tegra186_usb3_port_ops,
  801. .count = 3,
  802. },
  803. },
  804. .ops = &tegra186_xusb_padctl_ops,
  805. .supply_names = tegra186_xusb_padctl_supply_names,
  806. .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
  807. };
  808. EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
  809. #endif
  810. #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
  811. static const char * const tegra194_xusb_padctl_supply_names[] = {
  812. "avdd-usb",
  813. "vclamp-usb",
  814. };
  815. static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
  816. TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
  817. TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
  818. TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
  819. TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
  820. };
  821. static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
  822. .name = "usb2",
  823. .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
  824. .lanes = tegra194_usb2_lanes,
  825. .ops = &tegra186_usb2_pad_ops,
  826. };
  827. static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
  828. TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
  829. TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
  830. TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
  831. TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
  832. };
  833. static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
  834. .name = "usb3",
  835. .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
  836. .lanes = tegra194_usb3_lanes,
  837. .ops = &tegra186_usb3_pad_ops,
  838. };
  839. static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
  840. &tegra194_usb2_pad,
  841. &tegra194_usb3_pad,
  842. };
  843. const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
  844. .num_pads = ARRAY_SIZE(tegra194_pads),
  845. .pads = tegra194_pads,
  846. .ports = {
  847. .usb2 = {
  848. .ops = &tegra186_usb2_port_ops,
  849. .count = 4,
  850. },
  851. .usb3 = {
  852. .ops = &tegra186_usb3_port_ops,
  853. .count = 4,
  854. },
  855. },
  856. .ops = &tegra186_xusb_padctl_ops,
  857. .supply_names = tegra194_xusb_padctl_supply_names,
  858. .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
  859. .supports_gen2 = true,
  860. };
  861. EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
  862. #endif
  863. MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
  864. MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
  865. MODULE_LICENSE("GPL v2");