phy-uniphier-usb3hs.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * phy-uniphier-usb3hs.c - HS-PHY driver for Socionext UniPhier USB3 controller
  4. * Copyright 2015-2018 Socionext Inc.
  5. * Author:
  6. * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
  7. * Contributors:
  8. * Motoya Tanigawa <tanigawa.motoya@socionext.com>
  9. * Masami Hiramatsu <masami.hiramatsu@linaro.org>
  10. */
  11. #include <linux/bitfield.h>
  12. #include <linux/bitops.h>
  13. #include <linux/clk.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/nvmem-consumer.h>
  17. #include <linux/of.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/phy/phy.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/reset.h>
  23. #include <linux/slab.h>
  24. #define HSPHY_CFG0 0x0
  25. #define HSPHY_CFG0_HS_I_MASK GENMASK(31, 28)
  26. #define HSPHY_CFG0_HSDISC_MASK GENMASK(27, 26)
  27. #define HSPHY_CFG0_SWING_MASK GENMASK(17, 16)
  28. #define HSPHY_CFG0_SEL_T_MASK GENMASK(15, 12)
  29. #define HSPHY_CFG0_RTERM_MASK GENMASK(7, 6)
  30. #define HSPHY_CFG0_TRIMMASK (HSPHY_CFG0_HS_I_MASK \
  31. | HSPHY_CFG0_SEL_T_MASK \
  32. | HSPHY_CFG0_RTERM_MASK)
  33. #define HSPHY_CFG1 0x4
  34. #define HSPHY_CFG1_DAT_EN BIT(29)
  35. #define HSPHY_CFG1_ADR_EN BIT(28)
  36. #define HSPHY_CFG1_ADR_MASK GENMASK(27, 16)
  37. #define HSPHY_CFG1_DAT_MASK GENMASK(23, 16)
  38. #define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) }
  39. #define RX_CHK_SYNC PHY_F(0, 5, 5) /* RX sync mode */
  40. #define RX_SYNC_SEL PHY_F(1, 1, 0) /* RX sync length */
  41. #define LS_SLEW PHY_F(10, 6, 6) /* LS mode slew rate */
  42. #define FS_LS_DRV PHY_F(10, 5, 5) /* FS/LS slew rate */
  43. #define MAX_PHY_PARAMS 4
  44. struct uniphier_u3hsphy_param {
  45. struct {
  46. int reg_no;
  47. int msb;
  48. int lsb;
  49. } field;
  50. u8 value;
  51. };
  52. struct uniphier_u3hsphy_trim_param {
  53. unsigned int rterm;
  54. unsigned int sel_t;
  55. unsigned int hs_i;
  56. };
  57. #define trim_param_is_valid(p) ((p)->rterm || (p)->sel_t || (p)->hs_i)
  58. struct uniphier_u3hsphy_priv {
  59. struct device *dev;
  60. void __iomem *base;
  61. struct clk *clk, *clk_parent, *clk_ext, *clk_parent_gio;
  62. struct reset_control *rst, *rst_parent, *rst_parent_gio;
  63. struct regulator *vbus;
  64. const struct uniphier_u3hsphy_soc_data *data;
  65. };
  66. struct uniphier_u3hsphy_soc_data {
  67. bool is_legacy;
  68. int nparams;
  69. const struct uniphier_u3hsphy_param param[MAX_PHY_PARAMS];
  70. u32 config0;
  71. u32 config1;
  72. void (*trim_func)(struct uniphier_u3hsphy_priv *priv, u32 *pconfig,
  73. struct uniphier_u3hsphy_trim_param *pt);
  74. };
  75. static void uniphier_u3hsphy_trim_ld20(struct uniphier_u3hsphy_priv *priv,
  76. u32 *pconfig,
  77. struct uniphier_u3hsphy_trim_param *pt)
  78. {
  79. *pconfig &= ~HSPHY_CFG0_RTERM_MASK;
  80. *pconfig |= FIELD_PREP(HSPHY_CFG0_RTERM_MASK, pt->rterm);
  81. *pconfig &= ~HSPHY_CFG0_SEL_T_MASK;
  82. *pconfig |= FIELD_PREP(HSPHY_CFG0_SEL_T_MASK, pt->sel_t);
  83. *pconfig &= ~HSPHY_CFG0_HS_I_MASK;
  84. *pconfig |= FIELD_PREP(HSPHY_CFG0_HS_I_MASK, pt->hs_i);
  85. }
  86. static int uniphier_u3hsphy_get_nvparam(struct uniphier_u3hsphy_priv *priv,
  87. const char *name, unsigned int *val)
  88. {
  89. struct nvmem_cell *cell;
  90. u8 *buf;
  91. cell = devm_nvmem_cell_get(priv->dev, name);
  92. if (IS_ERR(cell))
  93. return PTR_ERR(cell);
  94. buf = nvmem_cell_read(cell, NULL);
  95. if (IS_ERR(buf))
  96. return PTR_ERR(buf);
  97. *val = *buf;
  98. kfree(buf);
  99. return 0;
  100. }
  101. static int uniphier_u3hsphy_get_nvparams(struct uniphier_u3hsphy_priv *priv,
  102. struct uniphier_u3hsphy_trim_param *pt)
  103. {
  104. int ret;
  105. ret = uniphier_u3hsphy_get_nvparam(priv, "rterm", &pt->rterm);
  106. if (ret)
  107. return ret;
  108. ret = uniphier_u3hsphy_get_nvparam(priv, "sel_t", &pt->sel_t);
  109. if (ret)
  110. return ret;
  111. ret = uniphier_u3hsphy_get_nvparam(priv, "hs_i", &pt->hs_i);
  112. if (ret)
  113. return ret;
  114. return 0;
  115. }
  116. static int uniphier_u3hsphy_update_config(struct uniphier_u3hsphy_priv *priv,
  117. u32 *pconfig)
  118. {
  119. struct uniphier_u3hsphy_trim_param trim;
  120. int ret, trimmed = 0;
  121. if (priv->data->trim_func) {
  122. ret = uniphier_u3hsphy_get_nvparams(priv, &trim);
  123. if (ret == -EPROBE_DEFER)
  124. return ret;
  125. /*
  126. * call trim_func only when trimming parameters that aren't
  127. * all-zero can be acquired. All-zero parameters mean nothing
  128. * has been written to nvmem.
  129. */
  130. if (!ret && trim_param_is_valid(&trim)) {
  131. priv->data->trim_func(priv, pconfig, &trim);
  132. trimmed = 1;
  133. } else {
  134. dev_dbg(priv->dev, "can't get parameter from nvmem\n");
  135. }
  136. }
  137. /* use default parameters without trimming values */
  138. if (!trimmed) {
  139. *pconfig &= ~HSPHY_CFG0_HSDISC_MASK;
  140. *pconfig |= FIELD_PREP(HSPHY_CFG0_HSDISC_MASK, 3);
  141. }
  142. return 0;
  143. }
  144. static void uniphier_u3hsphy_set_param(struct uniphier_u3hsphy_priv *priv,
  145. const struct uniphier_u3hsphy_param *p)
  146. {
  147. u32 val;
  148. u32 field_mask = GENMASK(p->field.msb, p->field.lsb);
  149. u8 data;
  150. val = readl(priv->base + HSPHY_CFG1);
  151. val &= ~HSPHY_CFG1_ADR_MASK;
  152. val |= FIELD_PREP(HSPHY_CFG1_ADR_MASK, p->field.reg_no)
  153. | HSPHY_CFG1_ADR_EN;
  154. writel(val, priv->base + HSPHY_CFG1);
  155. val = readl(priv->base + HSPHY_CFG1);
  156. val &= ~HSPHY_CFG1_ADR_EN;
  157. writel(val, priv->base + HSPHY_CFG1);
  158. val = readl(priv->base + HSPHY_CFG1);
  159. val &= ~FIELD_PREP(HSPHY_CFG1_DAT_MASK, field_mask);
  160. data = field_mask & (p->value << p->field.lsb);
  161. val |= FIELD_PREP(HSPHY_CFG1_DAT_MASK, data) | HSPHY_CFG1_DAT_EN;
  162. writel(val, priv->base + HSPHY_CFG1);
  163. val = readl(priv->base + HSPHY_CFG1);
  164. val &= ~HSPHY_CFG1_DAT_EN;
  165. writel(val, priv->base + HSPHY_CFG1);
  166. }
  167. static int uniphier_u3hsphy_power_on(struct phy *phy)
  168. {
  169. struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
  170. int ret;
  171. ret = clk_prepare_enable(priv->clk_ext);
  172. if (ret)
  173. return ret;
  174. ret = clk_prepare_enable(priv->clk);
  175. if (ret)
  176. goto out_clk_ext_disable;
  177. ret = reset_control_deassert(priv->rst);
  178. if (ret)
  179. goto out_clk_disable;
  180. if (priv->vbus) {
  181. ret = regulator_enable(priv->vbus);
  182. if (ret)
  183. goto out_rst_assert;
  184. }
  185. return 0;
  186. out_rst_assert:
  187. reset_control_assert(priv->rst);
  188. out_clk_disable:
  189. clk_disable_unprepare(priv->clk);
  190. out_clk_ext_disable:
  191. clk_disable_unprepare(priv->clk_ext);
  192. return ret;
  193. }
  194. static int uniphier_u3hsphy_power_off(struct phy *phy)
  195. {
  196. struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
  197. if (priv->vbus)
  198. regulator_disable(priv->vbus);
  199. reset_control_assert(priv->rst);
  200. clk_disable_unprepare(priv->clk);
  201. clk_disable_unprepare(priv->clk_ext);
  202. return 0;
  203. }
  204. static int uniphier_u3hsphy_init(struct phy *phy)
  205. {
  206. struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
  207. u32 config0, config1;
  208. int i, ret;
  209. ret = clk_prepare_enable(priv->clk_parent);
  210. if (ret)
  211. return ret;
  212. ret = clk_prepare_enable(priv->clk_parent_gio);
  213. if (ret)
  214. goto out_clk_disable;
  215. ret = reset_control_deassert(priv->rst_parent);
  216. if (ret)
  217. goto out_clk_gio_disable;
  218. ret = reset_control_deassert(priv->rst_parent_gio);
  219. if (ret)
  220. goto out_rst_assert;
  221. if ((priv->data->is_legacy)
  222. || (!priv->data->config0 && !priv->data->config1))
  223. return 0;
  224. config0 = priv->data->config0;
  225. config1 = priv->data->config1;
  226. ret = uniphier_u3hsphy_update_config(priv, &config0);
  227. if (ret)
  228. goto out_rst_assert;
  229. writel(config0, priv->base + HSPHY_CFG0);
  230. writel(config1, priv->base + HSPHY_CFG1);
  231. for (i = 0; i < priv->data->nparams; i++)
  232. uniphier_u3hsphy_set_param(priv, &priv->data->param[i]);
  233. return 0;
  234. out_rst_assert:
  235. reset_control_assert(priv->rst_parent);
  236. out_clk_gio_disable:
  237. clk_disable_unprepare(priv->clk_parent_gio);
  238. out_clk_disable:
  239. clk_disable_unprepare(priv->clk_parent);
  240. return ret;
  241. }
  242. static int uniphier_u3hsphy_exit(struct phy *phy)
  243. {
  244. struct uniphier_u3hsphy_priv *priv = phy_get_drvdata(phy);
  245. reset_control_assert(priv->rst_parent_gio);
  246. reset_control_assert(priv->rst_parent);
  247. clk_disable_unprepare(priv->clk_parent_gio);
  248. clk_disable_unprepare(priv->clk_parent);
  249. return 0;
  250. }
  251. static const struct phy_ops uniphier_u3hsphy_ops = {
  252. .init = uniphier_u3hsphy_init,
  253. .exit = uniphier_u3hsphy_exit,
  254. .power_on = uniphier_u3hsphy_power_on,
  255. .power_off = uniphier_u3hsphy_power_off,
  256. .owner = THIS_MODULE,
  257. };
  258. static int uniphier_u3hsphy_probe(struct platform_device *pdev)
  259. {
  260. struct device *dev = &pdev->dev;
  261. struct uniphier_u3hsphy_priv *priv;
  262. struct phy_provider *phy_provider;
  263. struct phy *phy;
  264. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  265. if (!priv)
  266. return -ENOMEM;
  267. priv->dev = dev;
  268. priv->data = of_device_get_match_data(dev);
  269. if (WARN_ON(!priv->data ||
  270. priv->data->nparams > MAX_PHY_PARAMS))
  271. return -EINVAL;
  272. priv->base = devm_platform_ioremap_resource(pdev, 0);
  273. if (IS_ERR(priv->base))
  274. return PTR_ERR(priv->base);
  275. if (!priv->data->is_legacy) {
  276. priv->clk = devm_clk_get(dev, "phy");
  277. if (IS_ERR(priv->clk))
  278. return PTR_ERR(priv->clk);
  279. priv->clk_ext = devm_clk_get_optional(dev, "phy-ext");
  280. if (IS_ERR(priv->clk_ext))
  281. return PTR_ERR(priv->clk_ext);
  282. priv->rst = devm_reset_control_get_shared(dev, "phy");
  283. if (IS_ERR(priv->rst))
  284. return PTR_ERR(priv->rst);
  285. } else {
  286. priv->clk_parent_gio = devm_clk_get(dev, "gio");
  287. if (IS_ERR(priv->clk_parent_gio))
  288. return PTR_ERR(priv->clk_parent_gio);
  289. priv->rst_parent_gio =
  290. devm_reset_control_get_shared(dev, "gio");
  291. if (IS_ERR(priv->rst_parent_gio))
  292. return PTR_ERR(priv->rst_parent_gio);
  293. }
  294. priv->clk_parent = devm_clk_get(dev, "link");
  295. if (IS_ERR(priv->clk_parent))
  296. return PTR_ERR(priv->clk_parent);
  297. priv->rst_parent = devm_reset_control_get_shared(dev, "link");
  298. if (IS_ERR(priv->rst_parent))
  299. return PTR_ERR(priv->rst_parent);
  300. priv->vbus = devm_regulator_get_optional(dev, "vbus");
  301. if (IS_ERR(priv->vbus)) {
  302. if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
  303. return PTR_ERR(priv->vbus);
  304. priv->vbus = NULL;
  305. }
  306. phy = devm_phy_create(dev, dev->of_node, &uniphier_u3hsphy_ops);
  307. if (IS_ERR(phy))
  308. return PTR_ERR(phy);
  309. phy_set_drvdata(phy, priv);
  310. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  311. return PTR_ERR_OR_ZERO(phy_provider);
  312. }
  313. static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = {
  314. .is_legacy = true,
  315. .nparams = 0,
  316. };
  317. static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = {
  318. .is_legacy = false,
  319. .nparams = 2,
  320. .param = {
  321. { RX_CHK_SYNC, 1 },
  322. { RX_SYNC_SEL, 1 },
  323. },
  324. };
  325. static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = {
  326. .is_legacy = false,
  327. .nparams = 4,
  328. .param = {
  329. { RX_CHK_SYNC, 1 },
  330. { RX_SYNC_SEL, 1 },
  331. { LS_SLEW, 1 },
  332. { FS_LS_DRV, 1 },
  333. },
  334. .trim_func = uniphier_u3hsphy_trim_ld20,
  335. .config0 = 0x92316680,
  336. .config1 = 0x00000106,
  337. };
  338. static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = {
  339. .is_legacy = false,
  340. .nparams = 2,
  341. .param = {
  342. { RX_CHK_SYNC, 1 },
  343. { RX_SYNC_SEL, 1 },
  344. },
  345. .trim_func = uniphier_u3hsphy_trim_ld20,
  346. .config0 = 0x92316680,
  347. .config1 = 0x00000106,
  348. };
  349. static const struct of_device_id uniphier_u3hsphy_match[] = {
  350. {
  351. .compatible = "socionext,uniphier-pro5-usb3-hsphy",
  352. .data = &uniphier_pro5_data,
  353. },
  354. {
  355. .compatible = "socionext,uniphier-pxs2-usb3-hsphy",
  356. .data = &uniphier_pxs2_data,
  357. },
  358. {
  359. .compatible = "socionext,uniphier-ld20-usb3-hsphy",
  360. .data = &uniphier_ld20_data,
  361. },
  362. {
  363. .compatible = "socionext,uniphier-pxs3-usb3-hsphy",
  364. .data = &uniphier_pxs3_data,
  365. },
  366. { /* sentinel */ }
  367. };
  368. MODULE_DEVICE_TABLE(of, uniphier_u3hsphy_match);
  369. static struct platform_driver uniphier_u3hsphy_driver = {
  370. .probe = uniphier_u3hsphy_probe,
  371. .driver = {
  372. .name = "uniphier-usb3-hsphy",
  373. .of_match_table = uniphier_u3hsphy_match,
  374. },
  375. };
  376. module_platform_driver(uniphier_u3hsphy_driver);
  377. MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
  378. MODULE_DESCRIPTION("UniPhier HS-PHY driver for USB3 controller");
  379. MODULE_LICENSE("GPL v2");